| /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| &mdss_mdp { |
| dsi_djn_hx83112b_1080p_cmd: qcom,mdss_dsi_djn_hx83112b_1080p_cmd { |
| qcom,mdss-dsi-panel-name = |
| "djn hx83112b 1080p cmd mode dsi panel"; |
| //[Arima][8901][JialongJhan] enable LCM Command mode 20190403 Start |
| qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; |
| //[Arima][8901][JialongJhan] enable LCM Command mode 20190403 End |
| qcom,mdss-dsi-panel-framerate = <60>; |
| qcom,mdss-dsi-virtual-channel-id = <0>; |
| qcom,mdss-dsi-stream = <0>; |
| qcom,mdss-dsi-panel-width = <1080>; |
| qcom,mdss-dsi-panel-height = <2160>; |
| qcom,mdss-dsi-h-front-porch = <40>; |
| qcom,mdss-dsi-h-back-porch = <12>; |
| qcom,mdss-dsi-h-pulse-width = <4>; |
| qcom,mdss-dsi-h-sync-skew = <0>; |
| qcom,mdss-dsi-v-back-porch = <2>; |
| qcom,mdss-dsi-v-front-porch = <32>; |
| qcom,mdss-dsi-v-pulse-width = <2>; |
| qcom,mdss-dsi-h-left-border = <0>; |
| qcom,mdss-dsi-h-right-border = <0>; |
| qcom,mdss-dsi-v-top-border = <0>; |
| qcom,mdss-dsi-v-bottom-border = <0>; |
| qcom,mdss-dsi-bpp = <24>; |
| qcom,mdss-dsi-underflow-color = <0xff>; |
| qcom,mdss-dsi-border-color = <0>; |
| //[Arima][8901][JialongJhan] enable LCM Command mode 20190403 Start |
| qcom,mdss-dsi-te-pin-select = <1>; |
| qcom,mdss-dsi-te-dcs-command = <1>; |
| qcom,mdss-dsi-te-check-enable; |
| qcom,mdss-dsi-te-using-te-pin; |
| //[Arima][8901][JialongJhan] enable LCM Command mode 20190403 End |
| //Qcom |
| qcom,mdss-tear-check-sync-init-val = <2160>; |
| qcom,mdss-tear-check-sync-threshold-start = <4>; |
| qcom,mdss-tear-check-sync-threshold-continue = <4>; |
| qcom,mdss-tear-check-start-pos = <2160>; |
| //Qcom |
| qcom,mdss-dsi-h-sync-pulse = <0>; |
| qcom,mdss-dsi-traffic-mode = "burst_mode"; |
| qcom,mdss-dsi-bllp-eof-power-mode; |
| qcom,mdss-dsi-bllp-power-mode; |
| qcom,mdss-dsi-lane-0-state; |
| qcom,mdss-dsi-lane-1-state; |
| qcom,mdss-dsi-lane-2-state; |
| qcom,mdss-dsi-lane-3-state; |
| //qcom,mdss-dsi-hfp-power-mode; |
| //qcom,mdss-dsi-hbp-power-mode; |
| qcom,mdss-dsi-hsa-power-mode; |
| qcom,mdss-pan-physical-width-dimension=<65>; |
| qcom,mdss-pan-physical-height-dimension=<128>; |
| qcom,mdss-dsi-panel-timings = [e6 38 26 00 68 6e 2a |
| 3c 44 03 04 00]; |
| qcom,mdss-dsi-t-clk-post = <0x0d>; |
| qcom,mdss-dsi-t-clk-pre = <0x2f>; |
| qcom,mdss-dsi-bl-min-level = <1>; |
| qcom,mdss-dsi-bl-max-level = <4095>; |
| qcom,mdss-dsi-dma-trigger = "trigger_sw"; |
| qcom,mdss-dsi-mdp-trigger = "none"; |
| //[Arima][8901][Jialong]LCM initial code from IC firmware Start |
| qcom,mdss-dsi-on-command = [39 01 00 00 00 00 04 B9 83 11 2B |
| 39 01 00 00 00 00 02 BD 01 |
| 39 01 00 00 00 00 03 C2 08 70 |
| 39 01 00 00 00 00 02 BD 03 |
| 39 01 00 00 00 00 05 B2 04 38 08 70 |
| 39 01 00 00 00 00 02 BD 00 |
| 39 01 00 00 00 00 0B B1 F8 27 27 00 00 0B 0E 0B 0E 33 |
| 39 01 00 00 00 00 03 D2 2D 2D |
| 39 01 00 00 00 00 0C B2 80 02 18 80 70 00 08 1C 08 11 05 |
| 39 01 00 00 00 00 02 E9 D1 |
| 39 01 00 00 00 00 03 B2 00 08 |
| 39 01 00 00 00 00 02 E9 00 |
| 39 01 00 00 00 00 02 BD 02 |
| 39 01 00 00 00 00 03 B2 B5 0A |
| 39 01 00 00 00 00 02 BD 00 |
| 39 01 00 00 00 00 09 DD 00 00 08 1C 08 34 34 88 |
| 39 01 00 00 00 00 19 B4 65 6B 00 00 D0 D4 36 CF 06 CE 00 CE 00 00 00 07 00 2A 07 01 07 00 00 2A |
| 39 01 00 00 00 00 02 BD 03 |
| 39 01 00 00 00 00 02 E9 C3 |
| 39 01 00 00 00 00 04 B4 01 67 2A |
| 39 01 00 00 00 00 02 E9 00 |
| 39 01 00 00 00 00 02 BD 00 |
| 39 01 00 00 00 00 02 C1 01 |
| 39 01 00 00 00 00 02 BD 01 |
| 39 01 00 00 00 00 3A C1 FF FB F9 F6 F4 F1 EF EA E7 E5 E2 DF DD DA D8 D5 D2 CF CC C5 BE B7 B0 A8 A0 98 8E 85 7B 72 69 5E 53 48 3E 35 2B 22 17 0D 09 07 05 01 00 26 F0 86 25 6E B6 DD F3 D8 CC 9B 00 |
| 39 01 00 00 00 00 02 BD 02 |
| 39 01 00 00 00 00 3A C1 FF FB F9 F6 F4 F1 EF EA E7 E5 E2 DF DD DA D8 D5 D2 CF CC C5 BE B7 B0 A8 A0 98 8E 85 7B 72 69 5E 53 48 3E 35 2B 22 17 0D 09 07 05 01 00 26 F0 86 25 6E B6 DD F3 D8 CC 9B 00 |
| 39 01 00 00 00 00 02 BD 03 |
| 39 01 00 00 00 00 3A C1 FF FB F9 F6 F4 F1 EF EA E7 E5 E2 DF DD DA D8 D5 D2 CF CC C5 BE B7 B0 A8 A0 98 8E 85 7B 72 69 5E 53 48 3E 35 2B 22 17 0D 09 07 05 01 00 26 F0 86 25 6E B6 DD F3 D8 CC 9B 00 |
| 39 01 00 00 00 00 02 BD 00 |
| 39 01 00 00 00 00 02 C2 C8 |
| 39 01 00 00 00 00 02 CC 08 |
| 39 01 00 00 00 00 26 D3 81 00 00 00 00 01 00 04 00 01 13 40 04 09 09 0B 0B 32 10 08 00 08 32 10 08 00 08 32 10 08 00 08 00 00 0A 08 7B |
| 39 01 00 00 00 00 02 E9 C5 |
| 39 01 00 00 00 00 02 C6 F7 |
| 39 01 00 00 00 00 02 E9 00 |
| 39 01 00 00 00 00 02 E9 D4 |
| 39 01 00 00 00 00 02 C6 6E |
| 39 01 00 00 00 00 02 E9 00 |
| 39 01 00 00 00 00 02 E9 EF |
| 39 01 00 00 00 00 02 D3 0C |
| 39 01 00 00 00 00 02 E9 00 |
| 39 01 00 00 00 00 02 BD 01 |
| 39 01 00 00 00 00 02 E9 C8 |
| 39 01 00 00 00 00 02 D3 A1 |
| 39 01 00 00 00 00 02 E9 00 |
| 39 01 00 00 00 00 02 BD 00 |
| 39 01 00 00 00 00 39 D5 18 18 19 18 18 20 18 18 18 10 10 18 18 00 00 18 18 01 01 18 18 28 28 18 18 18 18 18 2F 2F 30 30 31 31 35 35 36 36 37 37 18 18 18 18 18 18 18 18 FC FC 00 00 FC FC 00 00 |
| 39 01 00 00 00 00 31 D6 18 18 19 18 18 20 19 18 18 10 10 18 18 00 00 18 18 01 01 18 18 28 28 18 18 18 18 18 2F 2F 30 30 31 31 35 35 36 36 37 37 18 18 18 18 18 18 18 18 |
| 39 01 00 00 00 00 19 D8 AA AA AA AF EA AA AA AA AA AF EA AA AA AA AB AF EF AA AA AA AA AF EA AA |
| 39 01 00 00 00 00 02 BD 01 |
| 39 01 00 00 00 00 0D D8 AA AA AB AF EA AA AA AA AE AF EA AA |
| 39 01 00 00 00 00 02 BD 02 |
| 39 01 00 00 00 00 0D D8 AA AA AA AF EA AA AA AA AA AF EA AA |
| 39 01 00 00 00 00 02 BD 03 |
| 39 01 00 00 00 00 19 D8 BA AA AA AF EA AA AA AA AA AF EA AA BA AA AA AF EA AA AA AA AA AF EA AA |
| 39 01 00 00 00 00 02 BD 00 |
| 39 01 00 00 00 00 02 E9 E4 |
| 39 01 00 00 00 00 03 E7 17 69 |
| 39 01 00 00 00 00 02 E9 00 |
| 39 01 00 00 00 00 1A E7 09 09 00 07 E8 00 26 00 07 00 00 E8 32 00 E9 0A 0A 00 00 00 01 01 00 12 04 |
| 39 01 00 00 00 00 02 BD 01 |
| 39 01 00 00 00 00 0A E7 02 00 01 20 01 18 08 A8 09 |
| 39 01 00 00 00 00 02 BD 02 |
| 39 01 00 00 00 00 04 E7 20 20 00 |
| 39 01 00 00 00 00 02 BD 03 |
| 39 01 00 00 00 00 07 E7 00 DC 11 70 00 20 |
| 39 01 00 00 00 00 02 E9 C9 |
| 39 01 00 00 00 00 07 E7 2A CE 02 70 01 04 |
| 39 01 00 00 00 00 02 E9 00 |
| 39 01 00 00 00 00 02 BD 00 |
| 39 01 00 00 00 00 02 D1 27 |
| 05 01 00 00 78 00 02 11 00 |
| 05 01 00 00 14 00 02 29 00 |
| 39 01 00 00 00 00 03 51 00 00 |
| 39 01 00 00 00 00 02 53 24]; |
| //[Arima][8901][Jialong]LCM initial code from IC firmware End |
| qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 |
| 05 01 00 00 78 00 02 10 00]; |
| qcom,mdss-dsi-off-dstb-command = [ |
| 39 01 00 00 00 00 04 B9 83 11 2A |
| 39 01 00 00 00 00 02 BD 00 |
| 39 01 00 00 50 00 02 B1 09]; |
| qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; |
| qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; |
| qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; |
| qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; |
| qcom,mdss-dsi-tx-eot-append; |
| qcom,mdss-dsi-lp11-init; |
| qcom,mdss-dsi-post-init-delay = <1>; |
| }; |
| }; |