| * ARM System MMU Architecture Implementation |
| |
| ARM SoCs may contain an implementation of the ARM System Memory |
| Management Unit Architecture, which can be used to provide 1 or 2 stages |
| of address translation to bus masters external to the CPU. |
| |
| The SMMU may also raise interrupts in response to various fault |
| conditions. |
| |
| ** System MMU required properties: |
| |
| - compatible : Should be one of: |
| |
| "arm,smmu-v1" |
| "arm,smmu-v2" |
| "arm,mmu-400" |
| "arm,mmu-401" |
| "arm,mmu-500" |
| "cavium,smmu-v2" |
| "qcom,smmu-v2" |
| "qcom,qsmmu-v500" |
| |
| depending on the particular implementation and/or the |
| version of the architecture implemented. |
| |
| - reg : Base address and size of the SMMU. |
| |
| - #global-interrupts : The number of global interrupts exposed by the |
| device. |
| |
| - interrupts : Interrupt list, with the first #global-irqs entries |
| corresponding to the global interrupts and any |
| following entries corresponding to context interrupts, |
| specified in order of their indexing by the SMMU. |
| |
| For SMMUv2 implementations, there must be exactly one |
| interrupt per context bank. In the case of a single, |
| combined interrupt, it must be listed multiple times. |
| |
| - mmu-masters : A list of phandles to device nodes representing bus |
| masters for which the SMMU can provide a translation |
| and their corresponding StreamIDs (see example below). |
| Each device node linked from this list must have a |
| "#stream-id-cells" property, indicating the number of |
| StreamIDs associated with it. |
| |
| ** System MMU optional properties: |
| |
| - dma-coherent : Present if page table walks made by the SMMU are |
| cache coherent with the CPU. |
| |
| NOTE: this only applies to the SMMU itself, not |
| masters connected upstream of the SMMU. |
| |
| - calxeda,smmu-secure-config-access : Enable proper handling of buggy |
| implementations that always use secure access to |
| SMMU configuration registers. In this case non-secure |
| aliases of secure registers have to be used during |
| SMMU configuration. |
| |
| - attach-impl-defs : global registers to program at device attach |
| time. This should be a list of 2-tuples of the format: |
| <offset reg_value>. |
| |
| - qcom,fatal-asf : Enable BUG_ON for address size faults. Some hardware |
| requires special fixups to recover from address size |
| faults. Rather than applying the fixups just BUG since |
| address size faults are due to a fundamental programming |
| error from which we don't care about recovering anyways. |
| |
| - qcom,skip-init : Disable resetting configuration for all context banks |
| during device reset. This is useful for targets where |
| some context banks are dedicated to other execution |
| environments outside of Linux and those other EEs are |
| programming their own stream match tables, SCTLR, etc. |
| Without setting this option we will trample on their |
| configuration. |
| |
| - qcom,dynamic : Allow dynamic domains to be attached. This is only |
| useful if the upstream hardware is capable of switching |
| between multiple domains within a single context bank. |
| |
| - clocks : List of clocks to be used during SMMU register access. See |
| Documentation/devicetree/bindings/clock/clock-bindings.txt |
| for information about the format. For each clock specified |
| here, there must be a corresponding entry in clock-names |
| (see below). |
| |
| - clock-names : List of clock names corresponding to the clocks specified in |
| the "clocks" property (above). See |
| Documentation/devicetree/bindings/clock/clock-bindings.txt |
| for more info. |
| |
| - (%s)-supply : Phandle of the regulator that should be powered on during |
| SMMU register access. (%s) is a string from the |
| qcom,regulator-names property. |
| |
| - qcom,regulator-names : |
| List of strings to use with the (%s)-supply property. |
| |
| - qcom,msm-bus,name |
| - qcom,msm-bus,num-cases |
| - qcom,msm-bus,num-paths |
| - qcom,msm-bus,vectors-KBps |
| : Refer to devicetree/bindings/arm/msm/msm_bus.txt |
| |
| Example: |
| |
| smmu { |
| compatible = "arm,smmu-v1"; |
| reg = <0xba5e0000 0x10000>; |
| #global-interrupts = <2>; |
| interrupts = <0 32 4>, |
| <0 33 4>, |
| <0 34 4>, /* This is the first context interrupt */ |
| <0 35 4>, |
| <0 36 4>, |
| <0 37 4>; |
| |
| /* |
| * Two DMA controllers, the first with two StreamIDs (0xd01d |
| * and 0xd01e) and the second with only one (0xd11c). |
| */ |
| mmu-masters = <&dma0 0xd01d 0xd01e>, |
| <&dma1 0xd11c>; |
| |
| attach-impl-defs = <0x124 0x3>, |
| <0x128 0xa5>, |
| <0x12c 0x1>; |
| }; |
| |
| |
| * Qualcomm MMU-500 TBU Device |
| |
| The qcom,qsmmu-v500 device implements a number of register regions containing |
| debug functionality. Each register region maps to a separate tbu from the |
| arm mmu-500 implementation. |
| |
| ** TBU required properties: |
| |
| - compatible : Should be one of: |
| "qcom,qsmmuv500-tbu" |
| |
| - reg : Base address and size. |
| |
| - reg-names : "base" and "status-reg" are expected |
| "base" is the main TBU register region. |
| "status-reg" indicates whether hw can process a new request. |
| |
| |
| Example: |
| smmu { |
| compatible = "qcom,qsmmu-v500"; |
| tbu@0x1000 { |
| compatible = "qcom,qsmmuv500-tbu"; |
| regs = <0x1000 0x1000>, |
| <0x2000 0x8>; |
| reg-names = "base", |
| "status-reg"; |
| }; |
| }; |