Will Deacon | 98c33c5 | 2013-06-24 18:31:24 +0100 | [diff] [blame] | 1 | * ARM System MMU Architecture Implementation |
| 2 | |
| 3 | ARM SoCs may contain an implementation of the ARM System Memory |
| 4 | Management Unit Architecture, which can be used to provide 1 or 2 stages |
| 5 | of address translation to bus masters external to the CPU. |
| 6 | |
| 7 | The SMMU may also raise interrupts in response to various fault |
| 8 | conditions. |
| 9 | |
| 10 | ** System MMU required properties: |
| 11 | |
| 12 | - compatible : Should be one of: |
| 13 | |
| 14 | "arm,smmu-v1" |
| 15 | "arm,smmu-v2" |
| 16 | "arm,mmu-400" |
Robin Murphy | d3aba04 | 2014-08-28 17:52:00 +0100 | [diff] [blame] | 17 | "arm,mmu-401" |
Will Deacon | 98c33c5 | 2013-06-24 18:31:24 +0100 | [diff] [blame] | 18 | "arm,mmu-500" |
Tirumalesh Chalamarla | 1bd37a6 | 2016-03-04 13:56:09 -0800 | [diff] [blame] | 19 | "cavium,smmu-v2" |
Patrick Daly | f0d4e21 | 2016-06-20 15:50:14 -0700 | [diff] [blame] | 20 | "qcom,smmu-v2" |
Patrick Daly | 1f8a288 | 2016-09-12 17:32:05 -0700 | [diff] [blame] | 21 | "qcom,qsmmu-v500" |
Will Deacon | 98c33c5 | 2013-06-24 18:31:24 +0100 | [diff] [blame] | 22 | |
| 23 | depending on the particular implementation and/or the |
| 24 | version of the architecture implemented. |
| 25 | |
| 26 | - reg : Base address and size of the SMMU. |
| 27 | |
| 28 | - #global-interrupts : The number of global interrupts exposed by the |
| 29 | device. |
| 30 | |
| 31 | - interrupts : Interrupt list, with the first #global-irqs entries |
| 32 | corresponding to the global interrupts and any |
| 33 | following entries corresponding to context interrupts, |
| 34 | specified in order of their indexing by the SMMU. |
| 35 | |
| 36 | For SMMUv2 implementations, there must be exactly one |
| 37 | interrupt per context bank. In the case of a single, |
| 38 | combined interrupt, it must be listed multiple times. |
| 39 | |
| 40 | - mmu-masters : A list of phandles to device nodes representing bus |
| 41 | masters for which the SMMU can provide a translation |
| 42 | and their corresponding StreamIDs (see example below). |
| 43 | Each device node linked from this list must have a |
| 44 | "#stream-id-cells" property, indicating the number of |
| 45 | StreamIDs associated with it. |
| 46 | |
| 47 | ** System MMU optional properties: |
| 48 | |
Robin Murphy | bae2c2d | 2015-07-29 19:46:05 +0100 | [diff] [blame] | 49 | - dma-coherent : Present if page table walks made by the SMMU are |
| 50 | cache coherent with the CPU. |
| 51 | |
| 52 | NOTE: this only applies to the SMMU itself, not |
| 53 | masters connected upstream of the SMMU. |
| 54 | |
Andreas Herrmann | 0c9d70d | 2014-01-30 20:17:52 +0000 | [diff] [blame] | 55 | - calxeda,smmu-secure-config-access : Enable proper handling of buggy |
| 56 | implementations that always use secure access to |
| 57 | SMMU configuration registers. In this case non-secure |
| 58 | aliases of secure registers have to be used during |
| 59 | SMMU configuration. |
| 60 | |
Mitchel Humpherys | 5494a5e | 2014-08-14 17:44:49 -0700 | [diff] [blame] | 61 | - attach-impl-defs : global registers to program at device attach |
| 62 | time. This should be a list of 2-tuples of the format: |
| 63 | <offset reg_value>. |
| 64 | |
Mitchel Humpherys | 07ba44b | 2015-01-30 14:58:52 -0800 | [diff] [blame] | 65 | - qcom,fatal-asf : Enable BUG_ON for address size faults. Some hardware |
| 66 | requires special fixups to recover from address size |
| 67 | faults. Rather than applying the fixups just BUG since |
| 68 | address size faults are due to a fundamental programming |
| 69 | error from which we don't care about recovering anyways. |
| 70 | |
Mitchel Humpherys | 9c2f648 | 2015-01-13 15:28:40 -0800 | [diff] [blame] | 71 | - qcom,skip-init : Disable resetting configuration for all context banks |
| 72 | during device reset. This is useful for targets where |
| 73 | some context banks are dedicated to other execution |
| 74 | environments outside of Linux and those other EEs are |
| 75 | programming their own stream match tables, SCTLR, etc. |
| 76 | Without setting this option we will trample on their |
| 77 | configuration. |
| 78 | |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 79 | - qcom,dynamic : Allow dynamic domains to be attached. This is only |
| 80 | useful if the upstream hardware is capable of switching |
| 81 | between multiple domains within a single context bank. |
| 82 | |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 83 | - clocks : List of clocks to be used during SMMU register access. See |
| 84 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 85 | for information about the format. For each clock specified |
| 86 | here, there must be a corresponding entry in clock-names |
| 87 | (see below). |
| 88 | |
| 89 | - clock-names : List of clock names corresponding to the clocks specified in |
| 90 | the "clocks" property (above). See |
| 91 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 92 | for more info. |
| 93 | |
Patrick Daly | 5b3d8c6 | 2016-11-01 15:34:11 -0700 | [diff] [blame] | 94 | - (%s)-supply : Phandle of the regulator that should be powered on during |
| 95 | SMMU register access. (%s) is a string from the |
| 96 | qcom,regulator-names property. |
| 97 | |
| 98 | - qcom,regulator-names : |
| 99 | List of strings to use with the (%s)-supply property. |
Mitchel Humpherys | f7666ae | 2014-07-23 17:35:07 -0700 | [diff] [blame] | 100 | |
Patrick Daly | cf7b0de | 2016-10-06 17:04:49 -0700 | [diff] [blame] | 101 | - qcom,msm-bus,name |
| 102 | - qcom,msm-bus,num-cases |
| 103 | - qcom,msm-bus,num-paths |
| 104 | - qcom,msm-bus,vectors-KBps |
| 105 | : Refer to devicetree/bindings/arm/msm/msm_bus.txt |
Patrick Daly | 2764f95 | 2016-09-06 19:22:44 -0700 | [diff] [blame] | 106 | |
Will Deacon | 98c33c5 | 2013-06-24 18:31:24 +0100 | [diff] [blame] | 107 | Example: |
| 108 | |
| 109 | smmu { |
| 110 | compatible = "arm,smmu-v1"; |
| 111 | reg = <0xba5e0000 0x10000>; |
| 112 | #global-interrupts = <2>; |
| 113 | interrupts = <0 32 4>, |
| 114 | <0 33 4>, |
| 115 | <0 34 4>, /* This is the first context interrupt */ |
| 116 | <0 35 4>, |
| 117 | <0 36 4>, |
| 118 | <0 37 4>; |
| 119 | |
| 120 | /* |
| 121 | * Two DMA controllers, the first with two StreamIDs (0xd01d |
| 122 | * and 0xd01e) and the second with only one (0xd11c). |
| 123 | */ |
| 124 | mmu-masters = <&dma0 0xd01d 0xd01e>, |
| 125 | <&dma1 0xd11c>; |
Mitchel Humpherys | 5494a5e | 2014-08-14 17:44:49 -0700 | [diff] [blame] | 126 | |
| 127 | attach-impl-defs = <0x124 0x3>, |
| 128 | <0x128 0xa5>, |
| 129 | <0x12c 0x1>; |
Will Deacon | 98c33c5 | 2013-06-24 18:31:24 +0100 | [diff] [blame] | 130 | }; |
Patrick Daly | 1f8a288 | 2016-09-12 17:32:05 -0700 | [diff] [blame] | 131 | |
| 132 | |
| 133 | * Qualcomm MMU-500 TBU Device |
| 134 | |
| 135 | The qcom,qsmmu-v500 device implements a number of register regions containing |
| 136 | debug functionality. Each register region maps to a separate tbu from the |
| 137 | arm mmu-500 implementation. |
| 138 | |
| 139 | ** TBU required properties: |
| 140 | |
| 141 | - compatible : Should be one of: |
| 142 | "qcom,qsmmuv500-tbu" |
| 143 | |
| 144 | - reg : Base address and size. |
| 145 | |
| 146 | - reg-names : "base" and "status-reg" are expected |
| 147 | "base" is the main TBU register region. |
| 148 | "status-reg" indicates whether hw can process a new request. |
| 149 | |
| 150 | |
| 151 | Example: |
| 152 | smmu { |
| 153 | compatible = "qcom,qsmmu-v500"; |
| 154 | tbu@0x1000 { |
| 155 | compatible = "qcom,qsmmuv500-tbu"; |
| 156 | regs = <0x1000 0x1000>, |
| 157 | <0x2000 0x8>; |
| 158 | reg-names = "base", |
| 159 | "status-reg"; |
| 160 | }; |
| 161 | }; |