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Oder Chiou1319b2f2014-04-28 19:59:10 +08001/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
Oder Chiouf3fa1bb2014-09-19 19:15:45 +080020#include <linux/gpio.h>
Fang, Yang Abaf2a0e2015-04-27 15:54:30 -070021#include <linux/gpio/consumer.h>
Fang, Yang A3168c202015-04-23 16:35:17 -070022#include <linux/acpi.h>
Fang, Yang A78c34fd2015-04-24 17:50:54 -070023#include <linux/dmi.h>
Oder Chiou1319b2f2014-04-28 19:59:10 +080024#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/jack.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32
Oder Chiou49ef7922014-05-20 15:01:53 +080033#include "rl6231.h"
Oder Chiou1319b2f2014-04-28 19:59:10 +080034#include "rt5645.h"
35
36#define RT5645_DEVICE_ID 0x6308
Bard Liao5c4ca992015-01-21 20:50:15 +080037#define RT5650_DEVICE_ID 0x6419
Oder Chiou1319b2f2014-04-28 19:59:10 +080038
39#define RT5645_PR_RANGE_BASE (0xff + 1)
40#define RT5645_PR_SPACING 0x100
41
42#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
43
44static const struct regmap_range_cfg rt5645_ranges[] = {
45 {
46 .name = "PR",
47 .range_min = RT5645_PR_BASE,
48 .range_max = RT5645_PR_BASE + 0xf8,
49 .selector_reg = RT5645_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5645_PRIV_DATA,
53 .window_len = 0x1,
54 },
55};
56
57static const struct reg_default init_list[] = {
58 {RT5645_PR_BASE + 0x3d, 0x3600},
Oder Chiou4809b962014-05-08 14:47:36 +080059 {RT5645_PR_BASE + 0x1c, 0xfd20},
60 {RT5645_PR_BASE + 0x20, 0x611f},
61 {RT5645_PR_BASE + 0x21, 0x4040},
62 {RT5645_PR_BASE + 0x23, 0x0004},
Oder Chiou1319b2f2014-04-28 19:59:10 +080063};
64#define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
65
Bard Liao5c4ca992015-01-21 20:50:15 +080066static const struct reg_default rt5650_init_list[] = {
67 {0xf6, 0x0100},
68};
69
Oder Chiou1319b2f2014-04-28 19:59:10 +080070static const struct reg_default rt5645_reg[] = {
71 { 0x00, 0x0000 },
72 { 0x01, 0xc8c8 },
73 { 0x02, 0xc8c8 },
74 { 0x03, 0xc8c8 },
75 { 0x0a, 0x0002 },
76 { 0x0b, 0x2827 },
77 { 0x0c, 0xe000 },
78 { 0x0d, 0x0000 },
79 { 0x0e, 0x0000 },
80 { 0x0f, 0x0808 },
81 { 0x14, 0x3333 },
82 { 0x16, 0x4b00 },
83 { 0x18, 0x018b },
84 { 0x19, 0xafaf },
85 { 0x1a, 0xafaf },
86 { 0x1b, 0x0001 },
87 { 0x1c, 0x2f2f },
88 { 0x1d, 0x2f2f },
89 { 0x1e, 0x0000 },
90 { 0x20, 0x0000 },
91 { 0x27, 0x7060 },
92 { 0x28, 0x7070 },
93 { 0x29, 0x8080 },
94 { 0x2a, 0x5656 },
95 { 0x2b, 0x5454 },
96 { 0x2c, 0xaaa0 },
Bard Liao5c4ca992015-01-21 20:50:15 +080097 { 0x2d, 0x0000 },
Oder Chiou1319b2f2014-04-28 19:59:10 +080098 { 0x2f, 0x1002 },
99 { 0x31, 0x5000 },
100 { 0x32, 0x0000 },
101 { 0x33, 0x0000 },
102 { 0x34, 0x0000 },
103 { 0x35, 0x0000 },
104 { 0x3b, 0x0000 },
105 { 0x3c, 0x007f },
106 { 0x3d, 0x0000 },
107 { 0x3e, 0x007f },
108 { 0x3f, 0x0000 },
109 { 0x40, 0x001f },
110 { 0x41, 0x0000 },
111 { 0x42, 0x001f },
112 { 0x45, 0x6000 },
113 { 0x46, 0x003e },
114 { 0x47, 0x003e },
115 { 0x48, 0xf807 },
116 { 0x4a, 0x0004 },
117 { 0x4d, 0x0000 },
118 { 0x4e, 0x0000 },
119 { 0x4f, 0x01ff },
120 { 0x50, 0x0000 },
121 { 0x51, 0x0000 },
122 { 0x52, 0x01ff },
123 { 0x53, 0xf000 },
124 { 0x56, 0x0111 },
125 { 0x57, 0x0064 },
126 { 0x58, 0xef0e },
127 { 0x59, 0xf0f0 },
128 { 0x5a, 0xef0e },
129 { 0x5b, 0xf0f0 },
130 { 0x5c, 0xef0e },
131 { 0x5d, 0xf0f0 },
132 { 0x5e, 0xf000 },
133 { 0x5f, 0x0000 },
134 { 0x61, 0x0300 },
135 { 0x62, 0x0000 },
136 { 0x63, 0x00c2 },
137 { 0x64, 0x0000 },
138 { 0x65, 0x0000 },
139 { 0x66, 0x0000 },
140 { 0x6a, 0x0000 },
141 { 0x6c, 0x0aaa },
142 { 0x70, 0x8000 },
143 { 0x71, 0x8000 },
144 { 0x72, 0x8000 },
145 { 0x73, 0x7770 },
146 { 0x74, 0x3e00 },
147 { 0x75, 0x2409 },
148 { 0x76, 0x000a },
149 { 0x77, 0x0c00 },
150 { 0x78, 0x0000 },
Fang, Yang Adf078d22014-10-28 18:36:36 -0300151 { 0x79, 0x0123 },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800152 { 0x80, 0x0000 },
153 { 0x81, 0x0000 },
154 { 0x82, 0x0000 },
155 { 0x83, 0x0000 },
156 { 0x84, 0x0000 },
157 { 0x85, 0x0000 },
158 { 0x8a, 0x0000 },
159 { 0x8e, 0x0004 },
160 { 0x8f, 0x1100 },
161 { 0x90, 0x0646 },
162 { 0x91, 0x0c06 },
163 { 0x93, 0x0000 },
164 { 0x94, 0x0200 },
165 { 0x95, 0x0000 },
166 { 0x9a, 0x2184 },
167 { 0x9b, 0x010a },
168 { 0x9c, 0x0aea },
169 { 0x9d, 0x000c },
170 { 0x9e, 0x0400 },
171 { 0xa0, 0xa0a8 },
172 { 0xa1, 0x0059 },
173 { 0xa2, 0x0001 },
174 { 0xae, 0x6000 },
175 { 0xaf, 0x0000 },
176 { 0xb0, 0x6000 },
177 { 0xb1, 0x0000 },
178 { 0xb2, 0x0000 },
179 { 0xb3, 0x001f },
180 { 0xb4, 0x020c },
181 { 0xb5, 0x1f00 },
182 { 0xb6, 0x0000 },
183 { 0xbb, 0x0000 },
184 { 0xbc, 0x0000 },
185 { 0xbd, 0x0000 },
186 { 0xbe, 0x0000 },
187 { 0xbf, 0x3100 },
188 { 0xc0, 0x0000 },
189 { 0xc1, 0x0000 },
190 { 0xc2, 0x0000 },
191 { 0xc3, 0x2000 },
192 { 0xcd, 0x0000 },
193 { 0xce, 0x0000 },
194 { 0xcf, 0x1813 },
195 { 0xd0, 0x0690 },
196 { 0xd1, 0x1c17 },
197 { 0xd3, 0xb320 },
198 { 0xd4, 0x0000 },
199 { 0xd6, 0x0400 },
200 { 0xd9, 0x0809 },
201 { 0xda, 0x0000 },
202 { 0xdb, 0x0003 },
203 { 0xdc, 0x0049 },
204 { 0xdd, 0x001b },
Bard Liao5c4ca992015-01-21 20:50:15 +0800205 { 0xdf, 0x0008 },
206 { 0xe0, 0x4000 },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800207 { 0xe6, 0x8000 },
208 { 0xe7, 0x0200 },
209 { 0xec, 0xb300 },
210 { 0xed, 0x0000 },
211 { 0xf0, 0x001f },
212 { 0xf1, 0x020c },
213 { 0xf2, 0x1f00 },
214 { 0xf3, 0x0000 },
215 { 0xf4, 0x4000 },
216 { 0xf8, 0x0000 },
217 { 0xf9, 0x0000 },
218 { 0xfa, 0x2060 },
219 { 0xfb, 0x4040 },
220 { 0xfc, 0x0000 },
221 { 0xfd, 0x0002 },
222 { 0xfe, 0x10ec },
223 { 0xff, 0x6308 },
224};
225
226static int rt5645_reset(struct snd_soc_codec *codec)
227{
228 return snd_soc_write(codec, RT5645_RESET, 0);
229}
230
231static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
232{
233 int i;
234
235 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
236 if (reg >= rt5645_ranges[i].range_min &&
237 reg <= rt5645_ranges[i].range_max) {
238 return true;
239 }
240 }
241
242 switch (reg) {
243 case RT5645_RESET:
244 case RT5645_PRIV_DATA:
245 case RT5645_IN1_CTRL1:
246 case RT5645_IN1_CTRL2:
247 case RT5645_IN1_CTRL3:
248 case RT5645_A_JD_CTRL1:
249 case RT5645_ADC_EQ_CTRL1:
250 case RT5645_EQ_CTRL1:
251 case RT5645_ALC_CTRL_1:
252 case RT5645_IRQ_CTRL2:
253 case RT5645_IRQ_CTRL3:
254 case RT5645_INT_IRQ_ST:
255 case RT5645_IL_CMD:
Bard Liao5c4ca992015-01-21 20:50:15 +0800256 case RT5650_4BTN_IL_CMD1:
Oder Chiou1319b2f2014-04-28 19:59:10 +0800257 case RT5645_VENDOR_ID:
258 case RT5645_VENDOR_ID1:
259 case RT5645_VENDOR_ID2:
Oder Chiou71bfa9b2014-05-08 15:42:37 +0800260 return true;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800261 default:
Oder Chiou71bfa9b2014-05-08 15:42:37 +0800262 return false;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800263 }
264}
265
266static bool rt5645_readable_register(struct device *dev, unsigned int reg)
267{
268 int i;
269
270 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
271 if (reg >= rt5645_ranges[i].range_min &&
272 reg <= rt5645_ranges[i].range_max) {
273 return true;
274 }
275 }
276
277 switch (reg) {
278 case RT5645_RESET:
279 case RT5645_SPK_VOL:
280 case RT5645_HP_VOL:
281 case RT5645_LOUT1:
282 case RT5645_IN1_CTRL1:
283 case RT5645_IN1_CTRL2:
284 case RT5645_IN1_CTRL3:
285 case RT5645_IN2_CTRL:
286 case RT5645_INL1_INR1_VOL:
287 case RT5645_SPK_FUNC_LIM:
288 case RT5645_ADJ_HPF_CTRL:
289 case RT5645_DAC1_DIG_VOL:
290 case RT5645_DAC2_DIG_VOL:
291 case RT5645_DAC_CTRL:
292 case RT5645_STO1_ADC_DIG_VOL:
293 case RT5645_MONO_ADC_DIG_VOL:
294 case RT5645_ADC_BST_VOL1:
295 case RT5645_ADC_BST_VOL2:
296 case RT5645_STO1_ADC_MIXER:
297 case RT5645_MONO_ADC_MIXER:
298 case RT5645_AD_DA_MIXER:
299 case RT5645_STO_DAC_MIXER:
300 case RT5645_MONO_DAC_MIXER:
301 case RT5645_DIG_MIXER:
Bard Liao5c4ca992015-01-21 20:50:15 +0800302 case RT5650_A_DAC_SOUR:
Oder Chiou1319b2f2014-04-28 19:59:10 +0800303 case RT5645_DIG_INF1_DATA:
304 case RT5645_PDM_OUT_CTRL:
305 case RT5645_REC_L1_MIXER:
306 case RT5645_REC_L2_MIXER:
307 case RT5645_REC_R1_MIXER:
308 case RT5645_REC_R2_MIXER:
309 case RT5645_HPMIXL_CTRL:
310 case RT5645_HPOMIXL_CTRL:
311 case RT5645_HPMIXR_CTRL:
312 case RT5645_HPOMIXR_CTRL:
313 case RT5645_HPO_MIXER:
314 case RT5645_SPK_L_MIXER:
315 case RT5645_SPK_R_MIXER:
316 case RT5645_SPO_MIXER:
317 case RT5645_SPO_CLSD_RATIO:
318 case RT5645_OUT_L1_MIXER:
319 case RT5645_OUT_R1_MIXER:
320 case RT5645_OUT_L_GAIN1:
321 case RT5645_OUT_L_GAIN2:
322 case RT5645_OUT_R_GAIN1:
323 case RT5645_OUT_R_GAIN2:
324 case RT5645_LOUT_MIXER:
325 case RT5645_HAPTIC_CTRL1:
326 case RT5645_HAPTIC_CTRL2:
327 case RT5645_HAPTIC_CTRL3:
328 case RT5645_HAPTIC_CTRL4:
329 case RT5645_HAPTIC_CTRL5:
330 case RT5645_HAPTIC_CTRL6:
331 case RT5645_HAPTIC_CTRL7:
332 case RT5645_HAPTIC_CTRL8:
333 case RT5645_HAPTIC_CTRL9:
334 case RT5645_HAPTIC_CTRL10:
335 case RT5645_PWR_DIG1:
336 case RT5645_PWR_DIG2:
337 case RT5645_PWR_ANLG1:
338 case RT5645_PWR_ANLG2:
339 case RT5645_PWR_MIXER:
340 case RT5645_PWR_VOL:
341 case RT5645_PRIV_INDEX:
342 case RT5645_PRIV_DATA:
343 case RT5645_I2S1_SDP:
344 case RT5645_I2S2_SDP:
345 case RT5645_ADDA_CLK1:
346 case RT5645_ADDA_CLK2:
347 case RT5645_DMIC_CTRL1:
348 case RT5645_DMIC_CTRL2:
349 case RT5645_TDM_CTRL_1:
350 case RT5645_TDM_CTRL_2:
Fang, Yang Adf078d22014-10-28 18:36:36 -0300351 case RT5645_TDM_CTRL_3:
Oder Chiou1fcb76d2015-06-10 14:34:29 +0800352 case RT5650_TDM_CTRL_4:
Oder Chiou1319b2f2014-04-28 19:59:10 +0800353 case RT5645_GLB_CLK:
354 case RT5645_PLL_CTRL1:
355 case RT5645_PLL_CTRL2:
356 case RT5645_ASRC_1:
357 case RT5645_ASRC_2:
358 case RT5645_ASRC_3:
359 case RT5645_ASRC_4:
360 case RT5645_DEPOP_M1:
361 case RT5645_DEPOP_M2:
362 case RT5645_DEPOP_M3:
363 case RT5645_MICBIAS:
364 case RT5645_A_JD_CTRL1:
365 case RT5645_VAD_CTRL4:
366 case RT5645_CLSD_OUT_CTRL:
367 case RT5645_ADC_EQ_CTRL1:
368 case RT5645_ADC_EQ_CTRL2:
369 case RT5645_EQ_CTRL1:
370 case RT5645_EQ_CTRL2:
371 case RT5645_ALC_CTRL_1:
372 case RT5645_ALC_CTRL_2:
373 case RT5645_ALC_CTRL_3:
374 case RT5645_ALC_CTRL_4:
375 case RT5645_ALC_CTRL_5:
376 case RT5645_JD_CTRL:
377 case RT5645_IRQ_CTRL1:
378 case RT5645_IRQ_CTRL2:
379 case RT5645_IRQ_CTRL3:
380 case RT5645_INT_IRQ_ST:
381 case RT5645_GPIO_CTRL1:
382 case RT5645_GPIO_CTRL2:
383 case RT5645_GPIO_CTRL3:
384 case RT5645_BASS_BACK:
385 case RT5645_MP3_PLUS1:
386 case RT5645_MP3_PLUS2:
387 case RT5645_ADJ_HPF1:
388 case RT5645_ADJ_HPF2:
389 case RT5645_HP_CALIB_AMP_DET:
390 case RT5645_SV_ZCD1:
391 case RT5645_SV_ZCD2:
392 case RT5645_IL_CMD:
393 case RT5645_IL_CMD2:
394 case RT5645_IL_CMD3:
Bard Liao5c4ca992015-01-21 20:50:15 +0800395 case RT5650_4BTN_IL_CMD1:
396 case RT5650_4BTN_IL_CMD2:
Oder Chiou1319b2f2014-04-28 19:59:10 +0800397 case RT5645_DRC1_HL_CTRL1:
398 case RT5645_DRC2_HL_CTRL1:
399 case RT5645_ADC_MONO_HP_CTRL1:
400 case RT5645_ADC_MONO_HP_CTRL2:
401 case RT5645_DRC2_CTRL1:
402 case RT5645_DRC2_CTRL2:
403 case RT5645_DRC2_CTRL3:
404 case RT5645_DRC2_CTRL4:
405 case RT5645_DRC2_CTRL5:
406 case RT5645_JD_CTRL3:
407 case RT5645_JD_CTRL4:
408 case RT5645_GEN_CTRL1:
409 case RT5645_GEN_CTRL2:
410 case RT5645_GEN_CTRL3:
411 case RT5645_VENDOR_ID:
412 case RT5645_VENDOR_ID1:
413 case RT5645_VENDOR_ID2:
Oder Chiou71bfa9b2014-05-08 15:42:37 +0800414 return true;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800415 default:
Oder Chiou71bfa9b2014-05-08 15:42:37 +0800416 return false;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800417 }
418}
419
420static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
Bard Liao177e1e12015-04-30 18:18:47 +0800421static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800422static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
Bard Liao177e1e12015-04-30 18:18:47 +0800423static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800424static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
425
426/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
427static unsigned int bst_tlv[] = {
428 TLV_DB_RANGE_HEAD(7),
429 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
430 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
431 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
432 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
433 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
434 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
435 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
436};
437
Oder Chiou1319b2f2014-04-28 19:59:10 +0800438static const struct snd_kcontrol_new rt5645_snd_controls[] = {
439 /* Speaker Output Volume */
440 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
441 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
442 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
443 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
444
445 /* Headphone Output Volume */
Nicolas Boichat692768c2015-05-14 08:43:31 +0800446 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
Oder Chiou1319b2f2014-04-28 19:59:10 +0800447 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
Nicolas Boichat692768c2015-05-14 08:43:31 +0800448 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
Oder Chiou1319b2f2014-04-28 19:59:10 +0800449 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
450
451 /* OUTPUT Control */
452 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
453 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
454 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
455 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
456 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
457 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
458
459 /* DAC Digital Volume */
460 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
461 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
462 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
Bard Liao177e1e12015-04-30 18:18:47 +0800463 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
Oder Chiou1319b2f2014-04-28 19:59:10 +0800464 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
Bard Liao177e1e12015-04-30 18:18:47 +0800465 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
Oder Chiou1319b2f2014-04-28 19:59:10 +0800466
467 /* IN1/IN2 Control */
468 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
469 RT5645_BST_SFT1, 8, 0, bst_tlv),
470 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
471 RT5645_BST_SFT2, 8, 0, bst_tlv),
472
473 /* INL/INR Volume Control */
474 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
475 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
476
477 /* ADC Digital Volume Control */
478 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
479 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
480 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
Bard Liao177e1e12015-04-30 18:18:47 +0800481 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
Oder Chiou1319b2f2014-04-28 19:59:10 +0800482 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
483 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
484 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
Bard Liao177e1e12015-04-30 18:18:47 +0800485 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
Oder Chiou1319b2f2014-04-28 19:59:10 +0800486
487 /* ADC Boost Volume Control */
488 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1,
489 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
490 adc_bst_tlv),
491 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5645_ADC_BST_VOL1,
492 RT5645_STO2_ADC_L_BST_SFT, RT5645_STO2_ADC_R_BST_SFT, 3, 0,
493 adc_bst_tlv),
494
495 /* I2S2 function select */
496 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
497 1, 1),
Oder Chiou1319b2f2014-04-28 19:59:10 +0800498};
499
500/**
501 * set_dmic_clk - Set parameter of dmic.
502 *
503 * @w: DAPM widget.
504 * @kcontrol: The kcontrol of this widget.
505 * @event: Event id.
506 *
Oder Chiou1319b2f2014-04-28 19:59:10 +0800507 */
508static int set_dmic_clk(struct snd_soc_dapm_widget *w,
509 struct snd_kcontrol *kcontrol, int event)
510{
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +0100511 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800512 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
Oder Chiou00a6d6e52015-08-05 10:03:18 +0800513 int idx, rate;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800514
Oder Chiou00a6d6e52015-08-05 10:03:18 +0800515 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap,
516 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT);
517 idx = rl6231_calc_dmic_clk(rate);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800518 if (idx < 0)
519 dev_err(codec->dev, "Failed to set DMIC clock\n");
520 else
521 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
522 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
523 return idx;
524}
525
526static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
527 struct snd_soc_dapm_widget *sink)
528{
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +0100529 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800530 unsigned int val;
531
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +0100532 val = snd_soc_read(codec, RT5645_GLB_CLK);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800533 val &= RT5645_SCLK_SRC_MASK;
534 if (val == RT5645_SCLK_SRC_PLL1)
535 return 1;
536 else
537 return 0;
538}
539
Bard Liao9e268352014-10-31 15:37:55 +0800540static int is_using_asrc(struct snd_soc_dapm_widget *source,
541 struct snd_soc_dapm_widget *sink)
542{
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +0100543 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
Bard Liao9e268352014-10-31 15:37:55 +0800544 unsigned int reg, shift, val;
545
546 switch (source->shift) {
547 case 0:
548 reg = RT5645_ASRC_3;
549 shift = 0;
550 break;
551 case 1:
552 reg = RT5645_ASRC_3;
553 shift = 4;
554 break;
555 case 3:
556 reg = RT5645_ASRC_2;
557 shift = 0;
558 break;
559 case 8:
560 reg = RT5645_ASRC_2;
561 shift = 4;
562 break;
563 case 9:
564 reg = RT5645_ASRC_2;
565 shift = 8;
566 break;
567 case 10:
568 reg = RT5645_ASRC_2;
569 shift = 12;
570 break;
571 default:
572 return 0;
573 }
574
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +0100575 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
Bard Liao9e268352014-10-31 15:37:55 +0800576 switch (val) {
577 case 1:
578 case 2:
579 case 3:
580 case 4:
581 return 1;
582 default:
583 return 0;
584 }
585
586}
587
Fang, Yang A79080a82015-02-04 18:19:31 -0800588/**
589 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
590 * @codec: SoC audio codec device.
591 * @filter_mask: mask of filters.
592 * @clk_src: clock source
593 *
594 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
595 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
596 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
597 * ASRC function will track i2s clock and generate a corresponding system clock
598 * for codec. This function provides an API to select the clock source for a
599 * set of filters specified by the mask. And the codec driver will turn on ASRC
600 * for these filters if ASRC is selected as their clock source.
601 */
602int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
603 unsigned int filter_mask, unsigned int clk_src)
604{
605 unsigned int asrc2_mask = 0;
606 unsigned int asrc2_value = 0;
607 unsigned int asrc3_mask = 0;
608 unsigned int asrc3_value = 0;
609
610 switch (clk_src) {
611 case RT5645_CLK_SEL_SYS:
612 case RT5645_CLK_SEL_I2S1_ASRC:
613 case RT5645_CLK_SEL_I2S2_ASRC:
614 case RT5645_CLK_SEL_SYS2:
615 break;
616
617 default:
618 return -EINVAL;
619 }
620
621 if (filter_mask & RT5645_DA_STEREO_FILTER) {
622 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
623 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
624 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
625 }
626
627 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
628 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
629 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
630 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
631 }
632
633 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
634 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
635 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
636 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
637 }
638
639 if (filter_mask & RT5645_AD_STEREO_FILTER) {
640 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
641 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
642 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
643 }
644
645 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
646 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
647 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
648 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
649 }
650
651 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
652 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
653 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
654 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
655 }
656
657 if (asrc2_mask)
658 snd_soc_update_bits(codec, RT5645_ASRC_2,
659 asrc2_mask, asrc2_value);
660
661 if (asrc3_mask)
662 snd_soc_update_bits(codec, RT5645_ASRC_3,
663 asrc3_mask, asrc3_value);
664
665 return 0;
666}
667EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
668
Oder Chiou1319b2f2014-04-28 19:59:10 +0800669/* Digital Mixer */
670static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
671 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
672 RT5645_M_ADC_L1_SFT, 1, 1),
673 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
674 RT5645_M_ADC_L2_SFT, 1, 1),
675};
676
677static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
678 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
679 RT5645_M_ADC_R1_SFT, 1, 1),
680 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
681 RT5645_M_ADC_R2_SFT, 1, 1),
682};
683
684static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
685 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
686 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
687 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
688 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
689};
690
691static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
692 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
693 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
694 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
695 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
696};
697
698static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
699 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
700 RT5645_M_ADCMIX_L_SFT, 1, 1),
701 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
702 RT5645_M_DAC1_L_SFT, 1, 1),
703};
704
705static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
706 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
707 RT5645_M_ADCMIX_R_SFT, 1, 1),
708 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
709 RT5645_M_DAC1_R_SFT, 1, 1),
710};
711
712static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
713 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
714 RT5645_M_DAC_L1_SFT, 1, 1),
715 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
716 RT5645_M_DAC_L2_SFT, 1, 1),
717 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
718 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
719};
720
721static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
722 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
723 RT5645_M_DAC_R1_SFT, 1, 1),
724 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
725 RT5645_M_DAC_R2_SFT, 1, 1),
726 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
727 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
728};
729
730static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
731 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
732 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
733 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
734 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
735 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
736 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
737};
738
739static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
740 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
741 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
742 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
743 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
744 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
745 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
746};
747
748static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
749 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
750 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
751 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
752 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
753 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
754 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
755};
756
757static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
758 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
759 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
760 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
761 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
762 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
763 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
764};
765
766/* Analog Input Mixer */
767static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
768 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
769 RT5645_M_HP_L_RM_L_SFT, 1, 1),
770 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
771 RT5645_M_IN_L_RM_L_SFT, 1, 1),
772 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
773 RT5645_M_BST2_RM_L_SFT, 1, 1),
774 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
775 RT5645_M_BST1_RM_L_SFT, 1, 1),
776 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
777 RT5645_M_OM_L_RM_L_SFT, 1, 1),
778};
779
780static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
781 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
782 RT5645_M_HP_R_RM_R_SFT, 1, 1),
783 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
784 RT5645_M_IN_R_RM_R_SFT, 1, 1),
785 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
786 RT5645_M_BST2_RM_R_SFT, 1, 1),
787 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
788 RT5645_M_BST1_RM_R_SFT, 1, 1),
789 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
790 RT5645_M_OM_R_RM_R_SFT, 1, 1),
791};
792
793static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
794 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
795 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
796 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
797 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
798 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
799 RT5645_M_IN_L_SM_L_SFT, 1, 1),
800 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
801 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
802};
803
804static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
805 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
806 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
807 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
808 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
809 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
810 RT5645_M_IN_R_SM_R_SFT, 1, 1),
811 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
812 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
813};
814
815static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
816 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
817 RT5645_M_BST1_OM_L_SFT, 1, 1),
818 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
819 RT5645_M_IN_L_OM_L_SFT, 1, 1),
820 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
821 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
822 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
823 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
824};
825
826static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
827 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
828 RT5645_M_BST2_OM_R_SFT, 1, 1),
829 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
830 RT5645_M_IN_R_OM_R_SFT, 1, 1),
831 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
832 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
833 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
834 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
835};
836
837static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
838 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
839 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
840 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
841 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
842 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
843 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
844 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
845 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
846};
847
848static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
849 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
850 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
851 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
852 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
853};
854
855static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
856 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
857 RT5645_M_DAC1_HM_SFT, 1, 1),
858 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
859 RT5645_M_HPVOL_HM_SFT, 1, 1),
860};
861
862static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
863 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
864 RT5645_M_DAC1_HV_SFT, 1, 1),
865 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
866 RT5645_M_DAC2_HV_SFT, 1, 1),
867 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
868 RT5645_M_IN_HV_SFT, 1, 1),
869 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
870 RT5645_M_BST1_HV_SFT, 1, 1),
871};
872
873static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
874 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
875 RT5645_M_DAC1_HV_SFT, 1, 1),
876 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
877 RT5645_M_DAC2_HV_SFT, 1, 1),
878 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
879 RT5645_M_IN_HV_SFT, 1, 1),
880 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
881 RT5645_M_BST2_HV_SFT, 1, 1),
882};
883
884static const struct snd_kcontrol_new rt5645_lout_mix[] = {
885 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
886 RT5645_M_DAC_L1_LM_SFT, 1, 1),
887 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
888 RT5645_M_DAC_R1_LM_SFT, 1, 1),
889 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
890 RT5645_M_OV_L_LM_SFT, 1, 1),
891 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
892 RT5645_M_OV_R_LM_SFT, 1, 1),
893};
894
895/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
896static const char * const rt5645_dac1_src[] = {
897 "IF1 DAC", "IF2 DAC", "IF3 DAC"
898};
899
900static SOC_ENUM_SINGLE_DECL(
901 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
902 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
903
904static const struct snd_kcontrol_new rt5645_dac1l_mux =
905 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
906
907static SOC_ENUM_SINGLE_DECL(
908 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
909 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
910
911static const struct snd_kcontrol_new rt5645_dac1r_mux =
912 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
913
914/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
915static const char * const rt5645_dac12_src[] = {
916 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
917};
918
919static SOC_ENUM_SINGLE_DECL(
920 rt5645_dac2l_enum, RT5645_DAC_CTRL,
921 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
922
923static const struct snd_kcontrol_new rt5645_dac_l2_mux =
924 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
925
926static const char * const rt5645_dacr2_src[] = {
927 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
928};
929
930static SOC_ENUM_SINGLE_DECL(
931 rt5645_dac2r_enum, RT5645_DAC_CTRL,
932 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
933
934static const struct snd_kcontrol_new rt5645_dac_r2_mux =
935 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
936
937
938/* INL/R source */
939static const char * const rt5645_inl_src[] = {
940 "IN2P", "MonoP"
941};
942
943static SOC_ENUM_SINGLE_DECL(
944 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
945 RT5645_INL_SEL_SFT, rt5645_inl_src);
946
947static const struct snd_kcontrol_new rt5645_inl_mux =
948 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
949
950static const char * const rt5645_inr_src[] = {
951 "IN2N", "MonoN"
952};
953
954static SOC_ENUM_SINGLE_DECL(
955 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
956 RT5645_INR_SEL_SFT, rt5645_inr_src);
957
958static const struct snd_kcontrol_new rt5645_inr_mux =
959 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
960
961/* Stereo1 ADC source */
962/* MX-27 [12] */
963static const char * const rt5645_stereo_adc1_src[] = {
964 "DAC MIX", "ADC"
965};
966
967static SOC_ENUM_SINGLE_DECL(
968 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
969 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
970
971static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
972 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
973
974/* MX-27 [11] */
975static const char * const rt5645_stereo_adc2_src[] = {
976 "DAC MIX", "DMIC"
977};
978
979static SOC_ENUM_SINGLE_DECL(
980 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
981 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
982
983static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
984 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
985
986/* MX-27 [8] */
987static const char * const rt5645_stereo_dmic_src[] = {
988 "DMIC1", "DMIC2"
989};
990
991static SOC_ENUM_SINGLE_DECL(
992 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
993 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
994
995static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
996 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
997
998/* Mono ADC source */
999/* MX-28 [12] */
1000static const char * const rt5645_mono_adc_l1_src[] = {
1001 "Mono DAC MIXL", "ADC"
1002};
1003
1004static SOC_ENUM_SINGLE_DECL(
1005 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1006 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1007
1008static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1009 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1010/* MX-28 [11] */
1011static const char * const rt5645_mono_adc_l2_src[] = {
1012 "Mono DAC MIXL", "DMIC"
1013};
1014
1015static SOC_ENUM_SINGLE_DECL(
1016 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1017 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1018
1019static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1020 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1021
1022/* MX-28 [8] */
1023static const char * const rt5645_mono_dmic_src[] = {
1024 "DMIC1", "DMIC2"
1025};
1026
1027static SOC_ENUM_SINGLE_DECL(
1028 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1029 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1030
1031static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1032 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1033/* MX-28 [1:0] */
1034static SOC_ENUM_SINGLE_DECL(
1035 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1036 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1037
1038static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1039 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1040/* MX-28 [4] */
1041static const char * const rt5645_mono_adc_r1_src[] = {
1042 "Mono DAC MIXR", "ADC"
1043};
1044
1045static SOC_ENUM_SINGLE_DECL(
1046 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1047 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1048
1049static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1050 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1051/* MX-28 [3] */
1052static const char * const rt5645_mono_adc_r2_src[] = {
1053 "Mono DAC MIXR", "DMIC"
1054};
1055
1056static SOC_ENUM_SINGLE_DECL(
1057 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1058 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1059
1060static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1061 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1062
1063/* MX-77 [9:8] */
1064static const char * const rt5645_if1_adc_in_src[] = {
Bard Liao21ab3f22015-04-30 18:18:44 +08001065 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1066 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
Oder Chiou1319b2f2014-04-28 19:59:10 +08001067};
1068
1069static SOC_ENUM_SINGLE_DECL(
1070 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1071 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1072
1073static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1074 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1075
Bard Liao21ab3f22015-04-30 18:18:44 +08001076/* MX-78 [4:0] */
1077static const char * const rt5650_if1_adc_in_src[] = {
1078 "IF_ADC1/IF_ADC2/DAC_REF/Null",
1079 "IF_ADC1/IF_ADC2/Null/DAC_REF",
1080 "IF_ADC1/DAC_REF/IF_ADC2/Null",
1081 "IF_ADC1/DAC_REF/Null/IF_ADC2",
1082 "IF_ADC1/Null/DAC_REF/IF_ADC2",
1083 "IF_ADC1/Null/IF_ADC2/DAC_REF",
1084
1085 "IF_ADC2/IF_ADC1/DAC_REF/Null",
1086 "IF_ADC2/IF_ADC1/Null/DAC_REF",
1087 "IF_ADC2/DAC_REF/IF_ADC1/Null",
1088 "IF_ADC2/DAC_REF/Null/IF_ADC1",
1089 "IF_ADC2/Null/DAC_REF/IF_ADC1",
1090 "IF_ADC2/Null/IF_ADC1/DAC_REF",
1091
1092 "DAC_REF/IF_ADC1/IF_ADC2/Null",
1093 "DAC_REF/IF_ADC1/Null/IF_ADC2",
1094 "DAC_REF/IF_ADC2/IF_ADC1/Null",
1095 "DAC_REF/IF_ADC2/Null/IF_ADC1",
1096 "DAC_REF/Null/IF_ADC1/IF_ADC2",
1097 "DAC_REF/Null/IF_ADC2/IF_ADC1",
1098
1099 "Null/IF_ADC1/IF_ADC2/DAC_REF",
1100 "Null/IF_ADC1/DAC_REF/IF_ADC2",
1101 "Null/IF_ADC2/IF_ADC1/DAC_REF",
1102 "Null/IF_ADC2/DAC_REF/IF_ADC1",
1103 "Null/DAC_REF/IF_ADC1/IF_ADC2",
1104 "Null/DAC_REF/IF_ADC2/IF_ADC1",
1105};
1106
1107static SOC_ENUM_SINGLE_DECL(
1108 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1109 0, rt5650_if1_adc_in_src);
1110
1111static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1112 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1113
1114/* MX-78 [15:14][13:12][11:10] */
1115static const char * const rt5645_tdm_adc_swap_select[] = {
1116 "L/R", "R/L", "L/L", "R/R"
1117};
1118
1119static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1120 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1121
1122static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1123 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1124
1125static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1126 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1127
1128static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1129 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1130
1131static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1132 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1133
1134static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1135 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1136
1137/* MX-77 [7:6][5:4][3:2] */
1138static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1139 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1140
1141static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1142 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1143
1144static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1145 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1146
1147static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1148 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1149
1150static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1151 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1152
1153static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1154 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1155
1156/* MX-79 [14:12][10:8][6:4][2:0] */
1157static const char * const rt5645_tdm_dac_swap_select[] = {
1158 "Slot0", "Slot1", "Slot2", "Slot3"
1159};
1160
1161static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1162 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1163
1164static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1165 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1166
1167static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1168 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1169
1170static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1171 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1172
1173static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1174 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1175
1176static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1177 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1178
1179static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1180 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1181
1182static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1183 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1184
1185/* MX-7a [14:12][10:8][6:4][2:0] */
1186static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1187 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1188
1189static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1190 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1191
1192static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1193 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1194
1195static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1196 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1197
1198static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1199 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1200
1201static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1202 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1203
1204static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1205 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1206
1207static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1208 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1209
Bard Liao5c4ca992015-01-21 20:50:15 +08001210/* MX-2d [3] [2] */
1211static const char * const rt5650_a_dac1_src[] = {
1212 "DAC1", "Stereo DAC Mixer"
1213};
1214
1215static SOC_ENUM_SINGLE_DECL(
1216 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1217 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1218
1219static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1220 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1221
1222static SOC_ENUM_SINGLE_DECL(
1223 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1224 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1225
1226static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1227 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1228
1229/* MX-2d [1] [0] */
1230static const char * const rt5650_a_dac2_src[] = {
1231 "Stereo DAC Mixer", "Mono DAC Mixer"
1232};
1233
1234static SOC_ENUM_SINGLE_DECL(
1235 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1236 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1237
1238static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1239 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1240
1241static SOC_ENUM_SINGLE_DECL(
1242 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1243 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1244
1245static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1246 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1247
Oder Chiou1319b2f2014-04-28 19:59:10 +08001248/* MX-2F [13:12] */
1249static const char * const rt5645_if2_adc_in_src[] = {
1250 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1251};
1252
1253static SOC_ENUM_SINGLE_DECL(
1254 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1255 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1256
1257static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1258 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1259
1260/* MX-2F [1:0] */
1261static const char * const rt5645_if3_adc_in_src[] = {
1262 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1263};
1264
1265static SOC_ENUM_SINGLE_DECL(
1266 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
1267 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
1268
1269static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
1270 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
1271
1272/* MX-31 [15] [13] [11] [9] */
1273static const char * const rt5645_pdm_src[] = {
1274 "Mono DAC", "Stereo DAC"
1275};
1276
1277static SOC_ENUM_SINGLE_DECL(
1278 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1279 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1280
1281static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1282 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1283
1284static SOC_ENUM_SINGLE_DECL(
1285 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1286 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1287
1288static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1289 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1290
1291/* MX-9D [9:8] */
1292static const char * const rt5645_vad_adc_src[] = {
1293 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1294};
1295
1296static SOC_ENUM_SINGLE_DECL(
1297 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1298 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1299
1300static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1301 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1302
1303static const struct snd_kcontrol_new spk_l_vol_control =
1304 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1305 RT5645_L_MUTE_SFT, 1, 1);
1306
1307static const struct snd_kcontrol_new spk_r_vol_control =
1308 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1309 RT5645_R_MUTE_SFT, 1, 1);
1310
1311static const struct snd_kcontrol_new hp_l_vol_control =
1312 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1313 RT5645_L_MUTE_SFT, 1, 1);
1314
1315static const struct snd_kcontrol_new hp_r_vol_control =
1316 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1317 RT5645_R_MUTE_SFT, 1, 1);
1318
1319static const struct snd_kcontrol_new pdm1_l_vol_control =
1320 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1321 RT5645_M_PDM1_L, 1, 1);
1322
1323static const struct snd_kcontrol_new pdm1_r_vol_control =
1324 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1325 RT5645_M_PDM1_R, 1, 1);
1326
1327static void hp_amp_power(struct snd_soc_codec *codec, int on)
1328{
1329 static int hp_amp_power_count;
1330 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1331
1332 if (on) {
1333 if (hp_amp_power_count <= 0) {
John Lind12d6c42015-05-12 20:43:02 +08001334 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1335 snd_soc_write(codec, RT5645_CHARGE_PUMP,
1336 0x0e06);
1337 snd_soc_write(codec, RT5645_DEPOP_M1, 0x001d);
1338 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1339 0x3e, 0x7400);
1340 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1341 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1342 RT5645_MAMP_INT_REG2, 0xfc00);
1343 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1344 } else {
1345 /* depop parameters */
1346 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1347 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1348 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1349 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1350 RT5645_HP_DCC_INT1, 0x9f01);
1351 mdelay(150);
1352 /* headphone amp power on */
1353 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1354 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1355 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1356 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1357 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1358 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1359 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1360 RT5645_PWR_HA,
1361 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1362 RT5645_PWR_HA);
1363 mdelay(5);
1364 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1365 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1366 RT5645_PWR_FV1 | RT5645_PWR_FV2);
Oder Chiou1319b2f2014-04-28 19:59:10 +08001367
John Lind12d6c42015-05-12 20:43:02 +08001368 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1369 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1370 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1371 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1372 0x14, 0x1aaa);
1373 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1374 0x24, 0x0430);
1375 }
Oder Chiou1319b2f2014-04-28 19:59:10 +08001376 }
1377 hp_amp_power_count++;
1378 } else {
1379 hp_amp_power_count--;
1380 if (hp_amp_power_count <= 0) {
John Lind12d6c42015-05-12 20:43:02 +08001381 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1382 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1383 0x3e, 0x7400);
1384 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1385 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1386 RT5645_MAMP_INT_REG2, 0xfc00);
1387 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1388 msleep(100);
1389 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001);
1390
1391 } else {
1392 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1393 RT5645_HP_SG_MASK |
1394 RT5645_HP_L_SMT_MASK |
1395 RT5645_HP_R_SMT_MASK,
1396 RT5645_HP_SG_DIS |
1397 RT5645_HP_L_SMT_DIS |
1398 RT5645_HP_R_SMT_DIS);
1399 /* headphone amp power down */
1400 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1401 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1402 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1403 RT5645_PWR_HA, 0);
1404 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1405 RT5645_DEPOP_MASK, 0);
1406 }
Oder Chiou1319b2f2014-04-28 19:59:10 +08001407 }
1408 }
1409}
1410
1411static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1412 struct snd_kcontrol *kcontrol, int event)
1413{
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +01001414 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Oder Chiou1319b2f2014-04-28 19:59:10 +08001415 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1416
1417 switch (event) {
1418 case SND_SOC_DAPM_POST_PMU:
1419 hp_amp_power(codec, 1);
1420 /* headphone unmute sequence */
John Lind12d6c42015-05-12 20:43:02 +08001421 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
Bard Liao5c4ca992015-01-21 20:50:15 +08001422 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1423 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1424 RT5645_CP_FQ3_MASK,
1425 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1426 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1427 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
John Lind12d6c42015-05-12 20:43:02 +08001428 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1429 RT5645_MAMP_INT_REG2, 0xfc00);
1430 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1431 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1432 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1433 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1434 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1435 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1436 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1437 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1438 msleep(40);
1439 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1440 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1441 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1442 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
Bard Liao5c4ca992015-01-21 20:50:15 +08001443 }
Oder Chiou1319b2f2014-04-28 19:59:10 +08001444 break;
1445
1446 case SND_SOC_DAPM_PRE_PMD:
1447 /* headphone mute sequence */
John Lind12d6c42015-05-12 20:43:02 +08001448 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
Bard Liao5c4ca992015-01-21 20:50:15 +08001449 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1450 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1451 RT5645_CP_FQ3_MASK,
1452 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1453 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1454 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
John Lind12d6c42015-05-12 20:43:02 +08001455 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1456 RT5645_MAMP_INT_REG2, 0xfc00);
1457 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1458 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1459 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1460 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1461 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1462 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1463 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1464 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1465 msleep(30);
Bard Liao5c4ca992015-01-21 20:50:15 +08001466 }
Oder Chiou1319b2f2014-04-28 19:59:10 +08001467 hp_amp_power(codec, 0);
1468 break;
1469
1470 default:
1471 return 0;
1472 }
1473
1474 return 0;
1475}
1476
1477static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1478 struct snd_kcontrol *kcontrol, int event)
1479{
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +01001480 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Oder Chiou1319b2f2014-04-28 19:59:10 +08001481
1482 switch (event) {
1483 case SND_SOC_DAPM_POST_PMU:
1484 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1485 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1486 RT5645_PWR_CLS_D_L,
1487 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1488 RT5645_PWR_CLS_D_L);
1489 break;
1490
1491 case SND_SOC_DAPM_PRE_PMD:
1492 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1493 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1494 RT5645_PWR_CLS_D_L, 0);
1495 break;
1496
1497 default:
1498 return 0;
1499 }
1500
1501 return 0;
1502}
1503
1504static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1505 struct snd_kcontrol *kcontrol, int event)
1506{
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +01001507 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Oder Chiou1319b2f2014-04-28 19:59:10 +08001508
1509 switch (event) {
1510 case SND_SOC_DAPM_POST_PMU:
1511 hp_amp_power(codec, 1);
1512 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1513 RT5645_PWR_LM, RT5645_PWR_LM);
1514 snd_soc_update_bits(codec, RT5645_LOUT1,
1515 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1516 break;
1517
1518 case SND_SOC_DAPM_PRE_PMD:
1519 snd_soc_update_bits(codec, RT5645_LOUT1,
1520 RT5645_L_MUTE | RT5645_R_MUTE,
1521 RT5645_L_MUTE | RT5645_R_MUTE);
1522 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1523 RT5645_PWR_LM, 0);
1524 hp_amp_power(codec, 0);
1525 break;
1526
1527 default:
1528 return 0;
1529 }
1530
1531 return 0;
1532}
1533
1534static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1535 struct snd_kcontrol *kcontrol, int event)
1536{
Lars-Peter Clausenc5f596c2015-01-15 12:52:13 +01001537 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
Oder Chiou1319b2f2014-04-28 19:59:10 +08001538
1539 switch (event) {
1540 case SND_SOC_DAPM_POST_PMU:
1541 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1542 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1543 break;
1544
1545 case SND_SOC_DAPM_PRE_PMD:
1546 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1547 RT5645_PWR_BST2_P, 0);
1548 break;
1549
1550 default:
1551 return 0;
1552 }
1553
1554 return 0;
1555}
1556
1557static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1558 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1559 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1560 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1561 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1562
1563 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1564 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1565 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1566 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1567
Bard Liao9e268352014-10-31 15:37:55 +08001568 /* ASRC */
1569 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1570 11, 0, NULL, 0),
1571 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1572 12, 0, NULL, 0),
1573 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1574 10, 0, NULL, 0),
1575 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1576 9, 0, NULL, 0),
1577 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1578 8, 0, NULL, 0),
1579 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1580 7, 0, NULL, 0),
1581 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1582 5, 0, NULL, 0),
1583 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1584 4, 0, NULL, 0),
1585 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1586 3, 0, NULL, 0),
1587 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1588 1, 0, NULL, 0),
1589 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1590 0, 0, NULL, 0),
1591
Oder Chiou1319b2f2014-04-28 19:59:10 +08001592 /* Input Side */
1593 /* micbias */
1594 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1595 RT5645_PWR_MB1_BIT, 0),
1596 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1597 RT5645_PWR_MB2_BIT, 0),
1598 /* Input Lines */
1599 SND_SOC_DAPM_INPUT("DMIC L1"),
1600 SND_SOC_DAPM_INPUT("DMIC R1"),
1601 SND_SOC_DAPM_INPUT("DMIC L2"),
1602 SND_SOC_DAPM_INPUT("DMIC R2"),
1603
1604 SND_SOC_DAPM_INPUT("IN1P"),
1605 SND_SOC_DAPM_INPUT("IN1N"),
1606 SND_SOC_DAPM_INPUT("IN2P"),
1607 SND_SOC_DAPM_INPUT("IN2N"),
1608
1609 SND_SOC_DAPM_INPUT("Haptic Generator"),
1610
1611 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1612 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1613 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1614 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1615 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1616 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1617 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1618 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1619 /* Boost */
1620 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1621 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1622 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1623 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1624 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1625 /* Input Volume */
1626 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1627 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1628 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1629 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1630 /* REC Mixer */
1631 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1632 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1633 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1634 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1635 /* ADCs */
1636 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1637 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1638
1639 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1640 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
1641 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
1642 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
1643
1644 /* ADC Mux */
1645 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1646 &rt5645_sto1_dmic_mux),
1647 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1648 &rt5645_sto_adc2_mux),
1649 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1650 &rt5645_sto_adc2_mux),
1651 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1652 &rt5645_sto_adc1_mux),
1653 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1654 &rt5645_sto_adc1_mux),
1655 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1656 &rt5645_mono_dmic_l_mux),
1657 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1658 &rt5645_mono_dmic_r_mux),
1659 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1660 &rt5645_mono_adc_l2_mux),
1661 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1662 &rt5645_mono_adc_l1_mux),
1663 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1664 &rt5645_mono_adc_r1_mux),
1665 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1666 &rt5645_mono_adc_r2_mux),
1667 /* ADC Mixer */
1668
1669 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
1670 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
Oder Chiou1319b2f2014-04-28 19:59:10 +08001671 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1672 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
1673 NULL, 0),
1674 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1675 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
1676 NULL, 0),
1677 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
1678 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1679 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1680 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
1681 NULL, 0),
1682 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
1683 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1684 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1685 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
1686 NULL, 0),
1687
1688 /* ADC PGA */
1689 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1690 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1691 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1692 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1693 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1694 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1695 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1696 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1697 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1698 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1699
1700 /* IF1 2 Mux */
Bard Liao21ab3f22015-04-30 18:18:44 +08001701 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
1702 0, 0, &rt5645_if1_adc1_in_mux),
1703 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
1704 0, 0, &rt5645_if1_adc2_in_mux),
1705 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
1706 0, 0, &rt5645_if1_adc3_in_mux),
1707 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
Oder Chiou1319b2f2014-04-28 19:59:10 +08001708 0, 0, &rt5645_if1_adc_in_mux),
Bard Liao21ab3f22015-04-30 18:18:44 +08001709
Oder Chiou1319b2f2014-04-28 19:59:10 +08001710 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1711 0, 0, &rt5645_if2_adc_in_mux),
1712
1713 /* Digital Interface */
1714 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1715 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
Bard Liao786aa092015-05-05 21:42:00 +08001716 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
Oder Chiou1319b2f2014-04-28 19:59:10 +08001717 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1718 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
Bard Liao786aa092015-05-05 21:42:00 +08001719 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
Bard Liao21ab3f22015-04-30 18:18:44 +08001720 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
1721 &rt5645_if1_dac0_tdm_sel_mux),
1722 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
1723 &rt5645_if1_dac1_tdm_sel_mux),
1724 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
1725 &rt5645_if1_dac2_tdm_sel_mux),
1726 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
1727 &rt5645_if1_dac3_tdm_sel_mux),
Oder Chiou1319b2f2014-04-28 19:59:10 +08001728 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1729 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1730 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1731 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
1732 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
1733 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1734 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1735 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1736 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1737
1738 /* Digital Interface Select */
1739 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
1740 0, 0, &rt5645_vad_adc_mux),
1741
1742 /* Audio Interface */
1743 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1744 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1745 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1746 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1747
1748 /* Output Side */
1749 /* DAC mixer before sound effect */
1750 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1751 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
1752 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1753 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
1754
1755 /* DAC2 channel Mux */
1756 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1757 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1758 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1759 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
1760 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1761 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
1762
1763 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
1764 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
1765
1766 /* DAC Mixer */
1767 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
1768 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
1769 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
1770 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1771 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
1772 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1773 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1774 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
1775 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1776 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
1777 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1778 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
1779 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1780 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
1781 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1782 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
1783 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1784 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
1785
1786 /* DACs */
1787 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
1788 0),
1789 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
1790 0),
1791 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
1792 0),
1793 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
1794 0),
1795 /* OUT Mixer */
1796 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
1797 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
1798 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
1799 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
1800 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
1801 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
1802 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
1803 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
1804 /* Ouput Volume */
1805 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
1806 &spk_l_vol_control),
1807 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
1808 &spk_r_vol_control),
1809 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
1810 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
1811 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
1812 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
1813 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
1814 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
1815 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
1816 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
1817 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1818 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1819 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1820 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
1821 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
1822
1823 /* HPO/LOUT/Mono Mixer */
1824 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
1825 ARRAY_SIZE(rt5645_spo_l_mix)),
1826 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
1827 ARRAY_SIZE(rt5645_spo_r_mix)),
1828 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
1829 ARRAY_SIZE(rt5645_hpo_mix)),
1830 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
1831 ARRAY_SIZE(rt5645_lout_mix)),
1832
1833 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
1834 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1835 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
1836 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1837 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
1838 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1839
1840 /* PDM */
1841 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
1842 0, NULL, 0),
1843 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
1844 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
1845
1846 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
1847 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
1848
1849 /* Output Lines */
1850 SND_SOC_DAPM_OUTPUT("HPOL"),
1851 SND_SOC_DAPM_OUTPUT("HPOR"),
1852 SND_SOC_DAPM_OUTPUT("LOUTL"),
1853 SND_SOC_DAPM_OUTPUT("LOUTR"),
1854 SND_SOC_DAPM_OUTPUT("PDM1L"),
1855 SND_SOC_DAPM_OUTPUT("PDM1R"),
1856 SND_SOC_DAPM_OUTPUT("SPOL"),
1857 SND_SOC_DAPM_OUTPUT("SPOR"),
1858};
1859
Bard Liao5c4ca992015-01-21 20:50:15 +08001860static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
1861 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
1862 0, 0, &rt5650_a_dac1_l_mux),
1863 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
1864 0, 0, &rt5650_a_dac1_r_mux),
1865 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
1866 0, 0, &rt5650_a_dac2_l_mux),
1867 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
1868 0, 0, &rt5650_a_dac2_r_mux),
Michele Curti851b81e2015-06-15 10:44:11 +08001869
1870 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
1871 0, 0, &rt5650_if1_adc1_in_mux),
1872 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
1873 0, 0, &rt5650_if1_adc2_in_mux),
1874 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
1875 0, 0, &rt5650_if1_adc3_in_mux),
1876 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
1877 0, 0, &rt5650_if1_adc_in_mux),
1878
1879 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
1880 &rt5650_if1_dac0_tdm_sel_mux),
1881 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
1882 &rt5650_if1_dac1_tdm_sel_mux),
1883 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
1884 &rt5650_if1_dac2_tdm_sel_mux),
1885 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
1886 &rt5650_if1_dac3_tdm_sel_mux),
Bard Liao5c4ca992015-01-21 20:50:15 +08001887};
1888
Oder Chiou1319b2f2014-04-28 19:59:10 +08001889static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
Bard Liao9e268352014-10-31 15:37:55 +08001890 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
Bard Liao9e268352014-10-31 15:37:55 +08001891 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
1892 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
1893 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
1894 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
1895 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
1896
1897 { "I2S1", NULL, "I2S1 ASRC" },
1898 { "I2S2", NULL, "I2S2 ASRC" },
1899
Oder Chiou1319b2f2014-04-28 19:59:10 +08001900 { "IN1P", NULL, "LDO2" },
1901 { "IN2P", NULL, "LDO2" },
1902
1903 { "DMIC1", NULL, "DMIC L1" },
1904 { "DMIC1", NULL, "DMIC R1" },
1905 { "DMIC2", NULL, "DMIC L2" },
1906 { "DMIC2", NULL, "DMIC R2" },
1907
1908 { "BST1", NULL, "IN1P" },
1909 { "BST1", NULL, "IN1N" },
1910 { "BST1", NULL, "JD Power" },
1911 { "BST1", NULL, "Mic Det Power" },
1912 { "BST2", NULL, "IN2P" },
1913 { "BST2", NULL, "IN2N" },
1914
1915 { "INL VOL", NULL, "IN2P" },
1916 { "INR VOL", NULL, "IN2N" },
1917
1918 { "RECMIXL", "HPOL Switch", "HPOL" },
1919 { "RECMIXL", "INL Switch", "INL VOL" },
1920 { "RECMIXL", "BST2 Switch", "BST2" },
1921 { "RECMIXL", "BST1 Switch", "BST1" },
1922 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
1923
1924 { "RECMIXR", "HPOR Switch", "HPOR" },
1925 { "RECMIXR", "INR Switch", "INR VOL" },
1926 { "RECMIXR", "BST2 Switch", "BST2" },
1927 { "RECMIXR", "BST1 Switch", "BST1" },
1928 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
1929
1930 { "ADC L", NULL, "RECMIXL" },
1931 { "ADC L", NULL, "ADC L power" },
1932 { "ADC R", NULL, "RECMIXR" },
1933 { "ADC R", NULL, "ADC R power" },
1934
1935 {"DMIC L1", NULL, "DMIC CLK"},
1936 {"DMIC L1", NULL, "DMIC1 Power"},
1937 {"DMIC R1", NULL, "DMIC CLK"},
1938 {"DMIC R1", NULL, "DMIC1 Power"},
1939 {"DMIC L2", NULL, "DMIC CLK"},
1940 {"DMIC L2", NULL, "DMIC2 Power"},
1941 {"DMIC R2", NULL, "DMIC CLK"},
1942 {"DMIC R2", NULL, "DMIC2 Power"},
1943
1944 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1945 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
Bard Liao9e268352014-10-31 15:37:55 +08001946 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
Oder Chiou1319b2f2014-04-28 19:59:10 +08001947
1948 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1949 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
Bard Liao9e268352014-10-31 15:37:55 +08001950 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
Oder Chiou1319b2f2014-04-28 19:59:10 +08001951
1952 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1953 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
Bard Liao9e268352014-10-31 15:37:55 +08001954 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
Oder Chiou1319b2f2014-04-28 19:59:10 +08001955
1956 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1957 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1958 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
1959 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1960
1961 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
1962 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1963 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1964 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1965
1966 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
1967 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1968 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1969 { "Mono ADC L1 Mux", "ADC", "ADC L" },
1970
1971 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1972 { "Mono ADC R1 Mux", "ADC", "ADC R" },
1973 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
1974 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1975
1976 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
1977 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
1978 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
1979 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
1980
1981 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
1982 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
1983 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1984
1985 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
1986 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
1987 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1988
1989 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
1990 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
1991 { "Mono ADC MIXL", NULL, "adc mono left filter" },
1992 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
1993
1994 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
1995 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
1996 { "Mono ADC MIXR", NULL, "adc mono right filter" },
1997 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
1998
1999 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2000 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2001 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2002
2003 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2004 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2005 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2006 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2007 { "VAD_ADC", NULL, "VAD ADC Mux" },
2008
Oder Chiou1319b2f2014-04-28 19:59:10 +08002009 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2010 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2011 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2012
2013 { "IF1 ADC", NULL, "I2S1" },
Oder Chiou1319b2f2014-04-28 19:59:10 +08002014 { "IF2 ADC", NULL, "I2S2" },
2015 { "IF2 ADC", NULL, "IF2 ADC Mux" },
2016
Oder Chiou1319b2f2014-04-28 19:59:10 +08002017 { "AIF2TX", NULL, "IF2 ADC" },
2018
Bard Liao21ab3f22015-04-30 18:18:44 +08002019 { "IF1 DAC0", NULL, "AIF1RX" },
Oder Chiou1319b2f2014-04-28 19:59:10 +08002020 { "IF1 DAC1", NULL, "AIF1RX" },
2021 { "IF1 DAC2", NULL, "AIF1RX" },
Bard Liao21ab3f22015-04-30 18:18:44 +08002022 { "IF1 DAC3", NULL, "AIF1RX" },
Oder Chiou1319b2f2014-04-28 19:59:10 +08002023 { "IF2 DAC", NULL, "AIF2RX" },
2024
Bard Liao21ab3f22015-04-30 18:18:44 +08002025 { "IF1 DAC0", NULL, "I2S1" },
Oder Chiou1319b2f2014-04-28 19:59:10 +08002026 { "IF1 DAC1", NULL, "I2S1" },
2027 { "IF1 DAC2", NULL, "I2S1" },
Bard Liao21ab3f22015-04-30 18:18:44 +08002028 { "IF1 DAC3", NULL, "I2S1" },
Oder Chiou1319b2f2014-04-28 19:59:10 +08002029 { "IF2 DAC", NULL, "I2S2" },
2030
Oder Chiou1319b2f2014-04-28 19:59:10 +08002031 { "IF2 DAC L", NULL, "IF2 DAC" },
2032 { "IF2 DAC R", NULL, "IF2 DAC" },
2033
Oder Chiou1319b2f2014-04-28 19:59:10 +08002034 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
Oder Chiou1319b2f2014-04-28 19:59:10 +08002035 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2036
2037 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2038 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2039 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2040 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2041 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2042 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2043
Oder Chiou1319b2f2014-04-28 19:59:10 +08002044 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2045 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2046 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2047 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2048 { "DAC L2 Volume", NULL, "dac mono left filter" },
2049
Oder Chiou1319b2f2014-04-28 19:59:10 +08002050 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2051 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2052 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2053 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2054 { "DAC R2 Volume", NULL, "dac mono right filter" },
2055
2056 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2057 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2058 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2059 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2060 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2061 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2062 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2063 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2064
2065 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2066 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2067 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2068 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2069 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2070 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2071 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2072 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2073
2074 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2075 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2076 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2077 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2078 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2079 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2080
Oder Chiou1319b2f2014-04-28 19:59:10 +08002081 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
Oder Chiou1319b2f2014-04-28 19:59:10 +08002082 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
Oder Chiou1319b2f2014-04-28 19:59:10 +08002083 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
Oder Chiou1319b2f2014-04-28 19:59:10 +08002084 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2085
2086 { "SPK MIXL", "BST1 Switch", "BST1" },
2087 { "SPK MIXL", "INL Switch", "INL VOL" },
2088 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2089 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2090 { "SPK MIXR", "BST2 Switch", "BST2" },
2091 { "SPK MIXR", "INR Switch", "INR VOL" },
2092 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2093 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2094
2095 { "OUT MIXL", "BST1 Switch", "BST1" },
2096 { "OUT MIXL", "INL Switch", "INL VOL" },
2097 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2098 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2099
2100 { "OUT MIXR", "BST2 Switch", "BST2" },
2101 { "OUT MIXR", "INR Switch", "INR VOL" },
2102 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2103 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2104
2105 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2106 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2107 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2108 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
2109 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2110 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2111 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2112 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2113 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
2114 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2115
2116 { "DAC 2", NULL, "DAC L2" },
2117 { "DAC 2", NULL, "DAC R2" },
2118 { "DAC 1", NULL, "DAC L1" },
2119 { "DAC 1", NULL, "DAC R1" },
2120 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
2121 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
2122 { "HPOVOL", NULL, "HPOVOL L" },
2123 { "HPOVOL", NULL, "HPOVOL R" },
2124 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2125 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2126
2127 { "SPKVOL L", "Switch", "SPK MIXL" },
2128 { "SPKVOL R", "Switch", "SPK MIXR" },
2129
2130 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2131 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2132 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2133 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2134 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2135 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2136
2137 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2138 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2139 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2140 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2141
2142 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2143 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2144 { "PDM1 L Mux", NULL, "PDM1 Power" },
2145 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2146 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2147 { "PDM1 R Mux", NULL, "PDM1 Power" },
2148
2149 { "HP amp", NULL, "HPO MIX" },
2150 { "HP amp", NULL, "JD Power" },
2151 { "HP amp", NULL, "Mic Det Power" },
2152 { "HP amp", NULL, "LDO2" },
2153 { "HPOL", NULL, "HP amp" },
2154 { "HPOR", NULL, "HP amp" },
2155
2156 { "LOUT amp", NULL, "LOUT MIX" },
2157 { "LOUTL", NULL, "LOUT amp" },
2158 { "LOUTR", NULL, "LOUT amp" },
2159
2160 { "PDM1 L", "Switch", "PDM1 L Mux" },
2161 { "PDM1 R", "Switch", "PDM1 R Mux" },
2162
2163 { "PDM1L", NULL, "PDM1 L" },
2164 { "PDM1R", NULL, "PDM1 R" },
2165
2166 { "SPK amp", NULL, "SPOL MIX" },
2167 { "SPK amp", NULL, "SPOR MIX" },
2168 { "SPOL", NULL, "SPK amp" },
2169 { "SPOR", NULL, "SPK amp" },
2170};
2171
Bard Liao5c4ca992015-01-21 20:50:15 +08002172static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2173 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2174 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2175 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2176 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2177
2178 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2179 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2180 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2181 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2182
2183 { "DAC L1", NULL, "A DAC1 L Mux" },
2184 { "DAC R1", NULL, "A DAC1 R Mux" },
2185 { "DAC L2", NULL, "A DAC2 L Mux" },
2186 { "DAC R2", NULL, "A DAC2 R Mux" },
Bard Liao21ab3f22015-04-30 18:18:44 +08002187
2188 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2189 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2190 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2191 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2192
2193 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2194 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2195 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2196 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2197
2198 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2199 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2200 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2201 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2202
2203 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2204 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2205 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2206
2207 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2208 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2209 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2210 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2211 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2212 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2213
2214 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2215 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2216 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2217 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2218 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2219 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2220
2221 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2222 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2223 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2224 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2225 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2226 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2227
2228 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2229 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2230 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2231 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2232 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2233 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2234 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2235
2236 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2237 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2238 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2239 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2240
2241 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2242 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2243 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2244 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2245
2246 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2247 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2248 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2249 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2250
2251 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2252 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2253 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2254 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2255
2256 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2257 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2258
2259 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2260 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
Bard Liao5c4ca992015-01-21 20:50:15 +08002261};
2262
2263static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2264 { "DAC L1", NULL, "Stereo DAC MIXL" },
2265 { "DAC R1", NULL, "Stereo DAC MIXR" },
2266 { "DAC L2", NULL, "Mono DAC MIXL" },
2267 { "DAC R2", NULL, "Mono DAC MIXR" },
Bard Liao21ab3f22015-04-30 18:18:44 +08002268
2269 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2270 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2271 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2272 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2273
2274 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2275 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2276 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2277 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2278
2279 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2280 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2281 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2282 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2283
2284 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2285 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2286 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2287
2288 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2289 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2290 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2291 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2292 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2293
2294 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2295 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2296 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2297 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2298
2299 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2300 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2301 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2302 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2303
2304 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2305 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2306 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2307 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2308
2309 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2310 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2311 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2312 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2313
2314 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2315 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2316
2317 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2318 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
Bard Liao5c4ca992015-01-21 20:50:15 +08002319};
2320
Oder Chiou1319b2f2014-04-28 19:59:10 +08002321static int rt5645_hw_params(struct snd_pcm_substream *substream,
2322 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2323{
2324 struct snd_soc_codec *codec = dai->codec;
2325 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
Bard Liao57bf2732015-03-27 20:19:06 +08002326 unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
Oder Chiou1319b2f2014-04-28 19:59:10 +08002327 int pre_div, bclk_ms, frame_size;
2328
2329 rt5645->lrck[dai->id] = params_rate(params);
Oder Chioud92950e2014-05-20 15:01:55 +08002330 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002331 if (pre_div < 0) {
2332 dev_err(codec->dev, "Unsupported clock setting\n");
2333 return -EINVAL;
2334 }
2335 frame_size = snd_soc_params_to_frame_size(params);
2336 if (frame_size < 0) {
2337 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2338 return -EINVAL;
2339 }
Bard Liao57bf2732015-03-27 20:19:06 +08002340
2341 switch (rt5645->codec_type) {
2342 case CODEC_TYPE_RT5650:
2343 dl_sft = 4;
2344 break;
2345 default:
2346 dl_sft = 2;
2347 break;
2348 }
2349
Oder Chiou1319b2f2014-04-28 19:59:10 +08002350 bclk_ms = frame_size > 32;
2351 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2352
2353 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2354 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2355 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2356 bclk_ms, pre_div, dai->id);
2357
2358 switch (params_width(params)) {
2359 case 16:
2360 break;
2361 case 20:
Bard Liao57bf2732015-03-27 20:19:06 +08002362 val_len = 0x1;
Oder Chiou1319b2f2014-04-28 19:59:10 +08002363 break;
2364 case 24:
Bard Liao57bf2732015-03-27 20:19:06 +08002365 val_len = 0x2;
Oder Chiou1319b2f2014-04-28 19:59:10 +08002366 break;
2367 case 8:
Bard Liao57bf2732015-03-27 20:19:06 +08002368 val_len = 0x3;
Oder Chiou1319b2f2014-04-28 19:59:10 +08002369 break;
2370 default:
2371 return -EINVAL;
2372 }
2373
2374 switch (dai->id) {
2375 case RT5645_AIF1:
Bard Liao33de3d52015-04-30 18:18:42 +08002376 mask_clk = RT5645_I2S_PD1_MASK;
2377 val_clk = pre_div << RT5645_I2S_PD1_SFT;
Oder Chiou1319b2f2014-04-28 19:59:10 +08002378 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
Bard Liao57bf2732015-03-27 20:19:06 +08002379 (0x3 << dl_sft), (val_len << dl_sft));
Oder Chiou1319b2f2014-04-28 19:59:10 +08002380 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2381 break;
2382 case RT5645_AIF2:
2383 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2384 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2385 pre_div << RT5645_I2S_PD2_SFT;
2386 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
Bard Liao57bf2732015-03-27 20:19:06 +08002387 (0x3 << dl_sft), (val_len << dl_sft));
Oder Chiou1319b2f2014-04-28 19:59:10 +08002388 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2389 break;
2390 default:
2391 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2392 return -EINVAL;
2393 }
2394
2395 return 0;
2396}
2397
2398static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2399{
2400 struct snd_soc_codec *codec = dai->codec;
2401 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
Bard Liao57bf2732015-03-27 20:19:06 +08002402 unsigned int reg_val = 0, pol_sft;
2403
2404 switch (rt5645->codec_type) {
2405 case CODEC_TYPE_RT5650:
2406 pol_sft = 8;
2407 break;
2408 default:
2409 pol_sft = 7;
2410 break;
2411 }
Oder Chiou1319b2f2014-04-28 19:59:10 +08002412
2413 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2414 case SND_SOC_DAIFMT_CBM_CFM:
2415 rt5645->master[dai->id] = 1;
2416 break;
2417 case SND_SOC_DAIFMT_CBS_CFS:
2418 reg_val |= RT5645_I2S_MS_S;
2419 rt5645->master[dai->id] = 0;
2420 break;
2421 default:
2422 return -EINVAL;
2423 }
2424
2425 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2426 case SND_SOC_DAIFMT_NB_NF:
2427 break;
2428 case SND_SOC_DAIFMT_IB_NF:
Bard Liao57bf2732015-03-27 20:19:06 +08002429 reg_val |= (1 << pol_sft);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002430 break;
2431 default:
2432 return -EINVAL;
2433 }
2434
2435 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2436 case SND_SOC_DAIFMT_I2S:
2437 break;
2438 case SND_SOC_DAIFMT_LEFT_J:
2439 reg_val |= RT5645_I2S_DF_LEFT;
2440 break;
2441 case SND_SOC_DAIFMT_DSP_A:
2442 reg_val |= RT5645_I2S_DF_PCM_A;
2443 break;
2444 case SND_SOC_DAIFMT_DSP_B:
2445 reg_val |= RT5645_I2S_DF_PCM_B;
2446 break;
2447 default:
2448 return -EINVAL;
2449 }
2450 switch (dai->id) {
2451 case RT5645_AIF1:
2452 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
Bard Liao57bf2732015-03-27 20:19:06 +08002453 RT5645_I2S_MS_MASK | (1 << pol_sft) |
Oder Chiou1319b2f2014-04-28 19:59:10 +08002454 RT5645_I2S_DF_MASK, reg_val);
2455 break;
Axel Lin8c325702014-05-17 19:17:32 +08002456 case RT5645_AIF2:
2457 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
Bard Liao57bf2732015-03-27 20:19:06 +08002458 RT5645_I2S_MS_MASK | (1 << pol_sft) |
Oder Chiou1319b2f2014-04-28 19:59:10 +08002459 RT5645_I2S_DF_MASK, reg_val);
2460 break;
2461 default:
2462 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2463 return -EINVAL;
2464 }
2465 return 0;
2466}
2467
2468static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2469 int clk_id, unsigned int freq, int dir)
2470{
2471 struct snd_soc_codec *codec = dai->codec;
2472 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2473 unsigned int reg_val = 0;
2474
2475 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2476 return 0;
2477
2478 switch (clk_id) {
2479 case RT5645_SCLK_S_MCLK:
2480 reg_val |= RT5645_SCLK_SRC_MCLK;
2481 break;
2482 case RT5645_SCLK_S_PLL1:
2483 reg_val |= RT5645_SCLK_SRC_PLL1;
2484 break;
2485 case RT5645_SCLK_S_RCCLK:
2486 reg_val |= RT5645_SCLK_SRC_RCCLK;
2487 break;
2488 default:
2489 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2490 return -EINVAL;
2491 }
2492 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2493 RT5645_SCLK_SRC_MASK, reg_val);
2494 rt5645->sysclk = freq;
2495 rt5645->sysclk_src = clk_id;
2496
2497 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2498
2499 return 0;
2500}
2501
Oder Chiou1319b2f2014-04-28 19:59:10 +08002502static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2503 unsigned int freq_in, unsigned int freq_out)
2504{
2505 struct snd_soc_codec *codec = dai->codec;
2506 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
Oder Chiou71c7a2d2014-05-20 15:01:54 +08002507 struct rl6231_pll_code pll_code;
Oder Chiou1319b2f2014-04-28 19:59:10 +08002508 int ret;
2509
2510 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2511 freq_out == rt5645->pll_out)
2512 return 0;
2513
2514 if (!freq_in || !freq_out) {
2515 dev_dbg(codec->dev, "PLL disabled\n");
2516
2517 rt5645->pll_in = 0;
2518 rt5645->pll_out = 0;
2519 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2520 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2521 return 0;
2522 }
2523
2524 switch (source) {
2525 case RT5645_PLL1_S_MCLK:
2526 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2527 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2528 break;
2529 case RT5645_PLL1_S_BCLK1:
2530 case RT5645_PLL1_S_BCLK2:
2531 switch (dai->id) {
2532 case RT5645_AIF1:
2533 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2534 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2535 break;
2536 case RT5645_AIF2:
2537 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2538 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2539 break;
2540 default:
2541 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2542 return -EINVAL;
2543 }
2544 break;
2545 default:
2546 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2547 return -EINVAL;
2548 }
2549
Oder Chiou71c7a2d2014-05-20 15:01:54 +08002550 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002551 if (ret < 0) {
2552 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2553 return ret;
2554 }
2555
2556 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2557 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2558 pll_code.n_code, pll_code.k_code);
2559
2560 snd_soc_write(codec, RT5645_PLL_CTRL1,
2561 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2562 snd_soc_write(codec, RT5645_PLL_CTRL2,
2563 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2564 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2565
2566 rt5645->pll_in = freq_in;
2567 rt5645->pll_out = freq_out;
2568 rt5645->pll_src = source;
2569
2570 return 0;
2571}
2572
2573static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2574 unsigned int rx_mask, int slots, int slot_width)
2575{
2576 struct snd_soc_codec *codec = dai->codec;
Bard Liao42ce5b82015-03-12 20:25:07 +08002577 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2578 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
2579 unsigned int mask, val = 0;
Oder Chiou1319b2f2014-04-28 19:59:10 +08002580
Bard Liao42ce5b82015-03-12 20:25:07 +08002581 switch (rt5645->codec_type) {
2582 case CODEC_TYPE_RT5650:
2583 en_sft = 15;
2584 i_slot_sft = 10;
2585 o_slot_sft = 8;
2586 i_width_sht = 6;
2587 o_width_sht = 4;
2588 mask = 0x8ff0;
2589 break;
2590 default:
2591 en_sft = 14;
2592 i_slot_sft = o_slot_sft = 12;
2593 i_width_sht = o_width_sht = 10;
2594 mask = 0x7c00;
2595 break;
2596 }
Bard Liao850577d2014-11-13 09:55:22 +08002597 if (rx_mask || tx_mask) {
Bard Liao42ce5b82015-03-12 20:25:07 +08002598 val |= (1 << en_sft);
2599 if (rt5645->codec_type == CODEC_TYPE_RT5645)
2600 snd_soc_update_bits(codec, RT5645_BASS_BACK,
2601 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
Bard Liao850577d2014-11-13 09:55:22 +08002602 }
Oder Chiou1319b2f2014-04-28 19:59:10 +08002603
2604 switch (slots) {
2605 case 4:
Bard Liao42ce5b82015-03-12 20:25:07 +08002606 val |= (1 << i_slot_sft) | (1 << o_slot_sft);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002607 break;
2608 case 6:
Bard Liao42ce5b82015-03-12 20:25:07 +08002609 val |= (2 << i_slot_sft) | (2 << o_slot_sft);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002610 break;
2611 case 8:
Bard Liao42ce5b82015-03-12 20:25:07 +08002612 val |= (3 << i_slot_sft) | (3 << o_slot_sft);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002613 break;
2614 case 2:
2615 default:
2616 break;
2617 }
2618
2619 switch (slot_width) {
2620 case 20:
Bard Liao42ce5b82015-03-12 20:25:07 +08002621 val |= (1 << i_width_sht) | (1 << o_width_sht);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002622 break;
2623 case 24:
Bard Liao42ce5b82015-03-12 20:25:07 +08002624 val |= (2 << i_width_sht) | (2 << o_width_sht);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002625 break;
2626 case 32:
Bard Liao42ce5b82015-03-12 20:25:07 +08002627 val |= (3 << i_width_sht) | (3 << o_width_sht);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002628 break;
2629 case 16:
2630 default:
2631 break;
2632 }
2633
Bard Liao42ce5b82015-03-12 20:25:07 +08002634 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, mask, val);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002635
2636 return 0;
2637}
2638
2639static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2640 enum snd_soc_bias_level level)
2641{
Bard Liao6e747d52015-04-28 09:59:43 +08002642 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2643
Oder Chiou1319b2f2014-04-28 19:59:10 +08002644 switch (level) {
Bard Liao0b2e4952014-11-04 13:15:10 +08002645 case SND_SOC_BIAS_PREPARE:
2646 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
Oder Chiou1319b2f2014-04-28 19:59:10 +08002647 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2648 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2649 RT5645_PWR_BG | RT5645_PWR_VREF2,
2650 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2651 RT5645_PWR_BG | RT5645_PWR_VREF2);
2652 mdelay(10);
2653 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2654 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2655 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2656 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2657 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2658 }
2659 break;
2660
Bard Liao0b2e4952014-11-04 13:15:10 +08002661 case SND_SOC_BIAS_STANDBY:
2662 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2663 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2664 RT5645_PWR_BG | RT5645_PWR_VREF2,
2665 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2666 RT5645_PWR_BG | RT5645_PWR_VREF2);
2667 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2668 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2669 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2670 break;
2671
Oder Chiou1319b2f2014-04-28 19:59:10 +08002672 case SND_SOC_BIAS_OFF:
2673 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
Bard Liao6e747d52015-04-28 09:59:43 +08002674 if (!rt5645->en_button_func)
2675 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2676 RT5645_DIG_GATE_CTRL, 0);
Bard Liao0b2e4952014-11-04 13:15:10 +08002677 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2678 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2679 RT5645_PWR_BG | RT5645_PWR_VREF2 |
2680 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002681 break;
2682
2683 default:
2684 break;
2685 }
Oder Chiou1319b2f2014-04-28 19:59:10 +08002686
2687 return 0;
2688}
2689
John Lind12d6c42015-05-12 20:43:02 +08002690static int rt5650_calibration(struct rt5645_priv *rt5645)
2691{
2692 int val, i;
2693 int ret = -1;
2694
2695 regcache_cache_bypass(rt5645->regmap, true);
2696 regmap_write(rt5645->regmap, RT5645_RESET, 0);
2697 regmap_write(rt5645->regmap, RT5645_GEN_CTRL3, 0x0800);
2698 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_CHOP_DAC_ADC,
2699 0x3600);
2700 regmap_write(rt5645->regmap, RT5645_PR_BASE + 0x25, 0x7000);
2701 regmap_write(rt5645->regmap, RT5645_I2S1_SDP, 0x8008);
2702 /* headset type */
2703 regmap_write(rt5645->regmap, RT5645_GEN_CTRL1, 0x2061);
2704 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006);
2705 regmap_write(rt5645->regmap, RT5645_PWR_ANLG1, 0x2012);
2706 regmap_write(rt5645->regmap, RT5645_PWR_MIXER, 0x0002);
2707 regmap_write(rt5645->regmap, RT5645_PWR_VOL, 0x0020);
2708 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
2709 regmap_write(rt5645->regmap, RT5645_IN1_CTRL1, 0x0006);
2710 regmap_write(rt5645->regmap, RT5645_IN1_CTRL2, 0x1827);
2711 regmap_write(rt5645->regmap, RT5645_IN1_CTRL2, 0x0827);
2712 msleep(400);
2713 /* Inline command */
2714 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0001);
2715 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD2, 0xc000);
2716 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD1, 0x0008);
2717 /* Calbration */
2718 regmap_write(rt5645->regmap, RT5645_GLB_CLK, 0x8000);
2719 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0000);
2720 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD2, 0xc000);
2721 regmap_write(rt5645->regmap, RT5650_4BTN_IL_CMD1, 0x0008);
2722 regmap_write(rt5645->regmap, RT5645_PWR_DIG2, 0x8800);
2723 regmap_write(rt5645->regmap, RT5645_PWR_ANLG1, 0xe8fa);
2724 regmap_write(rt5645->regmap, RT5645_PWR_ANLG2, 0x8c04);
2725 regmap_write(rt5645->regmap, RT5645_DEPOP_M2, 0x3100);
2726 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);
2727 regmap_write(rt5645->regmap, RT5645_BASS_BACK, 0x8a13);
2728 regmap_write(rt5645->regmap, RT5645_GEN_CTRL3, 0x0820);
2729 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x000d);
2730 /* Power on and Calbration */
2731 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_HP_DCC_INT1,
2732 0x9f01);
2733 msleep(200);
2734 for (i = 0; i < 5; i++) {
2735 regmap_read(rt5645->regmap, RT5645_PR_BASE + 0x7a, &val);
2736 if (val != 0 && val != 0x3f3f) {
2737 ret = 0;
2738 break;
2739 }
2740 msleep(50);
2741 }
2742 pr_debug("%s: PR-7A = 0x%x\n", __func__, val);
2743
2744 /* mute */
2745 regmap_write(rt5645->regmap, RT5645_PR_BASE + 0x3e, 0x7400);
2746 regmap_write(rt5645->regmap, RT5645_DEPOP_M3, 0x0737);
2747 regmap_write(rt5645->regmap, RT5645_PR_BASE + RT5645_MAMP_INT_REG2,
2748 0xfc00);
2749 regmap_write(rt5645->regmap, RT5645_DEPOP_M2, 0x1140);
2750 regmap_write(rt5645->regmap, RT5645_DEPOP_M1, 0x0000);
2751 regmap_write(rt5645->regmap, RT5645_GEN_CTRL2, 0x4020);
2752 regmap_write(rt5645->regmap, RT5645_PWR_ANLG2, 0x0006);
2753 regmap_write(rt5645->regmap, RT5645_PWR_DIG2, 0x0000);
2754 msleep(350);
2755
2756 regcache_cache_bypass(rt5645->regmap, false);
2757
2758 return ret;
2759}
2760
Bard Liao6e747d52015-04-28 09:59:43 +08002761static void rt5645_enable_push_button_irq(struct snd_soc_codec *codec,
2762 bool enable)
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002763{
2764 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
Bard Liao6e747d52015-04-28 09:59:43 +08002765
2766 if (enable) {
Nicolas Boichat22f5d9f2015-06-10 11:54:13 +08002767 snd_soc_dapm_mutex_lock(&codec->dapm);
Bard Liao6e747d52015-04-28 09:59:43 +08002768 snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm,
2769 "ADC L power");
2770 snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm,
2771 "ADC R power");
2772 snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm,
2773 "LDO2");
2774 snd_soc_dapm_force_enable_pin_unlocked(&codec->dapm,
2775 "Mic Det Power");
2776 snd_soc_dapm_sync_unlocked(&codec->dapm);
Nicolas Boichat22f5d9f2015-06-10 11:54:13 +08002777 snd_soc_dapm_mutex_unlock(&codec->dapm);
2778
Bard Liao6e747d52015-04-28 09:59:43 +08002779 snd_soc_update_bits(codec,
2780 RT5645_INT_IRQ_ST, 0x8, 0x8);
2781 snd_soc_update_bits(codec,
2782 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
2783 snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
2784 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
2785 snd_soc_read(codec, RT5650_4BTN_IL_CMD1));
2786 } else {
2787 snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
2788 snd_soc_update_bits(codec, RT5645_INT_IRQ_ST, 0x8, 0x0);
Nicolas Boichat22f5d9f2015-06-10 11:54:13 +08002789
2790 snd_soc_dapm_mutex_lock(&codec->dapm);
Bard Liao6e747d52015-04-28 09:59:43 +08002791 snd_soc_dapm_disable_pin_unlocked(&codec->dapm,
2792 "ADC L power");
2793 snd_soc_dapm_disable_pin_unlocked(&codec->dapm,
2794 "ADC R power");
2795 if (rt5645->pdata.jd_mode == 0)
2796 snd_soc_dapm_disable_pin_unlocked(&codec->dapm,
2797 "LDO2");
2798 snd_soc_dapm_disable_pin_unlocked(&codec->dapm,
2799 "Mic Det Power");
2800 snd_soc_dapm_sync_unlocked(&codec->dapm);
Nicolas Boichat22f5d9f2015-06-10 11:54:13 +08002801 snd_soc_dapm_mutex_unlock(&codec->dapm);
Bard Liao6e747d52015-04-28 09:59:43 +08002802 }
2803}
2804
2805static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert)
2806{
2807 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002808 unsigned int val;
2809
Bard Liao6e747d52015-04-28 09:59:43 +08002810 if (jack_insert) {
John Lin05a9b462015-05-12 20:43:05 +08002811 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006);
2812
Bard Liao6e747d52015-04-28 09:59:43 +08002813 if (codec->component.card->instantiated) {
John Lin05a9b462015-05-12 20:43:05 +08002814 /* for jack type detect */
2815 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
Bard Liao6e747d52015-04-28 09:59:43 +08002816 snd_soc_dapm_force_enable_pin(&codec->dapm,
2817 "Mic Det Power");
2818 snd_soc_dapm_sync(&codec->dapm);
2819 } else {
2820 /* Power up necessary bits for JD if dapm is
2821 not ready yet */
John Lin05a9b462015-05-12 20:43:05 +08002822 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
2823 RT5645_PWR_MB | RT5645_PWR_VREF2,
2824 RT5645_PWR_MB | RT5645_PWR_VREF2);
2825 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
Bard Liao6e747d52015-04-28 09:59:43 +08002826 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
John Lin05a9b462015-05-12 20:43:05 +08002827 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
Bard Liao6e747d52015-04-28 09:59:43 +08002828 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
2829 }
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002830
John Lin05a9b462015-05-12 20:43:05 +08002831 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
2832 regmap_write(rt5645->regmap, RT5645_IN1_CTRL1, 0x0006);
2833 regmap_update_bits(rt5645->regmap,
2834 RT5645_IN1_CTRL2, 0x1000, 0x1000);
2835 msleep(100);
2836 regmap_update_bits(rt5645->regmap,
2837 RT5645_IN1_CTRL2, 0x1000, 0x0000);
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002838
John Lin05a9b462015-05-12 20:43:05 +08002839 msleep(450);
2840 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
2841 val &= 0x7;
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002842 dev_dbg(codec->dev, "val = %d\n", val);
2843
Bard Liao6e747d52015-04-28 09:59:43 +08002844 if (val == 1 || val == 2) {
2845 rt5645->jack_type = SND_JACK_HEADSET;
2846 if (rt5645->en_button_func) {
Bard Liao6e747d52015-04-28 09:59:43 +08002847 rt5645_enable_push_button_irq(codec, true);
2848 }
2849 } else {
John Linb7f22472015-05-12 20:43:04 +08002850 if (codec->component.card->instantiated) {
2851 snd_soc_dapm_disable_pin(&codec->dapm,
2852 "Mic Det Power");
2853 snd_soc_dapm_sync(&codec->dapm);
2854 } else
2855 regmap_update_bits(rt5645->regmap,
2856 RT5645_PWR_VOL, RT5645_PWR_MIC_DET, 0);
Bard Liao6e747d52015-04-28 09:59:43 +08002857 rt5645->jack_type = SND_JACK_HEADPHONE;
2858 }
2859
2860 } else { /* jack out */
2861 rt5645->jack_type = 0;
2862 if (rt5645->en_button_func)
2863 rt5645_enable_push_button_irq(codec, false);
John Linb7f22472015-05-12 20:43:04 +08002864 else {
2865 if (codec->component.card->instantiated) {
2866 if (rt5645->pdata.jd_mode == 0)
2867 snd_soc_dapm_disable_pin(&codec->dapm,
2868 "LDO2");
2869 snd_soc_dapm_disable_pin(&codec->dapm,
2870 "Mic Det Power");
2871 snd_soc_dapm_sync(&codec->dapm);
2872 } else {
2873 if (rt5645->pdata.jd_mode == 0)
2874 regmap_update_bits(rt5645->regmap,
2875 RT5645_PWR_MIXER,
2876 RT5645_PWR_LDO2, 0);
2877 regmap_update_bits(rt5645->regmap,
2878 RT5645_PWR_VOL, RT5645_PWR_MIC_DET, 0);
2879 }
2880 }
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002881 }
2882
Bard Liao6e747d52015-04-28 09:59:43 +08002883 return rt5645->jack_type;
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002884}
2885
Bard Liaod5660422015-04-30 10:30:01 +08002886static int rt5645_irq_detection(struct rt5645_priv *rt5645);
John Lin345b0f52015-05-18 10:34:03 +08002887static irqreturn_t rt5645_irq(int irq, void *data);
Bard Liaod5660422015-04-30 10:30:01 +08002888
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002889int rt5645_set_jack_detect(struct snd_soc_codec *codec,
Bard Liao6e747d52015-04-28 09:59:43 +08002890 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
2891 struct snd_soc_jack *btn_jack)
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002892{
2893 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2894
Bard Liao471f2082014-11-14 14:25:37 +08002895 rt5645->hp_jack = hp_jack;
2896 rt5645->mic_jack = mic_jack;
Bard Liao6e747d52015-04-28 09:59:43 +08002897 rt5645->btn_jack = btn_jack;
2898 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
2899 rt5645->en_button_func = true;
2900 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2901 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
2902 regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1,
2903 RT5645_HP_CB_MASK, RT5645_HP_CB_PU);
2904 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
2905 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2906 }
John Lin345b0f52015-05-18 10:34:03 +08002907 rt5645_irq(0, rt5645);
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002908
2909 return 0;
2910}
2911EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
2912
Oder Chioucd6e82b2014-10-07 10:25:37 +08002913static void rt5645_jack_detect_work(struct work_struct *work)
2914{
2915 struct rt5645_priv *rt5645 =
2916 container_of(work, struct rt5645_priv, jack_detect_work.work);
2917
Bard Liao6e747d52015-04-28 09:59:43 +08002918 rt5645_irq_detection(rt5645);
Oder Chioucd6e82b2014-10-07 10:25:37 +08002919}
2920
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002921static irqreturn_t rt5645_irq(int irq, void *data)
2922{
2923 struct rt5645_priv *rt5645 = data;
2924
Oder Chioucd6e82b2014-10-07 10:25:37 +08002925 queue_delayed_work(system_power_efficient_wq,
2926 &rt5645->jack_detect_work, msecs_to_jiffies(250));
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002927
2928 return IRQ_HANDLED;
2929}
2930
Bard Liao6e747d52015-04-28 09:59:43 +08002931static int rt5645_button_detect(struct snd_soc_codec *codec)
2932{
2933 int btn_type, val;
2934
2935 val = snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
2936 pr_debug("val=0x%x\n", val);
2937 btn_type = val & 0xfff0;
2938 snd_soc_write(codec, RT5650_4BTN_IL_CMD1, val);
2939
2940 return btn_type;
2941}
2942
2943static int rt5645_irq_detection(struct rt5645_priv *rt5645)
2944{
2945 int val, btn_type, gpio_state = 0, report = 0;
2946
2947 switch (rt5645->pdata.jd_mode) {
2948 case 0: /* Not using rt5645 JD */
Oder Chiou0b0cefc2015-06-10 14:27:57 +08002949 if (rt5645->gpiod_hp_det) {
2950 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
2951 dev_dbg(rt5645->codec->dev, "gpio_state = %d\n",
2952 gpio_state);
2953 report = rt5645_jack_detect(rt5645->codec, gpio_state);
Bard Liao6e747d52015-04-28 09:59:43 +08002954 }
2955 snd_soc_jack_report(rt5645->hp_jack,
2956 report, SND_JACK_HEADPHONE);
2957 snd_soc_jack_report(rt5645->mic_jack,
2958 report, SND_JACK_MICROPHONE);
2959 return report;
2960 case 1: /* 2 port */
2961 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0070;
2962 break;
2963 default: /* 1 port */
2964 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0020;
2965 break;
2966
2967 }
2968
2969 switch (val) {
2970 /* jack in */
2971 case 0x30: /* 2 port */
2972 case 0x0: /* 1 port or 2 port */
2973 if (rt5645->jack_type == 0) {
2974 report = rt5645_jack_detect(rt5645->codec, 1);
2975 /* for push button and jack out */
2976 break;
2977 }
2978 btn_type = 0;
2979 if (snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x4) {
2980 /* button pressed */
2981 report = SND_JACK_HEADSET;
2982 btn_type = rt5645_button_detect(rt5645->codec);
2983 /* rt5650 can report three kinds of button behavior,
2984 one click, double click and hold. However,
2985 currently we will report button pressed/released
2986 event. So all the three button behaviors are
2987 treated as button pressed. */
2988 switch (btn_type) {
2989 case 0x8000:
2990 case 0x4000:
2991 case 0x2000:
2992 report |= SND_JACK_BTN_0;
2993 break;
2994 case 0x1000:
2995 case 0x0800:
2996 case 0x0400:
2997 report |= SND_JACK_BTN_1;
2998 break;
2999 case 0x0200:
3000 case 0x0100:
3001 case 0x0080:
3002 report |= SND_JACK_BTN_2;
3003 break;
3004 case 0x0040:
3005 case 0x0020:
3006 case 0x0010:
3007 report |= SND_JACK_BTN_3;
3008 break;
3009 case 0x0000: /* unpressed */
3010 break;
3011 default:
3012 dev_err(rt5645->codec->dev,
3013 "Unexpected button code 0x%04x\n",
3014 btn_type);
3015 break;
3016 }
3017 }
3018 if (btn_type == 0)/* button release */
3019 report = rt5645->jack_type;
3020
3021 break;
3022 /* jack out */
3023 case 0x70: /* 2 port */
3024 case 0x10: /* 2 port */
3025 case 0x20: /* 1 port */
3026 report = 0;
3027 snd_soc_update_bits(rt5645->codec,
3028 RT5645_INT_IRQ_ST, 0x1, 0x0);
3029 rt5645_jack_detect(rt5645->codec, 0);
3030 break;
3031 default:
3032 break;
3033 }
3034
3035 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
3036 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
3037 if (rt5645->en_button_func)
3038 snd_soc_jack_report(rt5645->btn_jack,
Bard Liaoe0b5d902015-04-30 18:18:46 +08003039 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3040 SND_JACK_BTN_2 | SND_JACK_BTN_3);
Bard Liao6e747d52015-04-28 09:59:43 +08003041
3042 return report;
3043}
3044
Oder Chiou1319b2f2014-04-28 19:59:10 +08003045static int rt5645_probe(struct snd_soc_codec *codec)
3046{
3047 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3048
3049 rt5645->codec = codec;
3050
Bard Liao5c4ca992015-01-21 20:50:15 +08003051 switch (rt5645->codec_type) {
3052 case CODEC_TYPE_RT5645:
3053 snd_soc_dapm_add_routes(&codec->dapm,
3054 rt5645_specific_dapm_routes,
3055 ARRAY_SIZE(rt5645_specific_dapm_routes));
3056 break;
3057 case CODEC_TYPE_RT5650:
3058 snd_soc_dapm_new_controls(&codec->dapm,
3059 rt5650_specific_dapm_widgets,
3060 ARRAY_SIZE(rt5650_specific_dapm_widgets));
3061 snd_soc_dapm_add_routes(&codec->dapm,
3062 rt5650_specific_dapm_routes,
3063 ARRAY_SIZE(rt5650_specific_dapm_routes));
3064 break;
3065 }
3066
Lars-Peter Clausenbd1204c2015-04-27 22:13:24 +02003067 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
Oder Chiou1319b2f2014-04-28 19:59:10 +08003068
Bard Liaobb656ad2014-11-05 15:02:08 +08003069 /* for JD function */
Bard Liaoac4fc3e2015-05-05 21:42:01 +08003070 if (rt5645->pdata.jd_mode) {
Bard Liaobb656ad2014-11-05 15:02:08 +08003071 snd_soc_dapm_force_enable_pin(&codec->dapm, "JD Power");
3072 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
3073 snd_soc_dapm_sync(&codec->dapm);
3074 }
3075
Oder Chiou1319b2f2014-04-28 19:59:10 +08003076 return 0;
3077}
3078
3079static int rt5645_remove(struct snd_soc_codec *codec)
3080{
3081 rt5645_reset(codec);
3082 return 0;
3083}
3084
3085#ifdef CONFIG_PM
3086static int rt5645_suspend(struct snd_soc_codec *codec)
3087{
3088 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3089
3090 regcache_cache_only(rt5645->regmap, true);
3091 regcache_mark_dirty(rt5645->regmap);
3092
3093 return 0;
3094}
3095
3096static int rt5645_resume(struct snd_soc_codec *codec)
3097{
3098 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3099
3100 regcache_cache_only(rt5645->regmap, false);
Oder Chiou0f776ef2014-05-08 14:47:37 +08003101 regcache_sync(rt5645->regmap);
Oder Chiou1319b2f2014-04-28 19:59:10 +08003102
3103 return 0;
3104}
3105#else
3106#define rt5645_suspend NULL
3107#define rt5645_resume NULL
3108#endif
3109
3110#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3111#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3112 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3113
Oder Chiou9e22f782014-05-08 14:47:35 +08003114static struct snd_soc_dai_ops rt5645_aif_dai_ops = {
Oder Chiou1319b2f2014-04-28 19:59:10 +08003115 .hw_params = rt5645_hw_params,
3116 .set_fmt = rt5645_set_dai_fmt,
3117 .set_sysclk = rt5645_set_dai_sysclk,
3118 .set_tdm_slot = rt5645_set_tdm_slot,
3119 .set_pll = rt5645_set_dai_pll,
3120};
3121
Oder Chiou9e22f782014-05-08 14:47:35 +08003122static struct snd_soc_dai_driver rt5645_dai[] = {
Oder Chiou1319b2f2014-04-28 19:59:10 +08003123 {
3124 .name = "rt5645-aif1",
3125 .id = RT5645_AIF1,
3126 .playback = {
3127 .stream_name = "AIF1 Playback",
3128 .channels_min = 1,
3129 .channels_max = 2,
3130 .rates = RT5645_STEREO_RATES,
3131 .formats = RT5645_FORMATS,
3132 },
3133 .capture = {
3134 .stream_name = "AIF1 Capture",
3135 .channels_min = 1,
3136 .channels_max = 2,
3137 .rates = RT5645_STEREO_RATES,
3138 .formats = RT5645_FORMATS,
3139 },
3140 .ops = &rt5645_aif_dai_ops,
3141 },
3142 {
3143 .name = "rt5645-aif2",
3144 .id = RT5645_AIF2,
3145 .playback = {
3146 .stream_name = "AIF2 Playback",
3147 .channels_min = 1,
3148 .channels_max = 2,
3149 .rates = RT5645_STEREO_RATES,
3150 .formats = RT5645_FORMATS,
3151 },
3152 .capture = {
3153 .stream_name = "AIF2 Capture",
3154 .channels_min = 1,
3155 .channels_max = 2,
3156 .rates = RT5645_STEREO_RATES,
3157 .formats = RT5645_FORMATS,
3158 },
3159 .ops = &rt5645_aif_dai_ops,
3160 },
3161};
3162
3163static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
3164 .probe = rt5645_probe,
3165 .remove = rt5645_remove,
3166 .suspend = rt5645_suspend,
3167 .resume = rt5645_resume,
3168 .set_bias_level = rt5645_set_bias_level,
3169 .idle_bias_off = true,
3170 .controls = rt5645_snd_controls,
3171 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
3172 .dapm_widgets = rt5645_dapm_widgets,
3173 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
3174 .dapm_routes = rt5645_dapm_routes,
3175 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
3176};
3177
3178static const struct regmap_config rt5645_regmap = {
3179 .reg_bits = 8,
3180 .val_bits = 16,
Bard Liaoafefc122015-03-27 20:19:07 +08003181 .use_single_rw = true,
Oder Chiou1319b2f2014-04-28 19:59:10 +08003182 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3183 RT5645_PR_SPACING),
3184 .volatile_reg = rt5645_volatile_register,
3185 .readable_reg = rt5645_readable_register,
3186
3187 .cache_type = REGCACHE_RBTREE,
3188 .reg_defaults = rt5645_reg,
3189 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3190 .ranges = rt5645_ranges,
3191 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3192};
3193
3194static const struct i2c_device_id rt5645_i2c_id[] = {
3195 { "rt5645", 0 },
Bard Liao5c4ca992015-01-21 20:50:15 +08003196 { "rt5650", 0 },
Oder Chiou1319b2f2014-04-28 19:59:10 +08003197 { }
3198};
3199MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3200
Fang, Yang A3168c202015-04-23 16:35:17 -07003201#ifdef CONFIG_ACPI
3202static struct acpi_device_id rt5645_acpi_match[] = {
3203 { "10EC5645", 0 },
3204 { "10EC5650", 0 },
3205 {},
3206};
3207MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3208#endif
3209
Fang, Yang A78c34fd2015-04-24 17:50:54 -07003210static struct rt5645_platform_data *rt5645_pdata;
3211
3212static struct rt5645_platform_data strago_platform_data = {
Bard Liaoac4fc3e2015-05-05 21:42:01 +08003213 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
Fang, Yang A78c34fd2015-04-24 17:50:54 -07003214 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
Fang, Yang A78c34fd2015-04-24 17:50:54 -07003215 .jd_mode = 3,
3216};
3217
3218static int strago_quirk_cb(const struct dmi_system_id *id)
3219{
3220 rt5645_pdata = &strago_platform_data;
3221
3222 return 1;
3223}
3224
Sudip Mukherjeec0d44e52015-04-28 17:51:41 +05303225static struct dmi_system_id dmi_platform_intel_braswell[] = {
Fang, Yang A78c34fd2015-04-24 17:50:54 -07003226 {
3227 .ident = "Intel Strago",
3228 .callback = strago_quirk_cb,
3229 .matches = {
3230 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3231 },
3232 },
3233 { }
3234};
3235
Oder Chiou48edaa42015-06-12 14:47:36 +08003236static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
3237{
3238 rt5645->pdata.in2_diff = device_property_read_bool(dev,
3239 "realtek,in2-differential");
3240 device_property_read_u32(dev,
3241 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin);
3242 device_property_read_u32(dev,
3243 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin);
3244 device_property_read_u32(dev,
3245 "realtek,jd-mode", &rt5645->pdata.jd_mode);
3246
3247 return 0;
3248}
3249
Oder Chiou1319b2f2014-04-28 19:59:10 +08003250static int rt5645_i2c_probe(struct i2c_client *i2c,
3251 const struct i2c_device_id *id)
3252{
3253 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
3254 struct rt5645_priv *rt5645;
3255 int ret;
3256 unsigned int val;
3257
3258 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
3259 GFP_KERNEL);
3260 if (rt5645 == NULL)
3261 return -ENOMEM;
3262
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08003263 rt5645->i2c = i2c;
Oder Chiou1319b2f2014-04-28 19:59:10 +08003264 i2c_set_clientdata(i2c, rt5645);
3265
Oder Chiou48edaa42015-06-12 14:47:36 +08003266 if (pdata)
Oder Chiou1319b2f2014-04-28 19:59:10 +08003267 rt5645->pdata = *pdata;
Oder Chiou48edaa42015-06-12 14:47:36 +08003268 else if (dmi_check_system(dmi_platform_intel_braswell))
3269 rt5645->pdata = *rt5645_pdata;
3270 else
3271 rt5645_parse_dt(rt5645, &i2c->dev);
Oder Chiou1319b2f2014-04-28 19:59:10 +08003272
Axel Lin25c88882015-06-12 17:19:15 +08003273 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
3274 GPIOD_IN);
Oder Chiou0b0cefc2015-06-10 14:27:57 +08003275
3276 if (IS_ERR(rt5645->gpiod_hp_det)) {
Oder Chiou0b0cefc2015-06-10 14:27:57 +08003277 dev_err(&i2c->dev, "failed to initialize gpiod\n");
Axel Lin25c88882015-06-12 17:19:15 +08003278 return PTR_ERR(rt5645->gpiod_hp_det);
Oder Chiou0b0cefc2015-06-10 14:27:57 +08003279 }
3280
Oder Chiou1319b2f2014-04-28 19:59:10 +08003281 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
3282 if (IS_ERR(rt5645->regmap)) {
3283 ret = PTR_ERR(rt5645->regmap);
3284 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3285 ret);
3286 return ret;
3287 }
3288
3289 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val);
Bard Liao5c4ca992015-01-21 20:50:15 +08003290
3291 switch (val) {
3292 case RT5645_DEVICE_ID:
3293 rt5645->codec_type = CODEC_TYPE_RT5645;
3294 break;
3295 case RT5650_DEVICE_ID:
3296 rt5645->codec_type = CODEC_TYPE_RT5650;
3297 break;
3298 default:
Oder Chiou1319b2f2014-04-28 19:59:10 +08003299 dev_err(&i2c->dev,
Bard Liao5c4ca992015-01-21 20:50:15 +08003300 "Device with ID register %x is not rt5645 or rt5650\n",
3301 val);
Oder Chiou1319b2f2014-04-28 19:59:10 +08003302 return -ENODEV;
3303 }
3304
John Lind12d6c42015-05-12 20:43:02 +08003305 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3306 ret = rt5650_calibration(rt5645);
3307
3308 if (ret < 0)
3309 pr_err("calibration failed!\n");
3310 }
3311
Oder Chiou1319b2f2014-04-28 19:59:10 +08003312 regmap_write(rt5645->regmap, RT5645_RESET, 0);
3313
3314 ret = regmap_register_patch(rt5645->regmap, init_list,
3315 ARRAY_SIZE(init_list));
3316 if (ret != 0)
3317 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3318
Bard Liao5c4ca992015-01-21 20:50:15 +08003319 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3320 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
3321 ARRAY_SIZE(rt5650_init_list));
3322 if (ret != 0)
3323 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
3324 ret);
3325 }
3326
Oder Chiou1319b2f2014-04-28 19:59:10 +08003327 if (rt5645->pdata.in2_diff)
3328 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
3329 RT5645_IN_DF2, RT5645_IN_DF2);
3330
Bard Liaoac4fc3e2015-05-05 21:42:01 +08003331 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
Oder Chiou1319b2f2014-04-28 19:59:10 +08003332 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3333 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
Bard Liaoac4fc3e2015-05-05 21:42:01 +08003334 }
3335 switch (rt5645->pdata.dmic1_data_pin) {
3336 case RT5645_DMIC_DATA_IN2N:
3337 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3338 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
3339 break;
Oder Chiou1319b2f2014-04-28 19:59:10 +08003340
Bard Liaoac4fc3e2015-05-05 21:42:01 +08003341 case RT5645_DMIC_DATA_GPIO5:
3342 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3343 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
3344 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3345 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
3346 break;
Oder Chiou1319b2f2014-04-28 19:59:10 +08003347
Bard Liaoac4fc3e2015-05-05 21:42:01 +08003348 case RT5645_DMIC_DATA_GPIO11:
3349 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3350 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
3351 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3352 RT5645_GP11_PIN_MASK,
3353 RT5645_GP11_PIN_DMIC1_SDA);
3354 break;
Oder Chiou1319b2f2014-04-28 19:59:10 +08003355
Bard Liaoac4fc3e2015-05-05 21:42:01 +08003356 default:
3357 break;
Oder Chiou1319b2f2014-04-28 19:59:10 +08003358 }
3359
Bard Liaoac4fc3e2015-05-05 21:42:01 +08003360 switch (rt5645->pdata.dmic2_data_pin) {
3361 case RT5645_DMIC_DATA_IN2P:
3362 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3363 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
3364 break;
3365
3366 case RT5645_DMIC_DATA_GPIO6:
3367 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3368 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
3369 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3370 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
3371 break;
3372
3373 case RT5645_DMIC_DATA_GPIO10:
3374 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3375 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
3376 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3377 RT5645_GP10_PIN_MASK,
3378 RT5645_GP10_PIN_DMIC2_SDA);
3379 break;
3380
3381 case RT5645_DMIC_DATA_GPIO12:
3382 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3383 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
3384 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3385 RT5645_GP12_PIN_MASK,
3386 RT5645_GP12_PIN_DMIC2_SDA);
3387 break;
3388
3389 default:
3390 break;
Bard Liaobb656ad2014-11-05 15:02:08 +08003391 }
3392
Bard Liao2d4e2d02014-11-18 16:50:18 +08003393 if (rt5645->pdata.jd_mode) {
Bard Liaoac4fc3e2015-05-05 21:42:01 +08003394 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3395 RT5645_IRQ_CLK_GATE_CTRL,
3396 RT5645_IRQ_CLK_GATE_CTRL);
3397 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3398 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
Bard Liaoac4fc3e2015-05-05 21:42:01 +08003399 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3400 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
Bard Liao2d4e2d02014-11-18 16:50:18 +08003401 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3402 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
3403 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3404 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
3405 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
3406 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
3407 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3408 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
3409 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3410 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3411 switch (rt5645->pdata.jd_mode) {
3412 case 1:
3413 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3414 RT5645_JD1_MODE_MASK,
3415 RT5645_JD1_MODE_0);
3416 break;
3417 case 2:
3418 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3419 RT5645_JD1_MODE_MASK,
3420 RT5645_JD1_MODE_1);
3421 break;
3422 case 3:
3423 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3424 RT5645_JD1_MODE_MASK,
3425 RT5645_JD1_MODE_2);
3426 break;
3427 default:
3428 break;
3429 }
3430 }
3431
Nicolas Boichat7ea34702015-06-05 18:42:12 +08003432 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
3433
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08003434 if (rt5645->i2c->irq) {
3435 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
3436 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3437 | IRQF_ONESHOT, "rt5645", rt5645);
3438 if (ret)
3439 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
3440 }
3441
Axel Lindd56eba2014-06-10 11:36:41 +08003442 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
3443 rt5645_dai, ARRAY_SIZE(rt5645_dai));
Oder Chiou1319b2f2014-04-28 19:59:10 +08003444}
3445
3446static int rt5645_i2c_remove(struct i2c_client *i2c)
3447{
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08003448 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
3449
3450 if (i2c->irq)
3451 free_irq(i2c->irq, rt5645);
3452
Oder Chioucd6e82b2014-10-07 10:25:37 +08003453 cancel_delayed_work_sync(&rt5645->jack_detect_work);
3454
Oder Chiou1319b2f2014-04-28 19:59:10 +08003455 snd_soc_unregister_codec(&i2c->dev);
3456
3457 return 0;
3458}
3459
Oder Chiou9e22f782014-05-08 14:47:35 +08003460static struct i2c_driver rt5645_i2c_driver = {
Oder Chiou1319b2f2014-04-28 19:59:10 +08003461 .driver = {
3462 .name = "rt5645",
3463 .owner = THIS_MODULE,
Fang, Yang A3168c202015-04-23 16:35:17 -07003464 .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
Oder Chiou1319b2f2014-04-28 19:59:10 +08003465 },
3466 .probe = rt5645_i2c_probe,
3467 .remove = rt5645_i2c_remove,
3468 .id_table = rt5645_i2c_id,
3469};
3470module_i2c_driver(rt5645_i2c_driver);
3471
3472MODULE_DESCRIPTION("ASoC RT5645 driver");
3473MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3474MODULE_LICENSE("GPL v2");