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Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001/*
2 * SuperH Timer Support - CMT
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Magnus Damm3fb1b6a2009-01-22 09:55:59 +000014 */
15
Magnus Damm3fb1b6a2009-01-22 09:55:59 +000016#include <linux/clk.h>
Magnus Damm3fb1b6a2009-01-22 09:55:59 +000017#include <linux/clockchips.h>
Laurent Pincharte7a9bcc2014-02-12 16:56:44 +010018#include <linux/clocksource.h>
19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/irq.h>
Paul Gortmaker7deeab52011-07-03 13:36:22 -040026#include <linux/module.h>
Laurent Pincharte7a9bcc2014-02-12 16:56:44 +010027#include <linux/platform_device.h>
Rafael J. Wysocki615a4452012-03-13 22:40:06 +010028#include <linux/pm_domain.h>
Rafael J. Wysockibad81382012-08-06 01:48:57 +020029#include <linux/pm_runtime.h>
Laurent Pincharte7a9bcc2014-02-12 16:56:44 +010030#include <linux/sh_timer.h>
31#include <linux/slab.h>
32#include <linux/spinlock.h>
Magnus Damm3fb1b6a2009-01-22 09:55:59 +000033
Laurent Pinchart2653caf2014-01-27 22:04:17 +010034struct sh_cmt_device;
Laurent Pinchart7269f932014-01-27 15:29:19 +010035
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +010036/*
37 * The CMT comes in 5 different identified flavours, depending not only on the
38 * SoC but also on the particular instance. The following table lists the main
39 * characteristics of those flavours.
40 *
41 * 16B 32B 32B-F 48B 48B-2
42 * -----------------------------------------------------------------------------
43 * Channels 2 1/4 1 6 2/8
44 * Control Width 16 16 16 16 32
45 * Counter Width 16 32 32 32/48 32/48
46 * Shared Start/Stop Y Y Y Y N
47 *
48 * The 48-bit gen2 version has a per-channel start/stop register located in the
49 * channel registers block. All other versions have a shared start/stop register
50 * located in the global space.
51 *
Laurent Pinchart81b3b272014-01-28 12:36:48 +010052 * Channels are indexed from 0 to N-1 in the documentation. The channel index
53 * infers the start/stop bit position in the control register and the channel
54 * registers block address. Some CMT instances have a subset of channels
55 * available, in which case the index in the documentation doesn't match the
56 * "real" index as implemented in hardware. This is for instance the case with
57 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
58 * in the documentation but using start/stop bit 5 and having its registers
59 * block at 0x60.
60 *
61 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +010062 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
63 */
64
65enum sh_cmt_model {
66 SH_CMT_16BIT,
67 SH_CMT_32BIT,
68 SH_CMT_32BIT_FAST,
69 SH_CMT_48BIT,
70 SH_CMT_48BIT_GEN2,
71};
72
73struct sh_cmt_info {
74 enum sh_cmt_model model;
75
76 unsigned long width; /* 16 or 32 bit version of hardware block */
77 unsigned long overflow_bit;
78 unsigned long clear_bits;
79
80 /* callbacks for CMSTR and CMCSR access */
81 unsigned long (*read_control)(void __iomem *base, unsigned long offs);
82 void (*write_control)(void __iomem *base, unsigned long offs,
83 unsigned long value);
84
85 /* callbacks for CMCNT and CMCOR access */
86 unsigned long (*read_count)(void __iomem *base, unsigned long offs);
87 void (*write_count)(void __iomem *base, unsigned long offs,
88 unsigned long value);
89};
90
Laurent Pinchart7269f932014-01-27 15:29:19 +010091struct sh_cmt_channel {
Laurent Pinchart2653caf2014-01-27 22:04:17 +010092 struct sh_cmt_device *cmt;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +000093
Laurent Pinchart81b3b272014-01-28 12:36:48 +010094 unsigned int index; /* Index in the documentation */
95 unsigned int hwidx; /* Real hardware index */
Laurent Pinchartc924d2d2014-01-27 22:04:17 +010096
Laurent Pinchart81b3b272014-01-28 12:36:48 +010097 void __iomem *iostart;
98 void __iomem *ioctrl;
99
100 unsigned int timer_bit;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000101 unsigned long flags;
102 unsigned long match_value;
103 unsigned long next_match_value;
104 unsigned long max_match_value;
105 unsigned long rate;
Paul Mundt7d0c3992012-05-25 13:36:43 +0900106 raw_spinlock_t lock;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000107 struct clock_event_device ced;
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000108 struct clocksource cs;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000109 unsigned long total_cycles;
Rafael J. Wysockibad81382012-08-06 01:48:57 +0200110 bool cs_enabled;
Laurent Pinchart7269f932014-01-27 15:29:19 +0100111};
112
Laurent Pinchart2653caf2014-01-27 22:04:17 +0100113struct sh_cmt_device {
Laurent Pinchart7269f932014-01-27 15:29:19 +0100114 struct platform_device *pdev;
115
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100116 const struct sh_cmt_info *info;
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100117 bool legacy;
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100118
Laurent Pinchart36f1ac92014-01-27 22:04:17 +0100119 void __iomem *mapbase_ch;
Laurent Pinchart7269f932014-01-27 15:29:19 +0100120 void __iomem *mapbase;
Laurent Pinchart7269f932014-01-27 15:29:19 +0100121 struct clk *clk;
122
Laurent Pinchartf5ec9b12014-01-27 22:04:17 +0100123 struct sh_cmt_channel *channels;
124 unsigned int num_channels;
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100125
126 bool has_clockevent;
127 bool has_clocksource;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000128};
129
Laurent Pinchartd14be992014-01-29 00:33:08 +0100130#define SH_CMT16_CMCSR_CMF (1 << 7)
131#define SH_CMT16_CMCSR_CMIE (1 << 6)
132#define SH_CMT16_CMCSR_CKS8 (0 << 0)
133#define SH_CMT16_CMCSR_CKS32 (1 << 0)
134#define SH_CMT16_CMCSR_CKS128 (2 << 0)
135#define SH_CMT16_CMCSR_CKS512 (3 << 0)
136#define SH_CMT16_CMCSR_CKS_MASK (3 << 0)
137
138#define SH_CMT32_CMCSR_CMF (1 << 15)
139#define SH_CMT32_CMCSR_OVF (1 << 14)
140#define SH_CMT32_CMCSR_WRFLG (1 << 13)
141#define SH_CMT32_CMCSR_STTF (1 << 12)
142#define SH_CMT32_CMCSR_STPF (1 << 11)
143#define SH_CMT32_CMCSR_SSIE (1 << 10)
144#define SH_CMT32_CMCSR_CMS (1 << 9)
145#define SH_CMT32_CMCSR_CMM (1 << 8)
146#define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7)
147#define SH_CMT32_CMCSR_CMR_NONE (0 << 4)
148#define SH_CMT32_CMCSR_CMR_DMA (1 << 4)
149#define SH_CMT32_CMCSR_CMR_IRQ (2 << 4)
150#define SH_CMT32_CMCSR_CMR_MASK (3 << 4)
151#define SH_CMT32_CMCSR_DBGIVD (1 << 3)
152#define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0)
153#define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0)
154#define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0)
155#define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0)
156#define SH_CMT32_CMCSR_CKS_MASK (7 << 0)
157
Magnus Damma6a912c2012-12-14 14:54:19 +0900158static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs)
Magnus Damm587acb32012-12-14 14:54:10 +0900159{
160 return ioread16(base + (offs << 1));
161}
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000162
Magnus Damma6a912c2012-12-14 14:54:19 +0900163static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs)
164{
165 return ioread32(base + (offs << 2));
166}
167
168static void sh_cmt_write16(void __iomem *base, unsigned long offs,
169 unsigned long value)
Magnus Damm587acb32012-12-14 14:54:10 +0900170{
171 iowrite16(value, base + (offs << 1));
172}
173
Magnus Damma6a912c2012-12-14 14:54:19 +0900174static void sh_cmt_write32(void __iomem *base, unsigned long offs,
175 unsigned long value)
176{
177 iowrite32(value, base + (offs << 2));
178}
179
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100180static const struct sh_cmt_info sh_cmt_info[] = {
181 [SH_CMT_16BIT] = {
182 .model = SH_CMT_16BIT,
183 .width = 16,
Laurent Pinchartd14be992014-01-29 00:33:08 +0100184 .overflow_bit = SH_CMT16_CMCSR_CMF,
185 .clear_bits = ~SH_CMT16_CMCSR_CMF,
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100186 .read_control = sh_cmt_read16,
187 .write_control = sh_cmt_write16,
188 .read_count = sh_cmt_read16,
189 .write_count = sh_cmt_write16,
190 },
191 [SH_CMT_32BIT] = {
192 .model = SH_CMT_32BIT,
193 .width = 32,
Laurent Pinchartd14be992014-01-29 00:33:08 +0100194 .overflow_bit = SH_CMT32_CMCSR_CMF,
195 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100196 .read_control = sh_cmt_read16,
197 .write_control = sh_cmt_write16,
198 .read_count = sh_cmt_read32,
199 .write_count = sh_cmt_write32,
200 },
201 [SH_CMT_32BIT_FAST] = {
202 .model = SH_CMT_32BIT_FAST,
203 .width = 32,
Laurent Pinchartd14be992014-01-29 00:33:08 +0100204 .overflow_bit = SH_CMT32_CMCSR_CMF,
205 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100206 .read_control = sh_cmt_read16,
207 .write_control = sh_cmt_write16,
208 .read_count = sh_cmt_read32,
209 .write_count = sh_cmt_write32,
210 },
211 [SH_CMT_48BIT] = {
212 .model = SH_CMT_48BIT,
213 .width = 32,
Laurent Pinchartd14be992014-01-29 00:33:08 +0100214 .overflow_bit = SH_CMT32_CMCSR_CMF,
215 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100216 .read_control = sh_cmt_read32,
217 .write_control = sh_cmt_write32,
218 .read_count = sh_cmt_read32,
219 .write_count = sh_cmt_write32,
220 },
221 [SH_CMT_48BIT_GEN2] = {
222 .model = SH_CMT_48BIT_GEN2,
223 .width = 32,
Laurent Pinchartd14be992014-01-29 00:33:08 +0100224 .overflow_bit = SH_CMT32_CMCSR_CMF,
225 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100226 .read_control = sh_cmt_read32,
227 .write_control = sh_cmt_write32,
228 .read_count = sh_cmt_read32,
229 .write_count = sh_cmt_write32,
230 },
231};
232
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000233#define CMCSR 0 /* channel register */
234#define CMCNT 1 /* channel register */
235#define CMCOR 2 /* channel register */
236
Laurent Pinchart7269f932014-01-27 15:29:19 +0100237static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
Magnus Damm1b56b962012-12-14 14:54:00 +0900238{
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100239 if (ch->iostart)
240 return ch->cmt->info->read_control(ch->iostart, 0);
241 else
242 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000243}
244
Laurent Pinchart7269f932014-01-27 15:29:19 +0100245static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch,
Magnus Damm1b56b962012-12-14 14:54:00 +0900246 unsigned long value)
247{
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100248 if (ch->iostart)
249 ch->cmt->info->write_control(ch->iostart, 0, value);
250 else
251 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
252}
253
254static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
255{
256 return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
Magnus Damm1b56b962012-12-14 14:54:00 +0900257}
258
Laurent Pinchart7269f932014-01-27 15:29:19 +0100259static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch,
Magnus Damm1b56b962012-12-14 14:54:00 +0900260 unsigned long value)
261{
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100262 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
263}
264
265static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
266{
267 return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
Magnus Damm1b56b962012-12-14 14:54:00 +0900268}
269
Laurent Pinchart7269f932014-01-27 15:29:19 +0100270static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch,
Magnus Damm1b56b962012-12-14 14:54:00 +0900271 unsigned long value)
272{
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100273 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
Magnus Damm1b56b962012-12-14 14:54:00 +0900274}
275
Laurent Pinchart7269f932014-01-27 15:29:19 +0100276static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch,
Magnus Damm1b56b962012-12-14 14:54:00 +0900277 unsigned long value)
278{
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100279 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
Magnus Damm1b56b962012-12-14 14:54:00 +0900280}
281
Laurent Pinchart7269f932014-01-27 15:29:19 +0100282static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch,
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000283 int *has_wrapped)
284{
285 unsigned long v1, v2, v3;
Magnus Damm5b644c72009-04-28 08:17:54 +0000286 int o1, o2;
287
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100288 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000289
290 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
291 do {
Magnus Damm5b644c72009-04-28 08:17:54 +0000292 o2 = o1;
Laurent Pinchart7269f932014-01-27 15:29:19 +0100293 v1 = sh_cmt_read_cmcnt(ch);
294 v2 = sh_cmt_read_cmcnt(ch);
295 v3 = sh_cmt_read_cmcnt(ch);
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100296 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
Magnus Damm5b644c72009-04-28 08:17:54 +0000297 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
298 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000299
Magnus Damm5b644c72009-04-28 08:17:54 +0000300 *has_wrapped = o1;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000301 return v2;
302}
303
Magnus Damm587acb32012-12-14 14:54:10 +0900304static DEFINE_RAW_SPINLOCK(sh_cmt_lock);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000305
Laurent Pinchart7269f932014-01-27 15:29:19 +0100306static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000307{
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000308 unsigned long flags, value;
309
310 /* start stop register shared by multiple timer channels */
Paul Mundt7d0c3992012-05-25 13:36:43 +0900311 raw_spin_lock_irqsave(&sh_cmt_lock, flags);
Laurent Pinchart7269f932014-01-27 15:29:19 +0100312 value = sh_cmt_read_cmstr(ch);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000313
314 if (start)
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100315 value |= 1 << ch->timer_bit;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000316 else
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100317 value &= ~(1 << ch->timer_bit);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000318
Laurent Pinchart7269f932014-01-27 15:29:19 +0100319 sh_cmt_write_cmstr(ch, value);
Paul Mundt7d0c3992012-05-25 13:36:43 +0900320 raw_spin_unlock_irqrestore(&sh_cmt_lock, flags);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000321}
322
Laurent Pinchart7269f932014-01-27 15:29:19 +0100323static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000324{
Magnus Damm3f7e5e22011-07-13 07:59:48 +0000325 int k, ret;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000326
Laurent Pinchart7269f932014-01-27 15:29:19 +0100327 pm_runtime_get_sync(&ch->cmt->pdev->dev);
328 dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
Rafael J. Wysockibad81382012-08-06 01:48:57 +0200329
Paul Mundt9436b4a2011-05-31 15:26:42 +0900330 /* enable clock */
Laurent Pinchart7269f932014-01-27 15:29:19 +0100331 ret = clk_enable(ch->cmt->clk);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000332 if (ret) {
Laurent Pinchart740a9512014-01-27 22:04:17 +0100333 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
334 ch->index);
Magnus Damm3f7e5e22011-07-13 07:59:48 +0000335 goto err0;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000336 }
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000337
338 /* make sure channel is disabled */
Laurent Pinchart7269f932014-01-27 15:29:19 +0100339 sh_cmt_start_stop_ch(ch, 0);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000340
341 /* configure channel, periodic mode and maximum timeout */
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100342 if (ch->cmt->info->width == 16) {
Laurent Pinchart7269f932014-01-27 15:29:19 +0100343 *rate = clk_get_rate(ch->cmt->clk) / 512;
Laurent Pinchartd14be992014-01-29 00:33:08 +0100344 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
345 SH_CMT16_CMCSR_CKS512);
Magnus Damm3014f472009-04-29 14:50:37 +0000346 } else {
Laurent Pinchart7269f932014-01-27 15:29:19 +0100347 *rate = clk_get_rate(ch->cmt->clk) / 8;
Laurent Pinchartd14be992014-01-29 00:33:08 +0100348 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
349 SH_CMT32_CMCSR_CMTOUT_IE |
350 SH_CMT32_CMCSR_CMR_IRQ |
351 SH_CMT32_CMCSR_CKS_RCLK8);
Magnus Damm3014f472009-04-29 14:50:37 +0000352 }
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000353
Laurent Pinchart7269f932014-01-27 15:29:19 +0100354 sh_cmt_write_cmcor(ch, 0xffffffff);
355 sh_cmt_write_cmcnt(ch, 0);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000356
Magnus Damm3f7e5e22011-07-13 07:59:48 +0000357 /*
358 * According to the sh73a0 user's manual, as CMCNT can be operated
359 * only by the RCLK (Pseudo 32 KHz), there's one restriction on
360 * modifying CMCNT register; two RCLK cycles are necessary before
361 * this register is either read or any modification of the value
362 * it holds is reflected in the LSI's actual operation.
363 *
364 * While at it, we're supposed to clear out the CMCNT as of this
365 * moment, so make sure it's processed properly here. This will
366 * take RCLKx2 at maximum.
367 */
368 for (k = 0; k < 100; k++) {
Laurent Pinchart7269f932014-01-27 15:29:19 +0100369 if (!sh_cmt_read_cmcnt(ch))
Magnus Damm3f7e5e22011-07-13 07:59:48 +0000370 break;
371 udelay(1);
372 }
373
Laurent Pinchart7269f932014-01-27 15:29:19 +0100374 if (sh_cmt_read_cmcnt(ch)) {
Laurent Pinchart740a9512014-01-27 22:04:17 +0100375 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
376 ch->index);
Magnus Damm3f7e5e22011-07-13 07:59:48 +0000377 ret = -ETIMEDOUT;
378 goto err1;
379 }
380
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000381 /* enable channel */
Laurent Pinchart7269f932014-01-27 15:29:19 +0100382 sh_cmt_start_stop_ch(ch, 1);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000383 return 0;
Magnus Damm3f7e5e22011-07-13 07:59:48 +0000384 err1:
385 /* stop clock */
Laurent Pinchart7269f932014-01-27 15:29:19 +0100386 clk_disable(ch->cmt->clk);
Magnus Damm3f7e5e22011-07-13 07:59:48 +0000387
388 err0:
389 return ret;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000390}
391
Laurent Pinchart7269f932014-01-27 15:29:19 +0100392static void sh_cmt_disable(struct sh_cmt_channel *ch)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000393{
394 /* disable channel */
Laurent Pinchart7269f932014-01-27 15:29:19 +0100395 sh_cmt_start_stop_ch(ch, 0);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000396
Magnus Dammbe890a12009-06-17 05:04:04 +0000397 /* disable interrupts in CMT block */
Laurent Pinchart7269f932014-01-27 15:29:19 +0100398 sh_cmt_write_cmcsr(ch, 0);
Magnus Dammbe890a12009-06-17 05:04:04 +0000399
Paul Mundt9436b4a2011-05-31 15:26:42 +0900400 /* stop clock */
Laurent Pinchart7269f932014-01-27 15:29:19 +0100401 clk_disable(ch->cmt->clk);
Rafael J. Wysockibad81382012-08-06 01:48:57 +0200402
Laurent Pinchart7269f932014-01-27 15:29:19 +0100403 dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
404 pm_runtime_put(&ch->cmt->pdev->dev);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000405}
406
407/* private flags */
408#define FLAG_CLOCKEVENT (1 << 0)
409#define FLAG_CLOCKSOURCE (1 << 1)
410#define FLAG_REPROGRAM (1 << 2)
411#define FLAG_SKIPEVENT (1 << 3)
412#define FLAG_IRQCONTEXT (1 << 4)
413
Laurent Pinchart7269f932014-01-27 15:29:19 +0100414static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000415 int absolute)
416{
417 unsigned long new_match;
Laurent Pinchart7269f932014-01-27 15:29:19 +0100418 unsigned long value = ch->next_match_value;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000419 unsigned long delay = 0;
420 unsigned long now = 0;
421 int has_wrapped;
422
Laurent Pinchart7269f932014-01-27 15:29:19 +0100423 now = sh_cmt_get_counter(ch, &has_wrapped);
424 ch->flags |= FLAG_REPROGRAM; /* force reprogram */
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000425
426 if (has_wrapped) {
427 /* we're competing with the interrupt handler.
428 * -> let the interrupt handler reprogram the timer.
429 * -> interrupt number two handles the event.
430 */
Laurent Pinchart7269f932014-01-27 15:29:19 +0100431 ch->flags |= FLAG_SKIPEVENT;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000432 return;
433 }
434
435 if (absolute)
436 now = 0;
437
438 do {
439 /* reprogram the timer hardware,
440 * but don't save the new match value yet.
441 */
442 new_match = now + value + delay;
Laurent Pinchart7269f932014-01-27 15:29:19 +0100443 if (new_match > ch->max_match_value)
444 new_match = ch->max_match_value;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000445
Laurent Pinchart7269f932014-01-27 15:29:19 +0100446 sh_cmt_write_cmcor(ch, new_match);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000447
Laurent Pinchart7269f932014-01-27 15:29:19 +0100448 now = sh_cmt_get_counter(ch, &has_wrapped);
449 if (has_wrapped && (new_match > ch->match_value)) {
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000450 /* we are changing to a greater match value,
451 * so this wrap must be caused by the counter
452 * matching the old value.
453 * -> first interrupt reprograms the timer.
454 * -> interrupt number two handles the event.
455 */
Laurent Pinchart7269f932014-01-27 15:29:19 +0100456 ch->flags |= FLAG_SKIPEVENT;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000457 break;
458 }
459
460 if (has_wrapped) {
461 /* we are changing to a smaller match value,
462 * so the wrap must be caused by the counter
463 * matching the new value.
464 * -> save programmed match value.
465 * -> let isr handle the event.
466 */
Laurent Pinchart7269f932014-01-27 15:29:19 +0100467 ch->match_value = new_match;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000468 break;
469 }
470
471 /* be safe: verify hardware settings */
472 if (now < new_match) {
473 /* timer value is below match value, all good.
474 * this makes sure we won't miss any match events.
475 * -> save programmed match value.
476 * -> let isr handle the event.
477 */
Laurent Pinchart7269f932014-01-27 15:29:19 +0100478 ch->match_value = new_match;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000479 break;
480 }
481
482 /* the counter has reached a value greater
483 * than our new match value. and since the
484 * has_wrapped flag isn't set we must have
485 * programmed a too close event.
486 * -> increase delay and retry.
487 */
488 if (delay)
489 delay <<= 1;
490 else
491 delay = 1;
492
493 if (!delay)
Laurent Pinchart740a9512014-01-27 22:04:17 +0100494 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
495 ch->index);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000496
497 } while (delay);
498}
499
Laurent Pinchart7269f932014-01-27 15:29:19 +0100500static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
Takashi YOSHII65ada542010-12-17 07:25:09 +0000501{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100502 if (delta > ch->max_match_value)
Laurent Pinchart740a9512014-01-27 22:04:17 +0100503 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
504 ch->index);
Takashi YOSHII65ada542010-12-17 07:25:09 +0000505
Laurent Pinchart7269f932014-01-27 15:29:19 +0100506 ch->next_match_value = delta;
507 sh_cmt_clock_event_program_verify(ch, 0);
Takashi YOSHII65ada542010-12-17 07:25:09 +0000508}
509
Laurent Pinchart7269f932014-01-27 15:29:19 +0100510static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000511{
512 unsigned long flags;
513
Laurent Pinchart7269f932014-01-27 15:29:19 +0100514 raw_spin_lock_irqsave(&ch->lock, flags);
515 __sh_cmt_set_next(ch, delta);
516 raw_spin_unlock_irqrestore(&ch->lock, flags);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000517}
518
519static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
520{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100521 struct sh_cmt_channel *ch = dev_id;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000522
523 /* clear flags */
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100524 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
525 ch->cmt->info->clear_bits);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000526
527 /* update clock source counter to begin with if enabled
528 * the wrap flag should be cleared by the timer specific
529 * isr before we end up here.
530 */
Laurent Pinchart7269f932014-01-27 15:29:19 +0100531 if (ch->flags & FLAG_CLOCKSOURCE)
532 ch->total_cycles += ch->match_value + 1;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000533
Laurent Pinchart7269f932014-01-27 15:29:19 +0100534 if (!(ch->flags & FLAG_REPROGRAM))
535 ch->next_match_value = ch->max_match_value;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000536
Laurent Pinchart7269f932014-01-27 15:29:19 +0100537 ch->flags |= FLAG_IRQCONTEXT;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000538
Laurent Pinchart7269f932014-01-27 15:29:19 +0100539 if (ch->flags & FLAG_CLOCKEVENT) {
540 if (!(ch->flags & FLAG_SKIPEVENT)) {
541 if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
542 ch->next_match_value = ch->max_match_value;
543 ch->flags |= FLAG_REPROGRAM;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000544 }
545
Laurent Pinchart7269f932014-01-27 15:29:19 +0100546 ch->ced.event_handler(&ch->ced);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000547 }
548 }
549
Laurent Pinchart7269f932014-01-27 15:29:19 +0100550 ch->flags &= ~FLAG_SKIPEVENT;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000551
Laurent Pinchart7269f932014-01-27 15:29:19 +0100552 if (ch->flags & FLAG_REPROGRAM) {
553 ch->flags &= ~FLAG_REPROGRAM;
554 sh_cmt_clock_event_program_verify(ch, 1);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000555
Laurent Pinchart7269f932014-01-27 15:29:19 +0100556 if (ch->flags & FLAG_CLOCKEVENT)
557 if ((ch->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
558 || (ch->match_value == ch->next_match_value))
559 ch->flags &= ~FLAG_REPROGRAM;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000560 }
561
Laurent Pinchart7269f932014-01-27 15:29:19 +0100562 ch->flags &= ~FLAG_IRQCONTEXT;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000563
564 return IRQ_HANDLED;
565}
566
Laurent Pinchart7269f932014-01-27 15:29:19 +0100567static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000568{
569 int ret = 0;
570 unsigned long flags;
571
Laurent Pinchart7269f932014-01-27 15:29:19 +0100572 raw_spin_lock_irqsave(&ch->lock, flags);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000573
Laurent Pinchart7269f932014-01-27 15:29:19 +0100574 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
575 ret = sh_cmt_enable(ch, &ch->rate);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000576
577 if (ret)
578 goto out;
Laurent Pinchart7269f932014-01-27 15:29:19 +0100579 ch->flags |= flag;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000580
581 /* setup timeout if no clockevent */
Laurent Pinchart7269f932014-01-27 15:29:19 +0100582 if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT)))
583 __sh_cmt_set_next(ch, ch->max_match_value);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000584 out:
Laurent Pinchart7269f932014-01-27 15:29:19 +0100585 raw_spin_unlock_irqrestore(&ch->lock, flags);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000586
587 return ret;
588}
589
Laurent Pinchart7269f932014-01-27 15:29:19 +0100590static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000591{
592 unsigned long flags;
593 unsigned long f;
594
Laurent Pinchart7269f932014-01-27 15:29:19 +0100595 raw_spin_lock_irqsave(&ch->lock, flags);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000596
Laurent Pinchart7269f932014-01-27 15:29:19 +0100597 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
598 ch->flags &= ~flag;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000599
Laurent Pinchart7269f932014-01-27 15:29:19 +0100600 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
601 sh_cmt_disable(ch);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000602
603 /* adjust the timeout to maximum if only clocksource left */
Laurent Pinchart7269f932014-01-27 15:29:19 +0100604 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
605 __sh_cmt_set_next(ch, ch->max_match_value);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000606
Laurent Pinchart7269f932014-01-27 15:29:19 +0100607 raw_spin_unlock_irqrestore(&ch->lock, flags);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000608}
609
Laurent Pinchart7269f932014-01-27 15:29:19 +0100610static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000611{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100612 return container_of(cs, struct sh_cmt_channel, cs);
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000613}
614
615static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
616{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100617 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000618 unsigned long flags, raw;
619 unsigned long value;
620 int has_wrapped;
621
Laurent Pinchart7269f932014-01-27 15:29:19 +0100622 raw_spin_lock_irqsave(&ch->lock, flags);
623 value = ch->total_cycles;
624 raw = sh_cmt_get_counter(ch, &has_wrapped);
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000625
626 if (unlikely(has_wrapped))
Laurent Pinchart7269f932014-01-27 15:29:19 +0100627 raw += ch->match_value + 1;
628 raw_spin_unlock_irqrestore(&ch->lock, flags);
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000629
630 return value + raw;
631}
632
633static int sh_cmt_clocksource_enable(struct clocksource *cs)
634{
Magnus Damm3593f5f2011-04-25 22:32:11 +0900635 int ret;
Laurent Pinchart7269f932014-01-27 15:29:19 +0100636 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000637
Laurent Pinchart7269f932014-01-27 15:29:19 +0100638 WARN_ON(ch->cs_enabled);
Rafael J. Wysockibad81382012-08-06 01:48:57 +0200639
Laurent Pinchart7269f932014-01-27 15:29:19 +0100640 ch->total_cycles = 0;
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000641
Laurent Pinchart7269f932014-01-27 15:29:19 +0100642 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
Rafael J. Wysockibad81382012-08-06 01:48:57 +0200643 if (!ret) {
Laurent Pinchart7269f932014-01-27 15:29:19 +0100644 __clocksource_updatefreq_hz(cs, ch->rate);
645 ch->cs_enabled = true;
Rafael J. Wysockibad81382012-08-06 01:48:57 +0200646 }
Magnus Damm3593f5f2011-04-25 22:32:11 +0900647 return ret;
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000648}
649
650static void sh_cmt_clocksource_disable(struct clocksource *cs)
651{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100652 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
Rafael J. Wysockibad81382012-08-06 01:48:57 +0200653
Laurent Pinchart7269f932014-01-27 15:29:19 +0100654 WARN_ON(!ch->cs_enabled);
Rafael J. Wysockibad81382012-08-06 01:48:57 +0200655
Laurent Pinchart7269f932014-01-27 15:29:19 +0100656 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
657 ch->cs_enabled = false;
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000658}
659
Rafael J. Wysocki9bb5ec82012-08-06 01:43:03 +0200660static void sh_cmt_clocksource_suspend(struct clocksource *cs)
661{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100662 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
Rafael J. Wysocki9bb5ec82012-08-06 01:43:03 +0200663
Laurent Pinchart7269f932014-01-27 15:29:19 +0100664 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
665 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
Rafael J. Wysocki9bb5ec82012-08-06 01:43:03 +0200666}
667
Magnus Dammc8162882010-02-02 14:41:40 -0800668static void sh_cmt_clocksource_resume(struct clocksource *cs)
669{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100670 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
Rafael J. Wysocki9bb5ec82012-08-06 01:43:03 +0200671
Laurent Pinchart7269f932014-01-27 15:29:19 +0100672 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
673 sh_cmt_start(ch, FLAG_CLOCKSOURCE);
Magnus Dammc8162882010-02-02 14:41:40 -0800674}
675
Laurent Pinchart7269f932014-01-27 15:29:19 +0100676static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
Laurent Pinchartfb28a652014-02-19 17:00:31 +0100677 const char *name)
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000678{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100679 struct clocksource *cs = &ch->cs;
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000680
681 cs->name = name;
Laurent Pinchartfb28a652014-02-19 17:00:31 +0100682 cs->rating = 125;
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000683 cs->read = sh_cmt_clocksource_read;
684 cs->enable = sh_cmt_clocksource_enable;
685 cs->disable = sh_cmt_clocksource_disable;
Rafael J. Wysocki9bb5ec82012-08-06 01:43:03 +0200686 cs->suspend = sh_cmt_clocksource_suspend;
Magnus Dammc8162882010-02-02 14:41:40 -0800687 cs->resume = sh_cmt_clocksource_resume;
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000688 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
689 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
Paul Mundtf4d7c352010-06-02 17:10:44 +0900690
Laurent Pinchart740a9512014-01-27 22:04:17 +0100691 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
692 ch->index);
Paul Mundtf4d7c352010-06-02 17:10:44 +0900693
Magnus Damm3593f5f2011-04-25 22:32:11 +0900694 /* Register with dummy 1 Hz value, gets updated in ->enable() */
695 clocksource_register_hz(cs, 1);
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000696 return 0;
697}
698
Laurent Pinchart7269f932014-01-27 15:29:19 +0100699static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000700{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100701 return container_of(ced, struct sh_cmt_channel, ced);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000702}
703
Laurent Pinchart7269f932014-01-27 15:29:19 +0100704static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000705{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100706 struct clock_event_device *ced = &ch->ced;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000707
Laurent Pinchart7269f932014-01-27 15:29:19 +0100708 sh_cmt_start(ch, FLAG_CLOCKEVENT);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000709
710 /* TODO: calculate good shift from rate and counter bit width */
711
712 ced->shift = 32;
Laurent Pinchart7269f932014-01-27 15:29:19 +0100713 ced->mult = div_sc(ch->rate, NSEC_PER_SEC, ced->shift);
714 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000715 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
716
717 if (periodic)
Laurent Pinchart7269f932014-01-27 15:29:19 +0100718 sh_cmt_set_next(ch, ((ch->rate + HZ/2) / HZ) - 1);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000719 else
Laurent Pinchart7269f932014-01-27 15:29:19 +0100720 sh_cmt_set_next(ch, ch->max_match_value);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000721}
722
723static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
724 struct clock_event_device *ced)
725{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100726 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000727
728 /* deal with old setting first */
729 switch (ced->mode) {
730 case CLOCK_EVT_MODE_PERIODIC:
731 case CLOCK_EVT_MODE_ONESHOT:
Laurent Pinchart7269f932014-01-27 15:29:19 +0100732 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000733 break;
734 default:
735 break;
736 }
737
738 switch (mode) {
739 case CLOCK_EVT_MODE_PERIODIC:
Laurent Pinchart7269f932014-01-27 15:29:19 +0100740 dev_info(&ch->cmt->pdev->dev,
Laurent Pinchart740a9512014-01-27 22:04:17 +0100741 "ch%u: used for periodic clock events\n", ch->index);
Laurent Pinchart7269f932014-01-27 15:29:19 +0100742 sh_cmt_clock_event_start(ch, 1);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000743 break;
744 case CLOCK_EVT_MODE_ONESHOT:
Laurent Pinchart7269f932014-01-27 15:29:19 +0100745 dev_info(&ch->cmt->pdev->dev,
Laurent Pinchart740a9512014-01-27 22:04:17 +0100746 "ch%u: used for oneshot clock events\n", ch->index);
Laurent Pinchart7269f932014-01-27 15:29:19 +0100747 sh_cmt_clock_event_start(ch, 0);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000748 break;
749 case CLOCK_EVT_MODE_SHUTDOWN:
750 case CLOCK_EVT_MODE_UNUSED:
Laurent Pinchart7269f932014-01-27 15:29:19 +0100751 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000752 break;
753 default:
754 break;
755 }
756}
757
758static int sh_cmt_clock_event_next(unsigned long delta,
759 struct clock_event_device *ced)
760{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100761 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000762
763 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
Laurent Pinchart7269f932014-01-27 15:29:19 +0100764 if (likely(ch->flags & FLAG_IRQCONTEXT))
765 ch->next_match_value = delta - 1;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000766 else
Laurent Pinchart7269f932014-01-27 15:29:19 +0100767 sh_cmt_set_next(ch, delta - 1);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000768
769 return 0;
770}
771
Rafael J. Wysocki9bb5ec82012-08-06 01:43:03 +0200772static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
773{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100774 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
Laurent Pinchart57dee992013-12-14 15:07:32 +0900775
Laurent Pinchart7269f932014-01-27 15:29:19 +0100776 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
777 clk_unprepare(ch->cmt->clk);
Rafael J. Wysocki9bb5ec82012-08-06 01:43:03 +0200778}
779
780static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
781{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100782 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
Laurent Pinchart57dee992013-12-14 15:07:32 +0900783
Laurent Pinchart7269f932014-01-27 15:29:19 +0100784 clk_prepare(ch->cmt->clk);
785 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
Rafael J. Wysocki9bb5ec82012-08-06 01:43:03 +0200786}
787
Laurent Pinchartbfa76bb2014-02-21 01:24:47 +0100788static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
789 const char *name)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000790{
Laurent Pinchart7269f932014-01-27 15:29:19 +0100791 struct clock_event_device *ced = &ch->ced;
Laurent Pinchartbfa76bb2014-02-21 01:24:47 +0100792 int irq;
793 int ret;
794
795 irq = platform_get_irq(ch->cmt->pdev, ch->cmt->legacy ? 0 : ch->index);
796 if (irq < 0) {
797 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",
798 ch->index);
799 return irq;
800 }
801
802 ret = request_irq(irq, sh_cmt_interrupt,
803 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
804 dev_name(&ch->cmt->pdev->dev), ch);
805 if (ret) {
806 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
807 ch->index, irq);
808 return ret;
809 }
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000810
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000811 ced->name = name;
812 ced->features = CLOCK_EVT_FEAT_PERIODIC;
813 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
Laurent Pinchartb7fcbb02014-02-19 17:00:31 +0100814 ced->rating = 125;
Laurent Pinchartf1ebe1e2014-02-19 16:19:44 +0100815 ced->cpumask = cpu_possible_mask;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000816 ced->set_next_event = sh_cmt_clock_event_next;
817 ced->set_mode = sh_cmt_clock_event_mode;
Rafael J. Wysocki9bb5ec82012-08-06 01:43:03 +0200818 ced->suspend = sh_cmt_clock_event_suspend;
819 ced->resume = sh_cmt_clock_event_resume;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000820
Laurent Pinchart740a9512014-01-27 22:04:17 +0100821 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
822 ch->index);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000823 clockevents_register_device(ced);
Laurent Pinchartbfa76bb2014-02-21 01:24:47 +0100824
825 return 0;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000826}
827
Laurent Pinchart1d053e12014-02-17 16:04:16 +0100828static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
Laurent Pinchartfb28a652014-02-19 17:00:31 +0100829 bool clockevent, bool clocksource)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000830{
Laurent Pinchartbfa76bb2014-02-21 01:24:47 +0100831 int ret;
832
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100833 if (clockevent) {
834 ch->cmt->has_clockevent = true;
Laurent Pinchartbfa76bb2014-02-21 01:24:47 +0100835 ret = sh_cmt_register_clockevent(ch, name);
836 if (ret < 0)
837 return ret;
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100838 }
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000839
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100840 if (clocksource) {
841 ch->cmt->has_clocksource = true;
Laurent Pinchartfb28a652014-02-19 17:00:31 +0100842 sh_cmt_register_clocksource(ch, name);
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100843 }
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000844
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000845 return 0;
846}
847
Laurent Pinchart740a9512014-01-27 22:04:17 +0100848static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100849 unsigned int hwidx, bool clockevent,
850 bool clocksource, struct sh_cmt_device *cmt)
Laurent Pinchartb882e7b2014-01-27 22:04:17 +0100851{
Laurent Pinchartb882e7b2014-01-27 22:04:17 +0100852 int ret;
853
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100854 /* Skip unused channels. */
855 if (!clockevent && !clocksource)
856 return 0;
Laurent Pinchartb882e7b2014-01-27 22:04:17 +0100857
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100858 ch->cmt = cmt;
859 ch->index = index;
860 ch->hwidx = hwidx;
861
862 /*
863 * Compute the address of the channel control register block. For the
864 * timers with a per-channel start/stop register, compute its address
865 * as well.
866 *
867 * For legacy configuration the address has been mapped explicitly.
868 */
869 if (cmt->legacy) {
870 ch->ioctrl = cmt->mapbase_ch;
871 } else {
872 switch (cmt->info->model) {
873 case SH_CMT_16BIT:
874 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
875 break;
876 case SH_CMT_32BIT:
877 case SH_CMT_48BIT:
878 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
879 break;
880 case SH_CMT_32BIT_FAST:
881 /*
882 * The 32-bit "fast" timer has a single channel at hwidx
883 * 5 but is located at offset 0x40 instead of 0x60 for
884 * some reason.
885 */
886 ch->ioctrl = cmt->mapbase + 0x40;
887 break;
888 case SH_CMT_48BIT_GEN2:
889 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
890 ch->ioctrl = ch->iostart + 0x10;
891 break;
892 }
893 }
894
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100895 if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
Laurent Pinchartb882e7b2014-01-27 22:04:17 +0100896 ch->max_match_value = ~0;
897 else
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100898 ch->max_match_value = (1 << cmt->info->width) - 1;
Laurent Pinchartb882e7b2014-01-27 22:04:17 +0100899
900 ch->match_value = ch->max_match_value;
901 raw_spin_lock_init(&ch->lock);
902
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100903 if (cmt->legacy) {
904 ch->timer_bit = ch->hwidx;
905 } else {
906 ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2
907 ? 0 : ch->hwidx;
908 }
909
Laurent Pinchart1d053e12014-02-17 16:04:16 +0100910 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100911 clockevent, clocksource);
Laurent Pinchartb882e7b2014-01-27 22:04:17 +0100912 if (ret) {
Laurent Pinchart740a9512014-01-27 22:04:17 +0100913 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
914 ch->index);
Laurent Pinchartb882e7b2014-01-27 22:04:17 +0100915 return ret;
916 }
917 ch->cs_enabled = false;
918
Laurent Pinchartb882e7b2014-01-27 22:04:17 +0100919 return 0;
920}
921
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100922static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000923{
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100924 struct resource *mem;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000925
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100926 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
927 if (!mem) {
928 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
929 return -ENXIO;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000930 }
931
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100932 cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem));
933 if (cmt->mapbase == NULL) {
934 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
935 return -ENXIO;
936 }
937
938 return 0;
939}
940
941static int sh_cmt_map_memory_legacy(struct sh_cmt_device *cmt)
942{
943 struct sh_timer_config *cfg = cmt->pdev->dev.platform_data;
944 struct resource *res, *res2;
945
946 /* map memory, let mapbase_ch point to our channel */
Laurent Pinchart2653caf2014-01-27 22:04:17 +0100947 res = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000948 if (!res) {
Laurent Pinchart2653caf2014-01-27 22:04:17 +0100949 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100950 return -ENXIO;
951 }
952
953 cmt->mapbase_ch = ioremap_nocache(res->start, resource_size(res));
954 if (cmt->mapbase_ch == NULL) {
955 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
956 return -ENXIO;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000957 }
958
Magnus Damm8874c5e2013-06-17 15:40:52 +0900959 /* optional resource for the shared timer start/stop register */
Laurent Pinchart2653caf2014-01-27 22:04:17 +0100960 res2 = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 1);
Magnus Damm8874c5e2013-06-17 15:40:52 +0900961
Magnus Damm8874c5e2013-06-17 15:40:52 +0900962 /* map second resource for CMSTR */
Laurent Pinchart36f1ac92014-01-27 22:04:17 +0100963 cmt->mapbase = ioremap_nocache(res2 ? res2->start :
964 res->start - cfg->channel_offset,
965 res2 ? resource_size(res2) : 2);
966 if (cmt->mapbase == NULL) {
Laurent Pinchart2653caf2014-01-27 22:04:17 +0100967 dev_err(&cmt->pdev->dev, "failed to remap I/O second memory\n");
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100968 iounmap(cmt->mapbase_ch);
969 return -ENXIO;
Magnus Damm8874c5e2013-06-17 15:40:52 +0900970 }
971
Laurent Pinchart2cda3ac2014-02-11 23:46:48 +0100972 /* identify the model based on the resources */
973 if (resource_size(res) == 6)
974 cmt->info = &sh_cmt_info[SH_CMT_16BIT];
975 else if (res2 && (resource_size(res2) == 4))
976 cmt->info = &sh_cmt_info[SH_CMT_48BIT_GEN2];
977 else
978 cmt->info = &sh_cmt_info[SH_CMT_32BIT];
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000979
Laurent Pinchart81b3b272014-01-28 12:36:48 +0100980 return 0;
981}
982
983static void sh_cmt_unmap_memory(struct sh_cmt_device *cmt)
984{
985 iounmap(cmt->mapbase);
986 if (cmt->mapbase_ch)
987 iounmap(cmt->mapbase_ch);
988}
989
990static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
991{
992 struct sh_timer_config *cfg = pdev->dev.platform_data;
993 const struct platform_device_id *id = pdev->id_entry;
994 unsigned int hw_channels;
995 int ret;
996
997 memset(cmt, 0, sizeof(*cmt));
998 cmt->pdev = pdev;
999
1000 if (!cfg) {
1001 dev_err(&cmt->pdev->dev, "missing platform data\n");
1002 return -ENXIO;
Laurent Pinchartf5ec9b12014-01-27 22:04:17 +01001003 }
1004
Laurent Pinchart81b3b272014-01-28 12:36:48 +01001005 cmt->info = (const struct sh_cmt_info *)id->driver_data;
1006 cmt->legacy = cmt->info ? false : true;
Laurent Pinchartf5ec9b12014-01-27 22:04:17 +01001007
Laurent Pinchart81b3b272014-01-28 12:36:48 +01001008 /* Get hold of clock. */
Laurent Pinchart24b4e072014-02-14 00:35:18 +01001009 cmt->clk = clk_get(&cmt->pdev->dev, cmt->legacy ? "cmt_fck" : "fck");
Laurent Pinchart81b3b272014-01-28 12:36:48 +01001010 if (IS_ERR(cmt->clk)) {
1011 dev_err(&cmt->pdev->dev, "cannot get clock\n");
1012 return PTR_ERR(cmt->clk);
1013 }
1014
1015 ret = clk_prepare(cmt->clk);
Laurent Pinchartb882e7b2014-01-27 22:04:17 +01001016 if (ret < 0)
Laurent Pinchart81b3b272014-01-28 12:36:48 +01001017 goto err_clk_put;
1018
1019 /*
1020 * Map the memory resource(s). We need to support both the legacy
1021 * platform device configuration (with one device per channel) and the
1022 * new version (with multiple channels per device).
1023 */
1024 if (cmt->legacy)
1025 ret = sh_cmt_map_memory_legacy(cmt);
1026 else
1027 ret = sh_cmt_map_memory(cmt);
1028
1029 if (ret < 0)
1030 goto err_clk_unprepare;
1031
1032 /* Allocate and setup the channels. */
1033 if (cmt->legacy) {
1034 cmt->num_channels = 1;
1035 hw_channels = 0;
1036 } else {
1037 cmt->num_channels = hweight8(cfg->channels_mask);
1038 hw_channels = cfg->channels_mask;
1039 }
1040
1041 cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels),
1042 GFP_KERNEL);
1043 if (cmt->channels == NULL) {
1044 ret = -ENOMEM;
1045 goto err_unmap;
1046 }
1047
1048 if (cmt->legacy) {
1049 ret = sh_cmt_setup_channel(&cmt->channels[0],
1050 cfg->timer_bit, cfg->timer_bit,
1051 cfg->clockevent_rating != 0,
1052 cfg->clocksource_rating != 0, cmt);
1053 if (ret < 0)
1054 goto err_unmap;
1055 } else {
1056 unsigned int mask = hw_channels;
1057 unsigned int i;
1058
1059 /*
1060 * Use the first channel as a clock event device and the second
1061 * channel as a clock source. If only one channel is available
1062 * use it for both.
1063 */
1064 for (i = 0; i < cmt->num_channels; ++i) {
1065 unsigned int hwidx = ffs(mask) - 1;
1066 bool clocksource = i == 1 || cmt->num_channels == 1;
1067 bool clockevent = i == 0;
1068
1069 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1070 clockevent, clocksource,
1071 cmt);
1072 if (ret < 0)
1073 goto err_unmap;
1074
1075 mask &= ~(1 << hwidx);
1076 }
1077 }
Paul Mundtda64c2a2010-02-25 16:37:46 +09001078
Laurent Pinchart2653caf2014-01-27 22:04:17 +01001079 platform_set_drvdata(pdev, cmt);
Magnus Dammadccc692012-12-14 14:53:51 +09001080
Paul Mundtda64c2a2010-02-25 16:37:46 +09001081 return 0;
Laurent Pinchart81b3b272014-01-28 12:36:48 +01001082
1083err_unmap:
Laurent Pinchartf5ec9b12014-01-27 22:04:17 +01001084 kfree(cmt->channels);
Laurent Pinchart81b3b272014-01-28 12:36:48 +01001085 sh_cmt_unmap_memory(cmt);
1086err_clk_unprepare:
Laurent Pinchart2653caf2014-01-27 22:04:17 +01001087 clk_unprepare(cmt->clk);
Laurent Pinchart81b3b272014-01-28 12:36:48 +01001088err_clk_put:
Laurent Pinchart2653caf2014-01-27 22:04:17 +01001089 clk_put(cmt->clk);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001090 return ret;
1091}
1092
Greg Kroah-Hartman18505142012-12-21 15:11:38 -08001093static int sh_cmt_probe(struct platform_device *pdev)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001094{
Laurent Pinchart2653caf2014-01-27 22:04:17 +01001095 struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001096 int ret;
1097
Rafael J. Wysocki9bb5ec82012-08-06 01:43:03 +02001098 if (!is_early_platform_device(pdev)) {
Rafael J. Wysockibad81382012-08-06 01:48:57 +02001099 pm_runtime_set_active(&pdev->dev);
1100 pm_runtime_enable(&pdev->dev);
Rafael J. Wysocki9bb5ec82012-08-06 01:43:03 +02001101 }
Rafael J. Wysocki615a4452012-03-13 22:40:06 +01001102
Laurent Pinchart2653caf2014-01-27 22:04:17 +01001103 if (cmt) {
Paul Mundt214a6072010-03-10 16:26:25 +09001104 dev_info(&pdev->dev, "kept as earlytimer\n");
Rafael J. Wysockibad81382012-08-06 01:48:57 +02001105 goto out;
Magnus Damme475eed2009-04-15 10:50:04 +00001106 }
1107
Laurent Pinchartb262bc72014-01-27 22:04:17 +01001108 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
Jingoo Han0178f412014-05-22 14:05:06 +02001109 if (cmt == NULL)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001110 return -ENOMEM;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001111
Laurent Pinchart2653caf2014-01-27 22:04:17 +01001112 ret = sh_cmt_setup(cmt, pdev);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001113 if (ret) {
Laurent Pinchart2653caf2014-01-27 22:04:17 +01001114 kfree(cmt);
Rafael J. Wysockibad81382012-08-06 01:48:57 +02001115 pm_runtime_idle(&pdev->dev);
1116 return ret;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001117 }
Rafael J. Wysockibad81382012-08-06 01:48:57 +02001118 if (is_early_platform_device(pdev))
1119 return 0;
1120
1121 out:
Laurent Pinchart81b3b272014-01-28 12:36:48 +01001122 if (cmt->has_clockevent || cmt->has_clocksource)
Rafael J. Wysockibad81382012-08-06 01:48:57 +02001123 pm_runtime_irq_safe(&pdev->dev);
1124 else
1125 pm_runtime_idle(&pdev->dev);
1126
1127 return 0;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001128}
1129
Greg Kroah-Hartman18505142012-12-21 15:11:38 -08001130static int sh_cmt_remove(struct platform_device *pdev)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001131{
1132 return -EBUSY; /* cannot unregister clockevent and clocksource */
1133}
1134
Laurent Pinchart81b3b272014-01-28 12:36:48 +01001135static const struct platform_device_id sh_cmt_id_table[] = {
1136 { "sh_cmt", 0 },
1137 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
1138 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
1139 { "sh-cmt-32-fast", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT_FAST] },
1140 { "sh-cmt-48", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT] },
1141 { "sh-cmt-48-gen2", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT_GEN2] },
1142 { }
1143};
1144MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
1145
Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001146static struct platform_driver sh_cmt_device_driver = {
1147 .probe = sh_cmt_probe,
Greg Kroah-Hartman18505142012-12-21 15:11:38 -08001148 .remove = sh_cmt_remove,
Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001149 .driver = {
1150 .name = "sh_cmt",
Laurent Pinchart81b3b272014-01-28 12:36:48 +01001151 },
1152 .id_table = sh_cmt_id_table,
Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001153};
1154
1155static int __init sh_cmt_init(void)
1156{
1157 return platform_driver_register(&sh_cmt_device_driver);
1158}
1159
1160static void __exit sh_cmt_exit(void)
1161{
1162 platform_driver_unregister(&sh_cmt_device_driver);
1163}
1164
Magnus Damme475eed2009-04-15 10:50:04 +00001165early_platform_init("earlytimer", &sh_cmt_device_driver);
Simon Hormane903a032013-03-05 15:40:42 +09001166subsys_initcall(sh_cmt_init);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001167module_exit(sh_cmt_exit);
1168
1169MODULE_AUTHOR("Magnus Damm");
1170MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1171MODULE_LICENSE("GPL v2");