Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Nouveau Community |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Martin Peres <martin.peres@labri.fr> |
| 23 | * Ben Skeggs |
| 24 | */ |
Ben Skeggs | 5f8824d | 2015-01-14 14:40:22 +1000 | [diff] [blame] | 25 | #include "nv04.h" |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 26 | |
Ben Skeggs | 2984506 | 2013-10-15 10:49:39 +1000 | [diff] [blame] | 27 | #include <subdev/timer.h> |
| 28 | |
Ben Skeggs | 2984506 | 2013-10-15 10:49:39 +1000 | [diff] [blame] | 29 | static int |
Ben Skeggs | 01d6b95 | 2015-08-20 14:54:06 +1000 | [diff] [blame^] | 30 | nv50_bus_hwsq_exec(struct nvkm_bus *bus, u32 *data, u32 size) |
Ben Skeggs | 2984506 | 2013-10-15 10:49:39 +1000 | [diff] [blame] | 31 | { |
Ben Skeggs | 2984506 | 2013-10-15 10:49:39 +1000 | [diff] [blame] | 32 | int i; |
| 33 | |
Ben Skeggs | 01d6b95 | 2015-08-20 14:54:06 +1000 | [diff] [blame^] | 34 | nv_mask(bus, 0x001098, 0x00000008, 0x00000000); |
| 35 | nv_wr32(bus, 0x001304, 0x00000000); |
Ben Skeggs | 2984506 | 2013-10-15 10:49:39 +1000 | [diff] [blame] | 36 | for (i = 0; i < size; i++) |
Ben Skeggs | 01d6b95 | 2015-08-20 14:54:06 +1000 | [diff] [blame^] | 37 | nv_wr32(bus, 0x001400 + (i * 4), data[i]); |
| 38 | nv_mask(bus, 0x001098, 0x00000018, 0x00000018); |
| 39 | nv_wr32(bus, 0x00130c, 0x00000003); |
Ben Skeggs | 2984506 | 2013-10-15 10:49:39 +1000 | [diff] [blame] | 40 | |
Ben Skeggs | 01d6b95 | 2015-08-20 14:54:06 +1000 | [diff] [blame^] | 41 | return nv_wait(bus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT; |
Ben Skeggs | 2984506 | 2013-10-15 10:49:39 +1000 | [diff] [blame] | 42 | } |
| 43 | |
| 44 | void |
Ben Skeggs | 5f8824d | 2015-01-14 14:40:22 +1000 | [diff] [blame] | 45 | nv50_bus_intr(struct nvkm_subdev *subdev) |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 46 | { |
Ben Skeggs | 01d6b95 | 2015-08-20 14:54:06 +1000 | [diff] [blame^] | 47 | struct nvkm_bus *bus = nvkm_bus(subdev); |
| 48 | u32 stat = nv_rd32(bus, 0x001100) & nv_rd32(bus, 0x001140); |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 49 | |
| 50 | if (stat & 0x00000008) { |
Ben Skeggs | 01d6b95 | 2015-08-20 14:54:06 +1000 | [diff] [blame^] | 51 | u32 addr = nv_rd32(bus, 0x009084); |
| 52 | u32 data = nv_rd32(bus, 0x009088); |
Martin Peres | 9d7175c | 2012-12-07 02:26:02 +0100 | [diff] [blame] | 53 | |
Ben Skeggs | 01d6b95 | 2015-08-20 14:54:06 +1000 | [diff] [blame^] | 54 | nv_error(bus, "MMIO %s of 0x%08x FAULT at 0x%06x\n", |
Martin Peres | 9d7175c | 2012-12-07 02:26:02 +0100 | [diff] [blame] | 55 | (addr & 0x00000002) ? "write" : "read", data, |
| 56 | (addr & 0x00fffffc)); |
| 57 | |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 58 | stat &= ~0x00000008; |
Ben Skeggs | 01d6b95 | 2015-08-20 14:54:06 +1000 | [diff] [blame^] | 59 | nv_wr32(bus, 0x001100, 0x00000008); |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 60 | } |
| 61 | |
| 62 | if (stat & 0x00010000) { |
Ben Skeggs | 01d6b95 | 2015-08-20 14:54:06 +1000 | [diff] [blame^] | 63 | subdev = nvkm_subdev(bus, NVDEV_SUBDEV_THERM); |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 64 | if (subdev && subdev->intr) |
| 65 | subdev->intr(subdev); |
| 66 | stat &= ~0x00010000; |
Ben Skeggs | 01d6b95 | 2015-08-20 14:54:06 +1000 | [diff] [blame^] | 67 | nv_wr32(bus, 0x001100, 0x00010000); |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 68 | } |
| 69 | |
| 70 | if (stat) { |
Ben Skeggs | 01d6b95 | 2015-08-20 14:54:06 +1000 | [diff] [blame^] | 71 | nv_error(bus, "unknown intr 0x%08x\n", stat); |
| 72 | nv_mask(bus, 0x001140, stat, 0); |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 73 | } |
| 74 | } |
| 75 | |
Ben Skeggs | 2984506 | 2013-10-15 10:49:39 +1000 | [diff] [blame] | 76 | int |
Ben Skeggs | 5f8824d | 2015-01-14 14:40:22 +1000 | [diff] [blame] | 77 | nv50_bus_init(struct nvkm_object *object) |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 78 | { |
Ben Skeggs | 01d6b95 | 2015-08-20 14:54:06 +1000 | [diff] [blame^] | 79 | struct nvkm_bus *bus = (void *)object; |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 80 | int ret; |
| 81 | |
Ben Skeggs | 01d6b95 | 2015-08-20 14:54:06 +1000 | [diff] [blame^] | 82 | ret = nvkm_bus_init(bus); |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 83 | if (ret) |
| 84 | return ret; |
| 85 | |
Ben Skeggs | 01d6b95 | 2015-08-20 14:54:06 +1000 | [diff] [blame^] | 86 | nv_wr32(bus, 0x001100, 0xffffffff); |
| 87 | nv_wr32(bus, 0x001140, 0x00010008); |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 88 | return 0; |
| 89 | } |
| 90 | |
Ben Skeggs | 5f8824d | 2015-01-14 14:40:22 +1000 | [diff] [blame] | 91 | struct nvkm_oclass * |
Ben Skeggs | 48ae0b3 | 2013-10-24 09:39:05 +1000 | [diff] [blame] | 92 | nv50_bus_oclass = &(struct nv04_bus_impl) { |
| 93 | .base.handle = NV_SUBDEV(BUS, 0x50), |
Ben Skeggs | 5f8824d | 2015-01-14 14:40:22 +1000 | [diff] [blame] | 94 | .base.ofuncs = &(struct nvkm_ofuncs) { |
Ben Skeggs | 48ae0b3 | 2013-10-24 09:39:05 +1000 | [diff] [blame] | 95 | .ctor = nv04_bus_ctor, |
Ben Skeggs | 5f8824d | 2015-01-14 14:40:22 +1000 | [diff] [blame] | 96 | .dtor = _nvkm_bus_dtor, |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 97 | .init = nv50_bus_init, |
Ben Skeggs | 5f8824d | 2015-01-14 14:40:22 +1000 | [diff] [blame] | 98 | .fini = _nvkm_bus_fini, |
Martin Peres | a10220b | 2012-11-04 01:01:53 +0100 | [diff] [blame] | 99 | }, |
Ben Skeggs | 48ae0b3 | 2013-10-24 09:39:05 +1000 | [diff] [blame] | 100 | .intr = nv50_bus_intr, |
Ben Skeggs | 2984506 | 2013-10-15 10:49:39 +1000 | [diff] [blame] | 101 | .hwsq_exec = nv50_bus_hwsq_exec, |
| 102 | .hwsq_size = 64, |
Ben Skeggs | 48ae0b3 | 2013-10-24 09:39:05 +1000 | [diff] [blame] | 103 | }.base; |