David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 1 | /* |
| 2 | include/comedi.h (installed as /usr/include/comedi.h) |
| 3 | header file for comedi |
| 4 | |
| 5 | COMEDI - Linux Control and Measurement Device Interface |
| 6 | Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org> |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU Lesser General Public License as published by |
| 10 | the Free Software Foundation; either version 2 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #ifndef _COMEDI_H |
| 20 | #define _COMEDI_H |
| 21 | |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 22 | #define COMEDI_MAJORVERSION 0 |
| 23 | #define COMEDI_MINORVERSION 7 |
| 24 | #define COMEDI_MICROVERSION 76 |
| 25 | #define VERSION "0.7.76" |
| 26 | |
| 27 | /* comedi's major device number */ |
| 28 | #define COMEDI_MAJOR 98 |
| 29 | |
| 30 | /* |
| 31 | maximum number of minor devices. This can be increased, although |
| 32 | kernel structures are currently statically allocated, thus you |
| 33 | don't want this to be much more than you actually use. |
| 34 | */ |
| 35 | #define COMEDI_NDEVICES 16 |
| 36 | |
| 37 | /* number of config options in the config structure */ |
| 38 | #define COMEDI_NDEVCONFOPTS 32 |
H Hartley Sweeten | d184313 | 2013-01-09 09:46:10 -0700 | [diff] [blame] | 39 | |
| 40 | /* |
| 41 | * NOTE: 'comedi_config --init-data' is deprecated |
| 42 | * |
| 43 | * The following indexes in the config options were used by |
| 44 | * comedi_config to pass firmware blobs from user space to the |
| 45 | * comedi drivers. The request_firmware() hotplug interface is |
| 46 | * now used by all comedi drivers instead. |
| 47 | */ |
| 48 | |
| 49 | /* length of nth chunk of firmware data -*/ |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 50 | #define COMEDI_DEVCONF_AUX_DATA3_LENGTH 25 |
| 51 | #define COMEDI_DEVCONF_AUX_DATA2_LENGTH 26 |
| 52 | #define COMEDI_DEVCONF_AUX_DATA1_LENGTH 27 |
| 53 | #define COMEDI_DEVCONF_AUX_DATA0_LENGTH 28 |
Mark Rankilor | e012b4c | 2010-05-06 18:07:44 +0800 | [diff] [blame] | 54 | /* most significant 32 bits of pointer address (if needed) */ |
| 55 | #define COMEDI_DEVCONF_AUX_DATA_HI 29 |
| 56 | /* least significant 32 bits of pointer address */ |
| 57 | #define COMEDI_DEVCONF_AUX_DATA_LO 30 |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 58 | #define COMEDI_DEVCONF_AUX_DATA_LENGTH 31 /* total data length */ |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 59 | |
| 60 | /* max length of device and driver names */ |
| 61 | #define COMEDI_NAMELEN 20 |
| 62 | |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 63 | /* packs and unpacks a channel/range number */ |
| 64 | |
Mark Rankilor | e012b4c | 2010-05-06 18:07:44 +0800 | [diff] [blame] | 65 | #define CR_PACK(chan, rng, aref) \ |
| 66 | ((((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan)) |
| 67 | #define CR_PACK_FLAGS(chan, range, aref, flags) \ |
| 68 | (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK)) |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 69 | |
| 70 | #define CR_CHAN(a) ((a)&0xffff) |
| 71 | #define CR_RANGE(a) (((a)>>16)&0xff) |
| 72 | #define CR_AREF(a) (((a)>>24)&0x03) |
| 73 | |
| 74 | #define CR_FLAGS_MASK 0xfc000000 |
| 75 | #define CR_ALT_FILTER (1<<26) |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 76 | #define CR_DITHER CR_ALT_FILTER |
| 77 | #define CR_DEGLITCH CR_ALT_FILTER |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 78 | #define CR_ALT_SOURCE (1<<27) |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 79 | #define CR_EDGE (1<<30) |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 80 | #define CR_INVERT (1<<31) |
| 81 | |
| 82 | #define AREF_GROUND 0x00 /* analog ref = analog ground */ |
| 83 | #define AREF_COMMON 0x01 /* analog ref = analog common */ |
| 84 | #define AREF_DIFF 0x02 /* analog ref = differential */ |
| 85 | #define AREF_OTHER 0x03 /* analog ref = other (undefined) */ |
| 86 | |
| 87 | /* counters -- these are arbitrary values */ |
| 88 | #define GPCT_RESET 0x0001 |
| 89 | #define GPCT_SET_SOURCE 0x0002 |
| 90 | #define GPCT_SET_GATE 0x0004 |
| 91 | #define GPCT_SET_DIRECTION 0x0008 |
| 92 | #define GPCT_SET_OPERATION 0x0010 |
| 93 | #define GPCT_ARM 0x0020 |
| 94 | #define GPCT_DISARM 0x0040 |
| 95 | #define GPCT_GET_INT_CLK_FRQ 0x0080 |
| 96 | |
| 97 | #define GPCT_INT_CLOCK 0x0001 |
| 98 | #define GPCT_EXT_PIN 0x0002 |
| 99 | #define GPCT_NO_GATE 0x0004 |
| 100 | #define GPCT_UP 0x0008 |
| 101 | #define GPCT_DOWN 0x0010 |
| 102 | #define GPCT_HWUD 0x0020 |
| 103 | #define GPCT_SIMPLE_EVENT 0x0040 |
| 104 | #define GPCT_SINGLE_PERIOD 0x0080 |
| 105 | #define GPCT_SINGLE_PW 0x0100 |
| 106 | #define GPCT_CONT_PULSE_OUT 0x0200 |
| 107 | #define GPCT_SINGLE_PULSE_OUT 0x0400 |
| 108 | |
| 109 | /* instructions */ |
| 110 | |
| 111 | #define INSN_MASK_WRITE 0x8000000 |
| 112 | #define INSN_MASK_READ 0x4000000 |
| 113 | #define INSN_MASK_SPECIAL 0x2000000 |
| 114 | |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 115 | #define INSN_READ (0 | INSN_MASK_READ) |
| 116 | #define INSN_WRITE (1 | INSN_MASK_WRITE) |
| 117 | #define INSN_BITS (2 | INSN_MASK_READ|INSN_MASK_WRITE) |
| 118 | #define INSN_CONFIG (3 | INSN_MASK_READ|INSN_MASK_WRITE) |
| 119 | #define INSN_GTOD (4 | INSN_MASK_READ|INSN_MASK_SPECIAL) |
| 120 | #define INSN_WAIT (5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL) |
| 121 | #define INSN_INTTRIG (6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL) |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 122 | |
| 123 | /* trigger flags */ |
| 124 | /* These flags are used in comedi_trig structures */ |
| 125 | |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 126 | #define TRIG_DITHER 0x0002 /* enable dithering */ |
| 127 | #define TRIG_DEGLITCH 0x0004 /* enable deglitching */ |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 128 | #define TRIG_CONFIG 0x0010 /* perform configuration, not triggering */ |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 129 | |
| 130 | /* command flags */ |
| 131 | /* These flags are used in comedi_cmd structures */ |
| 132 | |
Ian Abbott | dd7eb12 | 2014-09-03 13:45:43 +0100 | [diff] [blame] | 133 | #define CMDF_BOGUS 0x00000001 /* do the motions */ |
| 134 | |
Mark Rankilor | e012b4c | 2010-05-06 18:07:44 +0800 | [diff] [blame] | 135 | /* try to use a real-time interrupt while performing command */ |
| 136 | #define CMDF_PRIORITY 0x00000008 |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 137 | |
Ian Abbott | 3e15acd | 2014-09-03 13:45:29 +0100 | [diff] [blame] | 138 | /* wake up on end-of-scan events */ |
| 139 | #define CMDF_WAKE_EOS 0x00000020 |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 140 | |
| 141 | #define CMDF_WRITE 0x00000040 |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 142 | |
| 143 | #define CMDF_RAWDATA 0x00000080 |
| 144 | |
Ian Abbott | 3ab4ca1 | 2014-09-03 13:45:45 +0100 | [diff] [blame] | 145 | /* timer rounding definitions */ |
| 146 | #define CMDF_ROUND_MASK 0x00030000 |
| 147 | #define CMDF_ROUND_NEAREST 0x00000000 |
| 148 | #define CMDF_ROUND_DOWN 0x00010000 |
| 149 | #define CMDF_ROUND_UP 0x00020000 |
| 150 | #define CMDF_ROUND_UP_NEXT 0x00030000 |
| 151 | |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 152 | #define COMEDI_EV_START 0x00040000 |
| 153 | #define COMEDI_EV_SCAN_BEGIN 0x00080000 |
| 154 | #define COMEDI_EV_CONVERT 0x00100000 |
| 155 | #define COMEDI_EV_SCAN_END 0x00200000 |
| 156 | #define COMEDI_EV_STOP 0x00400000 |
| 157 | |
Ian Abbott | 3e15acd | 2014-09-03 13:45:29 +0100 | [diff] [blame] | 158 | /* compatibility definitions */ |
Ian Abbott | dd7eb12 | 2014-09-03 13:45:43 +0100 | [diff] [blame] | 159 | #define TRIG_BOGUS CMDF_BOGUS |
Ian Abbott | 3e15acd | 2014-09-03 13:45:29 +0100 | [diff] [blame] | 160 | #define TRIG_RT CMDF_PRIORITY |
| 161 | #define TRIG_WAKE_EOS CMDF_WAKE_EOS |
| 162 | #define TRIG_WRITE CMDF_WRITE |
Ian Abbott | 3ab4ca1 | 2014-09-03 13:45:45 +0100 | [diff] [blame] | 163 | #define TRIG_ROUND_MASK CMDF_ROUND_MASK |
| 164 | #define TRIG_ROUND_NEAREST CMDF_ROUND_NEAREST |
| 165 | #define TRIG_ROUND_DOWN CMDF_ROUND_DOWN |
| 166 | #define TRIG_ROUND_UP CMDF_ROUND_UP |
| 167 | #define TRIG_ROUND_UP_NEXT CMDF_ROUND_UP_NEXT |
Ian Abbott | 3e15acd | 2014-09-03 13:45:29 +0100 | [diff] [blame] | 168 | |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 169 | /* trigger sources */ |
| 170 | |
| 171 | #define TRIG_ANY 0xffffffff |
| 172 | #define TRIG_INVALID 0x00000000 |
| 173 | |
Mark | a9560a7 | 2010-05-10 17:56:05 +0800 | [diff] [blame] | 174 | #define TRIG_NONE 0x00000001 /* never trigger */ |
| 175 | #define TRIG_NOW 0x00000002 /* trigger now + N ns */ |
| 176 | #define TRIG_FOLLOW 0x00000004 /* trigger on next lower level trig */ |
| 177 | #define TRIG_TIME 0x00000008 /* trigger at time N ns */ |
| 178 | #define TRIG_TIMER 0x00000010 /* trigger at rate N ns */ |
| 179 | #define TRIG_COUNT 0x00000020 /* trigger when count reaches N */ |
| 180 | #define TRIG_EXT 0x00000040 /* trigger on external signal N */ |
| 181 | #define TRIG_INT 0x00000080 /* trigger on comedi-internal signal N */ |
| 182 | #define TRIG_OTHER 0x00000100 /* driver defined */ |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 183 | |
| 184 | /* subdevice flags */ |
| 185 | |
| 186 | #define SDF_BUSY 0x0001 /* device is busy */ |
| 187 | #define SDF_BUSY_OWNER 0x0002 /* device is busy with your job */ |
| 188 | #define SDF_LOCKED 0x0004 /* subdevice is locked */ |
| 189 | #define SDF_LOCK_OWNER 0x0008 /* you own lock */ |
| 190 | #define SDF_MAXDATA 0x0010 /* maxdata depends on channel */ |
| 191 | #define SDF_FLAGS 0x0020 /* flags depend on channel */ |
| 192 | #define SDF_RANGETYPE 0x0040 /* range type depends on channel */ |
| 193 | #define SDF_MODE0 0x0080 /* can do mode 0 */ |
| 194 | #define SDF_MODE1 0x0100 /* can do mode 1 */ |
| 195 | #define SDF_MODE2 0x0200 /* can do mode 2 */ |
| 196 | #define SDF_MODE3 0x0400 /* can do mode 3 */ |
| 197 | #define SDF_MODE4 0x0800 /* can do mode 4 */ |
| 198 | #define SDF_CMD 0x1000 /* can do commands (deprecated) */ |
Mark | a9560a7 | 2010-05-10 17:56:05 +0800 | [diff] [blame] | 199 | #define SDF_SOFT_CALIBRATED 0x2000 /* subdevice uses software calibration */ |
| 200 | #define SDF_CMD_WRITE 0x4000 /* can do output commands */ |
| 201 | #define SDF_CMD_READ 0x8000 /* can do input commands */ |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 202 | |
Mark | a9560a7 | 2010-05-10 17:56:05 +0800 | [diff] [blame] | 203 | /* subdevice can be read (e.g. analog input) */ |
| 204 | #define SDF_READABLE 0x00010000 |
| 205 | /* subdevice can be written (e.g. analog output) */ |
| 206 | #define SDF_WRITABLE 0x00020000 |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 207 | #define SDF_WRITEABLE SDF_WRITABLE /* spelling error in API */ |
Mark | a9560a7 | 2010-05-10 17:56:05 +0800 | [diff] [blame] | 208 | /* subdevice does not have externally visible lines */ |
| 209 | #define SDF_INTERNAL 0x00040000 |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 210 | #define SDF_GROUND 0x00100000 /* can do aref=ground */ |
| 211 | #define SDF_COMMON 0x00200000 /* can do aref=common */ |
| 212 | #define SDF_DIFF 0x00400000 /* can do aref=diff */ |
| 213 | #define SDF_OTHER 0x00800000 /* can do aref=other */ |
| 214 | #define SDF_DITHER 0x01000000 /* can do dithering */ |
| 215 | #define SDF_DEGLITCH 0x02000000 /* can do deglitching */ |
| 216 | #define SDF_MMAP 0x04000000 /* can do mmap() */ |
| 217 | #define SDF_RUNNING 0x08000000 /* subdevice is acquiring data */ |
| 218 | #define SDF_LSAMPL 0x10000000 /* subdevice uses 32-bit samples */ |
| 219 | #define SDF_PACKED 0x20000000 /* subdevice can do packed DIO */ |
| 220 | /* re recyle these flags for PWM */ |
Mithlesh Thukral | 0a85b6f | 2009-06-08 21:04:41 +0530 | [diff] [blame] | 221 | #define SDF_PWM_COUNTER SDF_MODE0 /* PWM can automatically switch off */ |
| 222 | #define SDF_PWM_HBRIDGE SDF_MODE1 /* PWM is signed (H-bridge) */ |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 223 | |
| 224 | /* subdevice types */ |
| 225 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 226 | enum comedi_subdevice_type { |
| 227 | COMEDI_SUBD_UNUSED, /* unused by driver */ |
| 228 | COMEDI_SUBD_AI, /* analog input */ |
| 229 | COMEDI_SUBD_AO, /* analog output */ |
| 230 | COMEDI_SUBD_DI, /* digital input */ |
| 231 | COMEDI_SUBD_DO, /* digital output */ |
| 232 | COMEDI_SUBD_DIO, /* digital input/output */ |
| 233 | COMEDI_SUBD_COUNTER, /* counter */ |
| 234 | COMEDI_SUBD_TIMER, /* timer */ |
| 235 | COMEDI_SUBD_MEMORY, /* memory, EEPROM, DPRAM */ |
| 236 | COMEDI_SUBD_CALIB, /* calibration DACs */ |
| 237 | COMEDI_SUBD_PROC, /* processor, DSP */ |
| 238 | COMEDI_SUBD_SERIAL, /* serial IO */ |
| 239 | COMEDI_SUBD_PWM /* PWM */ |
| 240 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 241 | |
| 242 | /* configuration instructions */ |
| 243 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 244 | enum configuration_ids { |
| 245 | INSN_CONFIG_DIO_INPUT = 0, |
| 246 | INSN_CONFIG_DIO_OUTPUT = 1, |
| 247 | INSN_CONFIG_DIO_OPENDRAIN = 2, |
| 248 | INSN_CONFIG_ANALOG_TRIG = 16, |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 249 | /* INSN_CONFIG_WAVEFORM = 17, */ |
| 250 | /* INSN_CONFIG_TRIG = 18, */ |
| 251 | /* INSN_CONFIG_COUNTER = 19, */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 252 | INSN_CONFIG_ALT_SOURCE = 20, |
| 253 | INSN_CONFIG_DIGITAL_TRIG = 21, |
| 254 | INSN_CONFIG_BLOCK_SIZE = 22, |
| 255 | INSN_CONFIG_TIMER_1 = 23, |
| 256 | INSN_CONFIG_FILTER = 24, |
| 257 | INSN_CONFIG_CHANGE_NOTIFY = 25, |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 258 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 259 | INSN_CONFIG_SERIAL_CLOCK = 26, /*ALPHA*/ |
| 260 | INSN_CONFIG_BIDIRECTIONAL_DATA = 27, |
| 261 | INSN_CONFIG_DIO_QUERY = 28, |
| 262 | INSN_CONFIG_PWM_OUTPUT = 29, |
| 263 | INSN_CONFIG_GET_PWM_OUTPUT = 30, |
| 264 | INSN_CONFIG_ARM = 31, |
| 265 | INSN_CONFIG_DISARM = 32, |
| 266 | INSN_CONFIG_GET_COUNTER_STATUS = 33, |
| 267 | INSN_CONFIG_RESET = 34, |
| 268 | /* Use CTR as single pulsegenerator */ |
| 269 | INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001, |
| 270 | /* Use CTR as pulsetraingenerator */ |
| 271 | INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002, |
| 272 | /* Use the counter as encoder */ |
| 273 | INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003, |
| 274 | INSN_CONFIG_SET_GATE_SRC = 2001, /* Set gate source */ |
| 275 | INSN_CONFIG_GET_GATE_SRC = 2002, /* Get gate source */ |
| 276 | /* Set master clock source */ |
| 277 | INSN_CONFIG_SET_CLOCK_SRC = 2003, |
| 278 | INSN_CONFIG_GET_CLOCK_SRC = 2004, /* Get master clock source */ |
| 279 | INSN_CONFIG_SET_OTHER_SRC = 2005, /* Set other source */ |
| 280 | /* INSN_CONFIG_GET_OTHER_SRC = 2006,*//* Get other source */ |
| 281 | /* Get size in bytes of subdevice's on-board fifos used during |
| 282 | * streaming input/output */ |
| 283 | INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006, |
| 284 | INSN_CONFIG_SET_COUNTER_MODE = 4097, |
| 285 | /* INSN_CONFIG_8254_SET_MODE is deprecated */ |
| 286 | INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE, |
| 287 | INSN_CONFIG_8254_READ_STATUS = 4098, |
| 288 | INSN_CONFIG_SET_ROUTING = 4099, |
| 289 | INSN_CONFIG_GET_ROUTING = 4109, |
| 290 | /* PWM */ |
| 291 | INSN_CONFIG_PWM_SET_PERIOD = 5000, /* sets frequency */ |
| 292 | INSN_CONFIG_PWM_GET_PERIOD = 5001, /* gets frequency */ |
| 293 | INSN_CONFIG_GET_PWM_STATUS = 5002, /* is it running? */ |
| 294 | /* sets H bridge: duty cycle and sign bit for a relay at the |
| 295 | * same time */ |
| 296 | INSN_CONFIG_PWM_SET_H_BRIDGE = 5003, |
| 297 | /* gets H bridge data: duty cycle and the sign bit */ |
| 298 | INSN_CONFIG_PWM_GET_H_BRIDGE = 5004 |
| 299 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 300 | |
Ian Abbott | 206cb10 | 2012-11-14 11:22:55 +0000 | [diff] [blame] | 301 | /* |
| 302 | * Settings for INSN_CONFIG_DIGITAL_TRIG: |
| 303 | * data[0] = INSN_CONFIG_DIGITAL_TRIG |
| 304 | * data[1] = trigger ID |
| 305 | * data[2] = configuration operation |
| 306 | * data[3] = configuration parameter 1 |
| 307 | * data[4] = configuration parameter 2 |
| 308 | * data[5] = configuration parameter 3 |
| 309 | * |
| 310 | * operation parameter 1 parameter 2 parameter 3 |
| 311 | * --------------------------------- ----------- ----------- ----------- |
| 312 | * COMEDI_DIGITAL_TRIG_DISABLE |
| 313 | * COMEDI_DIGITAL_TRIG_ENABLE_EDGES left-shift rising-edges falling-edges |
| 314 | * COMEDI_DIGITAL_TRIG_ENABLE_LEVELS left-shift high-levels low-levels |
| 315 | * |
| 316 | * COMEDI_DIGITAL_TRIG_DISABLE returns the trigger to its default, inactive, |
| 317 | * unconfigured state. |
| 318 | * |
| 319 | * COMEDI_DIGITAL_TRIG_ENABLE_EDGES sets the rising and/or falling edge inputs |
| 320 | * that each can fire the trigger. |
| 321 | * |
| 322 | * COMEDI_DIGITAL_TRIG_ENABLE_LEVELS sets a combination of high and/or low |
| 323 | * level inputs that can fire the trigger. |
| 324 | * |
| 325 | * "left-shift" is useful if the trigger has more than 32 inputs to specify the |
| 326 | * first input for this configuration. |
| 327 | * |
| 328 | * Some sequences of INSN_CONFIG_DIGITAL_TRIG instructions may have a (partly) |
| 329 | * accumulative effect, depending on the low-level driver. This is useful |
| 330 | * when setting up a trigger that has more than 32 inputs or has a combination |
| 331 | * of edge and level triggered inputs. |
| 332 | */ |
| 333 | enum comedi_digital_trig_op { |
| 334 | COMEDI_DIGITAL_TRIG_DISABLE = 0, |
| 335 | COMEDI_DIGITAL_TRIG_ENABLE_EDGES = 1, |
| 336 | COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = 2 |
| 337 | }; |
| 338 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 339 | enum comedi_io_direction { |
| 340 | COMEDI_INPUT = 0, |
| 341 | COMEDI_OUTPUT = 1, |
| 342 | COMEDI_OPENDRAIN = 2 |
| 343 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 344 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 345 | enum comedi_support_level { |
| 346 | COMEDI_UNKNOWN_SUPPORT = 0, |
| 347 | COMEDI_SUPPORTED, |
| 348 | COMEDI_UNSUPPORTED |
| 349 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 350 | |
| 351 | /* ioctls */ |
| 352 | |
| 353 | #define CIO 'd' |
Bill Pemberton | 0707bb0 | 2009-03-16 22:06:20 -0400 | [diff] [blame] | 354 | #define COMEDI_DEVCONFIG _IOW(CIO, 0, struct comedi_devconfig) |
Bill Pemberton | 063db04 | 2009-03-16 22:06:15 -0400 | [diff] [blame] | 355 | #define COMEDI_DEVINFO _IOR(CIO, 1, struct comedi_devinfo) |
Bill Pemberton | bd52efb | 2009-03-16 22:06:09 -0400 | [diff] [blame] | 356 | #define COMEDI_SUBDINFO _IOR(CIO, 2, struct comedi_subdinfo) |
Bill Pemberton | a18b416 | 2009-03-16 22:06:04 -0400 | [diff] [blame] | 357 | #define COMEDI_CHANINFO _IOR(CIO, 3, struct comedi_chaninfo) |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 358 | #define COMEDI_TRIG _IOWR(CIO, 4, comedi_trig) |
| 359 | #define COMEDI_LOCK _IO(CIO, 5) |
| 360 | #define COMEDI_UNLOCK _IO(CIO, 6) |
| 361 | #define COMEDI_CANCEL _IO(CIO, 7) |
Bill Pemberton | d0a353f | 2009-03-16 22:06:26 -0400 | [diff] [blame] | 362 | #define COMEDI_RANGEINFO _IOR(CIO, 8, struct comedi_rangeinfo) |
Bill Pemberton | ea6d0d4 | 2009-03-16 22:05:47 -0400 | [diff] [blame] | 363 | #define COMEDI_CMD _IOR(CIO, 9, struct comedi_cmd) |
| 364 | #define COMEDI_CMDTEST _IOR(CIO, 10, struct comedi_cmd) |
Bill Pemberton | da613f4 | 2009-03-16 22:05:59 -0400 | [diff] [blame] | 365 | #define COMEDI_INSNLIST _IOR(CIO, 11, struct comedi_insnlist) |
Bill Pemberton | 90035c0 | 2009-03-16 22:05:53 -0400 | [diff] [blame] | 366 | #define COMEDI_INSN _IOR(CIO, 12, struct comedi_insn) |
Bill Pemberton | be6aba4 | 2009-03-16 22:06:37 -0400 | [diff] [blame] | 367 | #define COMEDI_BUFCONFIG _IOR(CIO, 13, struct comedi_bufconfig) |
Bill Pemberton | 9aa5339 | 2009-03-16 22:06:42 -0400 | [diff] [blame] | 368 | #define COMEDI_BUFINFO _IOWR(CIO, 14, struct comedi_bufinfo) |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 369 | #define COMEDI_POLL _IO(CIO, 15) |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 370 | |
| 371 | /* structures */ |
| 372 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 373 | struct comedi_trig { |
| 374 | unsigned int subdev; /* subdevice */ |
| 375 | unsigned int mode; /* mode */ |
| 376 | unsigned int flags; |
| 377 | unsigned int n_chan; /* number of channels */ |
| 378 | unsigned int *chanlist; /* channel/range list */ |
| 379 | short *data; /* data list, size depends on subd flags */ |
| 380 | unsigned int n; /* number of scans */ |
| 381 | unsigned int trigsrc; |
| 382 | unsigned int trigvar; |
| 383 | unsigned int trigvar1; |
| 384 | unsigned int data_len; |
| 385 | unsigned int unused[3]; |
| 386 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 387 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 388 | struct comedi_insn { |
| 389 | unsigned int insn; |
| 390 | unsigned int n; |
| 391 | unsigned int __user *data; |
| 392 | unsigned int subdev; |
| 393 | unsigned int chanspec; |
| 394 | unsigned int unused[3]; |
| 395 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 396 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 397 | struct comedi_insnlist { |
| 398 | unsigned int n_insns; |
| 399 | struct comedi_insn __user *insns; |
| 400 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 401 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 402 | struct comedi_cmd { |
| 403 | unsigned int subdev; |
| 404 | unsigned int flags; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 405 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 406 | unsigned int start_src; |
| 407 | unsigned int start_arg; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 408 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 409 | unsigned int scan_begin_src; |
| 410 | unsigned int scan_begin_arg; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 411 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 412 | unsigned int convert_src; |
| 413 | unsigned int convert_arg; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 414 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 415 | unsigned int scan_end_src; |
| 416 | unsigned int scan_end_arg; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 417 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 418 | unsigned int stop_src; |
| 419 | unsigned int stop_arg; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 420 | |
H Hartley Sweeten | 9be56c6 | 2012-09-18 11:41:04 -0700 | [diff] [blame] | 421 | unsigned int *chanlist; /* channel/range list */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 422 | unsigned int chanlist_len; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 423 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 424 | short __user *data; /* data list, size depends on subd flags */ |
| 425 | unsigned int data_len; |
| 426 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 427 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 428 | struct comedi_chaninfo { |
| 429 | unsigned int subdev; |
| 430 | unsigned int __user *maxdata_list; |
| 431 | unsigned int __user *flaglist; |
| 432 | unsigned int __user *rangelist; |
| 433 | unsigned int unused[4]; |
| 434 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 435 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 436 | struct comedi_rangeinfo { |
| 437 | unsigned int range_type; |
| 438 | void __user *range_ptr; |
| 439 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 440 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 441 | struct comedi_krange { |
| 442 | int min; /* fixed point, multiply by 1e-6 */ |
| 443 | int max; /* fixed point, multiply by 1e-6 */ |
| 444 | unsigned int flags; |
| 445 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 446 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 447 | struct comedi_subdinfo { |
| 448 | unsigned int type; |
| 449 | unsigned int n_chan; |
| 450 | unsigned int subd_flags; |
| 451 | unsigned int timer_type; |
| 452 | unsigned int len_chanlist; |
| 453 | unsigned int maxdata; |
| 454 | unsigned int flags; /* channel flags */ |
| 455 | unsigned int range_type; /* lookup in kernel */ |
| 456 | unsigned int settling_time_0; |
| 457 | /* see support_level enum for values */ |
| 458 | unsigned insn_bits_support; |
| 459 | unsigned int unused[8]; |
| 460 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 461 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 462 | struct comedi_devinfo { |
| 463 | unsigned int version_code; |
| 464 | unsigned int n_subdevs; |
| 465 | char driver_name[COMEDI_NAMELEN]; |
| 466 | char board_name[COMEDI_NAMELEN]; |
| 467 | int read_subdevice; |
| 468 | int write_subdevice; |
| 469 | int unused[30]; |
| 470 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 471 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 472 | struct comedi_devconfig { |
| 473 | char board_name[COMEDI_NAMELEN]; |
| 474 | int options[COMEDI_NDEVCONFOPTS]; |
| 475 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 476 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 477 | struct comedi_bufconfig { |
| 478 | unsigned int subdevice; |
| 479 | unsigned int flags; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 480 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 481 | unsigned int maximum_size; |
| 482 | unsigned int size; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 483 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 484 | unsigned int unused[4]; |
| 485 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 486 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 487 | struct comedi_bufinfo { |
| 488 | unsigned int subdevice; |
| 489 | unsigned int bytes_read; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 490 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 491 | unsigned int buf_write_ptr; |
| 492 | unsigned int buf_read_ptr; |
| 493 | unsigned int buf_write_count; |
| 494 | unsigned int buf_read_count; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 495 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 496 | unsigned int bytes_written; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 497 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 498 | unsigned int unused[4]; |
| 499 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 500 | |
| 501 | /* range stuff */ |
| 502 | |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 503 | #define __RANGE(a, b) ((((a)&0xffff)<<16)|((b)&0xffff)) |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 504 | |
| 505 | #define RANGE_OFFSET(a) (((a)>>16)&0xffff) |
| 506 | #define RANGE_LENGTH(b) ((b)&0xffff) |
| 507 | |
| 508 | #define RF_UNIT(flags) ((flags)&0xff) |
| 509 | #define RF_EXTERNAL (1<<8) |
| 510 | |
| 511 | #define UNIT_volt 0 |
| 512 | #define UNIT_mA 1 |
| 513 | #define UNIT_none 2 |
| 514 | |
| 515 | #define COMEDI_MIN_SPEED ((unsigned int)0xffffffff) |
| 516 | |
| 517 | /* callback stuff */ |
| 518 | /* only relevant to kernel modules. */ |
| 519 | |
| 520 | #define COMEDI_CB_EOS 1 /* end of scan */ |
W. Trevor King | 35a36e6 | 2012-04-16 13:25:18 -0400 | [diff] [blame] | 521 | #define COMEDI_CB_EOA 2 /* end of acquisition/output */ |
Mark Rankilor | b464f79 | 2010-05-13 18:28:38 +0800 | [diff] [blame] | 522 | #define COMEDI_CB_BLOCK 4 /* data has arrived: |
| 523 | * wakes up read() / write() */ |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 524 | #define COMEDI_CB_EOBUF 8 /* DEPRECATED: end of buffer */ |
| 525 | #define COMEDI_CB_ERROR 16 /* card error during acquisition */ |
| 526 | #define COMEDI_CB_OVERFLOW 32 /* buffer overflow/underflow */ |
| 527 | |
| 528 | /**********************************************************/ |
| 529 | /* everything after this line is ALPHA */ |
| 530 | /**********************************************************/ |
| 531 | |
| 532 | /* |
| 533 | 8254 specific configuration. |
| 534 | |
| 535 | It supports two config commands: |
| 536 | |
| 537 | 0 ID: INSN_CONFIG_SET_COUNTER_MODE |
| 538 | 1 8254 Mode |
| 539 | I8254_MODE0, I8254_MODE1, ..., I8254_MODE5 |
| 540 | OR'ed with: |
| 541 | I8254_BCD, I8254_BINARY |
| 542 | |
| 543 | 0 ID: INSN_CONFIG_8254_READ_STATUS |
| 544 | 1 <-- Status byte returned here. |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 545 | B7 = Output |
| 546 | B6 = NULL Count |
| 547 | B5 - B0 Current mode. |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 548 | |
| 549 | */ |
| 550 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 551 | enum i8254_mode { |
| 552 | I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */ |
| 553 | I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */ |
| 554 | I8254_MODE2 = (2 << 1), /* Rate generator */ |
| 555 | I8254_MODE3 = (3 << 1), /* Square wave mode */ |
| 556 | I8254_MODE4 = (4 << 1), /* Software triggered strobe */ |
| 557 | I8254_MODE5 = (5 << 1), /* Hardware triggered strobe |
| 558 | * (retriggerable) */ |
| 559 | I8254_BCD = 1, /* use binary-coded decimal instead of binary |
Mark Rankilor | b464f79 | 2010-05-13 18:28:38 +0800 | [diff] [blame] | 560 | * (pretty useless) */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 561 | I8254_BINARY = 0 |
| 562 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 563 | |
H Hartley Sweeten | 40af57a | 2014-07-18 14:28:13 -0700 | [diff] [blame] | 564 | #define NI_USUAL_PFI_SELECT(x) (((x) < 10) ? (0x1 + (x)) : (0xb + (x))) |
| 565 | #define NI_USUAL_RTSI_SELECT(x) (((x) < 7) ? (0xb + (x)) : 0x1b) |
Ralf Thielow | f80d1d2 | 2011-05-28 01:37:03 +0200 | [diff] [blame] | 566 | |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 567 | /* mode bits for NI general-purpose counters, set with |
| 568 | * INSN_CONFIG_SET_COUNTER_MODE */ |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 569 | #define NI_GPCT_COUNTING_MODE_SHIFT 16 |
| 570 | #define NI_GPCT_INDEX_PHASE_BITSHIFT 20 |
| 571 | #define NI_GPCT_COUNTING_DIRECTION_SHIFT 24 |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 572 | enum ni_gpct_mode_bits { |
| 573 | NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4, |
| 574 | NI_GPCT_EDGE_GATE_MODE_MASK = 0x18, |
| 575 | NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0, |
| 576 | NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8, |
| 577 | NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10, |
| 578 | NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18, |
| 579 | NI_GPCT_STOP_MODE_MASK = 0x60, |
| 580 | NI_GPCT_STOP_ON_GATE_BITS = 0x00, |
| 581 | NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20, |
| 582 | NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40, |
| 583 | NI_GPCT_LOAD_B_SELECT_BIT = 0x80, |
| 584 | NI_GPCT_OUTPUT_MODE_MASK = 0x300, |
| 585 | NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100, |
| 586 | NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200, |
| 587 | NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300, |
| 588 | NI_GPCT_HARDWARE_DISARM_MASK = 0xc00, |
| 589 | NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000, |
| 590 | NI_GPCT_DISARM_AT_TC_BITS = 0x400, |
| 591 | NI_GPCT_DISARM_AT_GATE_BITS = 0x800, |
| 592 | NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00, |
| 593 | NI_GPCT_LOADING_ON_TC_BIT = 0x1000, |
| 594 | NI_GPCT_LOADING_ON_GATE_BIT = 0x4000, |
| 595 | NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT, |
| 596 | NI_GPCT_COUNTING_MODE_NORMAL_BITS = |
| 597 | 0x0 << NI_GPCT_COUNTING_MODE_SHIFT, |
| 598 | NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS = |
| 599 | 0x1 << NI_GPCT_COUNTING_MODE_SHIFT, |
| 600 | NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS = |
| 601 | 0x2 << NI_GPCT_COUNTING_MODE_SHIFT, |
| 602 | NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS = |
| 603 | 0x3 << NI_GPCT_COUNTING_MODE_SHIFT, |
| 604 | NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS = |
| 605 | 0x4 << NI_GPCT_COUNTING_MODE_SHIFT, |
| 606 | NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS = |
| 607 | 0x6 << NI_GPCT_COUNTING_MODE_SHIFT, |
| 608 | NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT, |
| 609 | NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS = |
| 610 | 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT, |
| 611 | NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS = |
| 612 | 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT, |
| 613 | NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS = |
| 614 | 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT, |
| 615 | NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS = |
| 616 | 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT, |
| 617 | NI_GPCT_INDEX_ENABLE_BIT = 0x400000, |
| 618 | NI_GPCT_COUNTING_DIRECTION_MASK = |
| 619 | 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT, |
| 620 | NI_GPCT_COUNTING_DIRECTION_DOWN_BITS = |
| 621 | 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT, |
| 622 | NI_GPCT_COUNTING_DIRECTION_UP_BITS = |
| 623 | 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT, |
| 624 | NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS = |
| 625 | 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT, |
| 626 | NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS = |
| 627 | 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT, |
| 628 | NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000, |
| 629 | NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0, |
| 630 | NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000, |
| 631 | NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000, |
| 632 | NI_GPCT_OR_GATE_BIT = 0x10000000, |
| 633 | NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000 |
| 634 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 635 | |
| 636 | /* Bits for setting a clock source with |
| 637 | * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 638 | enum ni_gpct_clock_source_bits { |
| 639 | NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f, |
| 640 | NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0, |
| 641 | NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1, |
| 642 | NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2, |
| 643 | NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3, |
| 644 | NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4, |
| 645 | NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5, |
| 646 | /* NI 660x-specific */ |
| 647 | NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6, |
| 648 | NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7, |
| 649 | NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8, |
| 650 | NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9, |
| 651 | NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000, |
| 652 | NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0, |
| 653 | /* divide source by 2 */ |
| 654 | NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000, |
| 655 | /* divide source by 8 */ |
| 656 | NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000, |
| 657 | NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000 |
| 658 | }; |
H Hartley Sweeten | 40af57a | 2014-07-18 14:28:13 -0700 | [diff] [blame] | 659 | |
| 660 | /* NI 660x-specific */ |
| 661 | #define NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(x) (0x10 + (x)) |
| 662 | |
| 663 | #define NI_GPCT_RTSI_CLOCK_SRC_BITS(x) (0x18 + (x)) |
| 664 | |
| 665 | /* no pfi on NI 660x */ |
| 666 | #define NI_GPCT_PFI_CLOCK_SRC_BITS(x) (0x20 + (x)) |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 667 | |
| 668 | /* Possibilities for setting a gate source with |
| 669 | INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters. |
| 670 | May be bitwise-or'd with CR_EDGE or CR_INVERT. */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 671 | enum ni_gpct_gate_select { |
| 672 | /* m-series gates */ |
| 673 | NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0, |
| 674 | NI_GPCT_AI_START2_GATE_SELECT = 0x12, |
| 675 | NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13, |
| 676 | NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14, |
| 677 | NI_GPCT_AI_START1_GATE_SELECT = 0x1c, |
| 678 | NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d, |
| 679 | NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e, |
| 680 | NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f, |
| 681 | /* more gates for 660x */ |
| 682 | NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100, |
| 683 | NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101, |
| 684 | /* more gates for 660x "second gate" */ |
| 685 | NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201, |
| 686 | NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e, |
| 687 | /* m-series "second gate" sources are unknown, |
| 688 | * we should add them here with an offset of 0x300 when |
| 689 | * known. */ |
| 690 | NI_GPCT_DISABLED_GATE_SELECT = 0x8000, |
| 691 | }; |
H Hartley Sweeten | 40af57a | 2014-07-18 14:28:13 -0700 | [diff] [blame] | 692 | |
| 693 | #define NI_GPCT_GATE_PIN_GATE_SELECT(x) (0x102 + (x)) |
| 694 | #define NI_GPCT_RTSI_GATE_SELECT(x) NI_USUAL_RTSI_SELECT(x) |
| 695 | #define NI_GPCT_PFI_GATE_SELECT(x) NI_USUAL_PFI_SELECT(x) |
| 696 | #define NI_GPCT_UP_DOWN_PIN_GATE_SELECT(x) (0x202 + (x)) |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 697 | |
| 698 | /* Possibilities for setting a source with |
| 699 | INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 700 | enum ni_gpct_other_index { |
| 701 | NI_GPCT_SOURCE_ENCODER_A, |
| 702 | NI_GPCT_SOURCE_ENCODER_B, |
| 703 | NI_GPCT_SOURCE_ENCODER_Z |
| 704 | }; |
H Hartley Sweeten | 40af57a | 2014-07-18 14:28:13 -0700 | [diff] [blame] | 705 | |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 706 | enum ni_gpct_other_select { |
| 707 | /* m-series gates */ |
| 708 | /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */ |
| 709 | NI_GPCT_DISABLED_OTHER_SELECT = 0x8000, |
| 710 | }; |
H Hartley Sweeten | 40af57a | 2014-07-18 14:28:13 -0700 | [diff] [blame] | 711 | |
| 712 | #define NI_GPCT_PFI_OTHER_SELECT(x) NI_USUAL_PFI_SELECT(x) |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 713 | |
| 714 | /* start sources for ni general-purpose counters for use with |
| 715 | INSN_CONFIG_ARM */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 716 | enum ni_gpct_arm_source { |
| 717 | NI_GPCT_ARM_IMMEDIATE = 0x0, |
| 718 | NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter |
| 719 | * and the adjacent paired |
| 720 | * counter simultaneously */ |
| 721 | /* NI doesn't document bits for selecting hardware arm triggers. |
| 722 | * If the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least |
| 723 | * significant bits (3 bits for 660x or 5 bits for m-series) |
| 724 | * through to the hardware. This will at least allow someone to |
| 725 | * figure out what the bits do later. */ |
| 726 | NI_GPCT_ARM_UNKNOWN = 0x1000, |
| 727 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 728 | |
| 729 | /* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 730 | enum ni_gpct_filter_select { |
| 731 | NI_GPCT_FILTER_OFF = 0x0, |
| 732 | NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1, |
| 733 | NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2, |
| 734 | NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3, |
| 735 | NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4, |
| 736 | NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5, |
| 737 | NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6 |
| 738 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 739 | |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 740 | /* PFI digital filtering options for ni m-series for use with |
| 741 | * INSN_CONFIG_FILTER. */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 742 | enum ni_pfi_filter_select { |
| 743 | NI_PFI_FILTER_OFF = 0x0, |
| 744 | NI_PFI_FILTER_125ns = 0x1, |
| 745 | NI_PFI_FILTER_6425ns = 0x2, |
| 746 | NI_PFI_FILTER_2550us = 0x3 |
| 747 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 748 | |
| 749 | /* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 750 | enum ni_mio_clock_source { |
| 751 | NI_MIO_INTERNAL_CLOCK = 0, |
| 752 | NI_MIO_RTSI_CLOCK = 1, /* doesn't work for m-series, use |
| 753 | NI_MIO_PLL_RTSI_CLOCK() */ |
| 754 | /* the NI_MIO_PLL_* sources are m-series only */ |
| 755 | NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2, |
| 756 | NI_MIO_PLL_PXI10_CLOCK = 3, |
| 757 | NI_MIO_PLL_RTSI0_CLOCK = 4 |
| 758 | }; |
H Hartley Sweeten | 40af57a | 2014-07-18 14:28:13 -0700 | [diff] [blame] | 759 | |
| 760 | #define NI_MIO_PLL_RTSI_CLOCK(x) (NI_MIO_PLL_RTSI0_CLOCK + (x)) |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 761 | |
| 762 | /* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING. |
| 763 | The numbers assigned are not arbitrary, they correspond to the bits required |
| 764 | to program the board. */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 765 | enum ni_rtsi_routing { |
| 766 | NI_RTSI_OUTPUT_ADR_START1 = 0, |
| 767 | NI_RTSI_OUTPUT_ADR_START2 = 1, |
| 768 | NI_RTSI_OUTPUT_SCLKG = 2, |
| 769 | NI_RTSI_OUTPUT_DACUPDN = 3, |
| 770 | NI_RTSI_OUTPUT_DA_START1 = 4, |
| 771 | NI_RTSI_OUTPUT_G_SRC0 = 5, |
| 772 | NI_RTSI_OUTPUT_G_GATE0 = 6, |
| 773 | NI_RTSI_OUTPUT_RGOUT0 = 7, |
| 774 | NI_RTSI_OUTPUT_RTSI_BRD_0 = 8, |
| 775 | NI_RTSI_OUTPUT_RTSI_OSC = 12 /* pre-m-series always have RTSI |
| 776 | * clock on line 7 */ |
| 777 | }; |
H Hartley Sweeten | 40af57a | 2014-07-18 14:28:13 -0700 | [diff] [blame] | 778 | |
| 779 | #define NI_RTSI_OUTPUT_RTSI_BRD(x) (NI_RTSI_OUTPUT_RTSI_BRD_0 + (x)) |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 780 | |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 781 | /* Signals which can be routed to an NI PFI pin on an m-series board with |
| 782 | * INSN_CONFIG_SET_ROUTING. These numbers are also returned by |
| 783 | * INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though their routing |
| 784 | * cannot be changed. The numbers assigned are not arbitrary, they correspond |
| 785 | * to the bits required to program the board. */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 786 | enum ni_pfi_routing { |
| 787 | NI_PFI_OUTPUT_PFI_DEFAULT = 0, |
| 788 | NI_PFI_OUTPUT_AI_START1 = 1, |
| 789 | NI_PFI_OUTPUT_AI_START2 = 2, |
| 790 | NI_PFI_OUTPUT_AI_CONVERT = 3, |
| 791 | NI_PFI_OUTPUT_G_SRC1 = 4, |
| 792 | NI_PFI_OUTPUT_G_GATE1 = 5, |
| 793 | NI_PFI_OUTPUT_AO_UPDATE_N = 6, |
| 794 | NI_PFI_OUTPUT_AO_START1 = 7, |
| 795 | NI_PFI_OUTPUT_AI_START_PULSE = 8, |
| 796 | NI_PFI_OUTPUT_G_SRC0 = 9, |
| 797 | NI_PFI_OUTPUT_G_GATE0 = 10, |
| 798 | NI_PFI_OUTPUT_EXT_STROBE = 11, |
| 799 | NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12, |
| 800 | NI_PFI_OUTPUT_GOUT0 = 13, |
| 801 | NI_PFI_OUTPUT_GOUT1 = 14, |
| 802 | NI_PFI_OUTPUT_FREQ_OUT = 15, |
| 803 | NI_PFI_OUTPUT_PFI_DO = 16, |
| 804 | NI_PFI_OUTPUT_I_ATRIG = 17, |
| 805 | NI_PFI_OUTPUT_RTSI0 = 18, |
| 806 | NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26, |
| 807 | NI_PFI_OUTPUT_SCXI_TRIG1 = 27, |
| 808 | NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28, |
| 809 | NI_PFI_OUTPUT_CDI_SAMPLE = 29, |
| 810 | NI_PFI_OUTPUT_CDO_UPDATE = 30 |
| 811 | }; |
H Hartley Sweeten | 40af57a | 2014-07-18 14:28:13 -0700 | [diff] [blame] | 812 | |
| 813 | #define NI_PFI_OUTPUT_RTSI(x) (NI_PFI_OUTPUT_RTSI0 + (x)) |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 814 | |
| 815 | /* Signals which can be routed to output on a NI PFI pin on a 660x board |
| 816 | with INSN_CONFIG_SET_ROUTING. The numbers assigned are |
| 817 | not arbitrary, they correspond to the bits required |
| 818 | to program the board. Lines 0 to 7 can only be set to |
| 819 | NI_660X_PFI_OUTPUT_DIO. Lines 32 to 39 can only be set to |
| 820 | NI_660X_PFI_OUTPUT_COUNTER. */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 821 | enum ni_660x_pfi_routing { |
| 822 | NI_660X_PFI_OUTPUT_COUNTER = 1, /* counter */ |
| 823 | NI_660X_PFI_OUTPUT_DIO = 2, /* static digital output */ |
| 824 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 825 | |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 826 | /* NI External Trigger lines. These values are not arbitrary, but are related |
| 827 | * to the bits required to program the board (offset by 1 for historical |
| 828 | * reasons). */ |
H Hartley Sweeten | 40af57a | 2014-07-18 14:28:13 -0700 | [diff] [blame] | 829 | #define NI_EXT_PFI(x) (NI_USUAL_PFI_SELECT(x) - 1) |
| 830 | #define NI_EXT_RTSI(x) (NI_USUAL_RTSI_SELECT(x) - 1) |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 831 | |
| 832 | /* status bits for INSN_CONFIG_GET_COUNTER_STATUS */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 833 | enum comedi_counter_status_flags { |
| 834 | COMEDI_COUNTER_ARMED = 0x1, |
| 835 | COMEDI_COUNTER_COUNTING = 0x2, |
| 836 | COMEDI_COUNTER_TERMINAL_COUNT = 0x4, |
| 837 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 838 | |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 839 | /* Clock sources for CDIO subdevice on NI m-series boards. Used as the |
| 840 | * scan_begin_arg for a comedi_command. These sources may also be bitwise-or'd |
| 841 | * with CR_INVERT to change polarity. */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 842 | enum ni_m_series_cdio_scan_begin_src { |
| 843 | NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0, |
| 844 | NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18, |
| 845 | NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19, |
| 846 | NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20, |
| 847 | NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28, |
| 848 | NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29, |
| 849 | NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30, |
| 850 | NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31, |
| 851 | NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32, |
| 852 | NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33 |
| 853 | }; |
H Hartley Sweeten | 40af57a | 2014-07-18 14:28:13 -0700 | [diff] [blame] | 854 | |
| 855 | #define NI_CDIO_SCAN_BEGIN_SRC_PFI(x) NI_USUAL_PFI_SELECT(x) |
| 856 | #define NI_CDIO_SCAN_BEGIN_SRC_RTSI(x) NI_USUAL_RTSI_SELECT(x) |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 857 | |
Greg Kroah-Hartman | e0dcef7 | 2008-11-13 16:36:22 -0800 | [diff] [blame] | 858 | /* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command on NI |
| 859 | * boards. These scan begin sources can also be bitwise-or'd with CR_INVERT to |
| 860 | * change polarity. */ |
H Hartley Sweeten | 40af57a | 2014-07-18 14:28:13 -0700 | [diff] [blame] | 861 | #define NI_AO_SCAN_BEGIN_SRC_PFI(x) NI_USUAL_PFI_SELECT(x) |
| 862 | #define NI_AO_SCAN_BEGIN_SRC_RTSI(x) NI_USUAL_RTSI_SELECT(x) |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 863 | |
| 864 | /* Bits for setting a clock source with |
| 865 | * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 866 | enum ni_freq_out_clock_source_bits { |
| 867 | NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, /* 10 MHz */ |
| 868 | NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC /* 100 KHz */ |
| 869 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 870 | |
| 871 | /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for |
| 872 | * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 873 | enum amplc_dio_clock_source { |
| 874 | AMPLC_DIO_CLK_CLKN, /* per channel external clock |
| 875 | input/output pin (pin is only an |
| 876 | input when clock source set to this |
| 877 | value, otherwise it is an output) */ |
| 878 | AMPLC_DIO_CLK_10MHZ, /* 10 MHz internal clock */ |
| 879 | AMPLC_DIO_CLK_1MHZ, /* 1 MHz internal clock */ |
| 880 | AMPLC_DIO_CLK_100KHZ, /* 100 kHz internal clock */ |
| 881 | AMPLC_DIO_CLK_10KHZ, /* 10 kHz internal clock */ |
| 882 | AMPLC_DIO_CLK_1KHZ, /* 1 kHz internal clock */ |
| 883 | AMPLC_DIO_CLK_OUTNM1, /* output of preceding counter channel |
| 884 | (for channel 0, preceding counter |
| 885 | channel is channel 2 on preceding |
| 886 | counter subdevice, for first counter |
| 887 | subdevice, preceding counter |
| 888 | subdevice is the last counter |
| 889 | subdevice) */ |
Ian Abbott | 025d1f6 | 2012-10-24 16:48:09 +0100 | [diff] [blame] | 890 | AMPLC_DIO_CLK_EXT, /* per chip external input pin */ |
| 891 | /* the following are "enhanced" clock sources for PCIe models */ |
| 892 | AMPLC_DIO_CLK_VCC, /* clock input HIGH */ |
| 893 | AMPLC_DIO_CLK_GND, /* clock input LOW */ |
| 894 | AMPLC_DIO_CLK_PAT_PRESENT, /* "pattern present" signal */ |
| 895 | AMPLC_DIO_CLK_20MHZ /* 20 MHz internal clock */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 896 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 897 | |
Ian Abbott | c59515a | 2012-10-24 16:48:12 +0100 | [diff] [blame] | 898 | /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for |
| 899 | * timer subdevice on some Amplicon DIO PCIe boards (amplc_dio200 driver). */ |
| 900 | enum amplc_dio_ts_clock_src { |
| 901 | AMPLC_DIO_TS_CLK_1GHZ, /* 1 ns period with 20 ns granularity */ |
| 902 | AMPLC_DIO_TS_CLK_1MHZ, /* 1 us period */ |
| 903 | AMPLC_DIO_TS_CLK_1KHZ /* 1 ms period */ |
| 904 | }; |
| 905 | |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 906 | /* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for |
| 907 | * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 908 | enum amplc_dio_gate_source { |
| 909 | AMPLC_DIO_GAT_VCC, /* internal high logic level */ |
| 910 | AMPLC_DIO_GAT_GND, /* internal low logic level */ |
| 911 | AMPLC_DIO_GAT_GATN, /* per channel external gate input */ |
| 912 | AMPLC_DIO_GAT_NOUTNM2, /* negated output of counter channel |
| 913 | minus 2 (for channels 0 or 1, |
| 914 | channel minus 2 is channel 1 or 2 on |
| 915 | the preceding counter subdevice, for |
| 916 | the first counter subdevice the |
| 917 | preceding counter subdevice is the |
| 918 | last counter subdevice) */ |
| 919 | AMPLC_DIO_GAT_RESERVED4, |
| 920 | AMPLC_DIO_GAT_RESERVED5, |
| 921 | AMPLC_DIO_GAT_RESERVED6, |
Ian Abbott | 025d1f6 | 2012-10-24 16:48:09 +0100 | [diff] [blame] | 922 | AMPLC_DIO_GAT_RESERVED7, |
| 923 | /* the following are "enhanced" gate sources for PCIe models */ |
| 924 | AMPLC_DIO_GAT_NGATN = 6, /* negated per channel gate input */ |
| 925 | AMPLC_DIO_GAT_OUTNM2, /* non-negated output of counter |
| 926 | channel minus 2 */ |
| 927 | AMPLC_DIO_GAT_PAT_PRESENT, /* "pattern present" signal */ |
| 928 | AMPLC_DIO_GAT_PAT_OCCURRED, /* "pattern occurred" latched */ |
| 929 | AMPLC_DIO_GAT_PAT_GONE, /* "pattern gone away" latched */ |
| 930 | AMPLC_DIO_GAT_NPAT_PRESENT, /* negated "pattern present" */ |
| 931 | AMPLC_DIO_GAT_NPAT_OCCURRED, /* negated "pattern occurred" */ |
| 932 | AMPLC_DIO_GAT_NPAT_GONE /* negated "pattern gone away" */ |
H Hartley Sweeten | 25b73c7 | 2012-09-18 11:40:15 -0700 | [diff] [blame] | 933 | }; |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 934 | |
H Hartley Sweeten | 5fc3918 | 2014-06-20 10:39:43 -0700 | [diff] [blame] | 935 | /* |
| 936 | * Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for |
| 937 | * the counter subdevice on the Kolter Electronic PCI-Counter board |
| 938 | * (ke_counter driver). |
| 939 | */ |
| 940 | enum ke_counter_clock_source { |
| 941 | KE_CLK_20MHZ, /* internal 20MHz (default) */ |
| 942 | KE_CLK_4MHZ, /* internal 4MHz (option) */ |
| 943 | KE_CLK_EXT /* external clock on pin 21 of D-Sub */ |
| 944 | }; |
| 945 | |
David Schleef | ed9eccb | 2008-11-04 20:29:31 -0800 | [diff] [blame] | 946 | #endif /* _COMEDI_H */ |