Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 1 | /* |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 2 | * Copyright (c) 2006 Ben Dooks |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 3 | * Copyright 2006-2009 Simtec Electronics |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | */ |
| 11 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 12 | #include <linux/spinlock.h> |
| 13 | #include <linux/workqueue.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/errno.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/clk.h> |
| 19 | #include <linux/platform_device.h> |
Ben Dooks | ee9c1fb | 2009-01-06 14:41:44 -0800 | [diff] [blame] | 20 | #include <linux/gpio.h> |
Ben Dooks | 1a0c220 | 2009-09-22 16:46:12 -0700 | [diff] [blame] | 21 | #include <linux/io.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 22 | #include <linux/slab.h> |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 23 | |
| 24 | #include <linux/spi/spi.h> |
| 25 | #include <linux/spi/spi_bitbang.h> |
Heiko Stuebner | f35ef7c | 2012-01-31 20:06:07 +0900 | [diff] [blame] | 26 | #include <linux/spi/s3c24xx.h> |
Paul Gortmaker | d7614de | 2011-07-03 15:44:29 -0400 | [diff] [blame] | 27 | #include <linux/module.h> |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 28 | |
Ben Dooks | 1362270 | 2008-10-30 10:14:38 +0000 | [diff] [blame] | 29 | #include <plat/regs-spi.h> |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 30 | |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 31 | #include <asm/fiq.h> |
| 32 | |
Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 33 | #include "spi-s3c24xx-fiq.h" |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 34 | |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 35 | /** |
| 36 | * s3c24xx_spi_devstate - per device data |
| 37 | * @hz: Last frequency calculated for @sppre field. |
| 38 | * @mode: Last mode setting for the @spcon field. |
| 39 | * @spcon: Value to write to the SPCON register. |
| 40 | * @sppre: Value to write to the SPPRE register. |
| 41 | */ |
| 42 | struct s3c24xx_spi_devstate { |
| 43 | unsigned int hz; |
| 44 | unsigned int mode; |
| 45 | u8 spcon; |
| 46 | u8 sppre; |
| 47 | }; |
| 48 | |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 49 | enum spi_fiq_mode { |
| 50 | FIQ_MODE_NONE = 0, |
| 51 | FIQ_MODE_TX = 1, |
| 52 | FIQ_MODE_RX = 2, |
| 53 | FIQ_MODE_TXRX = 3, |
| 54 | }; |
| 55 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 56 | struct s3c24xx_spi { |
| 57 | /* bitbang has to be first */ |
| 58 | struct spi_bitbang bitbang; |
| 59 | struct completion done; |
| 60 | |
| 61 | void __iomem *regs; |
| 62 | int irq; |
| 63 | int len; |
| 64 | int count; |
| 65 | |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 66 | struct fiq_handler fiq_handler; |
| 67 | enum spi_fiq_mode fiq_mode; |
| 68 | unsigned char fiq_inuse; |
| 69 | unsigned char fiq_claimed; |
| 70 | |
Arnaud Patard (Rtp | 6c912a3 | 2007-03-16 13:38:36 -0800 | [diff] [blame] | 71 | void (*set_cs)(struct s3c2410_spi_info *spi, |
Ben Dooks | 8736b92 | 2007-01-26 00:56:43 -0800 | [diff] [blame] | 72 | int cs, int pol); |
| 73 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 74 | /* data buffers */ |
| 75 | const unsigned char *tx; |
| 76 | unsigned char *rx; |
| 77 | |
| 78 | struct clk *clk; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 79 | struct spi_master *master; |
| 80 | struct spi_device *curdev; |
| 81 | struct device *dev; |
| 82 | struct s3c2410_spi_info *pdata; |
| 83 | }; |
| 84 | |
| 85 | #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT) |
| 86 | #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP) |
| 87 | |
| 88 | static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev) |
| 89 | { |
| 90 | return spi_master_get_devdata(sdev->master); |
| 91 | } |
| 92 | |
Ben Dooks | 8736b92 | 2007-01-26 00:56:43 -0800 | [diff] [blame] | 93 | static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol) |
| 94 | { |
Ben Dooks | ee9c1fb | 2009-01-06 14:41:44 -0800 | [diff] [blame] | 95 | gpio_set_value(spi->pin_cs, pol); |
Ben Dooks | 8736b92 | 2007-01-26 00:56:43 -0800 | [diff] [blame] | 96 | } |
| 97 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 98 | static void s3c24xx_spi_chipsel(struct spi_device *spi, int value) |
| 99 | { |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 100 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 101 | struct s3c24xx_spi *hw = to_hw(spi); |
| 102 | unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 103 | |
| 104 | /* change the chipselect state and the state of the spi engine clock */ |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 105 | |
| 106 | switch (value) { |
| 107 | case BITBANG_CS_INACTIVE: |
Ben Dooks | 3d2c5b4 | 2007-04-16 22:53:22 -0700 | [diff] [blame] | 108 | hw->set_cs(hw->pdata, spi->chip_select, cspol^1); |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 109 | writeb(cs->spcon, hw->regs + S3C2410_SPCON); |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 110 | break; |
| 111 | |
| 112 | case BITBANG_CS_ACTIVE: |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 113 | writeb(cs->spcon | S3C2410_SPCON_ENSCK, |
| 114 | hw->regs + S3C2410_SPCON); |
Ben Dooks | 3d2c5b4 | 2007-04-16 22:53:22 -0700 | [diff] [blame] | 115 | hw->set_cs(hw->pdata, spi->chip_select, cspol); |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 116 | break; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 117 | } |
| 118 | } |
| 119 | |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 120 | static int s3c24xx_spi_update_state(struct spi_device *spi, |
| 121 | struct spi_transfer *t) |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 122 | { |
| 123 | struct s3c24xx_spi *hw = to_hw(spi); |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 124 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 125 | unsigned int hz; |
| 126 | unsigned int div; |
Ben Dooks | b897878 | 2009-08-18 14:11:16 -0700 | [diff] [blame] | 127 | unsigned long clk; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 128 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 129 | hz = t ? t->speed_hz : spi->max_speed_hz; |
| 130 | |
Ben Dooks | 1915297 | 2009-08-18 14:11:17 -0700 | [diff] [blame] | 131 | if (!hz) |
| 132 | hz = spi->max_speed_hz; |
| 133 | |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 134 | if (spi->mode != cs->mode) { |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 135 | u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 136 | |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 137 | if (spi->mode & SPI_CPHA) |
| 138 | spcon |= S3C2410_SPCON_CPHA_FMTB; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 139 | |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 140 | if (spi->mode & SPI_CPOL) |
| 141 | spcon |= S3C2410_SPCON_CPOL_HIGH; |
Ben Dooks | b897878 | 2009-08-18 14:11:16 -0700 | [diff] [blame] | 142 | |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 143 | cs->mode = spi->mode; |
| 144 | cs->spcon = spcon; |
| 145 | } |
Ben Dooks | b897878 | 2009-08-18 14:11:16 -0700 | [diff] [blame] | 146 | |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 147 | if (cs->hz != hz) { |
| 148 | clk = clk_get_rate(hw->clk); |
| 149 | div = DIV_ROUND_UP(clk, hz * 2) - 1; |
| 150 | |
| 151 | if (div > 255) |
| 152 | div = 255; |
| 153 | |
| 154 | dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n", |
| 155 | div, hz, clk / (2 * (div + 1))); |
| 156 | |
| 157 | cs->hz = hz; |
| 158 | cs->sppre = div; |
| 159 | } |
| 160 | |
| 161 | return 0; |
| 162 | } |
| 163 | |
| 164 | static int s3c24xx_spi_setupxfer(struct spi_device *spi, |
| 165 | struct spi_transfer *t) |
| 166 | { |
| 167 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
| 168 | struct s3c24xx_spi *hw = to_hw(spi); |
| 169 | int ret; |
| 170 | |
| 171 | ret = s3c24xx_spi_update_state(spi, t); |
| 172 | if (!ret) |
| 173 | writeb(cs->sppre, hw->regs + S3C2410_SPPRE); |
| 174 | |
| 175 | return ret; |
| 176 | } |
| 177 | |
| 178 | static int s3c24xx_spi_setup(struct spi_device *spi) |
| 179 | { |
| 180 | struct s3c24xx_spi_devstate *cs = spi->controller_state; |
| 181 | struct s3c24xx_spi *hw = to_hw(spi); |
| 182 | int ret; |
| 183 | |
| 184 | /* allocate settings on the first call */ |
| 185 | if (!cs) { |
Axel Lin | c586feb | 2014-03-31 11:37:29 +0800 | [diff] [blame] | 186 | cs = devm_kzalloc(&spi->dev, |
| 187 | sizeof(struct s3c24xx_spi_devstate), |
| 188 | GFP_KERNEL); |
Jingoo Han | 0375cff | 2014-04-29 17:20:02 +0900 | [diff] [blame^] | 189 | if (!cs) |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 190 | return -ENOMEM; |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 191 | |
| 192 | cs->spcon = SPCON_DEFAULT; |
| 193 | cs->hz = -1; |
| 194 | spi->controller_state = cs; |
| 195 | } |
| 196 | |
| 197 | /* initialise the state from the device */ |
| 198 | ret = s3c24xx_spi_update_state(spi, NULL); |
| 199 | if (ret) |
| 200 | return ret; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 201 | |
| 202 | spin_lock(&hw->bitbang.lock); |
| 203 | if (!hw->bitbang.busy) { |
| 204 | hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); |
| 205 | /* need to ndelay for 0.5 clocktick ? */ |
| 206 | } |
| 207 | spin_unlock(&hw->bitbang.lock); |
| 208 | |
| 209 | return 0; |
| 210 | } |
| 211 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 212 | static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count) |
| 213 | { |
David Brownell | 4b1badf | 2006-12-29 16:48:39 -0800 | [diff] [blame] | 214 | return hw->tx ? hw->tx[count] : 0; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 215 | } |
| 216 | |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 217 | #ifdef CONFIG_SPI_S3C24XX_FIQ |
| 218 | /* Support for FIQ based pseudo-DMA to improve the transfer speed. |
| 219 | * |
| 220 | * This code uses the assembly helper in spi_s3c24xx_spi.S which is |
| 221 | * used by the FIQ core to move data between main memory and the peripheral |
| 222 | * block. Since this is code running on the processor, there is no problem |
| 223 | * with cache coherency of the buffers, so we can use any buffer we like. |
| 224 | */ |
| 225 | |
| 226 | /** |
| 227 | * struct spi_fiq_code - FIQ code and header |
| 228 | * @length: The length of the code fragment, excluding this header. |
| 229 | * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at. |
| 230 | * @data: The code itself to install as a FIQ handler. |
| 231 | */ |
| 232 | struct spi_fiq_code { |
| 233 | u32 length; |
| 234 | u32 ack_offset; |
| 235 | u8 data[0]; |
| 236 | }; |
| 237 | |
| 238 | extern struct spi_fiq_code s3c24xx_spi_fiq_txrx; |
| 239 | extern struct spi_fiq_code s3c24xx_spi_fiq_tx; |
| 240 | extern struct spi_fiq_code s3c24xx_spi_fiq_rx; |
| 241 | |
| 242 | /** |
| 243 | * ack_bit - turn IRQ into IRQ acknowledgement bit |
| 244 | * @irq: The interrupt number |
| 245 | * |
| 246 | * Returns the bit to write to the interrupt acknowledge register. |
| 247 | */ |
| 248 | static inline u32 ack_bit(unsigned int irq) |
| 249 | { |
| 250 | return 1 << (irq - IRQ_EINT0); |
| 251 | } |
| 252 | |
| 253 | /** |
| 254 | * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer |
| 255 | * @hw: The hardware state. |
| 256 | * |
| 257 | * Claim the FIQ handler (only one can be active at any one time) and |
| 258 | * then setup the correct transfer code for this transfer. |
| 259 | * |
Daniel Mack | 3ad2f3f | 2010-02-03 08:01:28 +0800 | [diff] [blame] | 260 | * This call updates all the necessary state information if successful, |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 261 | * so the caller does not need to do anything more than start the transfer |
| 262 | * as normal, since the IRQ will have been re-routed to the FIQ handler. |
| 263 | */ |
Sachin Kamat | cfeb331 | 2013-09-10 11:20:13 +0530 | [diff] [blame] | 264 | static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw) |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 265 | { |
| 266 | struct pt_regs regs; |
| 267 | enum spi_fiq_mode mode; |
| 268 | struct spi_fiq_code *code; |
| 269 | int ret; |
| 270 | |
| 271 | if (!hw->fiq_claimed) { |
| 272 | /* try and claim fiq if we haven't got it, and if not |
| 273 | * then return and simply use another transfer method */ |
| 274 | |
| 275 | ret = claim_fiq(&hw->fiq_handler); |
| 276 | if (ret) |
| 277 | return; |
| 278 | } |
| 279 | |
| 280 | if (hw->tx && !hw->rx) |
| 281 | mode = FIQ_MODE_TX; |
| 282 | else if (hw->rx && !hw->tx) |
| 283 | mode = FIQ_MODE_RX; |
| 284 | else |
| 285 | mode = FIQ_MODE_TXRX; |
| 286 | |
| 287 | regs.uregs[fiq_rspi] = (long)hw->regs; |
| 288 | regs.uregs[fiq_rrx] = (long)hw->rx; |
| 289 | regs.uregs[fiq_rtx] = (long)hw->tx + 1; |
| 290 | regs.uregs[fiq_rcount] = hw->len - 1; |
| 291 | regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ; |
| 292 | |
| 293 | set_fiq_regs(®s); |
| 294 | |
| 295 | if (hw->fiq_mode != mode) { |
| 296 | u32 *ack_ptr; |
| 297 | |
| 298 | hw->fiq_mode = mode; |
| 299 | |
| 300 | switch (mode) { |
| 301 | case FIQ_MODE_TX: |
| 302 | code = &s3c24xx_spi_fiq_tx; |
| 303 | break; |
| 304 | case FIQ_MODE_RX: |
| 305 | code = &s3c24xx_spi_fiq_rx; |
| 306 | break; |
| 307 | case FIQ_MODE_TXRX: |
| 308 | code = &s3c24xx_spi_fiq_txrx; |
| 309 | break; |
| 310 | default: |
| 311 | code = NULL; |
| 312 | } |
| 313 | |
| 314 | BUG_ON(!code); |
| 315 | |
| 316 | ack_ptr = (u32 *)&code->data[code->ack_offset]; |
| 317 | *ack_ptr = ack_bit(hw->irq); |
| 318 | |
| 319 | set_fiq_handler(&code->data, code->length); |
| 320 | } |
| 321 | |
| 322 | s3c24xx_set_fiq(hw->irq, true); |
| 323 | |
| 324 | hw->fiq_mode = mode; |
| 325 | hw->fiq_inuse = 1; |
| 326 | } |
| 327 | |
| 328 | /** |
| 329 | * s3c24xx_spi_fiqop - FIQ core code callback |
| 330 | * @pw: Data registered with the handler |
| 331 | * @release: Whether this is a release or a return. |
| 332 | * |
| 333 | * Called by the FIQ code when another module wants to use the FIQ, so |
| 334 | * return whether we are currently using this or not and then update our |
| 335 | * internal state. |
| 336 | */ |
| 337 | static int s3c24xx_spi_fiqop(void *pw, int release) |
| 338 | { |
| 339 | struct s3c24xx_spi *hw = pw; |
| 340 | int ret = 0; |
| 341 | |
| 342 | if (release) { |
| 343 | if (hw->fiq_inuse) |
| 344 | ret = -EBUSY; |
| 345 | |
| 346 | /* note, we do not need to unroute the FIQ, as the FIQ |
| 347 | * vector code de-routes it to signal the end of transfer */ |
| 348 | |
| 349 | hw->fiq_mode = FIQ_MODE_NONE; |
| 350 | hw->fiq_claimed = 0; |
| 351 | } else { |
| 352 | hw->fiq_claimed = 1; |
| 353 | } |
| 354 | |
| 355 | return ret; |
| 356 | } |
| 357 | |
| 358 | /** |
| 359 | * s3c24xx_spi_initfiq - setup the information for the FIQ core |
| 360 | * @hw: The hardware state. |
| 361 | * |
| 362 | * Setup the fiq_handler block to pass to the FIQ core. |
| 363 | */ |
| 364 | static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw) |
| 365 | { |
| 366 | hw->fiq_handler.dev_id = hw; |
| 367 | hw->fiq_handler.name = dev_name(hw->dev); |
| 368 | hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop; |
| 369 | } |
| 370 | |
| 371 | /** |
| 372 | * s3c24xx_spi_usefiq - return if we should be using FIQ. |
| 373 | * @hw: The hardware state. |
| 374 | * |
| 375 | * Return true if the platform data specifies whether this channel is |
| 376 | * allowed to use the FIQ. |
| 377 | */ |
| 378 | static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw) |
| 379 | { |
| 380 | return hw->pdata->use_fiq; |
| 381 | } |
| 382 | |
| 383 | /** |
| 384 | * s3c24xx_spi_usingfiq - return if channel is using FIQ |
| 385 | * @spi: The hardware state. |
| 386 | * |
| 387 | * Return whether the channel is currently using the FIQ (separate from |
| 388 | * whether the FIQ is claimed). |
| 389 | */ |
| 390 | static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi) |
| 391 | { |
| 392 | return spi->fiq_inuse; |
| 393 | } |
| 394 | #else |
| 395 | |
| 396 | static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { } |
| 397 | static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { } |
| 398 | static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; } |
| 399 | static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; } |
| 400 | |
| 401 | #endif /* CONFIG_SPI_S3C24XX_FIQ */ |
| 402 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 403 | static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t) |
| 404 | { |
| 405 | struct s3c24xx_spi *hw = to_hw(spi); |
| 406 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 407 | hw->tx = t->tx_buf; |
| 408 | hw->rx = t->rx_buf; |
| 409 | hw->len = t->len; |
| 410 | hw->count = 0; |
| 411 | |
Ben Dooks | 4bb5eba | 2008-04-15 14:34:44 -0700 | [diff] [blame] | 412 | init_completion(&hw->done); |
| 413 | |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 414 | hw->fiq_inuse = 0; |
| 415 | if (s3c24xx_spi_usefiq(hw) && t->len >= 3) |
| 416 | s3c24xx_spi_tryfiq(hw); |
| 417 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 418 | /* send the first byte */ |
| 419 | writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT); |
Ben Dooks | 4bb5eba | 2008-04-15 14:34:44 -0700 | [diff] [blame] | 420 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 421 | wait_for_completion(&hw->done); |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 422 | return hw->count; |
| 423 | } |
| 424 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 425 | static irqreturn_t s3c24xx_spi_irq(int irq, void *dev) |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 426 | { |
| 427 | struct s3c24xx_spi *hw = dev; |
| 428 | unsigned int spsta = readb(hw->regs + S3C2410_SPSTA); |
| 429 | unsigned int count = hw->count; |
| 430 | |
| 431 | if (spsta & S3C2410_SPSTA_DCOL) { |
| 432 | dev_dbg(hw->dev, "data-collision\n"); |
| 433 | complete(&hw->done); |
| 434 | goto irq_done; |
| 435 | } |
| 436 | |
| 437 | if (!(spsta & S3C2410_SPSTA_READY)) { |
| 438 | dev_dbg(hw->dev, "spi not ready for tx?\n"); |
| 439 | complete(&hw->done); |
| 440 | goto irq_done; |
| 441 | } |
| 442 | |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 443 | if (!s3c24xx_spi_usingfiq(hw)) { |
| 444 | hw->count++; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 445 | |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 446 | if (hw->rx) |
| 447 | hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT); |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 448 | |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 449 | count++; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 450 | |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 451 | if (count < hw->len) |
| 452 | writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT); |
| 453 | else |
| 454 | complete(&hw->done); |
| 455 | } else { |
| 456 | hw->count = hw->len; |
| 457 | hw->fiq_inuse = 0; |
| 458 | |
| 459 | if (hw->rx) |
| 460 | hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT); |
| 461 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 462 | complete(&hw->done); |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 463 | } |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 464 | |
| 465 | irq_done: |
| 466 | return IRQ_HANDLED; |
| 467 | } |
| 468 | |
Ben Dooks | 5aa6cf3 | 2008-08-04 13:41:10 -0700 | [diff] [blame] | 469 | static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw) |
| 470 | { |
| 471 | /* for the moment, permanently enable the clock */ |
| 472 | |
| 473 | clk_enable(hw->clk); |
| 474 | |
| 475 | /* program defaults into the registers */ |
| 476 | |
| 477 | writeb(0xff, hw->regs + S3C2410_SPPRE); |
| 478 | writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN); |
| 479 | writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON); |
Ben Dooks | cf46b97 | 2008-10-15 22:02:41 -0700 | [diff] [blame] | 480 | |
Ben Dooks | ee9c1fb | 2009-01-06 14:41:44 -0800 | [diff] [blame] | 481 | if (hw->pdata) { |
| 482 | if (hw->set_cs == s3c24xx_spi_gpiocs) |
| 483 | gpio_direction_output(hw->pdata->pin_cs, 1); |
| 484 | |
| 485 | if (hw->pdata->gpio_setup) |
| 486 | hw->pdata->gpio_setup(hw->pdata, 1); |
| 487 | } |
Ben Dooks | 5aa6cf3 | 2008-08-04 13:41:10 -0700 | [diff] [blame] | 488 | } |
| 489 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 490 | static int s3c24xx_spi_probe(struct platform_device *pdev) |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 491 | { |
Ben Dooks | 50f426b | 2008-04-15 14:34:45 -0700 | [diff] [blame] | 492 | struct s3c2410_spi_info *pdata; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 493 | struct s3c24xx_spi *hw; |
| 494 | struct spi_master *master; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 495 | struct resource *res; |
| 496 | int err = 0; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 497 | |
| 498 | master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi)); |
| 499 | if (master == NULL) { |
| 500 | dev_err(&pdev->dev, "No memory for spi_master\n"); |
Jingoo Han | c9f722e | 2013-12-09 19:19:13 +0900 | [diff] [blame] | 501 | return -ENOMEM; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 502 | } |
| 503 | |
| 504 | hw = spi_master_get_devdata(master); |
| 505 | memset(hw, 0, sizeof(struct s3c24xx_spi)); |
| 506 | |
Axel Lin | 94c69f7 | 2013-09-10 15:43:41 +0800 | [diff] [blame] | 507 | hw->master = master; |
Jingoo Han | 8074cf0 | 2013-07-30 16:58:59 +0900 | [diff] [blame] | 508 | hw->pdata = pdata = dev_get_platdata(&pdev->dev); |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 509 | hw->dev = &pdev->dev; |
| 510 | |
Ben Dooks | 50f426b | 2008-04-15 14:34:45 -0700 | [diff] [blame] | 511 | if (pdata == NULL) { |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 512 | dev_err(&pdev->dev, "No platform data supplied\n"); |
| 513 | err = -ENOENT; |
| 514 | goto err_no_pdata; |
| 515 | } |
| 516 | |
| 517 | platform_set_drvdata(pdev, hw); |
| 518 | init_completion(&hw->done); |
| 519 | |
Ben Dooks | bec0806 | 2009-12-14 22:20:24 -0800 | [diff] [blame] | 520 | /* initialise fiq handler */ |
| 521 | |
| 522 | s3c24xx_spi_initfiq(hw); |
| 523 | |
Ben Dooks | d1e7780 | 2008-04-15 14:34:46 -0700 | [diff] [blame] | 524 | /* setup the master state. */ |
| 525 | |
David Brownell | e7db06b | 2009-06-17 16:26:04 -0700 | [diff] [blame] | 526 | /* the spi->mode bits understood by this driver: */ |
| 527 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
| 528 | |
Ben Dooks | d1e7780 | 2008-04-15 14:34:46 -0700 | [diff] [blame] | 529 | master->num_chipselect = hw->pdata->num_cs; |
Ben Dooks | cb1d0a7 | 2008-07-28 15:46:33 -0700 | [diff] [blame] | 530 | master->bus_num = pdata->bus_num; |
Axel Lin | 08850fa | 2014-02-14 20:38:16 +0800 | [diff] [blame] | 531 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
Ben Dooks | d1e7780 | 2008-04-15 14:34:46 -0700 | [diff] [blame] | 532 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 533 | /* setup the state for the bitbang driver */ |
| 534 | |
| 535 | hw->bitbang.master = hw->master; |
| 536 | hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer; |
| 537 | hw->bitbang.chipselect = s3c24xx_spi_chipsel; |
| 538 | hw->bitbang.txrx_bufs = s3c24xx_spi_txrx; |
Ben Dooks | 570327d | 2009-09-22 16:46:14 -0700 | [diff] [blame] | 539 | |
| 540 | hw->master->setup = s3c24xx_spi_setup; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 541 | |
| 542 | dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); |
| 543 | |
| 544 | /* find and map our resources */ |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 545 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Jingoo Han | c9f722e | 2013-12-09 19:19:13 +0900 | [diff] [blame] | 546 | hw->regs = devm_ioremap_resource(&pdev->dev, res); |
| 547 | if (IS_ERR(hw->regs)) { |
| 548 | err = PTR_ERR(hw->regs); |
| 549 | goto err_no_pdata; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 550 | } |
| 551 | |
| 552 | hw->irq = platform_get_irq(pdev, 0); |
| 553 | if (hw->irq < 0) { |
| 554 | dev_err(&pdev->dev, "No IRQ specified\n"); |
| 555 | err = -ENOENT; |
Jingoo Han | c9f722e | 2013-12-09 19:19:13 +0900 | [diff] [blame] | 556 | goto err_no_pdata; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 557 | } |
| 558 | |
Jingoo Han | c9f722e | 2013-12-09 19:19:13 +0900 | [diff] [blame] | 559 | err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0, |
| 560 | pdev->name, hw); |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 561 | if (err) { |
| 562 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); |
Jingoo Han | c9f722e | 2013-12-09 19:19:13 +0900 | [diff] [blame] | 563 | goto err_no_pdata; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 564 | } |
| 565 | |
Jingoo Han | c9f722e | 2013-12-09 19:19:13 +0900 | [diff] [blame] | 566 | hw->clk = devm_clk_get(&pdev->dev, "spi"); |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 567 | if (IS_ERR(hw->clk)) { |
| 568 | dev_err(&pdev->dev, "No clock for device\n"); |
| 569 | err = PTR_ERR(hw->clk); |
Jingoo Han | c9f722e | 2013-12-09 19:19:13 +0900 | [diff] [blame] | 570 | goto err_no_pdata; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 571 | } |
| 572 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 573 | /* setup any gpio we can */ |
| 574 | |
Ben Dooks | 50f426b | 2008-04-15 14:34:45 -0700 | [diff] [blame] | 575 | if (!pdata->set_cs) { |
Ben Dooks | ee9c1fb | 2009-01-06 14:41:44 -0800 | [diff] [blame] | 576 | if (pdata->pin_cs < 0) { |
| 577 | dev_err(&pdev->dev, "No chipselect pin\n"); |
Julia Lawall | b2af045 | 2012-08-22 13:42:47 +0200 | [diff] [blame] | 578 | err = -EINVAL; |
Ben Dooks | ee9c1fb | 2009-01-06 14:41:44 -0800 | [diff] [blame] | 579 | goto err_register; |
| 580 | } |
Ben Dooks | 8736b92 | 2007-01-26 00:56:43 -0800 | [diff] [blame] | 581 | |
Jingoo Han | c9f722e | 2013-12-09 19:19:13 +0900 | [diff] [blame] | 582 | err = devm_gpio_request(&pdev->dev, pdata->pin_cs, |
| 583 | dev_name(&pdev->dev)); |
Ben Dooks | ee9c1fb | 2009-01-06 14:41:44 -0800 | [diff] [blame] | 584 | if (err) { |
| 585 | dev_err(&pdev->dev, "Failed to get gpio for cs\n"); |
| 586 | goto err_register; |
| 587 | } |
| 588 | |
| 589 | hw->set_cs = s3c24xx_spi_gpiocs; |
| 590 | gpio_direction_output(pdata->pin_cs, 1); |
Ben Dooks | 8736b92 | 2007-01-26 00:56:43 -0800 | [diff] [blame] | 591 | } else |
Ben Dooks | 50f426b | 2008-04-15 14:34:45 -0700 | [diff] [blame] | 592 | hw->set_cs = pdata->set_cs; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 593 | |
Ben Dooks | ee9c1fb | 2009-01-06 14:41:44 -0800 | [diff] [blame] | 594 | s3c24xx_spi_initialsetup(hw); |
| 595 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 596 | /* register our spi controller */ |
| 597 | |
| 598 | err = spi_bitbang_start(&hw->bitbang); |
| 599 | if (err) { |
| 600 | dev_err(&pdev->dev, "Failed to register SPI master\n"); |
| 601 | goto err_register; |
| 602 | } |
| 603 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 604 | return 0; |
| 605 | |
| 606 | err_register: |
| 607 | clk_disable(hw->clk); |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 608 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 609 | err_no_pdata: |
Joe Perches | a419aef | 2009-08-18 11:18:35 -0700 | [diff] [blame] | 610 | spi_master_put(hw->master); |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 611 | return err; |
| 612 | } |
| 613 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 614 | static int s3c24xx_spi_remove(struct platform_device *dev) |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 615 | { |
| 616 | struct s3c24xx_spi *hw = platform_get_drvdata(dev); |
| 617 | |
Axel Lin | c6e7b8c | 2011-05-15 07:35:16 +0800 | [diff] [blame] | 618 | spi_bitbang_stop(&hw->bitbang); |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 619 | clk_disable(hw->clk); |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 620 | spi_master_put(hw->master); |
| 621 | return 0; |
| 622 | } |
| 623 | |
| 624 | |
| 625 | #ifdef CONFIG_PM |
| 626 | |
Ben Dooks | 6d61320 | 2009-09-22 16:46:13 -0700 | [diff] [blame] | 627 | static int s3c24xx_spi_suspend(struct device *dev) |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 628 | { |
Axel Lin | a1216394 | 2013-08-09 15:35:16 +0800 | [diff] [blame] | 629 | struct s3c24xx_spi *hw = dev_get_drvdata(dev); |
Axel Lin | 3806037 | 2014-03-05 15:17:23 +0800 | [diff] [blame] | 630 | int ret; |
| 631 | |
| 632 | ret = spi_master_suspend(hw->master); |
| 633 | if (ret) |
| 634 | return ret; |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 635 | |
Ben Dooks | cf46b97 | 2008-10-15 22:02:41 -0700 | [diff] [blame] | 636 | if (hw->pdata && hw->pdata->gpio_setup) |
| 637 | hw->pdata->gpio_setup(hw->pdata, 0); |
| 638 | |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 639 | clk_disable(hw->clk); |
| 640 | return 0; |
| 641 | } |
| 642 | |
Ben Dooks | 6d61320 | 2009-09-22 16:46:13 -0700 | [diff] [blame] | 643 | static int s3c24xx_spi_resume(struct device *dev) |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 644 | { |
Axel Lin | a1216394 | 2013-08-09 15:35:16 +0800 | [diff] [blame] | 645 | struct s3c24xx_spi *hw = dev_get_drvdata(dev); |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 646 | |
Ben Dooks | 5aa6cf3 | 2008-08-04 13:41:10 -0700 | [diff] [blame] | 647 | s3c24xx_spi_initialsetup(hw); |
Axel Lin | 3806037 | 2014-03-05 15:17:23 +0800 | [diff] [blame] | 648 | return spi_master_resume(hw->master); |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 649 | } |
| 650 | |
Alexey Dobriyan | 4714521 | 2009-12-14 18:00:08 -0800 | [diff] [blame] | 651 | static const struct dev_pm_ops s3c24xx_spi_pmops = { |
Ben Dooks | 6d61320 | 2009-09-22 16:46:13 -0700 | [diff] [blame] | 652 | .suspend = s3c24xx_spi_suspend, |
| 653 | .resume = s3c24xx_spi_resume, |
| 654 | }; |
| 655 | |
| 656 | #define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 657 | #else |
Ben Dooks | 6d61320 | 2009-09-22 16:46:13 -0700 | [diff] [blame] | 658 | #define S3C24XX_SPI_PMOPS NULL |
| 659 | #endif /* CONFIG_PM */ |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 660 | |
Kay Sievers | 7e38c3c | 2008-04-10 21:29:20 -0700 | [diff] [blame] | 661 | MODULE_ALIAS("platform:s3c2410-spi"); |
Ben Dooks | 42cde43 | 2008-09-13 02:33:24 -0700 | [diff] [blame] | 662 | static struct platform_driver s3c24xx_spi_driver = { |
Grant Likely | 940ab88 | 2011-10-05 11:29:49 -0600 | [diff] [blame] | 663 | .probe = s3c24xx_spi_probe, |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 664 | .remove = s3c24xx_spi_remove, |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 665 | .driver = { |
| 666 | .name = "s3c2410-spi", |
| 667 | .owner = THIS_MODULE, |
Ben Dooks | 6d61320 | 2009-09-22 16:46:13 -0700 | [diff] [blame] | 668 | .pm = S3C24XX_SPI_PMOPS, |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 669 | }, |
| 670 | }; |
Grant Likely | 940ab88 | 2011-10-05 11:29:49 -0600 | [diff] [blame] | 671 | module_platform_driver(s3c24xx_spi_driver); |
Ben Dooks | 7fba534 | 2006-05-20 15:00:18 -0700 | [diff] [blame] | 672 | |
| 673 | MODULE_DESCRIPTION("S3C24XX SPI Driver"); |
| 674 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); |
| 675 | MODULE_LICENSE("GPL"); |