Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2005-2011 Atheros Communications Inc. |
| 3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. |
| 4 | * |
| 5 | * Permission to use, copy, modify, and/or distribute this software for any |
| 6 | * purpose with or without fee is hereby granted, provided that the above |
| 7 | * copyright notice and this permission notice appear in all copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/pci.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/spinlock.h> |
Kalle Valo | 650b91f | 2013-11-20 10:00:49 +0200 | [diff] [blame] | 22 | #include <linux/bitops.h> |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 23 | |
| 24 | #include "core.h" |
| 25 | #include "debug.h" |
| 26 | |
| 27 | #include "targaddrs.h" |
| 28 | #include "bmi.h" |
| 29 | |
| 30 | #include "hif.h" |
| 31 | #include "htc.h" |
| 32 | |
| 33 | #include "ce.h" |
| 34 | #include "pci.h" |
| 35 | |
Michal Kazior | cfe9c45 | 2013-11-25 14:06:27 +0100 | [diff] [blame] | 36 | enum ath10k_pci_irq_mode { |
| 37 | ATH10K_PCI_IRQ_AUTO = 0, |
| 38 | ATH10K_PCI_IRQ_LEGACY = 1, |
| 39 | ATH10K_PCI_IRQ_MSI = 2, |
| 40 | }; |
| 41 | |
Kalle Valo | 3509846 | 2014-03-28 09:32:27 +0200 | [diff] [blame] | 42 | enum ath10k_pci_reset_mode { |
| 43 | ATH10K_PCI_RESET_AUTO = 0, |
| 44 | ATH10K_PCI_RESET_WARM_ONLY = 1, |
| 45 | }; |
| 46 | |
Michal Kazior | cfe9c45 | 2013-11-25 14:06:27 +0100 | [diff] [blame] | 47 | static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; |
Kalle Valo | 3509846 | 2014-03-28 09:32:27 +0200 | [diff] [blame] | 48 | static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; |
Michal Kazior | cfe9c45 | 2013-11-25 14:06:27 +0100 | [diff] [blame] | 49 | |
Michal Kazior | cfe9c45 | 2013-11-25 14:06:27 +0100 | [diff] [blame] | 50 | module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); |
| 51 | MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); |
| 52 | |
Kalle Valo | 3509846 | 2014-03-28 09:32:27 +0200 | [diff] [blame] | 53 | module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); |
| 54 | MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); |
| 55 | |
Kalle Valo | 0399eca | 2014-03-28 09:32:21 +0200 | [diff] [blame] | 56 | /* how long wait to wait for target to initialise, in ms */ |
| 57 | #define ATH10K_PCI_TARGET_WAIT 3000 |
Michal Kazior | 61c95ce | 2014-05-14 16:56:16 +0300 | [diff] [blame] | 58 | #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 |
Kalle Valo | 0399eca | 2014-03-28 09:32:21 +0200 | [diff] [blame] | 59 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 60 | #define QCA988X_2_0_DEVICE_ID (0x003c) |
Michal Kazior | 36582e5 | 2015-08-13 14:32:26 +0200 | [diff] [blame] | 61 | #define QCA6164_2_1_DEVICE_ID (0x0041) |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 62 | #define QCA6174_2_1_DEVICE_ID (0x003e) |
Vasanthakumar Thiagarajan | 8bd4702 | 2015-06-18 12:31:03 +0530 | [diff] [blame] | 63 | #define QCA99X0_2_0_DEVICE_ID (0x0040) |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 64 | #define QCA9377_1_0_DEVICE_ID (0x0042) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 65 | |
Benoit Taine | 9baa3c3 | 2014-08-08 15:56:03 +0200 | [diff] [blame] | 66 | static const struct pci_device_id ath10k_pci_id_table[] = { |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 67 | { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */ |
Michal Kazior | 36582e5 | 2015-08-13 14:32:26 +0200 | [diff] [blame] | 68 | { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */ |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 69 | { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */ |
Vasanthakumar Thiagarajan | 8a055a8 | 2015-07-29 11:40:39 +0300 | [diff] [blame] | 70 | { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */ |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 71 | { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */ |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 72 | {0} |
| 73 | }; |
| 74 | |
Michal Kazior | 7505f7c | 2014-12-02 10:55:54 +0200 | [diff] [blame] | 75 | static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = { |
| 76 | /* QCA988X pre 2.0 chips are not supported because they need some nasty |
| 77 | * hacks. ath10k doesn't have them and these devices crash horribly |
| 78 | * because of that. |
| 79 | */ |
| 80 | { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV }, |
Michal Kazior | 36582e5 | 2015-08-13 14:32:26 +0200 | [diff] [blame] | 81 | |
| 82 | { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, |
| 83 | { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, |
| 84 | { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, |
| 85 | { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, |
| 86 | { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, |
| 87 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 88 | { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, |
| 89 | { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, |
| 90 | { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, |
| 91 | { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, |
| 92 | { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, |
Michal Kazior | 36582e5 | 2015-08-13 14:32:26 +0200 | [diff] [blame] | 93 | |
Vasanthakumar Thiagarajan | 8a055a8 | 2015-07-29 11:40:39 +0300 | [diff] [blame] | 94 | { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV }, |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 95 | { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV }, |
Michal Kazior | 7505f7c | 2014-12-02 10:55:54 +0200 | [diff] [blame] | 96 | }; |
| 97 | |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 98 | static void ath10k_pci_buffer_cleanup(struct ath10k *ar); |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 99 | static int ath10k_pci_cold_reset(struct ath10k *ar); |
Vasanthakumar Thiagarajan | 6e4202c | 2015-06-18 12:31:06 +0530 | [diff] [blame] | 100 | static int ath10k_pci_safe_chip_reset(struct ath10k *ar); |
Michal Kazior | d7fb47f | 2013-11-08 08:01:26 +0100 | [diff] [blame] | 101 | static int ath10k_pci_wait_for_target_init(struct ath10k *ar); |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 102 | static int ath10k_pci_init_irq(struct ath10k *ar); |
| 103 | static int ath10k_pci_deinit_irq(struct ath10k *ar); |
| 104 | static int ath10k_pci_request_irq(struct ath10k *ar); |
| 105 | static void ath10k_pci_free_irq(struct ath10k *ar); |
Michal Kazior | 85622cd | 2013-11-25 14:06:22 +0100 | [diff] [blame] | 106 | static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe, |
| 107 | struct ath10k_ce_pipe *rx_pipe, |
| 108 | struct bmi_xfer *xfer); |
Vasanthakumar Thiagarajan | 6e4202c | 2015-06-18 12:31:06 +0530 | [diff] [blame] | 109 | static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar); |
Rajkumar Manoharan | 0e5b295 | 2015-10-12 18:27:01 +0530 | [diff] [blame] | 110 | static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state); |
Rajkumar Manoharan | 9d9bdbb | 2015-10-12 18:27:02 +0530 | [diff] [blame] | 111 | static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state); |
Rajkumar Manoharan | a70587b | 2015-10-12 18:27:04 +0530 | [diff] [blame] | 112 | static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state); |
| 113 | static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 114 | |
| 115 | static const struct ce_attr host_ce_config_wlan[] = { |
Kalle Valo | 48e9c22 | 2013-09-01 10:01:32 +0300 | [diff] [blame] | 116 | /* CE0: host->target HTC control and raw streams */ |
| 117 | { |
| 118 | .flags = CE_ATTR_FLAGS, |
| 119 | .src_nentries = 16, |
| 120 | .src_sz_max = 256, |
| 121 | .dest_nentries = 0, |
Rajkumar Manoharan | 0e5b295 | 2015-10-12 18:27:01 +0530 | [diff] [blame] | 122 | .send_cb = ath10k_pci_htc_tx_cb, |
Kalle Valo | 48e9c22 | 2013-09-01 10:01:32 +0300 | [diff] [blame] | 123 | }, |
| 124 | |
| 125 | /* CE1: target->host HTT + HTC control */ |
| 126 | { |
| 127 | .flags = CE_ATTR_FLAGS, |
| 128 | .src_nentries = 0, |
Michal Kazior | 6383864 | 2015-02-09 15:04:55 +0100 | [diff] [blame] | 129 | .src_sz_max = 2048, |
Kalle Valo | 48e9c22 | 2013-09-01 10:01:32 +0300 | [diff] [blame] | 130 | .dest_nentries = 512, |
Rajkumar Manoharan | 9d9bdbb | 2015-10-12 18:27:02 +0530 | [diff] [blame] | 131 | .recv_cb = ath10k_pci_htc_rx_cb, |
Kalle Valo | 48e9c22 | 2013-09-01 10:01:32 +0300 | [diff] [blame] | 132 | }, |
| 133 | |
| 134 | /* CE2: target->host WMI */ |
| 135 | { |
| 136 | .flags = CE_ATTR_FLAGS, |
| 137 | .src_nentries = 0, |
| 138 | .src_sz_max = 2048, |
Rajkumar Manoharan | 30abb33 | 2015-03-04 15:43:44 +0200 | [diff] [blame] | 139 | .dest_nentries = 128, |
Rajkumar Manoharan | 9d9bdbb | 2015-10-12 18:27:02 +0530 | [diff] [blame] | 140 | .recv_cb = ath10k_pci_htc_rx_cb, |
Kalle Valo | 48e9c22 | 2013-09-01 10:01:32 +0300 | [diff] [blame] | 141 | }, |
| 142 | |
| 143 | /* CE3: host->target WMI */ |
| 144 | { |
| 145 | .flags = CE_ATTR_FLAGS, |
| 146 | .src_nentries = 32, |
| 147 | .src_sz_max = 2048, |
| 148 | .dest_nentries = 0, |
Rajkumar Manoharan | 0e5b295 | 2015-10-12 18:27:01 +0530 | [diff] [blame] | 149 | .send_cb = ath10k_pci_htc_tx_cb, |
Kalle Valo | 48e9c22 | 2013-09-01 10:01:32 +0300 | [diff] [blame] | 150 | }, |
| 151 | |
| 152 | /* CE4: host->target HTT */ |
| 153 | { |
| 154 | .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, |
| 155 | .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES, |
| 156 | .src_sz_max = 256, |
| 157 | .dest_nentries = 0, |
Rajkumar Manoharan | a70587b | 2015-10-12 18:27:04 +0530 | [diff] [blame] | 158 | .send_cb = ath10k_pci_htt_tx_cb, |
Kalle Valo | 48e9c22 | 2013-09-01 10:01:32 +0300 | [diff] [blame] | 159 | }, |
| 160 | |
Rajkumar Manoharan | a70587b | 2015-10-12 18:27:04 +0530 | [diff] [blame] | 161 | /* CE5: target->host HTT (HIF->HTT) */ |
Kalle Valo | 48e9c22 | 2013-09-01 10:01:32 +0300 | [diff] [blame] | 162 | { |
| 163 | .flags = CE_ATTR_FLAGS, |
| 164 | .src_nentries = 0, |
Rajkumar Manoharan | a70587b | 2015-10-12 18:27:04 +0530 | [diff] [blame] | 165 | .src_sz_max = 512, |
| 166 | .dest_nentries = 512, |
| 167 | .recv_cb = ath10k_pci_htt_rx_cb, |
Kalle Valo | 48e9c22 | 2013-09-01 10:01:32 +0300 | [diff] [blame] | 168 | }, |
| 169 | |
| 170 | /* CE6: target autonomous hif_memcpy */ |
| 171 | { |
| 172 | .flags = CE_ATTR_FLAGS, |
| 173 | .src_nentries = 0, |
| 174 | .src_sz_max = 0, |
| 175 | .dest_nentries = 0, |
| 176 | }, |
| 177 | |
| 178 | /* CE7: ce_diag, the Diagnostic Window */ |
| 179 | { |
| 180 | .flags = CE_ATTR_FLAGS, |
| 181 | .src_nentries = 2, |
| 182 | .src_sz_max = DIAG_TRANSFER_LIMIT, |
| 183 | .dest_nentries = 2, |
| 184 | }, |
Vasanthakumar Thiagarajan | 050af06 | 2015-06-18 12:31:04 +0530 | [diff] [blame] | 185 | |
| 186 | /* CE8: target->host pktlog */ |
| 187 | { |
| 188 | .flags = CE_ATTR_FLAGS, |
| 189 | .src_nentries = 0, |
| 190 | .src_sz_max = 2048, |
| 191 | .dest_nentries = 128, |
| 192 | }, |
| 193 | |
| 194 | /* CE9 target autonomous qcache memcpy */ |
| 195 | { |
| 196 | .flags = CE_ATTR_FLAGS, |
| 197 | .src_nentries = 0, |
| 198 | .src_sz_max = 0, |
| 199 | .dest_nentries = 0, |
| 200 | }, |
| 201 | |
| 202 | /* CE10: target autonomous hif memcpy */ |
| 203 | { |
| 204 | .flags = CE_ATTR_FLAGS, |
| 205 | .src_nentries = 0, |
| 206 | .src_sz_max = 0, |
| 207 | .dest_nentries = 0, |
| 208 | }, |
| 209 | |
| 210 | /* CE11: target autonomous hif memcpy */ |
| 211 | { |
| 212 | .flags = CE_ATTR_FLAGS, |
| 213 | .src_nentries = 0, |
| 214 | .src_sz_max = 0, |
| 215 | .dest_nentries = 0, |
| 216 | }, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 217 | }; |
| 218 | |
| 219 | /* Target firmware's Copy Engine configuration. */ |
| 220 | static const struct ce_pipe_config target_ce_config_wlan[] = { |
Kalle Valo | d88effb | 2013-09-01 10:01:39 +0300 | [diff] [blame] | 221 | /* CE0: host->target HTC control and raw streams */ |
| 222 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 223 | .pipenum = __cpu_to_le32(0), |
| 224 | .pipedir = __cpu_to_le32(PIPEDIR_OUT), |
| 225 | .nentries = __cpu_to_le32(32), |
| 226 | .nbytes_max = __cpu_to_le32(256), |
| 227 | .flags = __cpu_to_le32(CE_ATTR_FLAGS), |
| 228 | .reserved = __cpu_to_le32(0), |
Kalle Valo | d88effb | 2013-09-01 10:01:39 +0300 | [diff] [blame] | 229 | }, |
| 230 | |
| 231 | /* CE1: target->host HTT + HTC control */ |
| 232 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 233 | .pipenum = __cpu_to_le32(1), |
| 234 | .pipedir = __cpu_to_le32(PIPEDIR_IN), |
| 235 | .nentries = __cpu_to_le32(32), |
Michal Kazior | 6383864 | 2015-02-09 15:04:55 +0100 | [diff] [blame] | 236 | .nbytes_max = __cpu_to_le32(2048), |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 237 | .flags = __cpu_to_le32(CE_ATTR_FLAGS), |
| 238 | .reserved = __cpu_to_le32(0), |
Kalle Valo | d88effb | 2013-09-01 10:01:39 +0300 | [diff] [blame] | 239 | }, |
| 240 | |
| 241 | /* CE2: target->host WMI */ |
| 242 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 243 | .pipenum = __cpu_to_le32(2), |
| 244 | .pipedir = __cpu_to_le32(PIPEDIR_IN), |
Rajkumar Manoharan | 30abb33 | 2015-03-04 15:43:44 +0200 | [diff] [blame] | 245 | .nentries = __cpu_to_le32(64), |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 246 | .nbytes_max = __cpu_to_le32(2048), |
| 247 | .flags = __cpu_to_le32(CE_ATTR_FLAGS), |
| 248 | .reserved = __cpu_to_le32(0), |
Kalle Valo | d88effb | 2013-09-01 10:01:39 +0300 | [diff] [blame] | 249 | }, |
| 250 | |
| 251 | /* CE3: host->target WMI */ |
| 252 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 253 | .pipenum = __cpu_to_le32(3), |
| 254 | .pipedir = __cpu_to_le32(PIPEDIR_OUT), |
| 255 | .nentries = __cpu_to_le32(32), |
| 256 | .nbytes_max = __cpu_to_le32(2048), |
| 257 | .flags = __cpu_to_le32(CE_ATTR_FLAGS), |
| 258 | .reserved = __cpu_to_le32(0), |
Kalle Valo | d88effb | 2013-09-01 10:01:39 +0300 | [diff] [blame] | 259 | }, |
| 260 | |
| 261 | /* CE4: host->target HTT */ |
| 262 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 263 | .pipenum = __cpu_to_le32(4), |
| 264 | .pipedir = __cpu_to_le32(PIPEDIR_OUT), |
| 265 | .nentries = __cpu_to_le32(256), |
| 266 | .nbytes_max = __cpu_to_le32(256), |
| 267 | .flags = __cpu_to_le32(CE_ATTR_FLAGS), |
| 268 | .reserved = __cpu_to_le32(0), |
Kalle Valo | d88effb | 2013-09-01 10:01:39 +0300 | [diff] [blame] | 269 | }, |
| 270 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 271 | /* NB: 50% of src nentries, since tx has 2 frags */ |
Kalle Valo | d88effb | 2013-09-01 10:01:39 +0300 | [diff] [blame] | 272 | |
Rajkumar Manoharan | a70587b | 2015-10-12 18:27:04 +0530 | [diff] [blame] | 273 | /* CE5: target->host HTT (HIF->HTT) */ |
Kalle Valo | d88effb | 2013-09-01 10:01:39 +0300 | [diff] [blame] | 274 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 275 | .pipenum = __cpu_to_le32(5), |
Rajkumar Manoharan | a70587b | 2015-10-12 18:27:04 +0530 | [diff] [blame] | 276 | .pipedir = __cpu_to_le32(PIPEDIR_IN), |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 277 | .nentries = __cpu_to_le32(32), |
Rajkumar Manoharan | a70587b | 2015-10-12 18:27:04 +0530 | [diff] [blame] | 278 | .nbytes_max = __cpu_to_le32(512), |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 279 | .flags = __cpu_to_le32(CE_ATTR_FLAGS), |
| 280 | .reserved = __cpu_to_le32(0), |
Kalle Valo | d88effb | 2013-09-01 10:01:39 +0300 | [diff] [blame] | 281 | }, |
| 282 | |
| 283 | /* CE6: Reserved for target autonomous hif_memcpy */ |
| 284 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 285 | .pipenum = __cpu_to_le32(6), |
| 286 | .pipedir = __cpu_to_le32(PIPEDIR_INOUT), |
| 287 | .nentries = __cpu_to_le32(32), |
| 288 | .nbytes_max = __cpu_to_le32(4096), |
| 289 | .flags = __cpu_to_le32(CE_ATTR_FLAGS), |
| 290 | .reserved = __cpu_to_le32(0), |
Kalle Valo | d88effb | 2013-09-01 10:01:39 +0300 | [diff] [blame] | 291 | }, |
| 292 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 293 | /* CE7 used only by Host */ |
Vasanthakumar Thiagarajan | 050af06 | 2015-06-18 12:31:04 +0530 | [diff] [blame] | 294 | { |
| 295 | .pipenum = __cpu_to_le32(7), |
| 296 | .pipedir = __cpu_to_le32(PIPEDIR_INOUT), |
| 297 | .nentries = __cpu_to_le32(0), |
| 298 | .nbytes_max = __cpu_to_le32(0), |
| 299 | .flags = __cpu_to_le32(0), |
| 300 | .reserved = __cpu_to_le32(0), |
| 301 | }, |
| 302 | |
| 303 | /* CE8 target->host packtlog */ |
| 304 | { |
| 305 | .pipenum = __cpu_to_le32(8), |
| 306 | .pipedir = __cpu_to_le32(PIPEDIR_IN), |
| 307 | .nentries = __cpu_to_le32(64), |
| 308 | .nbytes_max = __cpu_to_le32(2048), |
| 309 | .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), |
| 310 | .reserved = __cpu_to_le32(0), |
| 311 | }, |
| 312 | |
| 313 | /* CE9 target autonomous qcache memcpy */ |
| 314 | { |
| 315 | .pipenum = __cpu_to_le32(9), |
| 316 | .pipedir = __cpu_to_le32(PIPEDIR_INOUT), |
| 317 | .nentries = __cpu_to_le32(32), |
| 318 | .nbytes_max = __cpu_to_le32(2048), |
| 319 | .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), |
| 320 | .reserved = __cpu_to_le32(0), |
| 321 | }, |
| 322 | |
| 323 | /* It not necessary to send target wlan configuration for CE10 & CE11 |
| 324 | * as these CEs are not actively used in target. |
| 325 | */ |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 326 | }; |
| 327 | |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 328 | /* |
| 329 | * Map from service/endpoint to Copy Engine. |
| 330 | * This table is derived from the CE_PCI TABLE, above. |
| 331 | * It is passed to the Target at startup for use by firmware. |
| 332 | */ |
| 333 | static const struct service_to_pipe target_service_to_ce_map_wlan[] = { |
| 334 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 335 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), |
| 336 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ |
| 337 | __cpu_to_le32(3), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 338 | }, |
| 339 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 340 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), |
| 341 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ |
| 342 | __cpu_to_le32(2), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 343 | }, |
| 344 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 345 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), |
| 346 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ |
| 347 | __cpu_to_le32(3), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 348 | }, |
| 349 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 350 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), |
| 351 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ |
| 352 | __cpu_to_le32(2), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 353 | }, |
| 354 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 355 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), |
| 356 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ |
| 357 | __cpu_to_le32(3), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 358 | }, |
| 359 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 360 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), |
| 361 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ |
| 362 | __cpu_to_le32(2), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 363 | }, |
| 364 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 365 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), |
| 366 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ |
| 367 | __cpu_to_le32(3), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 368 | }, |
| 369 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 370 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), |
| 371 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ |
| 372 | __cpu_to_le32(2), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 373 | }, |
| 374 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 375 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), |
| 376 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ |
| 377 | __cpu_to_le32(3), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 378 | }, |
| 379 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 380 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), |
| 381 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ |
| 382 | __cpu_to_le32(2), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 383 | }, |
| 384 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 385 | __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), |
| 386 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ |
| 387 | __cpu_to_le32(0), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 388 | }, |
| 389 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 390 | __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), |
| 391 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ |
| 392 | __cpu_to_le32(1), |
| 393 | }, |
| 394 | { /* not used */ |
| 395 | __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), |
| 396 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ |
| 397 | __cpu_to_le32(0), |
| 398 | }, |
| 399 | { /* not used */ |
| 400 | __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), |
| 401 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ |
| 402 | __cpu_to_le32(1), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 403 | }, |
| 404 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 405 | __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), |
| 406 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ |
| 407 | __cpu_to_le32(4), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 408 | }, |
| 409 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 410 | __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), |
| 411 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ |
Rajkumar Manoharan | a70587b | 2015-10-12 18:27:04 +0530 | [diff] [blame] | 412 | __cpu_to_le32(5), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 413 | }, |
| 414 | |
| 415 | /* (Additions here) */ |
| 416 | |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 417 | { /* must be last */ |
| 418 | __cpu_to_le32(0), |
| 419 | __cpu_to_le32(0), |
| 420 | __cpu_to_le32(0), |
Michal Kazior | d7bfb7a | 2014-08-26 19:14:02 +0300 | [diff] [blame] | 421 | }, |
| 422 | }; |
| 423 | |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 424 | static bool ath10k_pci_is_awake(struct ath10k *ar) |
| 425 | { |
| 426 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 427 | u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + |
| 428 | RTC_STATE_ADDRESS); |
| 429 | |
| 430 | return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; |
| 431 | } |
| 432 | |
| 433 | static void __ath10k_pci_wake(struct ath10k *ar) |
| 434 | { |
| 435 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 436 | |
| 437 | lockdep_assert_held(&ar_pci->ps_lock); |
| 438 | |
| 439 | ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n", |
| 440 | ar_pci->ps_wake_refcount, ar_pci->ps_awake); |
| 441 | |
| 442 | iowrite32(PCIE_SOC_WAKE_V_MASK, |
| 443 | ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + |
| 444 | PCIE_SOC_WAKE_ADDRESS); |
| 445 | } |
| 446 | |
| 447 | static void __ath10k_pci_sleep(struct ath10k *ar) |
| 448 | { |
| 449 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 450 | |
| 451 | lockdep_assert_held(&ar_pci->ps_lock); |
| 452 | |
| 453 | ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n", |
| 454 | ar_pci->ps_wake_refcount, ar_pci->ps_awake); |
| 455 | |
| 456 | iowrite32(PCIE_SOC_WAKE_RESET, |
| 457 | ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + |
| 458 | PCIE_SOC_WAKE_ADDRESS); |
| 459 | ar_pci->ps_awake = false; |
| 460 | } |
| 461 | |
| 462 | static int ath10k_pci_wake_wait(struct ath10k *ar) |
| 463 | { |
| 464 | int tot_delay = 0; |
| 465 | int curr_delay = 5; |
| 466 | |
| 467 | while (tot_delay < PCIE_WAKE_TIMEOUT) { |
Maharaja Kennadyrajan | 39b91b8 | 2015-10-06 15:19:28 +0300 | [diff] [blame] | 468 | if (ath10k_pci_is_awake(ar)) { |
| 469 | if (tot_delay > PCIE_WAKE_LATE_US) |
| 470 | ath10k_warn(ar, "device wakeup took %d ms which is unusally long, otherwise it works normally.\n", |
| 471 | tot_delay / 1000); |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 472 | return 0; |
Maharaja Kennadyrajan | 39b91b8 | 2015-10-06 15:19:28 +0300 | [diff] [blame] | 473 | } |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 474 | |
| 475 | udelay(curr_delay); |
| 476 | tot_delay += curr_delay; |
| 477 | |
| 478 | if (curr_delay < 50) |
| 479 | curr_delay += 5; |
| 480 | } |
| 481 | |
| 482 | return -ETIMEDOUT; |
| 483 | } |
| 484 | |
Anilkumar Kolli | 1aaf8ef | 2015-10-16 15:54:51 +0300 | [diff] [blame] | 485 | static int ath10k_pci_force_wake(struct ath10k *ar) |
| 486 | { |
| 487 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 488 | unsigned long flags; |
| 489 | int ret = 0; |
| 490 | |
| 491 | spin_lock_irqsave(&ar_pci->ps_lock, flags); |
| 492 | |
| 493 | if (!ar_pci->ps_awake) { |
| 494 | iowrite32(PCIE_SOC_WAKE_V_MASK, |
| 495 | ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + |
| 496 | PCIE_SOC_WAKE_ADDRESS); |
| 497 | |
| 498 | ret = ath10k_pci_wake_wait(ar); |
| 499 | if (ret == 0) |
| 500 | ar_pci->ps_awake = true; |
| 501 | } |
| 502 | |
| 503 | spin_unlock_irqrestore(&ar_pci->ps_lock, flags); |
| 504 | |
| 505 | return ret; |
| 506 | } |
| 507 | |
| 508 | static void ath10k_pci_force_sleep(struct ath10k *ar) |
| 509 | { |
| 510 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 511 | unsigned long flags; |
| 512 | |
| 513 | spin_lock_irqsave(&ar_pci->ps_lock, flags); |
| 514 | |
| 515 | iowrite32(PCIE_SOC_WAKE_RESET, |
| 516 | ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + |
| 517 | PCIE_SOC_WAKE_ADDRESS); |
| 518 | ar_pci->ps_awake = false; |
| 519 | |
| 520 | spin_unlock_irqrestore(&ar_pci->ps_lock, flags); |
| 521 | } |
| 522 | |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 523 | static int ath10k_pci_wake(struct ath10k *ar) |
| 524 | { |
| 525 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 526 | unsigned long flags; |
| 527 | int ret = 0; |
| 528 | |
Anilkumar Kolli | 1aaf8ef | 2015-10-16 15:54:51 +0300 | [diff] [blame] | 529 | if (ar_pci->pci_ps == 0) |
| 530 | return ret; |
| 531 | |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 532 | spin_lock_irqsave(&ar_pci->ps_lock, flags); |
| 533 | |
| 534 | ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n", |
| 535 | ar_pci->ps_wake_refcount, ar_pci->ps_awake); |
| 536 | |
| 537 | /* This function can be called very frequently. To avoid excessive |
| 538 | * CPU stalls for MMIO reads use a cache var to hold the device state. |
| 539 | */ |
| 540 | if (!ar_pci->ps_awake) { |
| 541 | __ath10k_pci_wake(ar); |
| 542 | |
| 543 | ret = ath10k_pci_wake_wait(ar); |
| 544 | if (ret == 0) |
| 545 | ar_pci->ps_awake = true; |
| 546 | } |
| 547 | |
| 548 | if (ret == 0) { |
| 549 | ar_pci->ps_wake_refcount++; |
| 550 | WARN_ON(ar_pci->ps_wake_refcount == 0); |
| 551 | } |
| 552 | |
| 553 | spin_unlock_irqrestore(&ar_pci->ps_lock, flags); |
| 554 | |
| 555 | return ret; |
| 556 | } |
| 557 | |
| 558 | static void ath10k_pci_sleep(struct ath10k *ar) |
| 559 | { |
| 560 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 561 | unsigned long flags; |
| 562 | |
Anilkumar Kolli | 1aaf8ef | 2015-10-16 15:54:51 +0300 | [diff] [blame] | 563 | if (ar_pci->pci_ps == 0) |
| 564 | return; |
| 565 | |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 566 | spin_lock_irqsave(&ar_pci->ps_lock, flags); |
| 567 | |
| 568 | ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n", |
| 569 | ar_pci->ps_wake_refcount, ar_pci->ps_awake); |
| 570 | |
| 571 | if (WARN_ON(ar_pci->ps_wake_refcount == 0)) |
| 572 | goto skip; |
| 573 | |
| 574 | ar_pci->ps_wake_refcount--; |
| 575 | |
| 576 | mod_timer(&ar_pci->ps_timer, jiffies + |
| 577 | msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC)); |
| 578 | |
| 579 | skip: |
| 580 | spin_unlock_irqrestore(&ar_pci->ps_lock, flags); |
| 581 | } |
| 582 | |
| 583 | static void ath10k_pci_ps_timer(unsigned long ptr) |
| 584 | { |
| 585 | struct ath10k *ar = (void *)ptr; |
| 586 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 587 | unsigned long flags; |
| 588 | |
| 589 | spin_lock_irqsave(&ar_pci->ps_lock, flags); |
| 590 | |
| 591 | ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n", |
| 592 | ar_pci->ps_wake_refcount, ar_pci->ps_awake); |
| 593 | |
| 594 | if (ar_pci->ps_wake_refcount > 0) |
| 595 | goto skip; |
| 596 | |
| 597 | __ath10k_pci_sleep(ar); |
| 598 | |
| 599 | skip: |
| 600 | spin_unlock_irqrestore(&ar_pci->ps_lock, flags); |
| 601 | } |
| 602 | |
| 603 | static void ath10k_pci_sleep_sync(struct ath10k *ar) |
| 604 | { |
| 605 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 606 | unsigned long flags; |
| 607 | |
Anilkumar Kolli | 1aaf8ef | 2015-10-16 15:54:51 +0300 | [diff] [blame] | 608 | if (ar_pci->pci_ps == 0) { |
| 609 | ath10k_pci_force_sleep(ar); |
| 610 | return; |
| 611 | } |
| 612 | |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 613 | del_timer_sync(&ar_pci->ps_timer); |
| 614 | |
| 615 | spin_lock_irqsave(&ar_pci->ps_lock, flags); |
| 616 | WARN_ON(ar_pci->ps_wake_refcount > 0); |
| 617 | __ath10k_pci_sleep(ar); |
| 618 | spin_unlock_irqrestore(&ar_pci->ps_lock, flags); |
| 619 | } |
| 620 | |
| 621 | void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value) |
| 622 | { |
| 623 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 624 | int ret; |
| 625 | |
Michal Kazior | aeae5b4 | 2015-06-15 14:46:42 +0300 | [diff] [blame] | 626 | if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) { |
| 627 | ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", |
| 628 | offset, offset + sizeof(value), ar_pci->mem_len); |
| 629 | return; |
| 630 | } |
| 631 | |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 632 | ret = ath10k_pci_wake(ar); |
| 633 | if (ret) { |
| 634 | ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n", |
| 635 | value, offset, ret); |
| 636 | return; |
| 637 | } |
| 638 | |
| 639 | iowrite32(value, ar_pci->mem + offset); |
| 640 | ath10k_pci_sleep(ar); |
| 641 | } |
| 642 | |
| 643 | u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) |
| 644 | { |
| 645 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 646 | u32 val; |
| 647 | int ret; |
| 648 | |
Michal Kazior | aeae5b4 | 2015-06-15 14:46:42 +0300 | [diff] [blame] | 649 | if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { |
| 650 | ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", |
| 651 | offset, offset + sizeof(val), ar_pci->mem_len); |
| 652 | return 0; |
| 653 | } |
| 654 | |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 655 | ret = ath10k_pci_wake(ar); |
| 656 | if (ret) { |
| 657 | ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n", |
| 658 | offset, ret); |
| 659 | return 0xffffffff; |
| 660 | } |
| 661 | |
| 662 | val = ioread32(ar_pci->mem + offset); |
| 663 | ath10k_pci_sleep(ar); |
| 664 | |
| 665 | return val; |
| 666 | } |
| 667 | |
| 668 | u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr) |
| 669 | { |
| 670 | return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr); |
| 671 | } |
| 672 | |
| 673 | void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) |
| 674 | { |
| 675 | ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); |
| 676 | } |
| 677 | |
| 678 | u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr) |
| 679 | { |
| 680 | return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr); |
| 681 | } |
| 682 | |
| 683 | void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) |
| 684 | { |
| 685 | ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val); |
| 686 | } |
| 687 | |
Michal Kazior | e539887 | 2013-11-25 14:06:20 +0100 | [diff] [blame] | 688 | static bool ath10k_pci_irq_pending(struct ath10k *ar) |
| 689 | { |
| 690 | u32 cause; |
| 691 | |
| 692 | /* Check if the shared legacy irq is for us */ |
| 693 | cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + |
| 694 | PCIE_INTR_CAUSE_ADDRESS); |
| 695 | if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) |
| 696 | return true; |
| 697 | |
| 698 | return false; |
| 699 | } |
| 700 | |
Michal Kazior | 2685218 | 2013-11-25 14:06:25 +0100 | [diff] [blame] | 701 | static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar) |
| 702 | { |
| 703 | /* IMPORTANT: INTR_CLR register has to be set after |
| 704 | * INTR_ENABLE is set to 0, otherwise interrupt can not be |
| 705 | * really cleared. */ |
| 706 | ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, |
| 707 | 0); |
| 708 | ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, |
| 709 | PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); |
| 710 | |
| 711 | /* IMPORTANT: this extra read transaction is required to |
| 712 | * flush the posted write buffer. */ |
Kalle Valo | cfbc06a | 2014-09-14 12:50:23 +0300 | [diff] [blame] | 713 | (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + |
| 714 | PCIE_INTR_ENABLE_ADDRESS); |
Michal Kazior | 2685218 | 2013-11-25 14:06:25 +0100 | [diff] [blame] | 715 | } |
| 716 | |
| 717 | static void ath10k_pci_enable_legacy_irq(struct ath10k *ar) |
| 718 | { |
| 719 | ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + |
| 720 | PCIE_INTR_ENABLE_ADDRESS, |
| 721 | PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); |
| 722 | |
| 723 | /* IMPORTANT: this extra read transaction is required to |
| 724 | * flush the posted write buffer. */ |
Kalle Valo | cfbc06a | 2014-09-14 12:50:23 +0300 | [diff] [blame] | 725 | (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + |
| 726 | PCIE_INTR_ENABLE_ADDRESS); |
Michal Kazior | 2685218 | 2013-11-25 14:06:25 +0100 | [diff] [blame] | 727 | } |
| 728 | |
Michal Kazior | 403d627 | 2014-08-22 14:23:31 +0200 | [diff] [blame] | 729 | static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) |
Michal Kazior | ab977bd | 2013-11-25 14:06:26 +0100 | [diff] [blame] | 730 | { |
Michal Kazior | ab977bd | 2013-11-25 14:06:26 +0100 | [diff] [blame] | 731 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 732 | |
Michal Kazior | 403d627 | 2014-08-22 14:23:31 +0200 | [diff] [blame] | 733 | if (ar_pci->num_msi_intrs > 1) |
| 734 | return "msi-x"; |
Kalle Valo | d8bb26b | 2014-09-14 12:50:33 +0300 | [diff] [blame] | 735 | |
| 736 | if (ar_pci->num_msi_intrs == 1) |
Michal Kazior | 403d627 | 2014-08-22 14:23:31 +0200 | [diff] [blame] | 737 | return "msi"; |
Kalle Valo | d8bb26b | 2014-09-14 12:50:33 +0300 | [diff] [blame] | 738 | |
| 739 | return "legacy"; |
Michal Kazior | ab977bd | 2013-11-25 14:06:26 +0100 | [diff] [blame] | 740 | } |
| 741 | |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 742 | static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) |
Michal Kazior | ab977bd | 2013-11-25 14:06:26 +0100 | [diff] [blame] | 743 | { |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 744 | struct ath10k *ar = pipe->hif_ce_state; |
Michal Kazior | ab977bd | 2013-11-25 14:06:26 +0100 | [diff] [blame] | 745 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 746 | struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; |
| 747 | struct sk_buff *skb; |
| 748 | dma_addr_t paddr; |
Michal Kazior | ab977bd | 2013-11-25 14:06:26 +0100 | [diff] [blame] | 749 | int ret; |
| 750 | |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 751 | skb = dev_alloc_skb(pipe->buf_sz); |
| 752 | if (!skb) |
| 753 | return -ENOMEM; |
| 754 | |
| 755 | WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); |
| 756 | |
| 757 | paddr = dma_map_single(ar->dev, skb->data, |
| 758 | skb->len + skb_tailroom(skb), |
| 759 | DMA_FROM_DEVICE); |
| 760 | if (unlikely(dma_mapping_error(ar->dev, paddr))) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 761 | ath10k_warn(ar, "failed to dma map pci rx buf\n"); |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 762 | dev_kfree_skb_any(skb); |
| 763 | return -EIO; |
| 764 | } |
| 765 | |
Michal Kazior | 8582bf3 | 2015-01-24 12:14:47 +0200 | [diff] [blame] | 766 | ATH10K_SKB_RXCB(skb)->paddr = paddr; |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 767 | |
Rajkumar Manoharan | ab4e3db | 2015-10-06 15:19:33 +0300 | [diff] [blame] | 768 | spin_lock_bh(&ar_pci->ce_lock); |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 769 | ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr); |
Rajkumar Manoharan | ab4e3db | 2015-10-06 15:19:33 +0300 | [diff] [blame] | 770 | spin_unlock_bh(&ar_pci->ce_lock); |
Michal Kazior | ab977bd | 2013-11-25 14:06:26 +0100 | [diff] [blame] | 771 | if (ret) { |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 772 | dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), |
| 773 | DMA_FROM_DEVICE); |
| 774 | dev_kfree_skb_any(skb); |
Michal Kazior | ab977bd | 2013-11-25 14:06:26 +0100 | [diff] [blame] | 775 | return ret; |
| 776 | } |
| 777 | |
| 778 | return 0; |
| 779 | } |
| 780 | |
Rajkumar Manoharan | ab4e3db | 2015-10-06 15:19:33 +0300 | [diff] [blame] | 781 | static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) |
Michal Kazior | ab977bd | 2013-11-25 14:06:26 +0100 | [diff] [blame] | 782 | { |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 783 | struct ath10k *ar = pipe->hif_ce_state; |
| 784 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 785 | struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; |
| 786 | int ret, num; |
| 787 | |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 788 | if (pipe->buf_sz == 0) |
| 789 | return; |
| 790 | |
| 791 | if (!ce_pipe->dest_ring) |
| 792 | return; |
| 793 | |
Rajkumar Manoharan | ab4e3db | 2015-10-06 15:19:33 +0300 | [diff] [blame] | 794 | spin_lock_bh(&ar_pci->ce_lock); |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 795 | num = __ath10k_ce_rx_num_free_bufs(ce_pipe); |
Rajkumar Manoharan | ab4e3db | 2015-10-06 15:19:33 +0300 | [diff] [blame] | 796 | spin_unlock_bh(&ar_pci->ce_lock); |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 797 | while (num--) { |
| 798 | ret = __ath10k_pci_rx_post_buf(pipe); |
| 799 | if (ret) { |
Rajkumar Manoharan | ab4e3db | 2015-10-06 15:19:33 +0300 | [diff] [blame] | 800 | if (ret == -ENOSPC) |
| 801 | break; |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 802 | ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 803 | mod_timer(&ar_pci->rx_post_retry, jiffies + |
| 804 | ATH10K_PCI_RX_POST_RETRY_MS); |
| 805 | break; |
| 806 | } |
| 807 | } |
| 808 | } |
| 809 | |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 810 | static void ath10k_pci_rx_post(struct ath10k *ar) |
| 811 | { |
| 812 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 813 | int i; |
| 814 | |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 815 | for (i = 0; i < CE_COUNT; i++) |
Rajkumar Manoharan | ab4e3db | 2015-10-06 15:19:33 +0300 | [diff] [blame] | 816 | ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]); |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 817 | } |
| 818 | |
| 819 | static void ath10k_pci_rx_replenish_retry(unsigned long ptr) |
| 820 | { |
| 821 | struct ath10k *ar = (void *)ptr; |
| 822 | |
| 823 | ath10k_pci_rx_post(ar); |
Michal Kazior | ab977bd | 2013-11-25 14:06:26 +0100 | [diff] [blame] | 824 | } |
| 825 | |
Vasanthakumar Thiagarajan | 418ca59 | 2015-06-18 12:31:05 +0530 | [diff] [blame] | 826 | static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) |
| 827 | { |
| 828 | u32 val = 0; |
| 829 | |
| 830 | switch (ar->hw_rev) { |
| 831 | case ATH10K_HW_QCA988X: |
| 832 | case ATH10K_HW_QCA6174: |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 833 | case ATH10K_HW_QCA9377: |
Vasanthakumar Thiagarajan | 418ca59 | 2015-06-18 12:31:05 +0530 | [diff] [blame] | 834 | val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + |
| 835 | CORE_CTRL_ADDRESS) & |
Vasanthakumar Thiagarajan | 3c7e256 | 2015-07-03 19:25:27 +0530 | [diff] [blame] | 836 | 0x7ff) << 21; |
Vasanthakumar Thiagarajan | 418ca59 | 2015-06-18 12:31:05 +0530 | [diff] [blame] | 837 | break; |
| 838 | case ATH10K_HW_QCA99X0: |
| 839 | val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); |
| 840 | break; |
| 841 | } |
| 842 | |
| 843 | val |= 0x100000 | (addr & 0xfffff); |
| 844 | return val; |
| 845 | } |
| 846 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 847 | /* |
| 848 | * Diagnostic read/write access is provided for startup/config/debug usage. |
| 849 | * Caller must guarantee proper alignment, when applicable, and single user |
| 850 | * at any moment. |
| 851 | */ |
| 852 | static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, |
| 853 | int nbytes) |
| 854 | { |
| 855 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 856 | int ret = 0; |
| 857 | u32 buf; |
| 858 | unsigned int completed_nbytes, orig_nbytes, remaining_bytes; |
| 859 | unsigned int id; |
| 860 | unsigned int flags; |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 861 | struct ath10k_ce_pipe *ce_diag; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 862 | /* Host buffer address in CE space */ |
| 863 | u32 ce_data; |
| 864 | dma_addr_t ce_data_base = 0; |
| 865 | void *data_buf = NULL; |
| 866 | int i; |
| 867 | |
Kalle Valo | eef2540 | 2014-09-24 14:16:52 +0300 | [diff] [blame] | 868 | spin_lock_bh(&ar_pci->ce_lock); |
| 869 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 870 | ce_diag = ar_pci->ce_diag; |
| 871 | |
| 872 | /* |
| 873 | * Allocate a temporary bounce buffer to hold caller's data |
| 874 | * to be DMA'ed from Target. This guarantees |
| 875 | * 1) 4-byte alignment |
| 876 | * 2) Buffer in DMA-able space |
| 877 | */ |
| 878 | orig_nbytes = nbytes; |
Michal Kazior | 68c0324 | 2014-03-28 10:02:35 +0200 | [diff] [blame] | 879 | data_buf = (unsigned char *)dma_alloc_coherent(ar->dev, |
| 880 | orig_nbytes, |
| 881 | &ce_data_base, |
| 882 | GFP_ATOMIC); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 883 | |
| 884 | if (!data_buf) { |
| 885 | ret = -ENOMEM; |
| 886 | goto done; |
| 887 | } |
| 888 | memset(data_buf, 0, orig_nbytes); |
| 889 | |
| 890 | remaining_bytes = orig_nbytes; |
| 891 | ce_data = ce_data_base; |
| 892 | while (remaining_bytes) { |
| 893 | nbytes = min_t(unsigned int, remaining_bytes, |
| 894 | DIAG_TRANSFER_LIMIT); |
| 895 | |
Kalle Valo | eef2540 | 2014-09-24 14:16:52 +0300 | [diff] [blame] | 896 | ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, ce_data); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 897 | if (ret != 0) |
| 898 | goto done; |
| 899 | |
| 900 | /* Request CE to send from Target(!) address to Host buffer */ |
| 901 | /* |
| 902 | * The address supplied by the caller is in the |
| 903 | * Target CPU virtual address space. |
| 904 | * |
| 905 | * In order to use this address with the diagnostic CE, |
| 906 | * convert it from Target CPU virtual address space |
| 907 | * to CE address space |
| 908 | */ |
Vasanthakumar Thiagarajan | 418ca59 | 2015-06-18 12:31:05 +0530 | [diff] [blame] | 909 | address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 910 | |
Kalle Valo | eef2540 | 2014-09-24 14:16:52 +0300 | [diff] [blame] | 911 | ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0, |
| 912 | 0); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 913 | if (ret) |
| 914 | goto done; |
| 915 | |
| 916 | i = 0; |
Rajkumar Manoharan | 765952e | 2015-10-23 18:01:05 +0530 | [diff] [blame] | 917 | while (ath10k_ce_completed_send_next_nolock(ce_diag, |
| 918 | NULL) != 0) { |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 919 | mdelay(1); |
| 920 | if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { |
| 921 | ret = -EBUSY; |
| 922 | goto done; |
| 923 | } |
| 924 | } |
| 925 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 926 | i = 0; |
Kalle Valo | eef2540 | 2014-09-24 14:16:52 +0300 | [diff] [blame] | 927 | while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf, |
| 928 | &completed_nbytes, |
| 929 | &id, &flags) != 0) { |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 930 | mdelay(1); |
| 931 | |
| 932 | if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { |
| 933 | ret = -EBUSY; |
| 934 | goto done; |
| 935 | } |
| 936 | } |
| 937 | |
| 938 | if (nbytes != completed_nbytes) { |
| 939 | ret = -EIO; |
| 940 | goto done; |
| 941 | } |
| 942 | |
| 943 | if (buf != ce_data) { |
| 944 | ret = -EIO; |
| 945 | goto done; |
| 946 | } |
| 947 | |
| 948 | remaining_bytes -= nbytes; |
| 949 | address += nbytes; |
| 950 | ce_data += nbytes; |
| 951 | } |
| 952 | |
| 953 | done: |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 954 | if (ret == 0) |
| 955 | memcpy(data, data_buf, orig_nbytes); |
| 956 | else |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 957 | ath10k_warn(ar, "failed to read diag value at 0x%x: %d\n", |
Kalle Valo | 50f87a6 | 2014-03-28 09:32:52 +0200 | [diff] [blame] | 958 | address, ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 959 | |
| 960 | if (data_buf) |
Michal Kazior | 68c0324 | 2014-03-28 10:02:35 +0200 | [diff] [blame] | 961 | dma_free_coherent(ar->dev, orig_nbytes, data_buf, |
| 962 | ce_data_base); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 963 | |
Kalle Valo | eef2540 | 2014-09-24 14:16:52 +0300 | [diff] [blame] | 964 | spin_unlock_bh(&ar_pci->ce_lock); |
| 965 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 966 | return ret; |
| 967 | } |
| 968 | |
Kalle Valo | 3d29a3e | 2014-08-25 08:37:26 +0300 | [diff] [blame] | 969 | static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value) |
| 970 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 971 | __le32 val = 0; |
| 972 | int ret; |
| 973 | |
| 974 | ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val)); |
| 975 | *value = __le32_to_cpu(val); |
| 976 | |
| 977 | return ret; |
Kalle Valo | 3d29a3e | 2014-08-25 08:37:26 +0300 | [diff] [blame] | 978 | } |
| 979 | |
| 980 | static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest, |
| 981 | u32 src, u32 len) |
| 982 | { |
| 983 | u32 host_addr, addr; |
| 984 | int ret; |
| 985 | |
| 986 | host_addr = host_interest_item_address(src); |
| 987 | |
| 988 | ret = ath10k_pci_diag_read32(ar, host_addr, &addr); |
| 989 | if (ret != 0) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 990 | ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n", |
Kalle Valo | 3d29a3e | 2014-08-25 08:37:26 +0300 | [diff] [blame] | 991 | src, ret); |
| 992 | return ret; |
| 993 | } |
| 994 | |
| 995 | ret = ath10k_pci_diag_read_mem(ar, addr, dest, len); |
| 996 | if (ret != 0) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 997 | ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n", |
Kalle Valo | 3d29a3e | 2014-08-25 08:37:26 +0300 | [diff] [blame] | 998 | addr, len, ret); |
| 999 | return ret; |
| 1000 | } |
| 1001 | |
| 1002 | return 0; |
| 1003 | } |
| 1004 | |
| 1005 | #define ath10k_pci_diag_read_hi(ar, dest, src, len) \ |
Kalle Valo | 8cc7f26 | 2014-09-14 12:50:39 +0300 | [diff] [blame] | 1006 | __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len) |
Kalle Valo | 3d29a3e | 2014-08-25 08:37:26 +0300 | [diff] [blame] | 1007 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1008 | static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, |
| 1009 | const void *data, int nbytes) |
| 1010 | { |
| 1011 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 1012 | int ret = 0; |
| 1013 | u32 buf; |
| 1014 | unsigned int completed_nbytes, orig_nbytes, remaining_bytes; |
| 1015 | unsigned int id; |
| 1016 | unsigned int flags; |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 1017 | struct ath10k_ce_pipe *ce_diag; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1018 | void *data_buf = NULL; |
| 1019 | u32 ce_data; /* Host buffer address in CE space */ |
| 1020 | dma_addr_t ce_data_base = 0; |
| 1021 | int i; |
| 1022 | |
Kalle Valo | eef2540 | 2014-09-24 14:16:52 +0300 | [diff] [blame] | 1023 | spin_lock_bh(&ar_pci->ce_lock); |
| 1024 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1025 | ce_diag = ar_pci->ce_diag; |
| 1026 | |
| 1027 | /* |
| 1028 | * Allocate a temporary bounce buffer to hold caller's data |
| 1029 | * to be DMA'ed to Target. This guarantees |
| 1030 | * 1) 4-byte alignment |
| 1031 | * 2) Buffer in DMA-able space |
| 1032 | */ |
| 1033 | orig_nbytes = nbytes; |
Michal Kazior | 68c0324 | 2014-03-28 10:02:35 +0200 | [diff] [blame] | 1034 | data_buf = (unsigned char *)dma_alloc_coherent(ar->dev, |
| 1035 | orig_nbytes, |
| 1036 | &ce_data_base, |
| 1037 | GFP_ATOMIC); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1038 | if (!data_buf) { |
| 1039 | ret = -ENOMEM; |
| 1040 | goto done; |
| 1041 | } |
| 1042 | |
| 1043 | /* Copy caller's data to allocated DMA buf */ |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1044 | memcpy(data_buf, data, orig_nbytes); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1045 | |
| 1046 | /* |
| 1047 | * The address supplied by the caller is in the |
| 1048 | * Target CPU virtual address space. |
| 1049 | * |
| 1050 | * In order to use this address with the diagnostic CE, |
| 1051 | * convert it from |
| 1052 | * Target CPU virtual address space |
| 1053 | * to |
| 1054 | * CE address space |
| 1055 | */ |
Vasanthakumar Thiagarajan | 418ca59 | 2015-06-18 12:31:05 +0530 | [diff] [blame] | 1056 | address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1057 | |
| 1058 | remaining_bytes = orig_nbytes; |
| 1059 | ce_data = ce_data_base; |
| 1060 | while (remaining_bytes) { |
| 1061 | /* FIXME: check cast */ |
| 1062 | nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT); |
| 1063 | |
| 1064 | /* Set up to receive directly into Target(!) address */ |
Kalle Valo | eef2540 | 2014-09-24 14:16:52 +0300 | [diff] [blame] | 1065 | ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, address); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1066 | if (ret != 0) |
| 1067 | goto done; |
| 1068 | |
| 1069 | /* |
| 1070 | * Request CE to send caller-supplied data that |
| 1071 | * was copied to bounce buffer to Target(!) address. |
| 1072 | */ |
Kalle Valo | eef2540 | 2014-09-24 14:16:52 +0300 | [diff] [blame] | 1073 | ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data, |
| 1074 | nbytes, 0, 0); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1075 | if (ret != 0) |
| 1076 | goto done; |
| 1077 | |
| 1078 | i = 0; |
Rajkumar Manoharan | 765952e | 2015-10-23 18:01:05 +0530 | [diff] [blame] | 1079 | while (ath10k_ce_completed_send_next_nolock(ce_diag, |
| 1080 | NULL) != 0) { |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1081 | mdelay(1); |
| 1082 | |
| 1083 | if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { |
| 1084 | ret = -EBUSY; |
| 1085 | goto done; |
| 1086 | } |
| 1087 | } |
| 1088 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1089 | i = 0; |
Kalle Valo | eef2540 | 2014-09-24 14:16:52 +0300 | [diff] [blame] | 1090 | while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf, |
| 1091 | &completed_nbytes, |
| 1092 | &id, &flags) != 0) { |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1093 | mdelay(1); |
| 1094 | |
| 1095 | if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { |
| 1096 | ret = -EBUSY; |
| 1097 | goto done; |
| 1098 | } |
| 1099 | } |
| 1100 | |
| 1101 | if (nbytes != completed_nbytes) { |
| 1102 | ret = -EIO; |
| 1103 | goto done; |
| 1104 | } |
| 1105 | |
| 1106 | if (buf != address) { |
| 1107 | ret = -EIO; |
| 1108 | goto done; |
| 1109 | } |
| 1110 | |
| 1111 | remaining_bytes -= nbytes; |
| 1112 | address += nbytes; |
| 1113 | ce_data += nbytes; |
| 1114 | } |
| 1115 | |
| 1116 | done: |
| 1117 | if (data_buf) { |
Michal Kazior | 68c0324 | 2014-03-28 10:02:35 +0200 | [diff] [blame] | 1118 | dma_free_coherent(ar->dev, orig_nbytes, data_buf, |
| 1119 | ce_data_base); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1120 | } |
| 1121 | |
| 1122 | if (ret != 0) |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1123 | ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n", |
Kalle Valo | 50f87a6 | 2014-03-28 09:32:52 +0200 | [diff] [blame] | 1124 | address, ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1125 | |
Kalle Valo | eef2540 | 2014-09-24 14:16:52 +0300 | [diff] [blame] | 1126 | spin_unlock_bh(&ar_pci->ce_lock); |
| 1127 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1128 | return ret; |
| 1129 | } |
| 1130 | |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1131 | static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value) |
| 1132 | { |
| 1133 | __le32 val = __cpu_to_le32(value); |
| 1134 | |
| 1135 | return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val)); |
| 1136 | } |
| 1137 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1138 | /* Called by lower (CE) layer when a send to Target completes. */ |
Rajkumar Manoharan | 0e5b295 | 2015-10-12 18:27:01 +0530 | [diff] [blame] | 1139 | static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1140 | { |
| 1141 | struct ath10k *ar = ce_state->ar; |
Michal Kazior | 1cb86d4 | 2014-11-27 11:09:38 +0100 | [diff] [blame] | 1142 | struct sk_buff_head list; |
| 1143 | struct sk_buff *skb; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1144 | |
Michal Kazior | 1cb86d4 | 2014-11-27 11:09:38 +0100 | [diff] [blame] | 1145 | __skb_queue_head_init(&list); |
Rajkumar Manoharan | 765952e | 2015-10-23 18:01:05 +0530 | [diff] [blame] | 1146 | while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { |
Michal Kazior | a16942e | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 1147 | /* no need to call tx completion for NULL pointers */ |
Michal Kazior | 1cb86d4 | 2014-11-27 11:09:38 +0100 | [diff] [blame] | 1148 | if (skb == NULL) |
Michal Kazior | 726346f | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 1149 | continue; |
| 1150 | |
Michal Kazior | 1cb86d4 | 2014-11-27 11:09:38 +0100 | [diff] [blame] | 1151 | __skb_queue_tail(&list, skb); |
Michal Kazior | 5440ce2 | 2013-09-03 15:09:58 +0200 | [diff] [blame] | 1152 | } |
Michal Kazior | 1cb86d4 | 2014-11-27 11:09:38 +0100 | [diff] [blame] | 1153 | |
| 1154 | while ((skb = __skb_dequeue(&list))) |
Rajkumar Manoharan | 0e5b295 | 2015-10-12 18:27:01 +0530 | [diff] [blame] | 1155 | ath10k_htc_tx_completion_handler(ar, skb); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1156 | } |
| 1157 | |
Rajkumar Manoharan | a70587b | 2015-10-12 18:27:04 +0530 | [diff] [blame] | 1158 | static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state, |
| 1159 | void (*callback)(struct ath10k *ar, |
| 1160 | struct sk_buff *skb)) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1161 | { |
| 1162 | struct ath10k *ar = ce_state->ar; |
| 1163 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Michal Kazior | 87263e5 | 2013-08-27 13:08:01 +0200 | [diff] [blame] | 1164 | struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1165 | struct sk_buff *skb; |
Michal Kazior | 1cb86d4 | 2014-11-27 11:09:38 +0100 | [diff] [blame] | 1166 | struct sk_buff_head list; |
Michal Kazior | 5440ce2 | 2013-09-03 15:09:58 +0200 | [diff] [blame] | 1167 | void *transfer_context; |
| 1168 | u32 ce_data; |
Michal Kazior | 2f5280d | 2014-02-27 18:50:05 +0200 | [diff] [blame] | 1169 | unsigned int nbytes, max_nbytes; |
Michal Kazior | 5440ce2 | 2013-09-03 15:09:58 +0200 | [diff] [blame] | 1170 | unsigned int transfer_id; |
| 1171 | unsigned int flags; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1172 | |
Michal Kazior | 1cb86d4 | 2014-11-27 11:09:38 +0100 | [diff] [blame] | 1173 | __skb_queue_head_init(&list); |
Michal Kazior | 5440ce2 | 2013-09-03 15:09:58 +0200 | [diff] [blame] | 1174 | while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, |
| 1175 | &ce_data, &nbytes, &transfer_id, |
| 1176 | &flags) == 0) { |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1177 | skb = transfer_context; |
Michal Kazior | 2f5280d | 2014-02-27 18:50:05 +0200 | [diff] [blame] | 1178 | max_nbytes = skb->len + skb_tailroom(skb); |
Michal Kazior | 8582bf3 | 2015-01-24 12:14:47 +0200 | [diff] [blame] | 1179 | dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, |
Michal Kazior | 2f5280d | 2014-02-27 18:50:05 +0200 | [diff] [blame] | 1180 | max_nbytes, DMA_FROM_DEVICE); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1181 | |
Michal Kazior | 2f5280d | 2014-02-27 18:50:05 +0200 | [diff] [blame] | 1182 | if (unlikely(max_nbytes < nbytes)) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1183 | ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", |
Michal Kazior | 2f5280d | 2014-02-27 18:50:05 +0200 | [diff] [blame] | 1184 | nbytes, max_nbytes); |
| 1185 | dev_kfree_skb_any(skb); |
| 1186 | continue; |
| 1187 | } |
| 1188 | |
| 1189 | skb_put(skb, nbytes); |
Michal Kazior | 1cb86d4 | 2014-11-27 11:09:38 +0100 | [diff] [blame] | 1190 | __skb_queue_tail(&list, skb); |
| 1191 | } |
Michal Kazior | a360e54 | 2014-09-23 10:22:54 +0200 | [diff] [blame] | 1192 | |
Michal Kazior | 1cb86d4 | 2014-11-27 11:09:38 +0100 | [diff] [blame] | 1193 | while ((skb = __skb_dequeue(&list))) { |
Michal Kazior | a360e54 | 2014-09-23 10:22:54 +0200 | [diff] [blame] | 1194 | ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", |
| 1195 | ce_state->id, skb->len); |
| 1196 | ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", |
| 1197 | skb->data, skb->len); |
| 1198 | |
Rajkumar Manoharan | a70587b | 2015-10-12 18:27:04 +0530 | [diff] [blame] | 1199 | callback(ar, skb); |
Michal Kazior | 2f5280d | 2014-02-27 18:50:05 +0200 | [diff] [blame] | 1200 | } |
Michal Kazior | c29a380 | 2014-07-21 21:03:10 +0300 | [diff] [blame] | 1201 | |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 1202 | ath10k_pci_rx_post_pipe(pipe_info); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1203 | } |
| 1204 | |
Rajkumar Manoharan | a70587b | 2015-10-12 18:27:04 +0530 | [diff] [blame] | 1205 | /* Called by lower (CE) layer when data is received from the Target. */ |
| 1206 | static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state) |
| 1207 | { |
| 1208 | ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); |
| 1209 | } |
| 1210 | |
| 1211 | /* Called by lower (CE) layer when a send to HTT Target completes. */ |
| 1212 | static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state) |
| 1213 | { |
| 1214 | struct ath10k *ar = ce_state->ar; |
| 1215 | struct sk_buff *skb; |
Rajkumar Manoharan | a70587b | 2015-10-12 18:27:04 +0530 | [diff] [blame] | 1216 | |
Rajkumar Manoharan | 765952e | 2015-10-23 18:01:05 +0530 | [diff] [blame] | 1217 | while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { |
Rajkumar Manoharan | a70587b | 2015-10-12 18:27:04 +0530 | [diff] [blame] | 1218 | /* no need to call tx completion for NULL pointers */ |
| 1219 | if (!skb) |
| 1220 | continue; |
| 1221 | |
| 1222 | dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, |
| 1223 | skb->len, DMA_TO_DEVICE); |
| 1224 | ath10k_htt_hif_tx_complete(ar, skb); |
| 1225 | } |
| 1226 | } |
| 1227 | |
| 1228 | static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) |
| 1229 | { |
| 1230 | skb_pull(skb, sizeof(struct ath10k_htc_hdr)); |
| 1231 | ath10k_htt_t2h_msg_handler(ar, skb); |
| 1232 | } |
| 1233 | |
| 1234 | /* Called by lower (CE) layer when HTT data is received from the Target. */ |
| 1235 | static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state) |
| 1236 | { |
| 1237 | /* CE4 polling needs to be done whenever CE pipe which transports |
| 1238 | * HTT Rx (target->host) is processed. |
| 1239 | */ |
| 1240 | ath10k_ce_per_engine_service(ce_state->ar, 4); |
| 1241 | |
| 1242 | ath10k_pci_process_rx_cb(ce_state, ath10k_pci_htt_rx_deliver); |
| 1243 | } |
| 1244 | |
Michal Kazior | 726346f | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 1245 | static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, |
| 1246 | struct ath10k_hif_sg_item *items, int n_items) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1247 | { |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1248 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Michal Kazior | 726346f | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 1249 | struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; |
| 1250 | struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; |
| 1251 | struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; |
Michal Kazior | 7147a13 | 2014-05-26 12:02:58 +0200 | [diff] [blame] | 1252 | unsigned int nentries_mask; |
| 1253 | unsigned int sw_index; |
| 1254 | unsigned int write_index; |
Michal Kazior | 08b8aa0 | 2014-05-26 12:02:59 +0200 | [diff] [blame] | 1255 | int err, i = 0; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1256 | |
Michal Kazior | 726346f | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 1257 | spin_lock_bh(&ar_pci->ce_lock); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1258 | |
Michal Kazior | 7147a13 | 2014-05-26 12:02:58 +0200 | [diff] [blame] | 1259 | nentries_mask = src_ring->nentries_mask; |
| 1260 | sw_index = src_ring->sw_index; |
| 1261 | write_index = src_ring->write_index; |
| 1262 | |
Michal Kazior | 726346f | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 1263 | if (unlikely(CE_RING_DELTA(nentries_mask, |
| 1264 | write_index, sw_index - 1) < n_items)) { |
| 1265 | err = -ENOBUFS; |
Michal Kazior | 08b8aa0 | 2014-05-26 12:02:59 +0200 | [diff] [blame] | 1266 | goto err; |
Michal Kazior | 726346f | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 1267 | } |
| 1268 | |
| 1269 | for (i = 0; i < n_items - 1; i++) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1270 | ath10k_dbg(ar, ATH10K_DBG_PCI, |
Michal Kazior | 726346f | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 1271 | "pci tx item %d paddr 0x%08x len %d n_items %d\n", |
| 1272 | i, items[i].paddr, items[i].len, n_items); |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1273 | ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", |
Michal Kazior | 726346f | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 1274 | items[i].vaddr, items[i].len); |
| 1275 | |
| 1276 | err = ath10k_ce_send_nolock(ce_pipe, |
| 1277 | items[i].transfer_context, |
| 1278 | items[i].paddr, |
| 1279 | items[i].len, |
| 1280 | items[i].transfer_id, |
| 1281 | CE_SEND_FLAG_GATHER); |
| 1282 | if (err) |
Michal Kazior | 08b8aa0 | 2014-05-26 12:02:59 +0200 | [diff] [blame] | 1283 | goto err; |
Michal Kazior | 726346f | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 1284 | } |
| 1285 | |
| 1286 | /* `i` is equal to `n_items -1` after for() */ |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1287 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1288 | ath10k_dbg(ar, ATH10K_DBG_PCI, |
Michal Kazior | 726346f | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 1289 | "pci tx item %d paddr 0x%08x len %d n_items %d\n", |
| 1290 | i, items[i].paddr, items[i].len, n_items); |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1291 | ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", |
Michal Kazior | 726346f | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 1292 | items[i].vaddr, items[i].len); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1293 | |
Michal Kazior | 726346f | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 1294 | err = ath10k_ce_send_nolock(ce_pipe, |
| 1295 | items[i].transfer_context, |
| 1296 | items[i].paddr, |
| 1297 | items[i].len, |
| 1298 | items[i].transfer_id, |
| 1299 | 0); |
| 1300 | if (err) |
Michal Kazior | 08b8aa0 | 2014-05-26 12:02:59 +0200 | [diff] [blame] | 1301 | goto err; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1302 | |
Michal Kazior | 08b8aa0 | 2014-05-26 12:02:59 +0200 | [diff] [blame] | 1303 | spin_unlock_bh(&ar_pci->ce_lock); |
| 1304 | return 0; |
| 1305 | |
| 1306 | err: |
| 1307 | for (; i > 0; i--) |
| 1308 | __ath10k_ce_send_revert(ce_pipe); |
| 1309 | |
Michal Kazior | 726346f | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 1310 | spin_unlock_bh(&ar_pci->ce_lock); |
| 1311 | return err; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1312 | } |
| 1313 | |
Kalle Valo | eef2540 | 2014-09-24 14:16:52 +0300 | [diff] [blame] | 1314 | static int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, |
| 1315 | size_t buf_len) |
| 1316 | { |
| 1317 | return ath10k_pci_diag_read_mem(ar, address, buf, buf_len); |
| 1318 | } |
| 1319 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1320 | static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) |
| 1321 | { |
| 1322 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Kalle Valo | 50f87a6 | 2014-03-28 09:32:52 +0200 | [diff] [blame] | 1323 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1324 | ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n"); |
Kalle Valo | 50f87a6 | 2014-03-28 09:32:52 +0200 | [diff] [blame] | 1325 | |
Michal Kazior | 3efcb3b | 2013-10-02 11:03:41 +0200 | [diff] [blame] | 1326 | return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1327 | } |
| 1328 | |
Ben Greear | 384914b | 2014-08-25 08:37:32 +0300 | [diff] [blame] | 1329 | static void ath10k_pci_dump_registers(struct ath10k *ar, |
| 1330 | struct ath10k_fw_crash_data *crash_data) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1331 | { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1332 | __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {}; |
| 1333 | int i, ret; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1334 | |
Ben Greear | 384914b | 2014-08-25 08:37:32 +0300 | [diff] [blame] | 1335 | lockdep_assert_held(&ar->data_lock); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1336 | |
Kalle Valo | 3d29a3e | 2014-08-25 08:37:26 +0300 | [diff] [blame] | 1337 | ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0], |
| 1338 | hi_failure_state, |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1339 | REG_DUMP_COUNT_QCA988X * sizeof(__le32)); |
Michal Kazior | 1d2b48d | 2013-11-08 08:01:34 +0100 | [diff] [blame] | 1340 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1341 | ath10k_err(ar, "failed to read firmware dump area: %d\n", ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1342 | return; |
| 1343 | } |
| 1344 | |
| 1345 | BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4); |
| 1346 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1347 | ath10k_err(ar, "firmware register dump:\n"); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1348 | for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4) |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1349 | ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n", |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1350 | i, |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1351 | __le32_to_cpu(reg_dump_values[i]), |
| 1352 | __le32_to_cpu(reg_dump_values[i + 1]), |
| 1353 | __le32_to_cpu(reg_dump_values[i + 2]), |
| 1354 | __le32_to_cpu(reg_dump_values[i + 3])); |
Michal Kazior | affd321 | 2013-07-16 09:54:35 +0200 | [diff] [blame] | 1355 | |
Michal Kazior | 1bbb119 | 2014-08-25 12:13:14 +0200 | [diff] [blame] | 1356 | if (!crash_data) |
| 1357 | return; |
| 1358 | |
Ben Greear | 384914b | 2014-08-25 08:37:32 +0300 | [diff] [blame] | 1359 | for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++) |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1360 | crash_data->registers[i] = reg_dump_values[i]; |
Ben Greear | 384914b | 2014-08-25 08:37:32 +0300 | [diff] [blame] | 1361 | } |
| 1362 | |
Kalle Valo | 0e9848c | 2014-08-25 08:37:37 +0300 | [diff] [blame] | 1363 | static void ath10k_pci_fw_crashed_dump(struct ath10k *ar) |
Ben Greear | 384914b | 2014-08-25 08:37:32 +0300 | [diff] [blame] | 1364 | { |
| 1365 | struct ath10k_fw_crash_data *crash_data; |
| 1366 | char uuid[50]; |
| 1367 | |
| 1368 | spin_lock_bh(&ar->data_lock); |
| 1369 | |
Ben Greear | f51dbe7 | 2014-09-29 14:41:46 +0300 | [diff] [blame] | 1370 | ar->stats.fw_crash_counter++; |
| 1371 | |
Ben Greear | 384914b | 2014-08-25 08:37:32 +0300 | [diff] [blame] | 1372 | crash_data = ath10k_debug_get_new_fw_crash_data(ar); |
| 1373 | |
| 1374 | if (crash_data) |
| 1375 | scnprintf(uuid, sizeof(uuid), "%pUl", &crash_data->uuid); |
| 1376 | else |
| 1377 | scnprintf(uuid, sizeof(uuid), "n/a"); |
| 1378 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1379 | ath10k_err(ar, "firmware crashed! (uuid %s)\n", uuid); |
Kalle Valo | 8a0c797 | 2014-08-25 08:37:45 +0300 | [diff] [blame] | 1380 | ath10k_print_driver_info(ar); |
Ben Greear | 384914b | 2014-08-25 08:37:32 +0300 | [diff] [blame] | 1381 | ath10k_pci_dump_registers(ar, crash_data); |
| 1382 | |
Ben Greear | 384914b | 2014-08-25 08:37:32 +0300 | [diff] [blame] | 1383 | spin_unlock_bh(&ar->data_lock); |
Michal Kazior | affd321 | 2013-07-16 09:54:35 +0200 | [diff] [blame] | 1384 | |
Michal Kazior | 5e90de8 | 2013-10-16 16:46:05 +0300 | [diff] [blame] | 1385 | queue_work(ar->workqueue, &ar->restart_work); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1386 | } |
| 1387 | |
| 1388 | static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, |
| 1389 | int force) |
| 1390 | { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1391 | ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n"); |
Kalle Valo | 50f87a6 | 2014-03-28 09:32:52 +0200 | [diff] [blame] | 1392 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1393 | if (!force) { |
| 1394 | int resources; |
| 1395 | /* |
| 1396 | * Decide whether to actually poll for completions, or just |
| 1397 | * wait for a later chance. |
| 1398 | * If there seem to be plenty of resources left, then just wait |
| 1399 | * since checking involves reading a CE register, which is a |
| 1400 | * relatively expensive operation. |
| 1401 | */ |
| 1402 | resources = ath10k_pci_hif_get_free_queue_number(ar, pipe); |
| 1403 | |
| 1404 | /* |
| 1405 | * If at least 50% of the total resources are still available, |
| 1406 | * don't bother checking again yet. |
| 1407 | */ |
| 1408 | if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1)) |
| 1409 | return; |
| 1410 | } |
| 1411 | ath10k_ce_per_engine_service(ar, pipe); |
| 1412 | } |
| 1413 | |
Michal Kazior | 96a9d0d | 2013-11-08 08:01:25 +0100 | [diff] [blame] | 1414 | static void ath10k_pci_kill_tasklet(struct ath10k *ar) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1415 | { |
| 1416 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1417 | int i; |
| 1418 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1419 | tasklet_kill(&ar_pci->intr_tq); |
Michal Kazior | 103d4f5 | 2013-11-08 08:01:24 +0100 | [diff] [blame] | 1420 | tasklet_kill(&ar_pci->msi_fw_err); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1421 | |
| 1422 | for (i = 0; i < CE_COUNT; i++) |
| 1423 | tasklet_kill(&ar_pci->pipe_info[i].intr); |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 1424 | |
| 1425 | del_timer_sync(&ar_pci->rx_post_retry); |
Michal Kazior | 96a9d0d | 2013-11-08 08:01:25 +0100 | [diff] [blame] | 1426 | } |
| 1427 | |
Rajkumar Manoharan | 400143e | 2015-10-12 18:27:06 +0530 | [diff] [blame] | 1428 | static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, |
| 1429 | u8 *ul_pipe, u8 *dl_pipe) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1430 | { |
Michal Kazior | 7c6aa25 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1431 | const struct service_to_pipe *entry; |
| 1432 | bool ul_set = false, dl_set = false; |
| 1433 | int i; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1434 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1435 | ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n"); |
Kalle Valo | 50f87a6 | 2014-03-28 09:32:52 +0200 | [diff] [blame] | 1436 | |
Michal Kazior | 7c6aa25 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1437 | for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) { |
| 1438 | entry = &target_service_to_ce_map_wlan[i]; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1439 | |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1440 | if (__le32_to_cpu(entry->service_id) != service_id) |
Michal Kazior | 7c6aa25 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1441 | continue; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1442 | |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1443 | switch (__le32_to_cpu(entry->pipedir)) { |
Michal Kazior | 7c6aa25 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1444 | case PIPEDIR_NONE: |
| 1445 | break; |
| 1446 | case PIPEDIR_IN: |
| 1447 | WARN_ON(dl_set); |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1448 | *dl_pipe = __le32_to_cpu(entry->pipenum); |
Michal Kazior | 7c6aa25 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1449 | dl_set = true; |
| 1450 | break; |
| 1451 | case PIPEDIR_OUT: |
| 1452 | WARN_ON(ul_set); |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1453 | *ul_pipe = __le32_to_cpu(entry->pipenum); |
Michal Kazior | 7c6aa25 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1454 | ul_set = true; |
| 1455 | break; |
| 1456 | case PIPEDIR_INOUT: |
| 1457 | WARN_ON(dl_set); |
| 1458 | WARN_ON(ul_set); |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1459 | *dl_pipe = __le32_to_cpu(entry->pipenum); |
| 1460 | *ul_pipe = __le32_to_cpu(entry->pipenum); |
Michal Kazior | 7c6aa25 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1461 | dl_set = true; |
| 1462 | ul_set = true; |
| 1463 | break; |
| 1464 | } |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1465 | } |
Michal Kazior | 7c6aa25 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1466 | |
| 1467 | if (WARN_ON(!ul_set || !dl_set)) |
| 1468 | return -ENOENT; |
| 1469 | |
Michal Kazior | 7c6aa25 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 1470 | return 0; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1471 | } |
| 1472 | |
| 1473 | static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, |
Kalle Valo | 5b07e07 | 2014-09-14 12:50:06 +0300 | [diff] [blame] | 1474 | u8 *ul_pipe, u8 *dl_pipe) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1475 | { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1476 | ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n"); |
Kalle Valo | 50f87a6 | 2014-03-28 09:32:52 +0200 | [diff] [blame] | 1477 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1478 | (void)ath10k_pci_hif_map_service_to_pipe(ar, |
| 1479 | ATH10K_HTC_SVC_ID_RSVD_CTRL, |
Rajkumar Manoharan | 400143e | 2015-10-12 18:27:06 +0530 | [diff] [blame] | 1480 | ul_pipe, dl_pipe); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1481 | } |
| 1482 | |
Michal Kazior | 7c0f0e3 | 2014-10-20 14:14:38 +0200 | [diff] [blame] | 1483 | static void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) |
| 1484 | { |
| 1485 | u32 val; |
| 1486 | |
Vasanthakumar Thiagarajan | 6e4202c | 2015-06-18 12:31:06 +0530 | [diff] [blame] | 1487 | switch (ar->hw_rev) { |
| 1488 | case ATH10K_HW_QCA988X: |
| 1489 | case ATH10K_HW_QCA6174: |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 1490 | case ATH10K_HW_QCA9377: |
Vasanthakumar Thiagarajan | 6e4202c | 2015-06-18 12:31:06 +0530 | [diff] [blame] | 1491 | val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + |
| 1492 | CORE_CTRL_ADDRESS); |
| 1493 | val &= ~CORE_CTRL_PCIE_REG_31_MASK; |
| 1494 | ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + |
| 1495 | CORE_CTRL_ADDRESS, val); |
| 1496 | break; |
| 1497 | case ATH10K_HW_QCA99X0: |
| 1498 | /* TODO: Find appropriate register configuration for QCA99X0 |
| 1499 | * to mask irq/MSI. |
| 1500 | */ |
| 1501 | break; |
| 1502 | } |
Michal Kazior | 7c0f0e3 | 2014-10-20 14:14:38 +0200 | [diff] [blame] | 1503 | } |
| 1504 | |
| 1505 | static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) |
| 1506 | { |
| 1507 | u32 val; |
| 1508 | |
Vasanthakumar Thiagarajan | 6e4202c | 2015-06-18 12:31:06 +0530 | [diff] [blame] | 1509 | switch (ar->hw_rev) { |
| 1510 | case ATH10K_HW_QCA988X: |
| 1511 | case ATH10K_HW_QCA6174: |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 1512 | case ATH10K_HW_QCA9377: |
Vasanthakumar Thiagarajan | 6e4202c | 2015-06-18 12:31:06 +0530 | [diff] [blame] | 1513 | val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + |
| 1514 | CORE_CTRL_ADDRESS); |
| 1515 | val |= CORE_CTRL_PCIE_REG_31_MASK; |
| 1516 | ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + |
| 1517 | CORE_CTRL_ADDRESS, val); |
| 1518 | break; |
| 1519 | case ATH10K_HW_QCA99X0: |
| 1520 | /* TODO: Find appropriate register configuration for QCA99X0 |
| 1521 | * to unmask irq/MSI. |
| 1522 | */ |
| 1523 | break; |
| 1524 | } |
Michal Kazior | 7c0f0e3 | 2014-10-20 14:14:38 +0200 | [diff] [blame] | 1525 | } |
| 1526 | |
Michal Kazior | ec5ba4d | 2014-08-22 14:23:33 +0200 | [diff] [blame] | 1527 | static void ath10k_pci_irq_disable(struct ath10k *ar) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1528 | { |
Michal Kazior | 7c0f0e3 | 2014-10-20 14:14:38 +0200 | [diff] [blame] | 1529 | ath10k_ce_disable_interrupts(ar); |
| 1530 | ath10k_pci_disable_and_clear_legacy_irq(ar); |
| 1531 | ath10k_pci_irq_msi_fw_mask(ar); |
| 1532 | } |
| 1533 | |
| 1534 | static void ath10k_pci_irq_sync(struct ath10k *ar) |
| 1535 | { |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1536 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Michal Kazior | ec5ba4d | 2014-08-22 14:23:33 +0200 | [diff] [blame] | 1537 | int i; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1538 | |
Michal Kazior | ec5ba4d | 2014-08-22 14:23:33 +0200 | [diff] [blame] | 1539 | for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++) |
| 1540 | synchronize_irq(ar_pci->pdev->irq + i); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1541 | } |
| 1542 | |
Michal Kazior | ec5ba4d | 2014-08-22 14:23:33 +0200 | [diff] [blame] | 1543 | static void ath10k_pci_irq_enable(struct ath10k *ar) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1544 | { |
Michal Kazior | ec5ba4d | 2014-08-22 14:23:33 +0200 | [diff] [blame] | 1545 | ath10k_ce_enable_interrupts(ar); |
Michal Kazior | e75db4e | 2014-08-28 22:14:16 +0300 | [diff] [blame] | 1546 | ath10k_pci_enable_legacy_irq(ar); |
Michal Kazior | 7c0f0e3 | 2014-10-20 14:14:38 +0200 | [diff] [blame] | 1547 | ath10k_pci_irq_msi_fw_unmask(ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1548 | } |
| 1549 | |
| 1550 | static int ath10k_pci_hif_start(struct ath10k *ar) |
| 1551 | { |
Janusz Dziedzic | 76d870e | 2015-05-18 09:38:16 +0000 | [diff] [blame] | 1552 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Kalle Valo | 9a14969 | 2015-10-05 17:56:36 +0300 | [diff] [blame] | 1553 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1554 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1555 | |
Michal Kazior | ec5ba4d | 2014-08-22 14:23:33 +0200 | [diff] [blame] | 1556 | ath10k_pci_irq_enable(ar); |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 1557 | ath10k_pci_rx_post(ar); |
Kalle Valo | 50f87a6 | 2014-03-28 09:32:52 +0200 | [diff] [blame] | 1558 | |
Janusz Dziedzic | 76d870e | 2015-05-18 09:38:16 +0000 | [diff] [blame] | 1559 | pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, |
| 1560 | ar_pci->link_ctl); |
| 1561 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1562 | return 0; |
| 1563 | } |
| 1564 | |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1565 | static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1566 | { |
| 1567 | struct ath10k *ar; |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1568 | struct ath10k_ce_pipe *ce_pipe; |
| 1569 | struct ath10k_ce_ring *ce_ring; |
| 1570 | struct sk_buff *skb; |
| 1571 | int i; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1572 | |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1573 | ar = pci_pipe->hif_ce_state; |
| 1574 | ce_pipe = pci_pipe->ce_hdl; |
| 1575 | ce_ring = ce_pipe->dest_ring; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1576 | |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1577 | if (!ce_ring) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1578 | return; |
| 1579 | |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1580 | if (!pci_pipe->buf_sz) |
| 1581 | return; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1582 | |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1583 | for (i = 0; i < ce_ring->nentries; i++) { |
| 1584 | skb = ce_ring->per_transfer_context[i]; |
| 1585 | if (!skb) |
| 1586 | continue; |
| 1587 | |
| 1588 | ce_ring->per_transfer_context[i] = NULL; |
| 1589 | |
Michal Kazior | 8582bf3 | 2015-01-24 12:14:47 +0200 | [diff] [blame] | 1590 | dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1591 | skb->len + skb_tailroom(skb), |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1592 | DMA_FROM_DEVICE); |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1593 | dev_kfree_skb_any(skb); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1594 | } |
| 1595 | } |
| 1596 | |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1597 | static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1598 | { |
| 1599 | struct ath10k *ar; |
| 1600 | struct ath10k_pci *ar_pci; |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1601 | struct ath10k_ce_pipe *ce_pipe; |
| 1602 | struct ath10k_ce_ring *ce_ring; |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1603 | struct sk_buff *skb; |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1604 | int i; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1605 | |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1606 | ar = pci_pipe->hif_ce_state; |
| 1607 | ar_pci = ath10k_pci_priv(ar); |
| 1608 | ce_pipe = pci_pipe->ce_hdl; |
| 1609 | ce_ring = ce_pipe->src_ring; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1610 | |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1611 | if (!ce_ring) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1612 | return; |
| 1613 | |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1614 | if (!pci_pipe->buf_sz) |
| 1615 | return; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1616 | |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1617 | for (i = 0; i < ce_ring->nentries; i++) { |
| 1618 | skb = ce_ring->per_transfer_context[i]; |
| 1619 | if (!skb) |
Michal Kazior | 2415fc1 | 2013-11-08 08:01:32 +0100 | [diff] [blame] | 1620 | continue; |
Michal Kazior | 2415fc1 | 2013-11-08 08:01:32 +0100 | [diff] [blame] | 1621 | |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1622 | ce_ring->per_transfer_context[i] = NULL; |
Michal Kazior | 099ac7c | 2014-10-28 10:32:05 +0100 | [diff] [blame] | 1623 | |
Rajkumar Manoharan | 0e5b295 | 2015-10-12 18:27:01 +0530 | [diff] [blame] | 1624 | ath10k_htc_tx_completion_handler(ar, skb); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1625 | } |
| 1626 | } |
| 1627 | |
| 1628 | /* |
| 1629 | * Cleanup residual buffers for device shutdown: |
| 1630 | * buffers that were enqueued for receive |
| 1631 | * buffers that were to be sent |
| 1632 | * Note: Buffers that had completed but which were |
| 1633 | * not yet processed are on a completion queue. They |
| 1634 | * are handled when the completion thread shuts down. |
| 1635 | */ |
| 1636 | static void ath10k_pci_buffer_cleanup(struct ath10k *ar) |
| 1637 | { |
| 1638 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 1639 | int pipe_num; |
| 1640 | |
Michal Kazior | fad6ed7 | 2013-11-08 08:01:23 +0100 | [diff] [blame] | 1641 | for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { |
Michal Kazior | 87263e5 | 2013-08-27 13:08:01 +0200 | [diff] [blame] | 1642 | struct ath10k_pci_pipe *pipe_info; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1643 | |
| 1644 | pipe_info = &ar_pci->pipe_info[pipe_num]; |
| 1645 | ath10k_pci_rx_pipe_cleanup(pipe_info); |
| 1646 | ath10k_pci_tx_pipe_cleanup(pipe_info); |
| 1647 | } |
| 1648 | } |
| 1649 | |
| 1650 | static void ath10k_pci_ce_deinit(struct ath10k *ar) |
| 1651 | { |
Michal Kazior | 25d0dbc | 2014-03-28 10:02:38 +0200 | [diff] [blame] | 1652 | int i; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1653 | |
Michal Kazior | 25d0dbc | 2014-03-28 10:02:38 +0200 | [diff] [blame] | 1654 | for (i = 0; i < CE_COUNT; i++) |
| 1655 | ath10k_ce_deinit_pipe(ar, i); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1656 | } |
| 1657 | |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 1658 | static void ath10k_pci_flush(struct ath10k *ar) |
| 1659 | { |
| 1660 | ath10k_pci_kill_tasklet(ar); |
| 1661 | ath10k_pci_buffer_cleanup(ar); |
| 1662 | } |
| 1663 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1664 | static void ath10k_pci_hif_stop(struct ath10k *ar) |
| 1665 | { |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 1666 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 1667 | unsigned long flags; |
| 1668 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1669 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); |
Michal Kazior | 32270b6 | 2013-08-02 09:15:47 +0200 | [diff] [blame] | 1670 | |
Michal Kazior | 10d23db | 2014-08-22 14:33:15 +0200 | [diff] [blame] | 1671 | /* Most likely the device has HTT Rx ring configured. The only way to |
| 1672 | * prevent the device from accessing (and possible corrupting) host |
| 1673 | * memory is to reset the chip now. |
Michal Kazior | e75db4e | 2014-08-28 22:14:16 +0300 | [diff] [blame] | 1674 | * |
| 1675 | * There's also no known way of masking MSI interrupts on the device. |
| 1676 | * For ranged MSI the CE-related interrupts can be masked. However |
| 1677 | * regardless how many MSI interrupts are assigned the first one |
| 1678 | * is always used for firmware indications (crashes) and cannot be |
| 1679 | * masked. To prevent the device from asserting the interrupt reset it |
| 1680 | * before proceeding with cleanup. |
Michal Kazior | 10d23db | 2014-08-22 14:33:15 +0200 | [diff] [blame] | 1681 | */ |
Vasanthakumar Thiagarajan | 6e4202c | 2015-06-18 12:31:06 +0530 | [diff] [blame] | 1682 | ath10k_pci_safe_chip_reset(ar); |
Michal Kazior | e75db4e | 2014-08-28 22:14:16 +0300 | [diff] [blame] | 1683 | |
| 1684 | ath10k_pci_irq_disable(ar); |
Michal Kazior | 7c0f0e3 | 2014-10-20 14:14:38 +0200 | [diff] [blame] | 1685 | ath10k_pci_irq_sync(ar); |
Michal Kazior | e75db4e | 2014-08-28 22:14:16 +0300 | [diff] [blame] | 1686 | ath10k_pci_flush(ar); |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 1687 | |
| 1688 | spin_lock_irqsave(&ar_pci->ps_lock, flags); |
| 1689 | WARN_ON(ar_pci->ps_wake_refcount > 0); |
| 1690 | spin_unlock_irqrestore(&ar_pci->ps_lock, flags); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1691 | } |
| 1692 | |
| 1693 | static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, |
| 1694 | void *req, u32 req_len, |
| 1695 | void *resp, u32 *resp_len) |
| 1696 | { |
| 1697 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 1698 | struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG]; |
| 1699 | struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST]; |
| 1700 | struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl; |
| 1701 | struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1702 | dma_addr_t req_paddr = 0; |
| 1703 | dma_addr_t resp_paddr = 0; |
| 1704 | struct bmi_xfer xfer = {}; |
| 1705 | void *treq, *tresp = NULL; |
| 1706 | int ret = 0; |
| 1707 | |
Michal Kazior | 85622cd | 2013-11-25 14:06:22 +0100 | [diff] [blame] | 1708 | might_sleep(); |
| 1709 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1710 | if (resp && !resp_len) |
| 1711 | return -EINVAL; |
| 1712 | |
| 1713 | if (resp && resp_len && *resp_len == 0) |
| 1714 | return -EINVAL; |
| 1715 | |
| 1716 | treq = kmemdup(req, req_len, GFP_KERNEL); |
| 1717 | if (!treq) |
| 1718 | return -ENOMEM; |
| 1719 | |
| 1720 | req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); |
| 1721 | ret = dma_mapping_error(ar->dev, req_paddr); |
Michal Kazior | 5e55e3c | 2015-08-19 13:10:43 +0200 | [diff] [blame] | 1722 | if (ret) { |
| 1723 | ret = -EIO; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1724 | goto err_dma; |
Michal Kazior | 5e55e3c | 2015-08-19 13:10:43 +0200 | [diff] [blame] | 1725 | } |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1726 | |
| 1727 | if (resp && resp_len) { |
| 1728 | tresp = kzalloc(*resp_len, GFP_KERNEL); |
| 1729 | if (!tresp) { |
| 1730 | ret = -ENOMEM; |
| 1731 | goto err_req; |
| 1732 | } |
| 1733 | |
| 1734 | resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, |
| 1735 | DMA_FROM_DEVICE); |
| 1736 | ret = dma_mapping_error(ar->dev, resp_paddr); |
Michal Kazior | 5e55e3c | 2015-08-19 13:10:43 +0200 | [diff] [blame] | 1737 | if (ret) { |
| 1738 | ret = EIO; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1739 | goto err_req; |
Michal Kazior | 5e55e3c | 2015-08-19 13:10:43 +0200 | [diff] [blame] | 1740 | } |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1741 | |
| 1742 | xfer.wait_for_resp = true; |
| 1743 | xfer.resp_len = 0; |
| 1744 | |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 1745 | ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1746 | } |
| 1747 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1748 | ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); |
| 1749 | if (ret) |
| 1750 | goto err_resp; |
| 1751 | |
Michal Kazior | 85622cd | 2013-11-25 14:06:22 +0100 | [diff] [blame] | 1752 | ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer); |
| 1753 | if (ret) { |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1754 | u32 unused_buffer; |
| 1755 | unsigned int unused_nbytes; |
| 1756 | unsigned int unused_id; |
| 1757 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1758 | ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer, |
| 1759 | &unused_nbytes, &unused_id); |
| 1760 | } else { |
| 1761 | /* non-zero means we did not time out */ |
| 1762 | ret = 0; |
| 1763 | } |
| 1764 | |
| 1765 | err_resp: |
| 1766 | if (resp) { |
| 1767 | u32 unused_buffer; |
| 1768 | |
| 1769 | ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer); |
| 1770 | dma_unmap_single(ar->dev, resp_paddr, |
| 1771 | *resp_len, DMA_FROM_DEVICE); |
| 1772 | } |
| 1773 | err_req: |
| 1774 | dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE); |
| 1775 | |
| 1776 | if (ret == 0 && resp_len) { |
| 1777 | *resp_len = min(*resp_len, xfer.resp_len); |
| 1778 | memcpy(resp, tresp, xfer.resp_len); |
| 1779 | } |
| 1780 | err_dma: |
| 1781 | kfree(treq); |
| 1782 | kfree(tresp); |
| 1783 | |
| 1784 | return ret; |
| 1785 | } |
| 1786 | |
Michal Kazior | 5440ce2 | 2013-09-03 15:09:58 +0200 | [diff] [blame] | 1787 | static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1788 | { |
Michal Kazior | 5440ce2 | 2013-09-03 15:09:58 +0200 | [diff] [blame] | 1789 | struct bmi_xfer *xfer; |
Michal Kazior | 5440ce2 | 2013-09-03 15:09:58 +0200 | [diff] [blame] | 1790 | |
Rajkumar Manoharan | 765952e | 2015-10-23 18:01:05 +0530 | [diff] [blame] | 1791 | if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer)) |
Michal Kazior | 5440ce2 | 2013-09-03 15:09:58 +0200 | [diff] [blame] | 1792 | return; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1793 | |
Michal Kazior | 2374b18 | 2014-07-14 16:25:25 +0300 | [diff] [blame] | 1794 | xfer->tx_done = true; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1795 | } |
| 1796 | |
Michal Kazior | 5440ce2 | 2013-09-03 15:09:58 +0200 | [diff] [blame] | 1797 | static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1798 | { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1799 | struct ath10k *ar = ce_state->ar; |
Michal Kazior | 5440ce2 | 2013-09-03 15:09:58 +0200 | [diff] [blame] | 1800 | struct bmi_xfer *xfer; |
| 1801 | u32 ce_data; |
| 1802 | unsigned int nbytes; |
| 1803 | unsigned int transfer_id; |
| 1804 | unsigned int flags; |
| 1805 | |
| 1806 | if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data, |
| 1807 | &nbytes, &transfer_id, &flags)) |
| 1808 | return; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1809 | |
Michal Kazior | 04ed9df | 2014-10-28 10:34:36 +0100 | [diff] [blame] | 1810 | if (WARN_ON_ONCE(!xfer)) |
| 1811 | return; |
| 1812 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1813 | if (!xfer->wait_for_resp) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1814 | ath10k_warn(ar, "unexpected: BMI data received; ignoring\n"); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1815 | return; |
| 1816 | } |
| 1817 | |
| 1818 | xfer->resp_len = nbytes; |
Michal Kazior | 2374b18 | 2014-07-14 16:25:25 +0300 | [diff] [blame] | 1819 | xfer->rx_done = true; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1820 | } |
| 1821 | |
Michal Kazior | 85622cd | 2013-11-25 14:06:22 +0100 | [diff] [blame] | 1822 | static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe, |
| 1823 | struct ath10k_ce_pipe *rx_pipe, |
| 1824 | struct bmi_xfer *xfer) |
| 1825 | { |
| 1826 | unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ; |
| 1827 | |
| 1828 | while (time_before_eq(jiffies, timeout)) { |
| 1829 | ath10k_pci_bmi_send_done(tx_pipe); |
| 1830 | ath10k_pci_bmi_recv_data(rx_pipe); |
| 1831 | |
Michal Kazior | 2374b18 | 2014-07-14 16:25:25 +0300 | [diff] [blame] | 1832 | if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) |
Michal Kazior | 85622cd | 2013-11-25 14:06:22 +0100 | [diff] [blame] | 1833 | return 0; |
| 1834 | |
| 1835 | schedule(); |
| 1836 | } |
| 1837 | |
| 1838 | return -ETIMEDOUT; |
| 1839 | } |
| 1840 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1841 | /* |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1842 | * Send an interrupt to the device to wake up the Target CPU |
| 1843 | * so it has an opportunity to notice any changed state. |
| 1844 | */ |
| 1845 | static int ath10k_pci_wake_target_cpu(struct ath10k *ar) |
| 1846 | { |
Michal Kazior | 9e26494 | 2014-09-02 11:00:21 +0300 | [diff] [blame] | 1847 | u32 addr, val; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1848 | |
Michal Kazior | 9e26494 | 2014-09-02 11:00:21 +0300 | [diff] [blame] | 1849 | addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS; |
| 1850 | val = ath10k_pci_read32(ar, addr); |
| 1851 | val |= CORE_CTRL_CPU_INTR_MASK; |
| 1852 | ath10k_pci_write32(ar, addr, val); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1853 | |
Michal Kazior | 1d2b48d | 2013-11-08 08:01:34 +0100 | [diff] [blame] | 1854 | return 0; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1855 | } |
| 1856 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 1857 | static int ath10k_pci_get_num_banks(struct ath10k *ar) |
| 1858 | { |
| 1859 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 1860 | |
| 1861 | switch (ar_pci->pdev->device) { |
| 1862 | case QCA988X_2_0_DEVICE_ID: |
Vasanthakumar Thiagarajan | 8bd4702 | 2015-06-18 12:31:03 +0530 | [diff] [blame] | 1863 | case QCA99X0_2_0_DEVICE_ID: |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 1864 | return 1; |
Michal Kazior | 36582e5 | 2015-08-13 14:32:26 +0200 | [diff] [blame] | 1865 | case QCA6164_2_1_DEVICE_ID: |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 1866 | case QCA6174_2_1_DEVICE_ID: |
| 1867 | switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) { |
| 1868 | case QCA6174_HW_1_0_CHIP_ID_REV: |
| 1869 | case QCA6174_HW_1_1_CHIP_ID_REV: |
Michal Kazior | 11a002e | 2015-04-20 09:20:41 +0000 | [diff] [blame] | 1870 | case QCA6174_HW_2_1_CHIP_ID_REV: |
| 1871 | case QCA6174_HW_2_2_CHIP_ID_REV: |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 1872 | return 3; |
| 1873 | case QCA6174_HW_1_3_CHIP_ID_REV: |
| 1874 | return 2; |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 1875 | case QCA6174_HW_3_0_CHIP_ID_REV: |
| 1876 | case QCA6174_HW_3_1_CHIP_ID_REV: |
| 1877 | case QCA6174_HW_3_2_CHIP_ID_REV: |
| 1878 | return 9; |
| 1879 | } |
| 1880 | break; |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 1881 | case QCA9377_1_0_DEVICE_ID: |
| 1882 | return 2; |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 1883 | } |
| 1884 | |
| 1885 | ath10k_warn(ar, "unknown number of banks, assuming 1\n"); |
| 1886 | return 1; |
| 1887 | } |
| 1888 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1889 | static int ath10k_pci_init_config(struct ath10k *ar) |
| 1890 | { |
| 1891 | u32 interconnect_targ_addr; |
| 1892 | u32 pcie_state_targ_addr = 0; |
| 1893 | u32 pipe_cfg_targ_addr = 0; |
| 1894 | u32 svc_to_pipe_map = 0; |
| 1895 | u32 pcie_config_flags = 0; |
| 1896 | u32 ealloc_value; |
| 1897 | u32 ealloc_targ_addr; |
| 1898 | u32 flag2_value; |
| 1899 | u32 flag2_targ_addr; |
| 1900 | int ret = 0; |
| 1901 | |
| 1902 | /* Download to Target the CE Config and the service-to-CE map */ |
| 1903 | interconnect_targ_addr = |
| 1904 | host_interest_item_address(HI_ITEM(hi_interconnect_state)); |
| 1905 | |
| 1906 | /* Supply Target-side CE configuration */ |
Michal Kazior | 9e26494 | 2014-09-02 11:00:21 +0300 | [diff] [blame] | 1907 | ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr, |
| 1908 | &pcie_state_targ_addr); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1909 | if (ret != 0) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1910 | ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1911 | return ret; |
| 1912 | } |
| 1913 | |
| 1914 | if (pcie_state_targ_addr == 0) { |
| 1915 | ret = -EIO; |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1916 | ath10k_err(ar, "Invalid pcie state addr\n"); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1917 | return ret; |
| 1918 | } |
| 1919 | |
Michal Kazior | 9e26494 | 2014-09-02 11:00:21 +0300 | [diff] [blame] | 1920 | ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1921 | offsetof(struct pcie_state, |
Michal Kazior | 9e26494 | 2014-09-02 11:00:21 +0300 | [diff] [blame] | 1922 | pipe_cfg_addr)), |
| 1923 | &pipe_cfg_targ_addr); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1924 | if (ret != 0) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1925 | ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1926 | return ret; |
| 1927 | } |
| 1928 | |
| 1929 | if (pipe_cfg_targ_addr == 0) { |
| 1930 | ret = -EIO; |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1931 | ath10k_err(ar, "Invalid pipe cfg addr\n"); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1932 | return ret; |
| 1933 | } |
| 1934 | |
| 1935 | ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr, |
Kalle Valo | 5b07e07 | 2014-09-14 12:50:06 +0300 | [diff] [blame] | 1936 | target_ce_config_wlan, |
Vasanthakumar Thiagarajan | 050af06 | 2015-06-18 12:31:04 +0530 | [diff] [blame] | 1937 | sizeof(struct ce_pipe_config) * |
| 1938 | NUM_TARGET_CE_CONFIG_WLAN); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1939 | |
| 1940 | if (ret != 0) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1941 | ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1942 | return ret; |
| 1943 | } |
| 1944 | |
Michal Kazior | 9e26494 | 2014-09-02 11:00:21 +0300 | [diff] [blame] | 1945 | ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1946 | offsetof(struct pcie_state, |
Michal Kazior | 9e26494 | 2014-09-02 11:00:21 +0300 | [diff] [blame] | 1947 | svc_to_pipe_map)), |
| 1948 | &svc_to_pipe_map); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1949 | if (ret != 0) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1950 | ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1951 | return ret; |
| 1952 | } |
| 1953 | |
| 1954 | if (svc_to_pipe_map == 0) { |
| 1955 | ret = -EIO; |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1956 | ath10k_err(ar, "Invalid svc_to_pipe map\n"); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1957 | return ret; |
| 1958 | } |
| 1959 | |
| 1960 | ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map, |
Kalle Valo | 5b07e07 | 2014-09-14 12:50:06 +0300 | [diff] [blame] | 1961 | target_service_to_ce_map_wlan, |
| 1962 | sizeof(target_service_to_ce_map_wlan)); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1963 | if (ret != 0) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1964 | ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1965 | return ret; |
| 1966 | } |
| 1967 | |
Michal Kazior | 9e26494 | 2014-09-02 11:00:21 +0300 | [diff] [blame] | 1968 | ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1969 | offsetof(struct pcie_state, |
Michal Kazior | 9e26494 | 2014-09-02 11:00:21 +0300 | [diff] [blame] | 1970 | config_flags)), |
| 1971 | &pcie_config_flags); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1972 | if (ret != 0) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1973 | ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1974 | return ret; |
| 1975 | } |
| 1976 | |
| 1977 | pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1; |
| 1978 | |
Michal Kazior | 9e26494 | 2014-09-02 11:00:21 +0300 | [diff] [blame] | 1979 | ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr + |
| 1980 | offsetof(struct pcie_state, |
| 1981 | config_flags)), |
| 1982 | pcie_config_flags); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1983 | if (ret != 0) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1984 | ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1985 | return ret; |
| 1986 | } |
| 1987 | |
| 1988 | /* configure early allocation */ |
| 1989 | ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc)); |
| 1990 | |
Michal Kazior | 9e26494 | 2014-09-02 11:00:21 +0300 | [diff] [blame] | 1991 | ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1992 | if (ret != 0) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 1993 | ath10k_err(ar, "Faile to get early alloc val: %d\n", ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1994 | return ret; |
| 1995 | } |
| 1996 | |
| 1997 | /* first bank is switched to IRAM */ |
| 1998 | ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) & |
| 1999 | HI_EARLY_ALLOC_MAGIC_MASK); |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 2000 | ealloc_value |= ((ath10k_pci_get_num_banks(ar) << |
| 2001 | HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) & |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2002 | HI_EARLY_ALLOC_IRAM_BANKS_MASK); |
| 2003 | |
Michal Kazior | 9e26494 | 2014-09-02 11:00:21 +0300 | [diff] [blame] | 2004 | ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2005 | if (ret != 0) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2006 | ath10k_err(ar, "Failed to set early alloc val: %d\n", ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2007 | return ret; |
| 2008 | } |
| 2009 | |
| 2010 | /* Tell Target to proceed with initialization */ |
| 2011 | flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2)); |
| 2012 | |
Michal Kazior | 9e26494 | 2014-09-02 11:00:21 +0300 | [diff] [blame] | 2013 | ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2014 | if (ret != 0) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2015 | ath10k_err(ar, "Failed to get option val: %d\n", ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2016 | return ret; |
| 2017 | } |
| 2018 | |
| 2019 | flag2_value |= HI_OPTION_EARLY_CFG_DONE; |
| 2020 | |
Michal Kazior | 9e26494 | 2014-09-02 11:00:21 +0300 | [diff] [blame] | 2021 | ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2022 | if (ret != 0) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2023 | ath10k_err(ar, "Failed to set option val: %d\n", ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2024 | return ret; |
| 2025 | } |
| 2026 | |
| 2027 | return 0; |
| 2028 | } |
| 2029 | |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 2030 | static int ath10k_pci_alloc_pipes(struct ath10k *ar) |
Michal Kazior | 25d0dbc | 2014-03-28 10:02:38 +0200 | [diff] [blame] | 2031 | { |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 2032 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 2033 | struct ath10k_pci_pipe *pipe; |
Michal Kazior | 25d0dbc | 2014-03-28 10:02:38 +0200 | [diff] [blame] | 2034 | int i, ret; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2035 | |
Michal Kazior | 25d0dbc | 2014-03-28 10:02:38 +0200 | [diff] [blame] | 2036 | for (i = 0; i < CE_COUNT; i++) { |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 2037 | pipe = &ar_pci->pipe_info[i]; |
| 2038 | pipe->ce_hdl = &ar_pci->ce_states[i]; |
| 2039 | pipe->pipe_num = i; |
| 2040 | pipe->hif_ce_state = ar; |
| 2041 | |
Rajkumar Manoharan | 9d9bdbb | 2015-10-12 18:27:02 +0530 | [diff] [blame] | 2042 | ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]); |
Michal Kazior | 25d0dbc | 2014-03-28 10:02:38 +0200 | [diff] [blame] | 2043 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2044 | ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", |
Michal Kazior | 25d0dbc | 2014-03-28 10:02:38 +0200 | [diff] [blame] | 2045 | i, ret); |
| 2046 | return ret; |
| 2047 | } |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 2048 | |
| 2049 | /* Last CE is Diagnostic Window */ |
Vasanthakumar Thiagarajan | 050af06 | 2015-06-18 12:31:04 +0530 | [diff] [blame] | 2050 | if (i == CE_DIAG_PIPE) { |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 2051 | ar_pci->ce_diag = pipe->ce_hdl; |
| 2052 | continue; |
| 2053 | } |
| 2054 | |
| 2055 | pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max); |
Michal Kazior | 25d0dbc | 2014-03-28 10:02:38 +0200 | [diff] [blame] | 2056 | } |
| 2057 | |
| 2058 | return 0; |
| 2059 | } |
| 2060 | |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 2061 | static void ath10k_pci_free_pipes(struct ath10k *ar) |
Michal Kazior | 25d0dbc | 2014-03-28 10:02:38 +0200 | [diff] [blame] | 2062 | { |
| 2063 | int i; |
| 2064 | |
| 2065 | for (i = 0; i < CE_COUNT; i++) |
| 2066 | ath10k_ce_free_pipe(ar, i); |
| 2067 | } |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2068 | |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 2069 | static int ath10k_pci_init_pipes(struct ath10k *ar) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2070 | { |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 2071 | int i, ret; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2072 | |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 2073 | for (i = 0; i < CE_COUNT; i++) { |
| 2074 | ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]); |
Michal Kazior | 25d0dbc | 2014-03-28 10:02:38 +0200 | [diff] [blame] | 2075 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2076 | ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 2077 | i, ret); |
Michal Kazior | 25d0dbc | 2014-03-28 10:02:38 +0200 | [diff] [blame] | 2078 | return ret; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2079 | } |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2080 | } |
| 2081 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2082 | return 0; |
| 2083 | } |
| 2084 | |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 2085 | static bool ath10k_pci_has_fw_crashed(struct ath10k *ar) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2086 | { |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 2087 | return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) & |
| 2088 | FW_IND_EVENT_PENDING; |
| 2089 | } |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2090 | |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 2091 | static void ath10k_pci_fw_crashed_clear(struct ath10k *ar) |
| 2092 | { |
| 2093 | u32 val; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2094 | |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 2095 | val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); |
| 2096 | val &= ~FW_IND_EVENT_PENDING; |
| 2097 | ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2098 | } |
| 2099 | |
Michal Kazior | de01357 | 2014-05-14 16:56:16 +0300 | [diff] [blame] | 2100 | /* this function effectively clears target memory controller assert line */ |
| 2101 | static void ath10k_pci_warm_reset_si0(struct ath10k *ar) |
| 2102 | { |
| 2103 | u32 val; |
| 2104 | |
| 2105 | val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); |
| 2106 | ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, |
| 2107 | val | SOC_RESET_CONTROL_SI0_RST_MASK); |
| 2108 | val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); |
| 2109 | |
| 2110 | msleep(10); |
| 2111 | |
| 2112 | val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); |
| 2113 | ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, |
| 2114 | val & ~SOC_RESET_CONTROL_SI0_RST_MASK); |
| 2115 | val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); |
| 2116 | |
| 2117 | msleep(10); |
| 2118 | } |
| 2119 | |
Michal Kazior | 61c1648 | 2014-10-28 10:32:06 +0100 | [diff] [blame] | 2120 | static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 2121 | { |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 2122 | u32 val; |
| 2123 | |
Kalle Valo | b39712c | 2014-03-28 09:32:46 +0200 | [diff] [blame] | 2124 | ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0); |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 2125 | |
Michal Kazior | 61c1648 | 2014-10-28 10:32:06 +0100 | [diff] [blame] | 2126 | val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + |
| 2127 | SOC_RESET_CONTROL_ADDRESS); |
| 2128 | ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, |
| 2129 | val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK); |
| 2130 | } |
| 2131 | |
| 2132 | static void ath10k_pci_warm_reset_ce(struct ath10k *ar) |
| 2133 | { |
| 2134 | u32 val; |
| 2135 | |
| 2136 | val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + |
| 2137 | SOC_RESET_CONTROL_ADDRESS); |
| 2138 | |
| 2139 | ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, |
| 2140 | val | SOC_RESET_CONTROL_CE_RST_MASK); |
| 2141 | msleep(10); |
| 2142 | ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, |
| 2143 | val & ~SOC_RESET_CONTROL_CE_RST_MASK); |
| 2144 | } |
| 2145 | |
| 2146 | static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) |
| 2147 | { |
| 2148 | u32 val; |
| 2149 | |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 2150 | val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + |
| 2151 | SOC_LF_TIMER_CONTROL0_ADDRESS); |
| 2152 | ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + |
| 2153 | SOC_LF_TIMER_CONTROL0_ADDRESS, |
| 2154 | val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK); |
Michal Kazior | 61c1648 | 2014-10-28 10:32:06 +0100 | [diff] [blame] | 2155 | } |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 2156 | |
Michal Kazior | 61c1648 | 2014-10-28 10:32:06 +0100 | [diff] [blame] | 2157 | static int ath10k_pci_warm_reset(struct ath10k *ar) |
| 2158 | { |
| 2159 | int ret; |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 2160 | |
Michal Kazior | 61c1648 | 2014-10-28 10:32:06 +0100 | [diff] [blame] | 2161 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n"); |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 2162 | |
Michal Kazior | 61c1648 | 2014-10-28 10:32:06 +0100 | [diff] [blame] | 2163 | spin_lock_bh(&ar->data_lock); |
| 2164 | ar->stats.fw_warm_reset_counter++; |
| 2165 | spin_unlock_bh(&ar->data_lock); |
| 2166 | |
| 2167 | ath10k_pci_irq_disable(ar); |
| 2168 | |
| 2169 | /* Make sure the target CPU is not doing anything dangerous, e.g. if it |
| 2170 | * were to access copy engine while host performs copy engine reset |
| 2171 | * then it is possible for the device to confuse pci-e controller to |
| 2172 | * the point of bringing host system to a complete stop (i.e. hang). |
| 2173 | */ |
Michal Kazior | de01357 | 2014-05-14 16:56:16 +0300 | [diff] [blame] | 2174 | ath10k_pci_warm_reset_si0(ar); |
Michal Kazior | 61c1648 | 2014-10-28 10:32:06 +0100 | [diff] [blame] | 2175 | ath10k_pci_warm_reset_cpu(ar); |
| 2176 | ath10k_pci_init_pipes(ar); |
| 2177 | ath10k_pci_wait_for_target_init(ar); |
Michal Kazior | de01357 | 2014-05-14 16:56:16 +0300 | [diff] [blame] | 2178 | |
Michal Kazior | 61c1648 | 2014-10-28 10:32:06 +0100 | [diff] [blame] | 2179 | ath10k_pci_warm_reset_clear_lf(ar); |
| 2180 | ath10k_pci_warm_reset_ce(ar); |
| 2181 | ath10k_pci_warm_reset_cpu(ar); |
| 2182 | ath10k_pci_init_pipes(ar); |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 2183 | |
Michal Kazior | 61c1648 | 2014-10-28 10:32:06 +0100 | [diff] [blame] | 2184 | ret = ath10k_pci_wait_for_target_init(ar); |
| 2185 | if (ret) { |
| 2186 | ath10k_warn(ar, "failed to wait for target init: %d\n", ret); |
| 2187 | return ret; |
| 2188 | } |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 2189 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2190 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n"); |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 2191 | |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 2192 | return 0; |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 2193 | } |
| 2194 | |
Vasanthakumar Thiagarajan | 6e4202c | 2015-06-18 12:31:06 +0530 | [diff] [blame] | 2195 | static int ath10k_pci_safe_chip_reset(struct ath10k *ar) |
| 2196 | { |
| 2197 | if (QCA_REV_988X(ar) || QCA_REV_6174(ar)) { |
| 2198 | return ath10k_pci_warm_reset(ar); |
| 2199 | } else if (QCA_REV_99X0(ar)) { |
| 2200 | ath10k_pci_irq_disable(ar); |
| 2201 | return ath10k_pci_qca99x0_chip_reset(ar); |
| 2202 | } else { |
| 2203 | return -ENOTSUPP; |
| 2204 | } |
| 2205 | } |
| 2206 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 2207 | static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar) |
Michal Kazior | 0bc14d0 | 2014-10-28 10:32:07 +0100 | [diff] [blame] | 2208 | { |
| 2209 | int i, ret; |
| 2210 | u32 val; |
| 2211 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 2212 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n"); |
Michal Kazior | 0bc14d0 | 2014-10-28 10:32:07 +0100 | [diff] [blame] | 2213 | |
| 2214 | /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset. |
| 2215 | * It is thus preferred to use warm reset which is safer but may not be |
| 2216 | * able to recover the device from all possible fail scenarios. |
| 2217 | * |
| 2218 | * Warm reset doesn't always work on first try so attempt it a few |
| 2219 | * times before giving up. |
| 2220 | */ |
| 2221 | for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) { |
| 2222 | ret = ath10k_pci_warm_reset(ar); |
| 2223 | if (ret) { |
| 2224 | ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n", |
| 2225 | i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, |
| 2226 | ret); |
| 2227 | continue; |
| 2228 | } |
| 2229 | |
| 2230 | /* FIXME: Sometimes copy engine doesn't recover after warm |
| 2231 | * reset. In most cases this needs cold reset. In some of these |
| 2232 | * cases the device is in such a state that a cold reset may |
| 2233 | * lock up the host. |
| 2234 | * |
| 2235 | * Reading any host interest register via copy engine is |
| 2236 | * sufficient to verify if device is capable of booting |
| 2237 | * firmware blob. |
| 2238 | */ |
| 2239 | ret = ath10k_pci_init_pipes(ar); |
| 2240 | if (ret) { |
| 2241 | ath10k_warn(ar, "failed to init copy engine: %d\n", |
| 2242 | ret); |
| 2243 | continue; |
| 2244 | } |
| 2245 | |
| 2246 | ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS, |
| 2247 | &val); |
| 2248 | if (ret) { |
| 2249 | ath10k_warn(ar, "failed to poke copy engine: %d\n", |
| 2250 | ret); |
| 2251 | continue; |
| 2252 | } |
| 2253 | |
| 2254 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n"); |
| 2255 | return 0; |
| 2256 | } |
| 2257 | |
| 2258 | if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) { |
| 2259 | ath10k_warn(ar, "refusing cold reset as requested\n"); |
| 2260 | return -EPERM; |
| 2261 | } |
| 2262 | |
| 2263 | ret = ath10k_pci_cold_reset(ar); |
| 2264 | if (ret) { |
| 2265 | ath10k_warn(ar, "failed to cold reset: %d\n", ret); |
| 2266 | return ret; |
| 2267 | } |
| 2268 | |
| 2269 | ret = ath10k_pci_wait_for_target_init(ar); |
| 2270 | if (ret) { |
| 2271 | ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", |
| 2272 | ret); |
| 2273 | return ret; |
| 2274 | } |
| 2275 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 2276 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n"); |
Michal Kazior | 0bc14d0 | 2014-10-28 10:32:07 +0100 | [diff] [blame] | 2277 | |
| 2278 | return 0; |
| 2279 | } |
| 2280 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 2281 | static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar) |
| 2282 | { |
| 2283 | int ret; |
| 2284 | |
| 2285 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n"); |
| 2286 | |
| 2287 | /* FIXME: QCA6174 requires cold + warm reset to work. */ |
| 2288 | |
| 2289 | ret = ath10k_pci_cold_reset(ar); |
| 2290 | if (ret) { |
| 2291 | ath10k_warn(ar, "failed to cold reset: %d\n", ret); |
| 2292 | return ret; |
| 2293 | } |
| 2294 | |
| 2295 | ret = ath10k_pci_wait_for_target_init(ar); |
| 2296 | if (ret) { |
| 2297 | ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", |
Kalle Valo | 617b0f4 | 2015-10-05 17:56:35 +0300 | [diff] [blame] | 2298 | ret); |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 2299 | return ret; |
| 2300 | } |
| 2301 | |
| 2302 | ret = ath10k_pci_warm_reset(ar); |
| 2303 | if (ret) { |
| 2304 | ath10k_warn(ar, "failed to warm reset: %d\n", ret); |
| 2305 | return ret; |
| 2306 | } |
| 2307 | |
| 2308 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n"); |
| 2309 | |
| 2310 | return 0; |
| 2311 | } |
| 2312 | |
Vasanthakumar Thiagarajan | 6e4202c | 2015-06-18 12:31:06 +0530 | [diff] [blame] | 2313 | static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar) |
| 2314 | { |
| 2315 | int ret; |
| 2316 | |
| 2317 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n"); |
| 2318 | |
| 2319 | ret = ath10k_pci_cold_reset(ar); |
| 2320 | if (ret) { |
| 2321 | ath10k_warn(ar, "failed to cold reset: %d\n", ret); |
| 2322 | return ret; |
| 2323 | } |
| 2324 | |
| 2325 | ret = ath10k_pci_wait_for_target_init(ar); |
| 2326 | if (ret) { |
| 2327 | ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", |
| 2328 | ret); |
| 2329 | return ret; |
| 2330 | } |
| 2331 | |
| 2332 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n"); |
| 2333 | |
| 2334 | return 0; |
| 2335 | } |
| 2336 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 2337 | static int ath10k_pci_chip_reset(struct ath10k *ar) |
| 2338 | { |
| 2339 | if (QCA_REV_988X(ar)) |
| 2340 | return ath10k_pci_qca988x_chip_reset(ar); |
| 2341 | else if (QCA_REV_6174(ar)) |
| 2342 | return ath10k_pci_qca6174_chip_reset(ar); |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 2343 | else if (QCA_REV_9377(ar)) |
| 2344 | return ath10k_pci_qca6174_chip_reset(ar); |
Vasanthakumar Thiagarajan | 6e4202c | 2015-06-18 12:31:06 +0530 | [diff] [blame] | 2345 | else if (QCA_REV_99X0(ar)) |
| 2346 | return ath10k_pci_qca99x0_chip_reset(ar); |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 2347 | else |
| 2348 | return -ENOTSUPP; |
| 2349 | } |
| 2350 | |
Michal Kazior | 0bc14d0 | 2014-10-28 10:32:07 +0100 | [diff] [blame] | 2351 | static int ath10k_pci_hif_power_up(struct ath10k *ar) |
Michal Kazior | 8c5c536 | 2013-07-16 09:38:50 +0200 | [diff] [blame] | 2352 | { |
Janusz Dziedzic | 76d870e | 2015-05-18 09:38:16 +0000 | [diff] [blame] | 2353 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Michal Kazior | 8c5c536 | 2013-07-16 09:38:50 +0200 | [diff] [blame] | 2354 | int ret; |
| 2355 | |
Michal Kazior | 0bc14d0 | 2014-10-28 10:32:07 +0100 | [diff] [blame] | 2356 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n"); |
| 2357 | |
Janusz Dziedzic | 76d870e | 2015-05-18 09:38:16 +0000 | [diff] [blame] | 2358 | pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, |
| 2359 | &ar_pci->link_ctl); |
| 2360 | pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, |
| 2361 | ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); |
| 2362 | |
Michal Kazior | 8c5c536 | 2013-07-16 09:38:50 +0200 | [diff] [blame] | 2363 | /* |
| 2364 | * Bring the target up cleanly. |
| 2365 | * |
| 2366 | * The target may be in an undefined state with an AUX-powered Target |
| 2367 | * and a Host in WoW mode. If the Host crashes, loses power, or is |
| 2368 | * restarted (without unloading the driver) then the Target is left |
| 2369 | * (aux) powered and running. On a subsequent driver load, the Target |
| 2370 | * is in an unexpected state. We try to catch that here in order to |
| 2371 | * reset the Target and retry the probe. |
| 2372 | */ |
Michal Kazior | 0bc14d0 | 2014-10-28 10:32:07 +0100 | [diff] [blame] | 2373 | ret = ath10k_pci_chip_reset(ar); |
Michal Kazior | 5b2589f | 2013-11-08 08:01:30 +0100 | [diff] [blame] | 2374 | if (ret) { |
Michal Kazior | a2fa880 | 2015-01-12 15:29:37 +0100 | [diff] [blame] | 2375 | if (ath10k_pci_has_fw_crashed(ar)) { |
| 2376 | ath10k_warn(ar, "firmware crashed during chip reset\n"); |
| 2377 | ath10k_pci_fw_crashed_clear(ar); |
| 2378 | ath10k_pci_fw_crashed_dump(ar); |
| 2379 | } |
| 2380 | |
Michal Kazior | 0bc14d0 | 2014-10-28 10:32:07 +0100 | [diff] [blame] | 2381 | ath10k_err(ar, "failed to reset chip: %d\n", ret); |
Bartosz Markowski | 707b1bbd | 2014-10-31 09:03:43 +0100 | [diff] [blame] | 2382 | goto err_sleep; |
Michal Kazior | 5b2589f | 2013-11-08 08:01:30 +0100 | [diff] [blame] | 2383 | } |
Michal Kazior | 8c5c536 | 2013-07-16 09:38:50 +0200 | [diff] [blame] | 2384 | |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 2385 | ret = ath10k_pci_init_pipes(ar); |
Michal Kazior | 8c5c536 | 2013-07-16 09:38:50 +0200 | [diff] [blame] | 2386 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2387 | ath10k_err(ar, "failed to initialize CE: %d\n", ret); |
Bartosz Markowski | 707b1bbd | 2014-10-31 09:03:43 +0100 | [diff] [blame] | 2388 | goto err_sleep; |
Michal Kazior | ab977bd | 2013-11-25 14:06:26 +0100 | [diff] [blame] | 2389 | } |
| 2390 | |
Michal Kazior | 98563d5 | 2013-11-08 08:01:33 +0100 | [diff] [blame] | 2391 | ret = ath10k_pci_init_config(ar); |
| 2392 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2393 | ath10k_err(ar, "failed to setup init config: %d\n", ret); |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 2394 | goto err_ce; |
Michal Kazior | 98563d5 | 2013-11-08 08:01:33 +0100 | [diff] [blame] | 2395 | } |
Michal Kazior | 8c5c536 | 2013-07-16 09:38:50 +0200 | [diff] [blame] | 2396 | |
| 2397 | ret = ath10k_pci_wake_target_cpu(ar); |
| 2398 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2399 | ath10k_err(ar, "could not wake up target CPU: %d\n", ret); |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 2400 | goto err_ce; |
Michal Kazior | 8c5c536 | 2013-07-16 09:38:50 +0200 | [diff] [blame] | 2401 | } |
| 2402 | |
| 2403 | return 0; |
| 2404 | |
| 2405 | err_ce: |
| 2406 | ath10k_pci_ce_deinit(ar); |
Michal Kazior | 0bc14d0 | 2014-10-28 10:32:07 +0100 | [diff] [blame] | 2407 | |
Bartosz Markowski | 707b1bbd | 2014-10-31 09:03:43 +0100 | [diff] [blame] | 2408 | err_sleep: |
Michal Kazior | 8c5c536 | 2013-07-16 09:38:50 +0200 | [diff] [blame] | 2409 | return ret; |
| 2410 | } |
| 2411 | |
| 2412 | static void ath10k_pci_hif_power_down(struct ath10k *ar) |
| 2413 | { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2414 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); |
Bartosz Markowski | 8cc8df9 | 2013-08-02 09:58:49 +0200 | [diff] [blame] | 2415 | |
Michal Kazior | c011b28 | 2014-10-28 10:32:08 +0100 | [diff] [blame] | 2416 | /* Currently hif_power_up performs effectively a reset and hif_stop |
| 2417 | * resets the chip as well so there's no point in resetting here. |
| 2418 | */ |
Michal Kazior | 8c5c536 | 2013-07-16 09:38:50 +0200 | [diff] [blame] | 2419 | } |
| 2420 | |
Michal Kazior | 8cd13ca | 2013-07-16 09:38:54 +0200 | [diff] [blame] | 2421 | #ifdef CONFIG_PM |
| 2422 | |
Michal Kazior | 8cd13ca | 2013-07-16 09:38:54 +0200 | [diff] [blame] | 2423 | static int ath10k_pci_hif_suspend(struct ath10k *ar) |
| 2424 | { |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 2425 | /* The grace timer can still be counting down and ar->ps_awake be true. |
| 2426 | * It is known that the device may be asleep after resuming regardless |
| 2427 | * of the SoC powersave state before suspending. Hence make sure the |
| 2428 | * device is asleep before proceeding. |
| 2429 | */ |
| 2430 | ath10k_pci_sleep_sync(ar); |
Michal Kazior | 320e14b | 2015-03-02 13:22:13 +0100 | [diff] [blame] | 2431 | |
Michal Kazior | 8cd13ca | 2013-07-16 09:38:54 +0200 | [diff] [blame] | 2432 | return 0; |
| 2433 | } |
| 2434 | |
| 2435 | static int ath10k_pci_hif_resume(struct ath10k *ar) |
| 2436 | { |
| 2437 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 2438 | struct pci_dev *pdev = ar_pci->pdev; |
| 2439 | u32 val; |
Anilkumar Kolli | 1aaf8ef | 2015-10-16 15:54:51 +0300 | [diff] [blame] | 2440 | int ret = 0; |
| 2441 | |
| 2442 | if (ar_pci->pci_ps == 0) { |
| 2443 | ret = ath10k_pci_force_wake(ar); |
| 2444 | if (ret) { |
| 2445 | ath10k_err(ar, "failed to wake up target: %d\n", ret); |
| 2446 | return ret; |
| 2447 | } |
| 2448 | } |
Michal Kazior | 8cd13ca | 2013-07-16 09:38:54 +0200 | [diff] [blame] | 2449 | |
Michal Kazior | 9ff4be9 | 2015-03-02 13:22:14 +0100 | [diff] [blame] | 2450 | /* Suspend/Resume resets the PCI configuration space, so we have to |
| 2451 | * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries |
| 2452 | * from interfering with C3 CPU state. pci_restore_state won't help |
| 2453 | * here since it only restores the first 64 bytes pci config header. |
| 2454 | */ |
| 2455 | pci_read_config_dword(pdev, 0x40, &val); |
| 2456 | if ((val & 0x0000ff00) != 0) |
| 2457 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); |
Michal Kazior | 8cd13ca | 2013-07-16 09:38:54 +0200 | [diff] [blame] | 2458 | |
Anilkumar Kolli | 1aaf8ef | 2015-10-16 15:54:51 +0300 | [diff] [blame] | 2459 | return ret; |
Michal Kazior | 8cd13ca | 2013-07-16 09:38:54 +0200 | [diff] [blame] | 2460 | } |
| 2461 | #endif |
| 2462 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2463 | static const struct ath10k_hif_ops ath10k_pci_hif_ops = { |
Michal Kazior | 726346f | 2014-02-27 18:50:04 +0200 | [diff] [blame] | 2464 | .tx_sg = ath10k_pci_hif_tx_sg, |
Kalle Valo | eef2540 | 2014-09-24 14:16:52 +0300 | [diff] [blame] | 2465 | .diag_read = ath10k_pci_hif_diag_read, |
Yanbo Li | 9f65ad2 | 2014-11-25 12:24:48 +0200 | [diff] [blame] | 2466 | .diag_write = ath10k_pci_diag_write_mem, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2467 | .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, |
| 2468 | .start = ath10k_pci_hif_start, |
| 2469 | .stop = ath10k_pci_hif_stop, |
| 2470 | .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, |
| 2471 | .get_default_pipe = ath10k_pci_hif_get_default_pipe, |
| 2472 | .send_complete_check = ath10k_pci_hif_send_complete_check, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2473 | .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, |
Michal Kazior | 8c5c536 | 2013-07-16 09:38:50 +0200 | [diff] [blame] | 2474 | .power_up = ath10k_pci_hif_power_up, |
| 2475 | .power_down = ath10k_pci_hif_power_down, |
Yanbo Li | 077a380 | 2014-11-25 12:24:33 +0200 | [diff] [blame] | 2476 | .read32 = ath10k_pci_read32, |
| 2477 | .write32 = ath10k_pci_write32, |
Michal Kazior | 8cd13ca | 2013-07-16 09:38:54 +0200 | [diff] [blame] | 2478 | #ifdef CONFIG_PM |
| 2479 | .suspend = ath10k_pci_hif_suspend, |
| 2480 | .resume = ath10k_pci_hif_resume, |
| 2481 | #endif |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2482 | }; |
| 2483 | |
| 2484 | static void ath10k_pci_ce_tasklet(unsigned long ptr) |
| 2485 | { |
Michal Kazior | 87263e5 | 2013-08-27 13:08:01 +0200 | [diff] [blame] | 2486 | struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2487 | struct ath10k_pci *ar_pci = pipe->ar_pci; |
| 2488 | |
| 2489 | ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num); |
| 2490 | } |
| 2491 | |
| 2492 | static void ath10k_msi_err_tasklet(unsigned long data) |
| 2493 | { |
| 2494 | struct ath10k *ar = (struct ath10k *)data; |
| 2495 | |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 2496 | if (!ath10k_pci_has_fw_crashed(ar)) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2497 | ath10k_warn(ar, "received unsolicited fw crash interrupt\n"); |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 2498 | return; |
| 2499 | } |
| 2500 | |
Michal Kazior | 6f3b7ff | 2015-01-24 12:14:52 +0200 | [diff] [blame] | 2501 | ath10k_pci_irq_disable(ar); |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 2502 | ath10k_pci_fw_crashed_clear(ar); |
| 2503 | ath10k_pci_fw_crashed_dump(ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2504 | } |
| 2505 | |
| 2506 | /* |
| 2507 | * Handler for a per-engine interrupt on a PARTICULAR CE. |
| 2508 | * This is used in cases where each CE has a private MSI interrupt. |
| 2509 | */ |
| 2510 | static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg) |
| 2511 | { |
| 2512 | struct ath10k *ar = arg; |
| 2513 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 2514 | int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL; |
| 2515 | |
Dan Carpenter | e574267 | 2013-06-18 10:28:46 +0300 | [diff] [blame] | 2516 | if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2517 | ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq, |
| 2518 | ce_id); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2519 | return IRQ_HANDLED; |
| 2520 | } |
| 2521 | |
| 2522 | /* |
| 2523 | * NOTE: We are able to derive ce_id from irq because we |
| 2524 | * use a one-to-one mapping for CE's 0..5. |
| 2525 | * CE's 6 & 7 do not use interrupts at all. |
| 2526 | * |
| 2527 | * This mapping must be kept in sync with the mapping |
| 2528 | * used by firmware. |
| 2529 | */ |
| 2530 | tasklet_schedule(&ar_pci->pipe_info[ce_id].intr); |
| 2531 | return IRQ_HANDLED; |
| 2532 | } |
| 2533 | |
| 2534 | static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg) |
| 2535 | { |
| 2536 | struct ath10k *ar = arg; |
| 2537 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 2538 | |
| 2539 | tasklet_schedule(&ar_pci->msi_fw_err); |
| 2540 | return IRQ_HANDLED; |
| 2541 | } |
| 2542 | |
| 2543 | /* |
| 2544 | * Top-level interrupt handler for all PCI interrupts from a Target. |
| 2545 | * When a block of MSI interrupts is allocated, this top-level handler |
| 2546 | * is not used; instead, we directly call the correct sub-handler. |
| 2547 | */ |
| 2548 | static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg) |
| 2549 | { |
| 2550 | struct ath10k *ar = arg; |
| 2551 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Anilkumar Kolli | 1aaf8ef | 2015-10-16 15:54:51 +0300 | [diff] [blame] | 2552 | int ret; |
| 2553 | |
| 2554 | if (ar_pci->pci_ps == 0) { |
| 2555 | ret = ath10k_pci_force_wake(ar); |
| 2556 | if (ret) { |
| 2557 | ath10k_warn(ar, "failed to wake device up on irq: %d\n", |
| 2558 | ret); |
| 2559 | return IRQ_NONE; |
| 2560 | } |
| 2561 | } |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2562 | |
| 2563 | if (ar_pci->num_msi_intrs == 0) { |
Michal Kazior | e539887 | 2013-11-25 14:06:20 +0100 | [diff] [blame] | 2564 | if (!ath10k_pci_irq_pending(ar)) |
| 2565 | return IRQ_NONE; |
| 2566 | |
Michal Kazior | 2685218 | 2013-11-25 14:06:25 +0100 | [diff] [blame] | 2567 | ath10k_pci_disable_and_clear_legacy_irq(ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2568 | } |
| 2569 | |
| 2570 | tasklet_schedule(&ar_pci->intr_tq); |
| 2571 | |
| 2572 | return IRQ_HANDLED; |
| 2573 | } |
| 2574 | |
| 2575 | static void ath10k_pci_tasklet(unsigned long data) |
| 2576 | { |
| 2577 | struct ath10k *ar = (struct ath10k *)data; |
| 2578 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 2579 | |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 2580 | if (ath10k_pci_has_fw_crashed(ar)) { |
Michal Kazior | 6f3b7ff | 2015-01-24 12:14:52 +0200 | [diff] [blame] | 2581 | ath10k_pci_irq_disable(ar); |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 2582 | ath10k_pci_fw_crashed_clear(ar); |
| 2583 | ath10k_pci_fw_crashed_dump(ar); |
| 2584 | return; |
| 2585 | } |
| 2586 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2587 | ath10k_ce_per_engine_service_any(ar); |
| 2588 | |
Michal Kazior | 2685218 | 2013-11-25 14:06:25 +0100 | [diff] [blame] | 2589 | /* Re-enable legacy irq that was disabled in the irq handler */ |
| 2590 | if (ar_pci->num_msi_intrs == 0) |
| 2591 | ath10k_pci_enable_legacy_irq(ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2592 | } |
| 2593 | |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2594 | static int ath10k_pci_request_irq_msix(struct ath10k *ar) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2595 | { |
| 2596 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2597 | int ret, i; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2598 | |
| 2599 | ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, |
| 2600 | ath10k_pci_msi_fw_handler, |
| 2601 | IRQF_SHARED, "ath10k_pci", ar); |
Michal Kazior | 591ecdb | 2013-07-31 10:55:15 +0200 | [diff] [blame] | 2602 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2603 | ath10k_warn(ar, "failed to request MSI-X fw irq %d: %d\n", |
Michal Kazior | 591ecdb | 2013-07-31 10:55:15 +0200 | [diff] [blame] | 2604 | ar_pci->pdev->irq + MSI_ASSIGN_FW, ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2605 | return ret; |
Michal Kazior | 591ecdb | 2013-07-31 10:55:15 +0200 | [diff] [blame] | 2606 | } |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2607 | |
| 2608 | for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) { |
| 2609 | ret = request_irq(ar_pci->pdev->irq + i, |
| 2610 | ath10k_pci_per_engine_handler, |
| 2611 | IRQF_SHARED, "ath10k_pci", ar); |
| 2612 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2613 | ath10k_warn(ar, "failed to request MSI-X ce irq %d: %d\n", |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2614 | ar_pci->pdev->irq + i, ret); |
| 2615 | |
Michal Kazior | 87b1423 | 2013-06-26 08:50:50 +0200 | [diff] [blame] | 2616 | for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--) |
| 2617 | free_irq(ar_pci->pdev->irq + i, ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2618 | |
Michal Kazior | 87b1423 | 2013-06-26 08:50:50 +0200 | [diff] [blame] | 2619 | free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2620 | return ret; |
| 2621 | } |
| 2622 | } |
| 2623 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2624 | return 0; |
| 2625 | } |
| 2626 | |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2627 | static int ath10k_pci_request_irq_msi(struct ath10k *ar) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2628 | { |
| 2629 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 2630 | int ret; |
| 2631 | |
| 2632 | ret = request_irq(ar_pci->pdev->irq, |
| 2633 | ath10k_pci_interrupt_handler, |
| 2634 | IRQF_SHARED, "ath10k_pci", ar); |
Kalle Valo | f378274 | 2013-10-17 11:36:15 +0300 | [diff] [blame] | 2635 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2636 | ath10k_warn(ar, "failed to request MSI irq %d: %d\n", |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2637 | ar_pci->pdev->irq, ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2638 | return ret; |
Kalle Valo | f378274 | 2013-10-17 11:36:15 +0300 | [diff] [blame] | 2639 | } |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2640 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2641 | return 0; |
| 2642 | } |
| 2643 | |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2644 | static int ath10k_pci_request_irq_legacy(struct ath10k *ar) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2645 | { |
| 2646 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2647 | int ret; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2648 | |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2649 | ret = request_irq(ar_pci->pdev->irq, |
| 2650 | ath10k_pci_interrupt_handler, |
| 2651 | IRQF_SHARED, "ath10k_pci", ar); |
Kalle Valo | f378274 | 2013-10-17 11:36:15 +0300 | [diff] [blame] | 2652 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2653 | ath10k_warn(ar, "failed to request legacy irq %d: %d\n", |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2654 | ar_pci->pdev->irq, ret); |
Kalle Valo | f378274 | 2013-10-17 11:36:15 +0300 | [diff] [blame] | 2655 | return ret; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2656 | } |
| 2657 | |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2658 | return 0; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2659 | } |
| 2660 | |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2661 | static int ath10k_pci_request_irq(struct ath10k *ar) |
| 2662 | { |
| 2663 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 2664 | |
| 2665 | switch (ar_pci->num_msi_intrs) { |
| 2666 | case 0: |
| 2667 | return ath10k_pci_request_irq_legacy(ar); |
| 2668 | case 1: |
| 2669 | return ath10k_pci_request_irq_msi(ar); |
Janusz Dziedzic | b8402d8 | 2015-09-17 08:17:33 +0200 | [diff] [blame] | 2670 | default: |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2671 | return ath10k_pci_request_irq_msix(ar); |
| 2672 | } |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2673 | } |
| 2674 | |
| 2675 | static void ath10k_pci_free_irq(struct ath10k *ar) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2676 | { |
| 2677 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 2678 | int i; |
| 2679 | |
| 2680 | /* There's at least one interrupt irregardless whether its legacy INTR |
| 2681 | * or MSI or MSI-X */ |
| 2682 | for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++) |
| 2683 | free_irq(ar_pci->pdev->irq + i, ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2684 | } |
| 2685 | |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2686 | static void ath10k_pci_init_irq_tasklets(struct ath10k *ar) |
| 2687 | { |
| 2688 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 2689 | int i; |
| 2690 | |
| 2691 | tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar); |
| 2692 | tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet, |
| 2693 | (unsigned long)ar); |
| 2694 | |
| 2695 | for (i = 0; i < CE_COUNT; i++) { |
| 2696 | ar_pci->pipe_info[i].ar_pci = ar_pci; |
| 2697 | tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet, |
| 2698 | (unsigned long)&ar_pci->pipe_info[i]); |
| 2699 | } |
| 2700 | } |
| 2701 | |
| 2702 | static int ath10k_pci_init_irq(struct ath10k *ar) |
| 2703 | { |
| 2704 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 2705 | int ret; |
| 2706 | |
| 2707 | ath10k_pci_init_irq_tasklets(ar); |
| 2708 | |
Michal Kazior | 403d627 | 2014-08-22 14:23:31 +0200 | [diff] [blame] | 2709 | if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO) |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2710 | ath10k_info(ar, "limiting irq mode to: %d\n", |
| 2711 | ath10k_pci_irq_mode); |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2712 | |
| 2713 | /* Try MSI-X */ |
Michal Kazior | 0edf257 | 2014-08-07 11:03:29 +0200 | [diff] [blame] | 2714 | if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO) { |
Janusz Dziedzic | b8402d8 | 2015-09-17 08:17:33 +0200 | [diff] [blame] | 2715 | ar_pci->num_msi_intrs = MSI_ASSIGN_CE_MAX + 1; |
Alexander Gordeev | 5ad6867 | 2014-02-13 17:50:02 +0200 | [diff] [blame] | 2716 | ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs, |
Kalle Valo | 5b07e07 | 2014-09-14 12:50:06 +0300 | [diff] [blame] | 2717 | ar_pci->num_msi_intrs); |
Alexander Gordeev | 5ad6867 | 2014-02-13 17:50:02 +0200 | [diff] [blame] | 2718 | if (ret > 0) |
Michal Kazior | cfe9c45 | 2013-11-25 14:06:27 +0100 | [diff] [blame] | 2719 | return 0; |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2720 | |
Michal Kazior | cfe9c45 | 2013-11-25 14:06:27 +0100 | [diff] [blame] | 2721 | /* fall-through */ |
| 2722 | } |
| 2723 | |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2724 | /* Try MSI */ |
Michal Kazior | cfe9c45 | 2013-11-25 14:06:27 +0100 | [diff] [blame] | 2725 | if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) { |
| 2726 | ar_pci->num_msi_intrs = 1; |
| 2727 | ret = pci_enable_msi(ar_pci->pdev); |
| 2728 | if (ret == 0) |
| 2729 | return 0; |
| 2730 | |
| 2731 | /* fall-through */ |
| 2732 | } |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2733 | |
| 2734 | /* Try legacy irq |
| 2735 | * |
| 2736 | * A potential race occurs here: The CORE_BASE write |
| 2737 | * depends on target correctly decoding AXI address but |
| 2738 | * host won't know when target writes BAR to CORE_CTRL. |
| 2739 | * This write might get lost if target has NOT written BAR. |
| 2740 | * For now, fix the race by repeating the write in below |
| 2741 | * synchronization checking. */ |
| 2742 | ar_pci->num_msi_intrs = 0; |
| 2743 | |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2744 | ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, |
| 2745 | PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2746 | |
| 2747 | return 0; |
| 2748 | } |
| 2749 | |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 2750 | static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar) |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2751 | { |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2752 | ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, |
| 2753 | 0); |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2754 | } |
| 2755 | |
| 2756 | static int ath10k_pci_deinit_irq(struct ath10k *ar) |
| 2757 | { |
| 2758 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 2759 | |
| 2760 | switch (ar_pci->num_msi_intrs) { |
| 2761 | case 0: |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 2762 | ath10k_pci_deinit_irq_legacy(ar); |
Janusz Dziedzic | b8402d8 | 2015-09-17 08:17:33 +0200 | [diff] [blame] | 2763 | break; |
Alexander Gordeev | bb8b621 | 2014-02-13 17:50:01 +0200 | [diff] [blame] | 2764 | default: |
| 2765 | pci_disable_msi(ar_pci->pdev); |
Janusz Dziedzic | b8402d8 | 2015-09-17 08:17:33 +0200 | [diff] [blame] | 2766 | break; |
Michal Kazior | fc15ca1 | 2013-11-25 14:06:21 +0100 | [diff] [blame] | 2767 | } |
| 2768 | |
Janusz Dziedzic | b8402d8 | 2015-09-17 08:17:33 +0200 | [diff] [blame] | 2769 | return 0; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2770 | } |
| 2771 | |
Michal Kazior | d7fb47f | 2013-11-08 08:01:26 +0100 | [diff] [blame] | 2772 | static int ath10k_pci_wait_for_target_init(struct ath10k *ar) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2773 | { |
| 2774 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Kalle Valo | 0399eca | 2014-03-28 09:32:21 +0200 | [diff] [blame] | 2775 | unsigned long timeout; |
Kalle Valo | 0399eca | 2014-03-28 09:32:21 +0200 | [diff] [blame] | 2776 | u32 val; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2777 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2778 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n"); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2779 | |
Kalle Valo | 0399eca | 2014-03-28 09:32:21 +0200 | [diff] [blame] | 2780 | timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT); |
| 2781 | |
| 2782 | do { |
| 2783 | val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); |
| 2784 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2785 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n", |
| 2786 | val); |
Kalle Valo | 50f87a6 | 2014-03-28 09:32:52 +0200 | [diff] [blame] | 2787 | |
Kalle Valo | 0399eca | 2014-03-28 09:32:21 +0200 | [diff] [blame] | 2788 | /* target should never return this */ |
| 2789 | if (val == 0xffffffff) |
| 2790 | continue; |
| 2791 | |
Michal Kazior | 7710cd2 | 2014-04-23 19:30:04 +0300 | [diff] [blame] | 2792 | /* the device has crashed so don't bother trying anymore */ |
| 2793 | if (val & FW_IND_EVENT_PENDING) |
| 2794 | break; |
| 2795 | |
Kalle Valo | 0399eca | 2014-03-28 09:32:21 +0200 | [diff] [blame] | 2796 | if (val & FW_IND_INITIALIZED) |
| 2797 | break; |
| 2798 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2799 | if (ar_pci->num_msi_intrs == 0) |
| 2800 | /* Fix potential race by repeating CORE_BASE writes */ |
Michal Kazior | a428249 | 2014-10-20 14:14:37 +0200 | [diff] [blame] | 2801 | ath10k_pci_enable_legacy_irq(ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2802 | |
Kalle Valo | 0399eca | 2014-03-28 09:32:21 +0200 | [diff] [blame] | 2803 | mdelay(10); |
| 2804 | } while (time_before(jiffies, timeout)); |
| 2805 | |
Michal Kazior | a428249 | 2014-10-20 14:14:37 +0200 | [diff] [blame] | 2806 | ath10k_pci_disable_and_clear_legacy_irq(ar); |
Michal Kazior | 7c0f0e3 | 2014-10-20 14:14:38 +0200 | [diff] [blame] | 2807 | ath10k_pci_irq_msi_fw_mask(ar); |
Michal Kazior | a428249 | 2014-10-20 14:14:37 +0200 | [diff] [blame] | 2808 | |
Michal Kazior | 6a4f6e1 | 2014-04-23 19:30:03 +0300 | [diff] [blame] | 2809 | if (val == 0xffffffff) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2810 | ath10k_err(ar, "failed to read device register, device is gone\n"); |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 2811 | return -EIO; |
Michal Kazior | 6a4f6e1 | 2014-04-23 19:30:03 +0300 | [diff] [blame] | 2812 | } |
| 2813 | |
Michal Kazior | 7710cd2 | 2014-04-23 19:30:04 +0300 | [diff] [blame] | 2814 | if (val & FW_IND_EVENT_PENDING) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2815 | ath10k_warn(ar, "device has crashed during init\n"); |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 2816 | return -ECOMM; |
Michal Kazior | 7710cd2 | 2014-04-23 19:30:04 +0300 | [diff] [blame] | 2817 | } |
| 2818 | |
Michal Kazior | 6a4f6e1 | 2014-04-23 19:30:03 +0300 | [diff] [blame] | 2819 | if (!(val & FW_IND_INITIALIZED)) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2820 | ath10k_err(ar, "failed to receive initialized event from target: %08x\n", |
Kalle Valo | 0399eca | 2014-03-28 09:32:21 +0200 | [diff] [blame] | 2821 | val); |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 2822 | return -ETIMEDOUT; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2823 | } |
| 2824 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2825 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n"); |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 2826 | return 0; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2827 | } |
| 2828 | |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 2829 | static int ath10k_pci_cold_reset(struct ath10k *ar) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2830 | { |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2831 | u32 val; |
| 2832 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2833 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n"); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2834 | |
Ben Greear | f51dbe7 | 2014-09-29 14:41:46 +0300 | [diff] [blame] | 2835 | spin_lock_bh(&ar->data_lock); |
| 2836 | |
| 2837 | ar->stats.fw_cold_reset_counter++; |
| 2838 | |
| 2839 | spin_unlock_bh(&ar->data_lock); |
| 2840 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2841 | /* Put Target, including PCIe, into RESET. */ |
Kalle Valo | e479ed4 | 2013-09-01 10:01:53 +0300 | [diff] [blame] | 2842 | val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2843 | val |= 1; |
Kalle Valo | e479ed4 | 2013-09-01 10:01:53 +0300 | [diff] [blame] | 2844 | ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2845 | |
Vasanthakumar Thiagarajan | acd1958 | 2015-07-10 14:31:20 +0530 | [diff] [blame] | 2846 | /* After writing into SOC_GLOBAL_RESET to put device into |
| 2847 | * reset and pulling out of reset pcie may not be stable |
| 2848 | * for any immediate pcie register access and cause bus error, |
| 2849 | * add delay before any pcie access request to fix this issue. |
| 2850 | */ |
| 2851 | msleep(20); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2852 | |
| 2853 | /* Pull Target, including PCIe, out of RESET. */ |
| 2854 | val &= ~1; |
Kalle Valo | e479ed4 | 2013-09-01 10:01:53 +0300 | [diff] [blame] | 2855 | ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2856 | |
Vasanthakumar Thiagarajan | acd1958 | 2015-07-10 14:31:20 +0530 | [diff] [blame] | 2857 | msleep(20); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2858 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2859 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n"); |
Kalle Valo | 50f87a6 | 2014-03-28 09:32:52 +0200 | [diff] [blame] | 2860 | |
Michal Kazior | 5b2589f | 2013-11-08 08:01:30 +0100 | [diff] [blame] | 2861 | return 0; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2862 | } |
| 2863 | |
Michal Kazior | 2986e3e | 2014-08-07 11:03:30 +0200 | [diff] [blame] | 2864 | static int ath10k_pci_claim(struct ath10k *ar) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2865 | { |
Michal Kazior | 2986e3e | 2014-08-07 11:03:30 +0200 | [diff] [blame] | 2866 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 2867 | struct pci_dev *pdev = ar_pci->pdev; |
Michal Kazior | 2986e3e | 2014-08-07 11:03:30 +0200 | [diff] [blame] | 2868 | int ret; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2869 | |
| 2870 | pci_set_drvdata(pdev, ar); |
| 2871 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2872 | ret = pci_enable_device(pdev); |
| 2873 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2874 | ath10k_err(ar, "failed to enable pci device: %d\n", ret); |
Michal Kazior | 2986e3e | 2014-08-07 11:03:30 +0200 | [diff] [blame] | 2875 | return ret; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2876 | } |
| 2877 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2878 | ret = pci_request_region(pdev, BAR_NUM, "ath"); |
| 2879 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2880 | ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM, |
Michal Kazior | 2986e3e | 2014-08-07 11:03:30 +0200 | [diff] [blame] | 2881 | ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2882 | goto err_device; |
| 2883 | } |
| 2884 | |
Michal Kazior | 2986e3e | 2014-08-07 11:03:30 +0200 | [diff] [blame] | 2885 | /* Target expects 32 bit DMA. Enforce it. */ |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2886 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
| 2887 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2888 | ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2889 | goto err_region; |
| 2890 | } |
| 2891 | |
| 2892 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
| 2893 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2894 | ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n", |
Michal Kazior | 2986e3e | 2014-08-07 11:03:30 +0200 | [diff] [blame] | 2895 | ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2896 | goto err_region; |
| 2897 | } |
| 2898 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2899 | pci_set_master(pdev); |
| 2900 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2901 | /* Arrange for access to Target SoC registers. */ |
Michal Kazior | aeae5b4 | 2015-06-15 14:46:42 +0300 | [diff] [blame] | 2902 | ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM); |
Michal Kazior | 2986e3e | 2014-08-07 11:03:30 +0200 | [diff] [blame] | 2903 | ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0); |
| 2904 | if (!ar_pci->mem) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2905 | ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2906 | ret = -EIO; |
| 2907 | goto err_master; |
| 2908 | } |
| 2909 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2910 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem); |
Michal Kazior | 2986e3e | 2014-08-07 11:03:30 +0200 | [diff] [blame] | 2911 | return 0; |
| 2912 | |
| 2913 | err_master: |
| 2914 | pci_clear_master(pdev); |
| 2915 | |
| 2916 | err_region: |
| 2917 | pci_release_region(pdev, BAR_NUM); |
| 2918 | |
| 2919 | err_device: |
| 2920 | pci_disable_device(pdev); |
| 2921 | |
| 2922 | return ret; |
| 2923 | } |
| 2924 | |
| 2925 | static void ath10k_pci_release(struct ath10k *ar) |
| 2926 | { |
| 2927 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 2928 | struct pci_dev *pdev = ar_pci->pdev; |
| 2929 | |
| 2930 | pci_iounmap(pdev, ar_pci->mem); |
| 2931 | pci_release_region(pdev, BAR_NUM); |
| 2932 | pci_clear_master(pdev); |
| 2933 | pci_disable_device(pdev); |
| 2934 | } |
| 2935 | |
Michal Kazior | 7505f7c | 2014-12-02 10:55:54 +0200 | [diff] [blame] | 2936 | static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id) |
| 2937 | { |
| 2938 | const struct ath10k_pci_supp_chip *supp_chip; |
| 2939 | int i; |
| 2940 | u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV); |
| 2941 | |
| 2942 | for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) { |
| 2943 | supp_chip = &ath10k_pci_supp_chips[i]; |
| 2944 | |
| 2945 | if (supp_chip->dev_id == dev_id && |
| 2946 | supp_chip->rev_id == rev_id) |
| 2947 | return true; |
| 2948 | } |
| 2949 | |
| 2950 | return false; |
| 2951 | } |
| 2952 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2953 | static int ath10k_pci_probe(struct pci_dev *pdev, |
| 2954 | const struct pci_device_id *pci_dev) |
| 2955 | { |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2956 | int ret = 0; |
| 2957 | struct ath10k *ar; |
| 2958 | struct ath10k_pci *ar_pci; |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 2959 | enum ath10k_hw_rev hw_rev; |
Michal Kazior | 2986e3e | 2014-08-07 11:03:30 +0200 | [diff] [blame] | 2960 | u32 chip_id; |
Anilkumar Kolli | 1aaf8ef | 2015-10-16 15:54:51 +0300 | [diff] [blame] | 2961 | bool pci_ps; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2962 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 2963 | switch (pci_dev->device) { |
| 2964 | case QCA988X_2_0_DEVICE_ID: |
| 2965 | hw_rev = ATH10K_HW_QCA988X; |
Anilkumar Kolli | 1aaf8ef | 2015-10-16 15:54:51 +0300 | [diff] [blame] | 2966 | pci_ps = false; |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 2967 | break; |
Michal Kazior | 36582e5 | 2015-08-13 14:32:26 +0200 | [diff] [blame] | 2968 | case QCA6164_2_1_DEVICE_ID: |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 2969 | case QCA6174_2_1_DEVICE_ID: |
| 2970 | hw_rev = ATH10K_HW_QCA6174; |
Anilkumar Kolli | 1aaf8ef | 2015-10-16 15:54:51 +0300 | [diff] [blame] | 2971 | pci_ps = true; |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 2972 | break; |
Vasanthakumar Thiagarajan | 8bd4702 | 2015-06-18 12:31:03 +0530 | [diff] [blame] | 2973 | case QCA99X0_2_0_DEVICE_ID: |
| 2974 | hw_rev = ATH10K_HW_QCA99X0; |
Anilkumar Kolli | 1aaf8ef | 2015-10-16 15:54:51 +0300 | [diff] [blame] | 2975 | pci_ps = false; |
Vasanthakumar Thiagarajan | 8bd4702 | 2015-06-18 12:31:03 +0530 | [diff] [blame] | 2976 | break; |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 2977 | case QCA9377_1_0_DEVICE_ID: |
| 2978 | hw_rev = ATH10K_HW_QCA9377; |
| 2979 | pci_ps = true; |
| 2980 | break; |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame] | 2981 | default: |
| 2982 | WARN_ON(1); |
| 2983 | return -ENOTSUPP; |
| 2984 | } |
| 2985 | |
| 2986 | ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI, |
| 2987 | hw_rev, &ath10k_pci_hif_ops); |
Michal Kazior | e7b5419 | 2014-08-07 11:03:27 +0200 | [diff] [blame] | 2988 | if (!ar) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2989 | dev_err(&pdev->dev, "failed to allocate core\n"); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2990 | return -ENOMEM; |
Michal Kazior | e7b5419 | 2014-08-07 11:03:27 +0200 | [diff] [blame] | 2991 | } |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2992 | |
Manikanta Pubbisetty | 0a51b34 | 2015-10-09 11:55:58 +0300 | [diff] [blame] | 2993 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", |
| 2994 | pdev->vendor, pdev->device, |
| 2995 | pdev->subsystem_vendor, pdev->subsystem_device); |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 2996 | |
Michal Kazior | e7b5419 | 2014-08-07 11:03:27 +0200 | [diff] [blame] | 2997 | ar_pci = ath10k_pci_priv(ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 2998 | ar_pci->pdev = pdev; |
| 2999 | ar_pci->dev = &pdev->dev; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3000 | ar_pci->ar = ar; |
Michal Kazior | 36582e5 | 2015-08-13 14:32:26 +0200 | [diff] [blame] | 3001 | ar->dev_id = pci_dev->device; |
Anilkumar Kolli | 1aaf8ef | 2015-10-16 15:54:51 +0300 | [diff] [blame] | 3002 | ar_pci->pci_ps = pci_ps; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3003 | |
Manikanta Pubbisetty | 0a51b34 | 2015-10-09 11:55:58 +0300 | [diff] [blame] | 3004 | ar->id.vendor = pdev->vendor; |
| 3005 | ar->id.device = pdev->device; |
| 3006 | ar->id.subsystem_vendor = pdev->subsystem_vendor; |
| 3007 | ar->id.subsystem_device = pdev->subsystem_device; |
Michal Kazior | de57e2c | 2015-04-17 09:19:17 +0000 | [diff] [blame] | 3008 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3009 | spin_lock_init(&ar_pci->ce_lock); |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 3010 | spin_lock_init(&ar_pci->ps_lock); |
| 3011 | |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 3012 | setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, |
| 3013 | (unsigned long)ar); |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 3014 | setup_timer(&ar_pci->ps_timer, ath10k_pci_ps_timer, |
| 3015 | (unsigned long)ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3016 | |
Michal Kazior | 2986e3e | 2014-08-07 11:03:30 +0200 | [diff] [blame] | 3017 | ret = ath10k_pci_claim(ar); |
Kalle Valo | e01ae68 | 2013-09-01 11:22:14 +0300 | [diff] [blame] | 3018 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 3019 | ath10k_err(ar, "failed to claim device: %d\n", ret); |
Michal Kazior | e7b5419 | 2014-08-07 11:03:27 +0200 | [diff] [blame] | 3020 | goto err_core_destroy; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3021 | } |
| 3022 | |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 3023 | ret = ath10k_pci_alloc_pipes(ar); |
Michal Kazior | 25d0dbc | 2014-03-28 10:02:38 +0200 | [diff] [blame] | 3024 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 3025 | ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", |
| 3026 | ret); |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 3027 | goto err_sleep; |
Michal Kazior | 25d0dbc | 2014-03-28 10:02:38 +0200 | [diff] [blame] | 3028 | } |
| 3029 | |
Michal Kazior | 403d627 | 2014-08-22 14:23:31 +0200 | [diff] [blame] | 3030 | ath10k_pci_ce_deinit(ar); |
Michal Kazior | 7c0f0e3 | 2014-10-20 14:14:38 +0200 | [diff] [blame] | 3031 | ath10k_pci_irq_disable(ar); |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 3032 | |
Anilkumar Kolli | 1aaf8ef | 2015-10-16 15:54:51 +0300 | [diff] [blame] | 3033 | if (ar_pci->pci_ps == 0) { |
| 3034 | ret = ath10k_pci_force_wake(ar); |
| 3035 | if (ret) { |
| 3036 | ath10k_warn(ar, "failed to wake up device : %d\n", ret); |
| 3037 | goto err_free_pipes; |
| 3038 | } |
| 3039 | } |
| 3040 | |
Michal Kazior | 403d627 | 2014-08-22 14:23:31 +0200 | [diff] [blame] | 3041 | ret = ath10k_pci_init_irq(ar); |
| 3042 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 3043 | ath10k_err(ar, "failed to init irqs: %d\n", ret); |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 3044 | goto err_free_pipes; |
Michal Kazior | 403d627 | 2014-08-22 14:23:31 +0200 | [diff] [blame] | 3045 | } |
| 3046 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 3047 | ath10k_info(ar, "pci irq %s interrupts %d irq_mode %d reset_mode %d\n", |
Michal Kazior | 403d627 | 2014-08-22 14:23:31 +0200 | [diff] [blame] | 3048 | ath10k_pci_get_irq_method(ar), ar_pci->num_msi_intrs, |
| 3049 | ath10k_pci_irq_mode, ath10k_pci_reset_mode); |
| 3050 | |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 3051 | ret = ath10k_pci_request_irq(ar); |
Michal Kazior | 403d627 | 2014-08-22 14:23:31 +0200 | [diff] [blame] | 3052 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 3053 | ath10k_warn(ar, "failed to request irqs: %d\n", ret); |
Michal Kazior | 403d627 | 2014-08-22 14:23:31 +0200 | [diff] [blame] | 3054 | goto err_deinit_irq; |
| 3055 | } |
| 3056 | |
Michal Kazior | 1a7fecb | 2015-01-24 12:14:48 +0200 | [diff] [blame] | 3057 | ret = ath10k_pci_chip_reset(ar); |
| 3058 | if (ret) { |
| 3059 | ath10k_err(ar, "failed to reset chip: %d\n", ret); |
| 3060 | goto err_free_irq; |
| 3061 | } |
| 3062 | |
| 3063 | chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); |
| 3064 | if (chip_id == 0xffffffff) { |
| 3065 | ath10k_err(ar, "failed to get chip id\n"); |
| 3066 | goto err_free_irq; |
| 3067 | } |
| 3068 | |
| 3069 | if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) { |
| 3070 | ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", |
| 3071 | pdev->device, chip_id); |
Michal Kazior | d9585a9 | 2015-04-10 13:01:27 +0000 | [diff] [blame] | 3072 | goto err_free_irq; |
Michal Kazior | 1a7fecb | 2015-01-24 12:14:48 +0200 | [diff] [blame] | 3073 | } |
| 3074 | |
Kalle Valo | e01ae68 | 2013-09-01 11:22:14 +0300 | [diff] [blame] | 3075 | ret = ath10k_core_register(ar, chip_id); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3076 | if (ret) { |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 3077 | ath10k_err(ar, "failed to register driver core: %d\n", ret); |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 3078 | goto err_free_irq; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3079 | } |
| 3080 | |
| 3081 | return 0; |
| 3082 | |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 3083 | err_free_irq: |
| 3084 | ath10k_pci_free_irq(ar); |
Michal Kazior | 2139627 | 2014-08-28 10:24:40 +0200 | [diff] [blame] | 3085 | ath10k_pci_kill_tasklet(ar); |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 3086 | |
Michal Kazior | 403d627 | 2014-08-22 14:23:31 +0200 | [diff] [blame] | 3087 | err_deinit_irq: |
| 3088 | ath10k_pci_deinit_irq(ar); |
| 3089 | |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 3090 | err_free_pipes: |
| 3091 | ath10k_pci_free_pipes(ar); |
Michal Kazior | 2986e3e | 2014-08-07 11:03:30 +0200 | [diff] [blame] | 3092 | |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 3093 | err_sleep: |
Michal Kazior | 0bcbbe6 | 2015-05-29 07:35:24 +0200 | [diff] [blame] | 3094 | ath10k_pci_sleep_sync(ar); |
Michal Kazior | 2986e3e | 2014-08-07 11:03:30 +0200 | [diff] [blame] | 3095 | ath10k_pci_release(ar); |
| 3096 | |
Michal Kazior | e7b5419 | 2014-08-07 11:03:27 +0200 | [diff] [blame] | 3097 | err_core_destroy: |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3098 | ath10k_core_destroy(ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3099 | |
| 3100 | return ret; |
| 3101 | } |
| 3102 | |
| 3103 | static void ath10k_pci_remove(struct pci_dev *pdev) |
| 3104 | { |
| 3105 | struct ath10k *ar = pci_get_drvdata(pdev); |
| 3106 | struct ath10k_pci *ar_pci; |
| 3107 | |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 3108 | ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n"); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3109 | |
| 3110 | if (!ar) |
| 3111 | return; |
| 3112 | |
| 3113 | ar_pci = ath10k_pci_priv(ar); |
| 3114 | |
| 3115 | if (!ar_pci) |
| 3116 | return; |
| 3117 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3118 | ath10k_core_unregister(ar); |
Michal Kazior | 5c771e7 | 2014-08-22 14:23:34 +0200 | [diff] [blame] | 3119 | ath10k_pci_free_irq(ar); |
Michal Kazior | 2139627 | 2014-08-28 10:24:40 +0200 | [diff] [blame] | 3120 | ath10k_pci_kill_tasklet(ar); |
Michal Kazior | 403d627 | 2014-08-22 14:23:31 +0200 | [diff] [blame] | 3121 | ath10k_pci_deinit_irq(ar); |
| 3122 | ath10k_pci_ce_deinit(ar); |
Michal Kazior | 84cbf3a | 2014-10-20 14:14:39 +0200 | [diff] [blame] | 3123 | ath10k_pci_free_pipes(ar); |
Michal Kazior | 77258d4 | 2015-05-18 09:38:18 +0000 | [diff] [blame] | 3124 | ath10k_pci_sleep_sync(ar); |
Michal Kazior | 2986e3e | 2014-08-07 11:03:30 +0200 | [diff] [blame] | 3125 | ath10k_pci_release(ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3126 | ath10k_core_destroy(ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3127 | } |
| 3128 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3129 | MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table); |
| 3130 | |
| 3131 | static struct pci_driver ath10k_pci_driver = { |
| 3132 | .name = "ath10k_pci", |
| 3133 | .id_table = ath10k_pci_id_table, |
| 3134 | .probe = ath10k_pci_probe, |
| 3135 | .remove = ath10k_pci_remove, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3136 | }; |
| 3137 | |
| 3138 | static int __init ath10k_pci_init(void) |
| 3139 | { |
| 3140 | int ret; |
| 3141 | |
| 3142 | ret = pci_register_driver(&ath10k_pci_driver); |
| 3143 | if (ret) |
Michal Kazior | 7aa7a72 | 2014-08-25 12:09:38 +0200 | [diff] [blame] | 3144 | printk(KERN_ERR "failed to register ath10k pci driver: %d\n", |
| 3145 | ret); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3146 | |
| 3147 | return ret; |
| 3148 | } |
| 3149 | module_init(ath10k_pci_init); |
| 3150 | |
| 3151 | static void __exit ath10k_pci_exit(void) |
| 3152 | { |
| 3153 | pci_unregister_driver(&ath10k_pci_driver); |
| 3154 | } |
| 3155 | |
| 3156 | module_exit(ath10k_pci_exit); |
| 3157 | |
| 3158 | MODULE_AUTHOR("Qualcomm Atheros"); |
| 3159 | MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices"); |
| 3160 | MODULE_LICENSE("Dual BSD/GPL"); |
Bartosz Markowski | 5c427f5 | 2015-02-18 13:16:37 +0100 | [diff] [blame] | 3161 | |
| 3162 | /* QCA988x 2.0 firmware files */ |
Bartosz Markowski | 8026cae | 2014-10-06 14:16:41 +0200 | [diff] [blame] | 3163 | MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE); |
| 3164 | MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE); |
| 3165 | MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE); |
Bartosz Markowski | 5c427f5 | 2015-02-18 13:16:37 +0100 | [diff] [blame] | 3166 | MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE); |
Kalle Valo | 53513c3 | 2015-03-25 13:12:42 +0200 | [diff] [blame] | 3167 | MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 3168 | MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE); |
Manikanta Pubbisetty | 0a51b34 | 2015-10-09 11:55:58 +0300 | [diff] [blame] | 3169 | MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); |
Bartosz Markowski | 5c427f5 | 2015-02-18 13:16:37 +0100 | [diff] [blame] | 3170 | |
| 3171 | /* QCA6174 2.1 firmware files */ |
| 3172 | MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE); |
Michal Kazior | e451c1d | 2015-05-26 13:09:22 +0200 | [diff] [blame] | 3173 | MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE); |
Bartosz Markowski | 5c427f5 | 2015-02-18 13:16:37 +0100 | [diff] [blame] | 3174 | MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE); |
Manikanta Pubbisetty | 0a51b34 | 2015-10-09 11:55:58 +0300 | [diff] [blame] | 3175 | MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE); |
Bartosz Markowski | 5c427f5 | 2015-02-18 13:16:37 +0100 | [diff] [blame] | 3176 | |
| 3177 | /* QCA6174 3.1 firmware files */ |
| 3178 | MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE); |
Michal Kazior | e451c1d | 2015-05-26 13:09:22 +0200 | [diff] [blame] | 3179 | MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE); |
Bartosz Markowski | 5c427f5 | 2015-02-18 13:16:37 +0100 | [diff] [blame] | 3180 | MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE); |
Manikanta Pubbisetty | 0a51b34 | 2015-10-09 11:55:58 +0300 | [diff] [blame] | 3181 | MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); |
Bartosz Markowski | a226b51 | 2015-10-28 15:09:53 +0100 | [diff] [blame] | 3182 | |
| 3183 | /* QCA9377 1.0 firmware files */ |
| 3184 | MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); |
| 3185 | MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE); |