arch/arm/boot/dts/r8a7790.dtsi

/*
 * Device Tree Source for the r8a7790 SoC
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r8a7790";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			clock-frequency = <1300000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
			clock-frequency = <1300000000>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <2>;
			clock-frequency = <1300000000>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <3>;
			clock-frequency = <1300000000>;
		};

		cpu4: cpu@4 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x100>;
			clock-frequency = <780000000>;
		};

		cpu5: cpu@5 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x101>;
			clock-frequency = <780000000>;
		};

		cpu6: cpu@6 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x102>;
			clock-frequency = <780000000>;
		};

		cpu7: cpu@7 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x103>;
			clock-frequency = <780000000>;
		};
	};

	gic: interrupt-controller@f1001000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0xf1001000 0 0x1000>,
			<0 0xf1002000 0 0x1000>,
			<0 0xf1004000 0 0x2000>,
			<0 0xf1006000 0 0x2000>;
		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	gpio0: gpio@ffc40000 {
		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
		reg = <0 0xffc40000 0 0x2c>;
		interrupt-parent = <&gic>;
		interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio1: gpio@ffc41000 {
		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
		reg = <0 0xffc41000 0 0x2c>;
		interrupt-parent = <&gic>;
		interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio2: gpio@ffc42000 {
		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
		reg = <0 0xffc42000 0 0x2c>;
		interrupt-parent = <&gic>;
		interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio3: gpio@ffc43000 {
		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
		reg = <0 0xffc43000 0 0x2c>;
		interrupt-parent = <&gic>;
		interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio4: gpio@ffc44000 {
		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
		reg = <0 0xffc44000 0 0x2c>;
		interrupt-parent = <&gic>;
		interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio5: gpio@ffc45000 {
		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
		reg = <0 0xffc45000 0 0x2c>;
		interrupt-parent = <&gic>;
		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 160 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	thermal@e61f0000 {
		compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
		interrupt-parent = <&gic>;
		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	irqc0: interrupt-controller@e61c0000 {
		compatible = "renesas,irqc";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0 0xe61c0000 0 0x200>;
		interrupt-parent = <&gic>;
		interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
			     <0 1 IRQ_TYPE_LEVEL_HIGH>,
			     <0 2 IRQ_TYPE_LEVEL_HIGH>,
			     <0 3 IRQ_TYPE_LEVEL_HIGH>;
	};

	i2c0: i2c@e6508000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7790";
		reg = <0 0xe6508000 0 0x40>;
		interrupt-parent = <&gic>;
		interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	i2c1: i2c@e6518000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7790";
		reg = <0 0xe6518000 0 0x40>;
		interrupt-parent = <&gic>;
		interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	i2c2: i2c@e6530000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7790";
		reg = <0 0xe6530000 0 0x40>;
		interrupt-parent = <&gic>;
		interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	i2c3: i2c@e6540000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7790";
		reg = <0 0xe6540000 0 0x40>;
		interrupt-parent = <&gic>;
		interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	mmcif0: mmcif@ee200000 {
		compatible = "renesas,sh-mmcif";
		reg = <0 0xee200000 0 0x80>;
		interrupt-parent = <&gic>;
		interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
		reg-io-width = <4>;
		status = "disabled";
	};

	mmcif1: mmc@ee220000 {
		compatible = "renesas,sh-mmcif";
		reg = <0 0xee220000 0 0x80>;
		interrupt-parent = <&gic>;
		interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
		reg-io-width = <4>;
		status = "disabled";
	};

	pfc: pfc@e6060000 {
		compatible = "renesas,pfc-r8a7790";
		reg = <0 0xe6060000 0 0x250>;
	};

	sdhi0: sd@ee100000 {
		compatible = "renesas,sdhi-r8a7790";
		reg = <0 0xee100000 0 0x100>;
		interrupt-parent = <&gic>;
		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
		cap-sd-highspeed;
		status = "disabled";
	};

	sdhi1: sd@ee120000 {
		compatible = "renesas,sdhi-r8a7790";
		reg = <0 0xee120000 0 0x100>;
		interrupt-parent = <&gic>;
		interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
		cap-sd-highspeed;
		status = "disabled";
	};

	sdhi2: sd@ee140000 {
		compatible = "renesas,sdhi-r8a7790";
		reg = <0 0xee140000 0 0x100>;
		interrupt-parent = <&gic>;
		interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
		cap-sd-highspeed;
		status = "disabled";
	};

	sdhi3: sd@ee160000 {
		compatible = "renesas,sdhi-r8a7790";
		reg = <0 0xee160000 0 0x100>;
		interrupt-parent = <&gic>;
		interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
		cap-sd-highspeed;
		status = "disabled";
	};
};