Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1 | /* |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * KVM/MIPS: Instruction/Exception emulation |
| 7 | * |
| 8 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. |
| 9 | * Authors: Sanjay Lal <sanjayl@kymasys.com> |
| 10 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 11 | |
| 12 | #include <linux/errno.h> |
| 13 | #include <linux/err.h> |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 14 | #include <linux/ktime.h> |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 15 | #include <linux/kvm_host.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/vmalloc.h> |
| 18 | #include <linux/fs.h> |
| 19 | #include <linux/bootmem.h> |
| 20 | #include <linux/random.h> |
| 21 | #include <asm/page.h> |
| 22 | #include <asm/cacheflush.h> |
James Hogan | f4956f6 | 2015-12-16 23:49:37 +0000 | [diff] [blame] | 23 | #include <asm/cacheops.h> |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 24 | #include <asm/cpu-info.h> |
| 25 | #include <asm/mmu_context.h> |
| 26 | #include <asm/tlbflush.h> |
| 27 | #include <asm/inst.h> |
| 28 | |
| 29 | #undef CONFIG_MIPS_MT |
| 30 | #include <asm/r4kcache.h> |
| 31 | #define CONFIG_MIPS_MT |
| 32 | |
Deng-Cheng Zhu | d7d5b05 | 2014-06-26 12:11:38 -0700 | [diff] [blame] | 33 | #include "interrupt.h" |
| 34 | #include "commpage.h" |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 35 | |
| 36 | #include "trace.h" |
| 37 | |
| 38 | /* |
| 39 | * Compute the return address and do emulate branch simulation, if required. |
| 40 | * This function should be called only in branch delay slot active. |
| 41 | */ |
| 42 | unsigned long kvm_compute_return_epc(struct kvm_vcpu *vcpu, |
| 43 | unsigned long instpc) |
| 44 | { |
| 45 | unsigned int dspcontrol; |
| 46 | union mips_instruction insn; |
| 47 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 48 | long epc = instpc; |
| 49 | long nextpc = KVM_INVALID_INST; |
| 50 | |
| 51 | if (epc & 3) |
| 52 | goto unaligned; |
| 53 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 54 | /* Read the instruction */ |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 55 | insn.word = kvm_get_inst((u32 *) epc, vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 56 | |
| 57 | if (insn.word == KVM_INVALID_INST) |
| 58 | return KVM_INVALID_INST; |
| 59 | |
| 60 | switch (insn.i_format.opcode) { |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 61 | /* jr and jalr are in r_format format. */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 62 | case spec_op: |
| 63 | switch (insn.r_format.func) { |
| 64 | case jalr_op: |
| 65 | arch->gprs[insn.r_format.rd] = epc + 8; |
| 66 | /* Fall through */ |
| 67 | case jr_op: |
| 68 | nextpc = arch->gprs[insn.r_format.rs]; |
| 69 | break; |
| 70 | } |
| 71 | break; |
| 72 | |
| 73 | /* |
| 74 | * This group contains: |
| 75 | * bltz_op, bgez_op, bltzl_op, bgezl_op, |
| 76 | * bltzal_op, bgezal_op, bltzall_op, bgezall_op. |
| 77 | */ |
| 78 | case bcond_op: |
| 79 | switch (insn.i_format.rt) { |
| 80 | case bltz_op: |
| 81 | case bltzl_op: |
| 82 | if ((long)arch->gprs[insn.i_format.rs] < 0) |
| 83 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 84 | else |
| 85 | epc += 8; |
| 86 | nextpc = epc; |
| 87 | break; |
| 88 | |
| 89 | case bgez_op: |
| 90 | case bgezl_op: |
| 91 | if ((long)arch->gprs[insn.i_format.rs] >= 0) |
| 92 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 93 | else |
| 94 | epc += 8; |
| 95 | nextpc = epc; |
| 96 | break; |
| 97 | |
| 98 | case bltzal_op: |
| 99 | case bltzall_op: |
| 100 | arch->gprs[31] = epc + 8; |
| 101 | if ((long)arch->gprs[insn.i_format.rs] < 0) |
| 102 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 103 | else |
| 104 | epc += 8; |
| 105 | nextpc = epc; |
| 106 | break; |
| 107 | |
| 108 | case bgezal_op: |
| 109 | case bgezall_op: |
| 110 | arch->gprs[31] = epc + 8; |
| 111 | if ((long)arch->gprs[insn.i_format.rs] >= 0) |
| 112 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 113 | else |
| 114 | epc += 8; |
| 115 | nextpc = epc; |
| 116 | break; |
| 117 | case bposge32_op: |
| 118 | if (!cpu_has_dsp) |
| 119 | goto sigill; |
| 120 | |
| 121 | dspcontrol = rddsp(0x01); |
| 122 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 123 | if (dspcontrol >= 32) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 124 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 125 | else |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 126 | epc += 8; |
| 127 | nextpc = epc; |
| 128 | break; |
| 129 | } |
| 130 | break; |
| 131 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 132 | /* These are unconditional and in j_format. */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 133 | case jal_op: |
| 134 | arch->gprs[31] = instpc + 8; |
| 135 | case j_op: |
| 136 | epc += 4; |
| 137 | epc >>= 28; |
| 138 | epc <<= 28; |
| 139 | epc |= (insn.j_format.target << 2); |
| 140 | nextpc = epc; |
| 141 | break; |
| 142 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 143 | /* These are conditional and in i_format. */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 144 | case beq_op: |
| 145 | case beql_op: |
| 146 | if (arch->gprs[insn.i_format.rs] == |
| 147 | arch->gprs[insn.i_format.rt]) |
| 148 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 149 | else |
| 150 | epc += 8; |
| 151 | nextpc = epc; |
| 152 | break; |
| 153 | |
| 154 | case bne_op: |
| 155 | case bnel_op: |
| 156 | if (arch->gprs[insn.i_format.rs] != |
| 157 | arch->gprs[insn.i_format.rt]) |
| 158 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 159 | else |
| 160 | epc += 8; |
| 161 | nextpc = epc; |
| 162 | break; |
| 163 | |
| 164 | case blez_op: /* not really i_format */ |
| 165 | case blezl_op: |
| 166 | /* rt field assumed to be zero */ |
| 167 | if ((long)arch->gprs[insn.i_format.rs] <= 0) |
| 168 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 169 | else |
| 170 | epc += 8; |
| 171 | nextpc = epc; |
| 172 | break; |
| 173 | |
| 174 | case bgtz_op: |
| 175 | case bgtzl_op: |
| 176 | /* rt field assumed to be zero */ |
| 177 | if ((long)arch->gprs[insn.i_format.rs] > 0) |
| 178 | epc = epc + 4 + (insn.i_format.simmediate << 2); |
| 179 | else |
| 180 | epc += 8; |
| 181 | nextpc = epc; |
| 182 | break; |
| 183 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 184 | /* And now the FPA/cp1 branch instructions. */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 185 | case cop1_op: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 186 | kvm_err("%s: unsupported cop1_op\n", __func__); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 187 | break; |
| 188 | } |
| 189 | |
| 190 | return nextpc; |
| 191 | |
| 192 | unaligned: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 193 | kvm_err("%s: unaligned epc\n", __func__); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 194 | return nextpc; |
| 195 | |
| 196 | sigill: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 197 | kvm_err("%s: DSP branch but not DSP ASE\n", __func__); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 198 | return nextpc; |
| 199 | } |
| 200 | |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 201 | enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 202 | { |
| 203 | unsigned long branch_pc; |
| 204 | enum emulation_result er = EMULATE_DONE; |
| 205 | |
| 206 | if (cause & CAUSEF_BD) { |
| 207 | branch_pc = kvm_compute_return_epc(vcpu, vcpu->arch.pc); |
| 208 | if (branch_pc == KVM_INVALID_INST) { |
| 209 | er = EMULATE_FAIL; |
| 210 | } else { |
| 211 | vcpu->arch.pc = branch_pc; |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 212 | kvm_debug("BD update_pc(): New PC: %#lx\n", |
| 213 | vcpu->arch.pc); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 214 | } |
| 215 | } else |
| 216 | vcpu->arch.pc += 4; |
| 217 | |
| 218 | kvm_debug("update_pc(): New PC: %#lx\n", vcpu->arch.pc); |
| 219 | |
| 220 | return er; |
| 221 | } |
| 222 | |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 223 | /** |
| 224 | * kvm_mips_count_disabled() - Find whether the CP0_Count timer is disabled. |
| 225 | * @vcpu: Virtual CPU. |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 226 | * |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 227 | * Returns: 1 if the CP0_Count timer is disabled by either the guest |
| 228 | * CP0_Cause.DC bit or the count_ctl.DC bit. |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 229 | * 0 otherwise (in which case CP0_Count timer is running). |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 230 | */ |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 231 | static inline int kvm_mips_count_disabled(struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 232 | { |
| 233 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 234 | |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 235 | return (vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) || |
| 236 | (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC); |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 237 | } |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 238 | |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 239 | /** |
| 240 | * kvm_mips_ktime_to_count() - Scale ktime_t to a 32-bit count. |
| 241 | * |
| 242 | * Caches the dynamic nanosecond bias in vcpu->arch.count_dyn_bias. |
| 243 | * |
| 244 | * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running). |
| 245 | */ |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 246 | static u32 kvm_mips_ktime_to_count(struct kvm_vcpu *vcpu, ktime_t now) |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 247 | { |
| 248 | s64 now_ns, periods; |
| 249 | u64 delta; |
| 250 | |
| 251 | now_ns = ktime_to_ns(now); |
| 252 | delta = now_ns + vcpu->arch.count_dyn_bias; |
| 253 | |
| 254 | if (delta >= vcpu->arch.count_period) { |
| 255 | /* If delta is out of safe range the bias needs adjusting */ |
| 256 | periods = div64_s64(now_ns, vcpu->arch.count_period); |
| 257 | vcpu->arch.count_dyn_bias = -periods * vcpu->arch.count_period; |
| 258 | /* Recalculate delta with new bias */ |
| 259 | delta = now_ns + vcpu->arch.count_dyn_bias; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 260 | } |
| 261 | |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 262 | /* |
| 263 | * We've ensured that: |
| 264 | * delta < count_period |
| 265 | * |
| 266 | * Therefore the intermediate delta*count_hz will never overflow since |
| 267 | * at the boundary condition: |
| 268 | * delta = count_period |
| 269 | * delta = NSEC_PER_SEC * 2^32 / count_hz |
| 270 | * delta * count_hz = NSEC_PER_SEC * 2^32 |
| 271 | */ |
| 272 | return div_u64(delta * vcpu->arch.count_hz, NSEC_PER_SEC); |
| 273 | } |
| 274 | |
| 275 | /** |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 276 | * kvm_mips_count_time() - Get effective current time. |
| 277 | * @vcpu: Virtual CPU. |
| 278 | * |
| 279 | * Get effective monotonic ktime. This is usually a straightforward ktime_get(), |
| 280 | * except when the master disable bit is set in count_ctl, in which case it is |
| 281 | * count_resume, i.e. the time that the count was disabled. |
| 282 | * |
| 283 | * Returns: Effective monotonic ktime for CP0_Count. |
| 284 | */ |
| 285 | static inline ktime_t kvm_mips_count_time(struct kvm_vcpu *vcpu) |
| 286 | { |
| 287 | if (unlikely(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) |
| 288 | return vcpu->arch.count_resume; |
| 289 | |
| 290 | return ktime_get(); |
| 291 | } |
| 292 | |
| 293 | /** |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 294 | * kvm_mips_read_count_running() - Read the current count value as if running. |
| 295 | * @vcpu: Virtual CPU. |
| 296 | * @now: Kernel time to read CP0_Count at. |
| 297 | * |
| 298 | * Returns the current guest CP0_Count register at time @now and handles if the |
| 299 | * timer interrupt is pending and hasn't been handled yet. |
| 300 | * |
| 301 | * Returns: The current value of the guest CP0_Count register. |
| 302 | */ |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 303 | static u32 kvm_mips_read_count_running(struct kvm_vcpu *vcpu, ktime_t now) |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 304 | { |
James Hogan | 4355c44 | 2016-04-22 10:38:45 +0100 | [diff] [blame] | 305 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 306 | ktime_t expires, threshold; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 307 | u32 count, compare; |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 308 | int running; |
| 309 | |
James Hogan | 4355c44 | 2016-04-22 10:38:45 +0100 | [diff] [blame] | 310 | /* Calculate the biased and scaled guest CP0_Count */ |
| 311 | count = vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now); |
| 312 | compare = kvm_read_c0_guest_compare(cop0); |
| 313 | |
| 314 | /* |
| 315 | * Find whether CP0_Count has reached the closest timer interrupt. If |
| 316 | * not, we shouldn't inject it. |
| 317 | */ |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 318 | if ((s32)(count - compare) < 0) |
James Hogan | 4355c44 | 2016-04-22 10:38:45 +0100 | [diff] [blame] | 319 | return count; |
| 320 | |
| 321 | /* |
| 322 | * The CP0_Count we're going to return has already reached the closest |
| 323 | * timer interrupt. Quickly check if it really is a new interrupt by |
| 324 | * looking at whether the interval until the hrtimer expiry time is |
| 325 | * less than 1/4 of the timer period. |
| 326 | */ |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 327 | expires = hrtimer_get_expires(&vcpu->arch.comparecount_timer); |
James Hogan | 4355c44 | 2016-04-22 10:38:45 +0100 | [diff] [blame] | 328 | threshold = ktime_add_ns(now, vcpu->arch.count_period / 4); |
| 329 | if (ktime_before(expires, threshold)) { |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 330 | /* |
| 331 | * Cancel it while we handle it so there's no chance of |
| 332 | * interference with the timeout handler. |
| 333 | */ |
| 334 | running = hrtimer_cancel(&vcpu->arch.comparecount_timer); |
| 335 | |
| 336 | /* Nothing should be waiting on the timeout */ |
| 337 | kvm_mips_callbacks->queue_timer_int(vcpu); |
| 338 | |
| 339 | /* |
| 340 | * Restart the timer if it was running based on the expiry time |
| 341 | * we read, so that we don't push it back 2 periods. |
| 342 | */ |
| 343 | if (running) { |
| 344 | expires = ktime_add_ns(expires, |
| 345 | vcpu->arch.count_period); |
| 346 | hrtimer_start(&vcpu->arch.comparecount_timer, expires, |
| 347 | HRTIMER_MODE_ABS); |
| 348 | } |
| 349 | } |
| 350 | |
James Hogan | 4355c44 | 2016-04-22 10:38:45 +0100 | [diff] [blame] | 351 | return count; |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 352 | } |
| 353 | |
| 354 | /** |
| 355 | * kvm_mips_read_count() - Read the current count value. |
| 356 | * @vcpu: Virtual CPU. |
| 357 | * |
| 358 | * Read the current guest CP0_Count value, taking into account whether the timer |
| 359 | * is stopped. |
| 360 | * |
| 361 | * Returns: The current guest CP0_Count value. |
| 362 | */ |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 363 | u32 kvm_mips_read_count(struct kvm_vcpu *vcpu) |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 364 | { |
| 365 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 366 | |
| 367 | /* If count disabled just read static copy of count */ |
| 368 | if (kvm_mips_count_disabled(vcpu)) |
| 369 | return kvm_read_c0_guest_count(cop0); |
| 370 | |
| 371 | return kvm_mips_read_count_running(vcpu, ktime_get()); |
| 372 | } |
| 373 | |
| 374 | /** |
| 375 | * kvm_mips_freeze_hrtimer() - Safely stop the hrtimer. |
| 376 | * @vcpu: Virtual CPU. |
| 377 | * @count: Output pointer for CP0_Count value at point of freeze. |
| 378 | * |
| 379 | * Freeze the hrtimer safely and return both the ktime and the CP0_Count value |
| 380 | * at the point it was frozen. It is guaranteed that any pending interrupts at |
| 381 | * the point it was frozen are handled, and none after that point. |
| 382 | * |
| 383 | * This is useful where the time/CP0_Count is needed in the calculation of the |
| 384 | * new parameters. |
| 385 | * |
| 386 | * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running). |
| 387 | * |
| 388 | * Returns: The ktime at the point of freeze. |
| 389 | */ |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 390 | static ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count) |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 391 | { |
| 392 | ktime_t now; |
| 393 | |
| 394 | /* stop hrtimer before finding time */ |
| 395 | hrtimer_cancel(&vcpu->arch.comparecount_timer); |
| 396 | now = ktime_get(); |
| 397 | |
| 398 | /* find count at this point and handle pending hrtimer */ |
| 399 | *count = kvm_mips_read_count_running(vcpu, now); |
| 400 | |
| 401 | return now; |
| 402 | } |
| 403 | |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 404 | /** |
| 405 | * kvm_mips_resume_hrtimer() - Resume hrtimer, updating expiry. |
| 406 | * @vcpu: Virtual CPU. |
| 407 | * @now: ktime at point of resume. |
| 408 | * @count: CP0_Count at point of resume. |
| 409 | * |
| 410 | * Resumes the timer and updates the timer expiry based on @now and @count. |
| 411 | * This can be used in conjunction with kvm_mips_freeze_timer() when timer |
| 412 | * parameters need to be changed. |
| 413 | * |
| 414 | * It is guaranteed that a timer interrupt immediately after resume will be |
| 415 | * handled, but not if CP_Compare is exactly at @count. That case is already |
| 416 | * handled by kvm_mips_freeze_timer(). |
| 417 | * |
| 418 | * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running). |
| 419 | */ |
| 420 | static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 421 | ktime_t now, u32 count) |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 422 | { |
| 423 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 424 | u32 compare; |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 425 | u64 delta; |
| 426 | ktime_t expire; |
| 427 | |
| 428 | /* Calculate timeout (wrap 0 to 2^32) */ |
| 429 | compare = kvm_read_c0_guest_compare(cop0); |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 430 | delta = (u64)(u32)(compare - count - 1) + 1; |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 431 | delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz); |
| 432 | expire = ktime_add_ns(now, delta); |
| 433 | |
| 434 | /* Update hrtimer to use new timeout */ |
| 435 | hrtimer_cancel(&vcpu->arch.comparecount_timer); |
| 436 | hrtimer_start(&vcpu->arch.comparecount_timer, expire, HRTIMER_MODE_ABS); |
| 437 | } |
| 438 | |
| 439 | /** |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 440 | * kvm_mips_write_count() - Modify the count and update timer. |
| 441 | * @vcpu: Virtual CPU. |
| 442 | * @count: Guest CP0_Count value to set. |
| 443 | * |
| 444 | * Sets the CP0_Count value and updates the timer accordingly. |
| 445 | */ |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 446 | void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count) |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 447 | { |
| 448 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 449 | ktime_t now; |
| 450 | |
| 451 | /* Calculate bias */ |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 452 | now = kvm_mips_count_time(vcpu); |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 453 | vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now); |
| 454 | |
| 455 | if (kvm_mips_count_disabled(vcpu)) |
| 456 | /* The timer's disabled, adjust the static count */ |
| 457 | kvm_write_c0_guest_count(cop0, count); |
| 458 | else |
| 459 | /* Update timeout */ |
| 460 | kvm_mips_resume_hrtimer(vcpu, now, count); |
| 461 | } |
| 462 | |
| 463 | /** |
| 464 | * kvm_mips_init_count() - Initialise timer. |
| 465 | * @vcpu: Virtual CPU. |
| 466 | * |
| 467 | * Initialise the timer to a sensible frequency, namely 100MHz, zero it, and set |
| 468 | * it going if it's enabled. |
| 469 | */ |
| 470 | void kvm_mips_init_count(struct kvm_vcpu *vcpu) |
| 471 | { |
| 472 | /* 100 MHz */ |
| 473 | vcpu->arch.count_hz = 100*1000*1000; |
| 474 | vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, |
| 475 | vcpu->arch.count_hz); |
| 476 | vcpu->arch.count_dyn_bias = 0; |
| 477 | |
| 478 | /* Starting at 0 */ |
| 479 | kvm_mips_write_count(vcpu, 0); |
| 480 | } |
| 481 | |
| 482 | /** |
James Hogan | f74a8e2 | 2014-05-29 10:16:38 +0100 | [diff] [blame] | 483 | * kvm_mips_set_count_hz() - Update the frequency of the timer. |
| 484 | * @vcpu: Virtual CPU. |
| 485 | * @count_hz: Frequency of CP0_Count timer in Hz. |
| 486 | * |
| 487 | * Change the frequency of the CP0_Count timer. This is done atomically so that |
| 488 | * CP0_Count is continuous and no timer interrupt is lost. |
| 489 | * |
| 490 | * Returns: -EINVAL if @count_hz is out of range. |
| 491 | * 0 on success. |
| 492 | */ |
| 493 | int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz) |
| 494 | { |
| 495 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 496 | int dc; |
| 497 | ktime_t now; |
| 498 | u32 count; |
| 499 | |
| 500 | /* ensure the frequency is in a sensible range... */ |
| 501 | if (count_hz <= 0 || count_hz > NSEC_PER_SEC) |
| 502 | return -EINVAL; |
| 503 | /* ... and has actually changed */ |
| 504 | if (vcpu->arch.count_hz == count_hz) |
| 505 | return 0; |
| 506 | |
| 507 | /* Safely freeze timer so we can keep it continuous */ |
| 508 | dc = kvm_mips_count_disabled(vcpu); |
| 509 | if (dc) { |
| 510 | now = kvm_mips_count_time(vcpu); |
| 511 | count = kvm_read_c0_guest_count(cop0); |
| 512 | } else { |
| 513 | now = kvm_mips_freeze_hrtimer(vcpu, &count); |
| 514 | } |
| 515 | |
| 516 | /* Update the frequency */ |
| 517 | vcpu->arch.count_hz = count_hz; |
| 518 | vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz); |
| 519 | vcpu->arch.count_dyn_bias = 0; |
| 520 | |
| 521 | /* Calculate adjusted bias so dynamic count is unchanged */ |
| 522 | vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now); |
| 523 | |
| 524 | /* Update and resume hrtimer */ |
| 525 | if (!dc) |
| 526 | kvm_mips_resume_hrtimer(vcpu, now, count); |
| 527 | return 0; |
| 528 | } |
| 529 | |
| 530 | /** |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 531 | * kvm_mips_write_compare() - Modify compare and update timer. |
| 532 | * @vcpu: Virtual CPU. |
| 533 | * @compare: New CP0_Compare value. |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 534 | * @ack: Whether to acknowledge timer interrupt. |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 535 | * |
| 536 | * Update CP0_Compare to a new value and update the timeout. |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 537 | * If @ack, atomically acknowledge any pending timer interrupt, otherwise ensure |
| 538 | * any pending timer interrupt is preserved. |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 539 | */ |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 540 | void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack) |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 541 | { |
| 542 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 543 | int dc; |
| 544 | u32 old_compare = kvm_read_c0_guest_compare(cop0); |
| 545 | ktime_t now; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 546 | u32 count; |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 547 | |
| 548 | /* if unchanged, must just be an ack */ |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 549 | if (old_compare == compare) { |
| 550 | if (!ack) |
| 551 | return; |
| 552 | kvm_mips_callbacks->dequeue_timer_int(vcpu); |
| 553 | kvm_write_c0_guest_compare(cop0, compare); |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 554 | return; |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 555 | } |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 556 | |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 557 | /* freeze_hrtimer() takes care of timer interrupts <= count */ |
| 558 | dc = kvm_mips_count_disabled(vcpu); |
| 559 | if (!dc) |
| 560 | now = kvm_mips_freeze_hrtimer(vcpu, &count); |
| 561 | |
| 562 | if (ack) |
| 563 | kvm_mips_callbacks->dequeue_timer_int(vcpu); |
| 564 | |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 565 | kvm_write_c0_guest_compare(cop0, compare); |
| 566 | |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 567 | /* resume_hrtimer() takes care of timer interrupts > count */ |
| 568 | if (!dc) |
| 569 | kvm_mips_resume_hrtimer(vcpu, now, count); |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 570 | } |
| 571 | |
| 572 | /** |
| 573 | * kvm_mips_count_disable() - Disable count. |
| 574 | * @vcpu: Virtual CPU. |
| 575 | * |
| 576 | * Disable the CP0_Count timer. A timer interrupt on or before the final stop |
| 577 | * time will be handled but not after. |
| 578 | * |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 579 | * Assumes CP0_Count was previously enabled but now Guest.CP0_Cause.DC or |
| 580 | * count_ctl.DC has been set (count disabled). |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 581 | * |
| 582 | * Returns: The time that the timer was stopped. |
| 583 | */ |
| 584 | static ktime_t kvm_mips_count_disable(struct kvm_vcpu *vcpu) |
| 585 | { |
| 586 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 587 | u32 count; |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 588 | ktime_t now; |
| 589 | |
| 590 | /* Stop hrtimer */ |
| 591 | hrtimer_cancel(&vcpu->arch.comparecount_timer); |
| 592 | |
| 593 | /* Set the static count from the dynamic count, handling pending TI */ |
| 594 | now = ktime_get(); |
| 595 | count = kvm_mips_read_count_running(vcpu, now); |
| 596 | kvm_write_c0_guest_count(cop0, count); |
| 597 | |
| 598 | return now; |
| 599 | } |
| 600 | |
| 601 | /** |
| 602 | * kvm_mips_count_disable_cause() - Disable count using CP0_Cause.DC. |
| 603 | * @vcpu: Virtual CPU. |
| 604 | * |
| 605 | * Disable the CP0_Count timer and set CP0_Cause.DC. A timer interrupt on or |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 606 | * before the final stop time will be handled if the timer isn't disabled by |
| 607 | * count_ctl.DC, but not after. |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 608 | * |
| 609 | * Assumes CP0_Cause.DC is clear (count enabled). |
| 610 | */ |
| 611 | void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu) |
| 612 | { |
| 613 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 614 | |
| 615 | kvm_set_c0_guest_cause(cop0, CAUSEF_DC); |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 616 | if (!(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) |
| 617 | kvm_mips_count_disable(vcpu); |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 618 | } |
| 619 | |
| 620 | /** |
| 621 | * kvm_mips_count_enable_cause() - Enable count using CP0_Cause.DC. |
| 622 | * @vcpu: Virtual CPU. |
| 623 | * |
| 624 | * Enable the CP0_Count timer and clear CP0_Cause.DC. A timer interrupt after |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 625 | * the start time will be handled if the timer isn't disabled by count_ctl.DC, |
| 626 | * potentially before even returning, so the caller should be careful with |
| 627 | * ordering of CP0_Cause modifications so as not to lose it. |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 628 | * |
| 629 | * Assumes CP0_Cause.DC is set (count disabled). |
| 630 | */ |
| 631 | void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu) |
| 632 | { |
| 633 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 634 | u32 count; |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 635 | |
| 636 | kvm_clear_c0_guest_cause(cop0, CAUSEF_DC); |
| 637 | |
| 638 | /* |
| 639 | * Set the dynamic count to match the static count. |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 640 | * This starts the hrtimer if count_ctl.DC allows it. |
| 641 | * Otherwise it conveniently updates the biases. |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 642 | */ |
| 643 | count = kvm_read_c0_guest_count(cop0); |
| 644 | kvm_mips_write_count(vcpu, count); |
| 645 | } |
| 646 | |
| 647 | /** |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 648 | * kvm_mips_set_count_ctl() - Update the count control KVM register. |
| 649 | * @vcpu: Virtual CPU. |
| 650 | * @count_ctl: Count control register new value. |
| 651 | * |
| 652 | * Set the count control KVM register. The timer is updated accordingly. |
| 653 | * |
| 654 | * Returns: -EINVAL if reserved bits are set. |
| 655 | * 0 on success. |
| 656 | */ |
| 657 | int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl) |
| 658 | { |
| 659 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 660 | s64 changed = count_ctl ^ vcpu->arch.count_ctl; |
| 661 | s64 delta; |
| 662 | ktime_t expire, now; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 663 | u32 count, compare; |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 664 | |
| 665 | /* Only allow defined bits to be changed */ |
| 666 | if (changed & ~(s64)(KVM_REG_MIPS_COUNT_CTL_DC)) |
| 667 | return -EINVAL; |
| 668 | |
| 669 | /* Apply new value */ |
| 670 | vcpu->arch.count_ctl = count_ctl; |
| 671 | |
| 672 | /* Master CP0_Count disable */ |
| 673 | if (changed & KVM_REG_MIPS_COUNT_CTL_DC) { |
| 674 | /* Is CP0_Cause.DC already disabling CP0_Count? */ |
| 675 | if (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC) { |
| 676 | if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) |
| 677 | /* Just record the current time */ |
| 678 | vcpu->arch.count_resume = ktime_get(); |
| 679 | } else if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) { |
| 680 | /* disable timer and record current time */ |
| 681 | vcpu->arch.count_resume = kvm_mips_count_disable(vcpu); |
| 682 | } else { |
| 683 | /* |
| 684 | * Calculate timeout relative to static count at resume |
| 685 | * time (wrap 0 to 2^32). |
| 686 | */ |
| 687 | count = kvm_read_c0_guest_count(cop0); |
| 688 | compare = kvm_read_c0_guest_compare(cop0); |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 689 | delta = (u64)(u32)(compare - count - 1) + 1; |
James Hogan | f823934 | 2014-05-29 10:16:37 +0100 | [diff] [blame] | 690 | delta = div_u64(delta * NSEC_PER_SEC, |
| 691 | vcpu->arch.count_hz); |
| 692 | expire = ktime_add_ns(vcpu->arch.count_resume, delta); |
| 693 | |
| 694 | /* Handle pending interrupt */ |
| 695 | now = ktime_get(); |
| 696 | if (ktime_compare(now, expire) >= 0) |
| 697 | /* Nothing should be waiting on the timeout */ |
| 698 | kvm_mips_callbacks->queue_timer_int(vcpu); |
| 699 | |
| 700 | /* Resume hrtimer without changing bias */ |
| 701 | count = kvm_mips_read_count_running(vcpu, now); |
| 702 | kvm_mips_resume_hrtimer(vcpu, now, count); |
| 703 | } |
| 704 | } |
| 705 | |
| 706 | return 0; |
| 707 | } |
| 708 | |
| 709 | /** |
| 710 | * kvm_mips_set_count_resume() - Update the count resume KVM register. |
| 711 | * @vcpu: Virtual CPU. |
| 712 | * @count_resume: Count resume register new value. |
| 713 | * |
| 714 | * Set the count resume KVM register. |
| 715 | * |
| 716 | * Returns: -EINVAL if out of valid range (0..now). |
| 717 | * 0 on success. |
| 718 | */ |
| 719 | int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume) |
| 720 | { |
| 721 | /* |
| 722 | * It doesn't make sense for the resume time to be in the future, as it |
| 723 | * would be possible for the next interrupt to be more than a full |
| 724 | * period in the future. |
| 725 | */ |
| 726 | if (count_resume < 0 || count_resume > ktime_to_ns(ktime_get())) |
| 727 | return -EINVAL; |
| 728 | |
| 729 | vcpu->arch.count_resume = ns_to_ktime(count_resume); |
| 730 | return 0; |
| 731 | } |
| 732 | |
| 733 | /** |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 734 | * kvm_mips_count_timeout() - Push timer forward on timeout. |
| 735 | * @vcpu: Virtual CPU. |
| 736 | * |
| 737 | * Handle an hrtimer event by push the hrtimer forward a period. |
| 738 | * |
| 739 | * Returns: The hrtimer_restart value to return to the hrtimer subsystem. |
| 740 | */ |
| 741 | enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu) |
| 742 | { |
| 743 | /* Add the Count period to the current expiry time */ |
| 744 | hrtimer_add_expires_ns(&vcpu->arch.comparecount_timer, |
| 745 | vcpu->arch.count_period); |
| 746 | return HRTIMER_RESTART; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 747 | } |
| 748 | |
| 749 | enum emulation_result kvm_mips_emul_eret(struct kvm_vcpu *vcpu) |
| 750 | { |
| 751 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 752 | enum emulation_result er = EMULATE_DONE; |
| 753 | |
| 754 | if (kvm_read_c0_guest_status(cop0) & ST0_EXL) { |
| 755 | kvm_debug("[%#lx] ERET to %#lx\n", vcpu->arch.pc, |
| 756 | kvm_read_c0_guest_epc(cop0)); |
| 757 | kvm_clear_c0_guest_status(cop0, ST0_EXL); |
| 758 | vcpu->arch.pc = kvm_read_c0_guest_epc(cop0); |
| 759 | |
| 760 | } else if (kvm_read_c0_guest_status(cop0) & ST0_ERL) { |
| 761 | kvm_clear_c0_guest_status(cop0, ST0_ERL); |
| 762 | vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0); |
| 763 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 764 | kvm_err("[%#lx] ERET when MIPS_SR_EXL|MIPS_SR_ERL == 0\n", |
| 765 | vcpu->arch.pc); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 766 | er = EMULATE_FAIL; |
| 767 | } |
| 768 | |
| 769 | return er; |
| 770 | } |
| 771 | |
| 772 | enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu) |
| 773 | { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 774 | kvm_debug("[%#lx] !!!WAIT!!! (%#lx)\n", vcpu->arch.pc, |
| 775 | vcpu->arch.pending_exceptions); |
| 776 | |
| 777 | ++vcpu->stat.wait_exits; |
James Hogan | 1e09e86 | 2016-06-14 09:40:12 +0100 | [diff] [blame] | 778 | trace_kvm_exit(vcpu, KVM_TRACE_EXIT_WAIT); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 779 | if (!vcpu->arch.pending_exceptions) { |
| 780 | vcpu->arch.wait = 1; |
| 781 | kvm_vcpu_block(vcpu); |
| 782 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 783 | /* |
| 784 | * We we are runnable, then definitely go off to user space to |
| 785 | * check if any I/O interrupts are pending. |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 786 | */ |
| 787 | if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) { |
| 788 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
| 789 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
| 790 | } |
| 791 | } |
| 792 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 793 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 794 | } |
| 795 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 796 | /* |
| 797 | * XXXKYMA: Linux doesn't seem to use TLBR, return EMULATE_FAIL for now so that |
| 798 | * we can catch this, if things ever change |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 799 | */ |
| 800 | enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu) |
| 801 | { |
| 802 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 803 | unsigned long pc = vcpu->arch.pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 804 | |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 805 | kvm_err("[%#lx] COP0_TLBR [%ld]\n", pc, kvm_read_c0_guest_index(cop0)); |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 806 | return EMULATE_FAIL; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 807 | } |
| 808 | |
| 809 | /* Write Guest TLB Entry @ Index */ |
| 810 | enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu) |
| 811 | { |
| 812 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 813 | int index = kvm_read_c0_guest_index(cop0); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 814 | struct kvm_mips_tlb *tlb = NULL; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 815 | unsigned long pc = vcpu->arch.pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 816 | |
| 817 | if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 818 | kvm_debug("%s: illegal index: %d\n", __func__, index); |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 819 | kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n", |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 820 | pc, index, kvm_read_c0_guest_entryhi(cop0), |
| 821 | kvm_read_c0_guest_entrylo0(cop0), |
| 822 | kvm_read_c0_guest_entrylo1(cop0), |
| 823 | kvm_read_c0_guest_pagemask(cop0)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 824 | index = (index & ~0x80000000) % KVM_MIPS_GUEST_TLB_SIZE; |
| 825 | } |
| 826 | |
| 827 | tlb = &vcpu->arch.guest_tlb[index]; |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 828 | /* |
| 829 | * Probe the shadow host TLB for the entry being overwritten, if one |
| 830 | * matches, invalidate it |
| 831 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 832 | kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 833 | |
| 834 | tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0); |
| 835 | tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0); |
James Hogan | 9fbfb06 | 2016-06-09 14:19:17 +0100 | [diff] [blame] | 836 | tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0); |
| 837 | tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 838 | |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 839 | kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n", |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 840 | pc, index, kvm_read_c0_guest_entryhi(cop0), |
| 841 | kvm_read_c0_guest_entrylo0(cop0), |
| 842 | kvm_read_c0_guest_entrylo1(cop0), |
| 843 | kvm_read_c0_guest_pagemask(cop0)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 844 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 845 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 846 | } |
| 847 | |
| 848 | /* Write Guest TLB Entry @ Random Index */ |
| 849 | enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu) |
| 850 | { |
| 851 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 852 | struct kvm_mips_tlb *tlb = NULL; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 853 | unsigned long pc = vcpu->arch.pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 854 | int index; |
| 855 | |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 856 | get_random_bytes(&index, sizeof(index)); |
| 857 | index &= (KVM_MIPS_GUEST_TLB_SIZE - 1); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 858 | |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 859 | tlb = &vcpu->arch.guest_tlb[index]; |
| 860 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 861 | /* |
| 862 | * Probe the shadow host TLB for the entry being overwritten, if one |
| 863 | * matches, invalidate it |
| 864 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 865 | kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 866 | |
| 867 | tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0); |
| 868 | tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0); |
James Hogan | 9fbfb06 | 2016-06-09 14:19:17 +0100 | [diff] [blame] | 869 | tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0); |
| 870 | tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 871 | |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 872 | kvm_debug("[%#lx] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n", |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 873 | pc, index, kvm_read_c0_guest_entryhi(cop0), |
| 874 | kvm_read_c0_guest_entrylo0(cop0), |
| 875 | kvm_read_c0_guest_entrylo1(cop0)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 876 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 877 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 878 | } |
| 879 | |
| 880 | enum emulation_result kvm_mips_emul_tlbp(struct kvm_vcpu *vcpu) |
| 881 | { |
| 882 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 883 | long entryhi = kvm_read_c0_guest_entryhi(cop0); |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 884 | unsigned long pc = vcpu->arch.pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 885 | int index = -1; |
| 886 | |
| 887 | index = kvm_mips_guest_tlb_lookup(vcpu, entryhi); |
| 888 | |
| 889 | kvm_write_c0_guest_index(cop0, index); |
| 890 | |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 891 | kvm_debug("[%#lx] COP0_TLBP (entryhi: %#lx), index: %d\n", pc, entryhi, |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 892 | index); |
| 893 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 894 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 895 | } |
| 896 | |
James Hogan | c771607 | 2014-06-26 15:11:29 +0100 | [diff] [blame] | 897 | /** |
| 898 | * kvm_mips_config1_wrmask() - Find mask of writable bits in guest Config1 |
| 899 | * @vcpu: Virtual CPU. |
| 900 | * |
| 901 | * Finds the mask of bits which are writable in the guest's Config1 CP0 |
| 902 | * register, by userland (currently read-only to the guest). |
| 903 | */ |
| 904 | unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu) |
| 905 | { |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 906 | unsigned int mask = 0; |
| 907 | |
| 908 | /* Permit FPU to be present if FPU is supported */ |
| 909 | if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) |
| 910 | mask |= MIPS_CONF1_FP; |
| 911 | |
| 912 | return mask; |
James Hogan | c771607 | 2014-06-26 15:11:29 +0100 | [diff] [blame] | 913 | } |
| 914 | |
| 915 | /** |
| 916 | * kvm_mips_config3_wrmask() - Find mask of writable bits in guest Config3 |
| 917 | * @vcpu: Virtual CPU. |
| 918 | * |
| 919 | * Finds the mask of bits which are writable in the guest's Config3 CP0 |
| 920 | * register, by userland (currently read-only to the guest). |
| 921 | */ |
| 922 | unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu) |
| 923 | { |
James Hogan | cef061d0 | 2016-06-15 19:29:54 +0100 | [diff] [blame] | 924 | /* Config4 and ULRI are optional */ |
| 925 | unsigned int mask = MIPS_CONF_M | MIPS_CONF3_ULRI; |
James Hogan | 2b6009d | 2015-02-06 23:01:00 +0000 | [diff] [blame] | 926 | |
| 927 | /* Permit MSA to be present if MSA is supported */ |
| 928 | if (kvm_mips_guest_can_have_msa(&vcpu->arch)) |
| 929 | mask |= MIPS_CONF3_MSA; |
| 930 | |
| 931 | return mask; |
James Hogan | c771607 | 2014-06-26 15:11:29 +0100 | [diff] [blame] | 932 | } |
| 933 | |
| 934 | /** |
| 935 | * kvm_mips_config4_wrmask() - Find mask of writable bits in guest Config4 |
| 936 | * @vcpu: Virtual CPU. |
| 937 | * |
| 938 | * Finds the mask of bits which are writable in the guest's Config4 CP0 |
| 939 | * register, by userland (currently read-only to the guest). |
| 940 | */ |
| 941 | unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu) |
| 942 | { |
| 943 | /* Config5 is optional */ |
James Hogan | 0510870 | 2016-06-15 19:29:56 +0100 | [diff] [blame^] | 944 | unsigned int mask = MIPS_CONF_M; |
| 945 | |
| 946 | /* KScrExist */ |
| 947 | mask |= (unsigned int)vcpu->arch.kscratch_enabled << 16; |
| 948 | |
| 949 | return mask; |
James Hogan | c771607 | 2014-06-26 15:11:29 +0100 | [diff] [blame] | 950 | } |
| 951 | |
| 952 | /** |
| 953 | * kvm_mips_config5_wrmask() - Find mask of writable bits in guest Config5 |
| 954 | * @vcpu: Virtual CPU. |
| 955 | * |
| 956 | * Finds the mask of bits which are writable in the guest's Config5 CP0 |
| 957 | * register, by the guest itself. |
| 958 | */ |
| 959 | unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu) |
| 960 | { |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 961 | unsigned int mask = 0; |
| 962 | |
James Hogan | 2b6009d | 2015-02-06 23:01:00 +0000 | [diff] [blame] | 963 | /* Permit MSAEn changes if MSA supported and enabled */ |
| 964 | if (kvm_mips_guest_has_msa(&vcpu->arch)) |
| 965 | mask |= MIPS_CONF5_MSAEN; |
| 966 | |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 967 | /* |
| 968 | * Permit guest FPU mode changes if FPU is enabled and the relevant |
| 969 | * feature exists according to FIR register. |
| 970 | */ |
| 971 | if (kvm_mips_guest_has_fpu(&vcpu->arch)) { |
| 972 | if (cpu_has_fre) |
| 973 | mask |= MIPS_CONF5_FRE; |
| 974 | /* We don't support UFR or UFE */ |
| 975 | } |
| 976 | |
| 977 | return mask; |
James Hogan | c771607 | 2014-06-26 15:11:29 +0100 | [diff] [blame] | 978 | } |
| 979 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 980 | enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst, |
| 981 | u32 *opc, u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 982 | struct kvm_run *run, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 983 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 984 | { |
| 985 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 986 | enum emulation_result er = EMULATE_DONE; |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 987 | u32 rt, rd, sel; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 988 | unsigned long curr_pc; |
| 989 | |
| 990 | /* |
| 991 | * Update PC and hold onto current PC in case there is |
| 992 | * an error and we want to rollback the PC |
| 993 | */ |
| 994 | curr_pc = vcpu->arch.pc; |
| 995 | er = update_pc(vcpu, cause); |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 996 | if (er == EMULATE_FAIL) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 997 | return er; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 998 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 999 | if (inst.co_format.co) { |
| 1000 | switch (inst.co_format.func) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1001 | case tlbr_op: /* Read indexed TLB entry */ |
| 1002 | er = kvm_mips_emul_tlbr(vcpu); |
| 1003 | break; |
| 1004 | case tlbwi_op: /* Write indexed */ |
| 1005 | er = kvm_mips_emul_tlbwi(vcpu); |
| 1006 | break; |
| 1007 | case tlbwr_op: /* Write random */ |
| 1008 | er = kvm_mips_emul_tlbwr(vcpu); |
| 1009 | break; |
| 1010 | case tlbp_op: /* TLB Probe */ |
| 1011 | er = kvm_mips_emul_tlbp(vcpu); |
| 1012 | break; |
| 1013 | case rfe_op: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1014 | kvm_err("!!!COP0_RFE!!!\n"); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1015 | break; |
| 1016 | case eret_op: |
| 1017 | er = kvm_mips_emul_eret(vcpu); |
| 1018 | goto dont_update_pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1019 | case wait_op: |
| 1020 | er = kvm_mips_emul_wait(vcpu); |
| 1021 | break; |
| 1022 | } |
| 1023 | } else { |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1024 | rt = inst.c0r_format.rt; |
| 1025 | rd = inst.c0r_format.rd; |
| 1026 | sel = inst.c0r_format.sel; |
| 1027 | |
| 1028 | switch (inst.c0r_format.rs) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1029 | case mfc_op: |
| 1030 | #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS |
| 1031 | cop0->stat[rd][sel]++; |
| 1032 | #endif |
| 1033 | /* Get reg */ |
| 1034 | if ((rd == MIPS_CP0_COUNT) && (sel == 0)) { |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 1035 | vcpu->arch.gprs[rt] = kvm_mips_read_count(vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1036 | } else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) { |
| 1037 | vcpu->arch.gprs[rt] = 0x0; |
| 1038 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS |
| 1039 | kvm_mips_trans_mfc0(inst, opc, vcpu); |
| 1040 | #endif |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1041 | } else { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1042 | vcpu->arch.gprs[rt] = cop0->reg[rd][sel]; |
| 1043 | |
| 1044 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS |
| 1045 | kvm_mips_trans_mfc0(inst, opc, vcpu); |
| 1046 | #endif |
| 1047 | } |
| 1048 | |
James Hogan | 6398da1 | 2016-06-14 09:40:15 +0100 | [diff] [blame] | 1049 | trace_kvm_hwr(vcpu, KVM_TRACE_MFC0, |
| 1050 | KVM_TRACE_COP0(rd, sel), |
| 1051 | vcpu->arch.gprs[rt]); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1052 | break; |
| 1053 | |
| 1054 | case dmfc_op: |
| 1055 | vcpu->arch.gprs[rt] = cop0->reg[rd][sel]; |
James Hogan | 6398da1 | 2016-06-14 09:40:15 +0100 | [diff] [blame] | 1056 | |
| 1057 | trace_kvm_hwr(vcpu, KVM_TRACE_DMFC0, |
| 1058 | KVM_TRACE_COP0(rd, sel), |
| 1059 | vcpu->arch.gprs[rt]); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1060 | break; |
| 1061 | |
| 1062 | case mtc_op: |
| 1063 | #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS |
| 1064 | cop0->stat[rd][sel]++; |
| 1065 | #endif |
James Hogan | 6398da1 | 2016-06-14 09:40:15 +0100 | [diff] [blame] | 1066 | trace_kvm_hwr(vcpu, KVM_TRACE_MTC0, |
| 1067 | KVM_TRACE_COP0(rd, sel), |
| 1068 | vcpu->arch.gprs[rt]); |
| 1069 | |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1070 | if ((rd == MIPS_CP0_TLB_INDEX) |
| 1071 | && (vcpu->arch.gprs[rt] >= |
| 1072 | KVM_MIPS_GUEST_TLB_SIZE)) { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1073 | kvm_err("Invalid TLB Index: %ld", |
| 1074 | vcpu->arch.gprs[rt]); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1075 | er = EMULATE_FAIL; |
| 1076 | break; |
| 1077 | } |
| 1078 | #define C0_EBASE_CORE_MASK 0xff |
| 1079 | if ((rd == MIPS_CP0_PRID) && (sel == 1)) { |
| 1080 | /* Preserve CORE number */ |
| 1081 | kvm_change_c0_guest_ebase(cop0, |
| 1082 | ~(C0_EBASE_CORE_MASK), |
| 1083 | vcpu->arch.gprs[rt]); |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1084 | kvm_err("MTCz, cop0->reg[EBASE]: %#lx\n", |
| 1085 | kvm_read_c0_guest_ebase(cop0)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1086 | } else if (rd == MIPS_CP0_TLB_HI && sel == 0) { |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1087 | u32 nasid = |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1088 | vcpu->arch.gprs[rt] & KVM_ENTRYHI_ASID; |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1089 | if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0) && |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 1090 | ((kvm_read_c0_guest_entryhi(cop0) & |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1091 | KVM_ENTRYHI_ASID) != nasid)) { |
James Hogan | 9887d1c | 2016-06-14 09:40:13 +0100 | [diff] [blame] | 1092 | trace_kvm_asid_change(vcpu, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1093 | kvm_read_c0_guest_entryhi(cop0) |
James Hogan | 9887d1c | 2016-06-14 09:40:13 +0100 | [diff] [blame] | 1094 | & KVM_ENTRYHI_ASID, |
| 1095 | nasid); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1096 | |
| 1097 | /* Blow away the shadow host TLBs */ |
| 1098 | kvm_mips_flush_host_tlb(1); |
| 1099 | } |
| 1100 | kvm_write_c0_guest_entryhi(cop0, |
| 1101 | vcpu->arch.gprs[rt]); |
| 1102 | } |
| 1103 | /* Are we writing to COUNT */ |
| 1104 | else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) { |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 1105 | kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1106 | goto done; |
| 1107 | } else if ((rd == MIPS_CP0_COMPARE) && (sel == 0)) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1108 | /* If we are writing to COMPARE */ |
| 1109 | /* Clear pending timer interrupt, if any */ |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 1110 | kvm_mips_write_compare(vcpu, |
James Hogan | b45bacd | 2016-04-22 10:38:46 +0100 | [diff] [blame] | 1111 | vcpu->arch.gprs[rt], |
| 1112 | true); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1113 | } else if ((rd == MIPS_CP0_STATUS) && (sel == 0)) { |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1114 | unsigned int old_val, val, change; |
| 1115 | |
| 1116 | old_val = kvm_read_c0_guest_status(cop0); |
| 1117 | val = vcpu->arch.gprs[rt]; |
| 1118 | change = val ^ old_val; |
| 1119 | |
| 1120 | /* Make sure that the NMI bit is never set */ |
| 1121 | val &= ~ST0_NMI; |
| 1122 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1123 | /* |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1124 | * Don't allow CU1 or FR to be set unless FPU |
| 1125 | * capability enabled and exists in guest |
| 1126 | * configuration. |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1127 | */ |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1128 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) |
| 1129 | val &= ~(ST0_CU1 | ST0_FR); |
| 1130 | |
| 1131 | /* |
| 1132 | * Also don't allow FR to be set if host doesn't |
| 1133 | * support it. |
| 1134 | */ |
| 1135 | if (!(current_cpu_data.fpu_id & MIPS_FPIR_F64)) |
| 1136 | val &= ~ST0_FR; |
| 1137 | |
| 1138 | |
| 1139 | /* Handle changes in FPU mode */ |
| 1140 | preempt_disable(); |
| 1141 | |
| 1142 | /* |
| 1143 | * FPU and Vector register state is made |
| 1144 | * UNPREDICTABLE by a change of FR, so don't |
| 1145 | * even bother saving it. |
| 1146 | */ |
| 1147 | if (change & ST0_FR) |
| 1148 | kvm_drop_fpu(vcpu); |
| 1149 | |
| 1150 | /* |
James Hogan | 2b6009d | 2015-02-06 23:01:00 +0000 | [diff] [blame] | 1151 | * If MSA state is already live, it is undefined |
| 1152 | * how it interacts with FR=0 FPU state, and we |
| 1153 | * don't want to hit reserved instruction |
| 1154 | * exceptions trying to save the MSA state later |
| 1155 | * when CU=1 && FR=1, so play it safe and save |
| 1156 | * it first. |
| 1157 | */ |
| 1158 | if (change & ST0_CU1 && !(val & ST0_FR) && |
James Hogan | f943176 | 2016-06-14 09:40:10 +0100 | [diff] [blame] | 1159 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) |
James Hogan | 2b6009d | 2015-02-06 23:01:00 +0000 | [diff] [blame] | 1160 | kvm_lose_fpu(vcpu); |
| 1161 | |
| 1162 | /* |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1163 | * Propagate CU1 (FPU enable) changes |
| 1164 | * immediately if the FPU context is already |
| 1165 | * loaded. When disabling we leave the context |
| 1166 | * loaded so it can be quickly enabled again in |
| 1167 | * the near future. |
| 1168 | */ |
| 1169 | if (change & ST0_CU1 && |
James Hogan | f943176 | 2016-06-14 09:40:10 +0100 | [diff] [blame] | 1170 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1171 | change_c0_status(ST0_CU1, val); |
| 1172 | |
| 1173 | preempt_enable(); |
| 1174 | |
| 1175 | kvm_write_c0_guest_status(cop0, val); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1176 | |
| 1177 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1178 | /* |
| 1179 | * If FPU present, we need CU1/FR bits to take |
| 1180 | * effect fairly soon. |
| 1181 | */ |
| 1182 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) |
| 1183 | kvm_mips_trans_mtc0(inst, opc, vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1184 | #endif |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1185 | } else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) { |
| 1186 | unsigned int old_val, val, change, wrmask; |
| 1187 | |
| 1188 | old_val = kvm_read_c0_guest_config5(cop0); |
| 1189 | val = vcpu->arch.gprs[rt]; |
| 1190 | |
| 1191 | /* Only a few bits are writable in Config5 */ |
| 1192 | wrmask = kvm_mips_config5_wrmask(vcpu); |
| 1193 | change = (val ^ old_val) & wrmask; |
| 1194 | val = old_val ^ change; |
| 1195 | |
| 1196 | |
James Hogan | 2b6009d | 2015-02-06 23:01:00 +0000 | [diff] [blame] | 1197 | /* Handle changes in FPU/MSA modes */ |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1198 | preempt_disable(); |
| 1199 | |
| 1200 | /* |
| 1201 | * Propagate FRE changes immediately if the FPU |
| 1202 | * context is already loaded. |
| 1203 | */ |
| 1204 | if (change & MIPS_CONF5_FRE && |
James Hogan | f943176 | 2016-06-14 09:40:10 +0100 | [diff] [blame] | 1205 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1206 | change_c0_config5(MIPS_CONF5_FRE, val); |
| 1207 | |
James Hogan | 2b6009d | 2015-02-06 23:01:00 +0000 | [diff] [blame] | 1208 | /* |
| 1209 | * Propagate MSAEn changes immediately if the |
| 1210 | * MSA context is already loaded. When disabling |
| 1211 | * we leave the context loaded so it can be |
| 1212 | * quickly enabled again in the near future. |
| 1213 | */ |
| 1214 | if (change & MIPS_CONF5_MSAEN && |
James Hogan | f943176 | 2016-06-14 09:40:10 +0100 | [diff] [blame] | 1215 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) |
James Hogan | 2b6009d | 2015-02-06 23:01:00 +0000 | [diff] [blame] | 1216 | change_c0_config5(MIPS_CONF5_MSAEN, |
| 1217 | val); |
| 1218 | |
James Hogan | 6cdc65e | 2015-02-03 13:59:38 +0000 | [diff] [blame] | 1219 | preempt_enable(); |
| 1220 | |
| 1221 | kvm_write_c0_guest_config5(cop0, val); |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 1222 | } else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) { |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1223 | u32 old_cause, new_cause; |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1224 | |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 1225 | old_cause = kvm_read_c0_guest_cause(cop0); |
| 1226 | new_cause = vcpu->arch.gprs[rt]; |
| 1227 | /* Update R/W bits */ |
| 1228 | kvm_change_c0_guest_cause(cop0, 0x08800300, |
| 1229 | new_cause); |
| 1230 | /* DC bit enabling/disabling timer? */ |
| 1231 | if ((old_cause ^ new_cause) & CAUSEF_DC) { |
| 1232 | if (new_cause & CAUSEF_DC) |
| 1233 | kvm_mips_count_disable_cause(vcpu); |
| 1234 | else |
| 1235 | kvm_mips_count_enable_cause(vcpu); |
| 1236 | } |
James Hogan | cef061d0 | 2016-06-15 19:29:54 +0100 | [diff] [blame] | 1237 | } else if ((rd == MIPS_CP0_HWRENA) && (sel == 0)) { |
| 1238 | u32 mask = MIPS_HWRENA_CPUNUM | |
| 1239 | MIPS_HWRENA_SYNCISTEP | |
| 1240 | MIPS_HWRENA_CC | |
| 1241 | MIPS_HWRENA_CCRES; |
| 1242 | |
| 1243 | if (kvm_read_c0_guest_config3(cop0) & |
| 1244 | MIPS_CONF3_ULRI) |
| 1245 | mask |= MIPS_HWRENA_ULR; |
| 1246 | cop0->reg[rd][sel] = vcpu->arch.gprs[rt] & mask; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1247 | } else { |
| 1248 | cop0->reg[rd][sel] = vcpu->arch.gprs[rt]; |
| 1249 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS |
| 1250 | kvm_mips_trans_mtc0(inst, opc, vcpu); |
| 1251 | #endif |
| 1252 | } |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1253 | break; |
| 1254 | |
| 1255 | case dmtc_op: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1256 | kvm_err("!!!!!!![%#lx]dmtc_op: rt: %d, rd: %d, sel: %d!!!!!!\n", |
| 1257 | vcpu->arch.pc, rt, rd, sel); |
James Hogan | 6398da1 | 2016-06-14 09:40:15 +0100 | [diff] [blame] | 1258 | trace_kvm_hwr(vcpu, KVM_TRACE_DMTC0, |
| 1259 | KVM_TRACE_COP0(rd, sel), |
| 1260 | vcpu->arch.gprs[rt]); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1261 | er = EMULATE_FAIL; |
| 1262 | break; |
| 1263 | |
James Hogan | b2c5963 | 2015-12-16 23:49:38 +0000 | [diff] [blame] | 1264 | case mfmc0_op: |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1265 | #ifdef KVM_MIPS_DEBUG_COP0_COUNTERS |
| 1266 | cop0->stat[MIPS_CP0_STATUS][0]++; |
| 1267 | #endif |
James Hogan | caa1faa | 2015-12-16 23:49:26 +0000 | [diff] [blame] | 1268 | if (rt != 0) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1269 | vcpu->arch.gprs[rt] = |
| 1270 | kvm_read_c0_guest_status(cop0); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1271 | /* EI */ |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1272 | if (inst.mfmc0_format.sc) { |
James Hogan | b2c5963 | 2015-12-16 23:49:38 +0000 | [diff] [blame] | 1273 | kvm_debug("[%#lx] mfmc0_op: EI\n", |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1274 | vcpu->arch.pc); |
| 1275 | kvm_set_c0_guest_status(cop0, ST0_IE); |
| 1276 | } else { |
James Hogan | b2c5963 | 2015-12-16 23:49:38 +0000 | [diff] [blame] | 1277 | kvm_debug("[%#lx] mfmc0_op: DI\n", |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1278 | vcpu->arch.pc); |
| 1279 | kvm_clear_c0_guest_status(cop0, ST0_IE); |
| 1280 | } |
| 1281 | |
| 1282 | break; |
| 1283 | |
| 1284 | case wrpgpr_op: |
| 1285 | { |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1286 | u32 css = cop0->reg[MIPS_CP0_STATUS][2] & 0xf; |
| 1287 | u32 pss = |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1288 | (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf; |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1289 | /* |
| 1290 | * We don't support any shadow register sets, so |
| 1291 | * SRSCtl[PSS] == SRSCtl[CSS] = 0 |
| 1292 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1293 | if (css || pss) { |
| 1294 | er = EMULATE_FAIL; |
| 1295 | break; |
| 1296 | } |
| 1297 | kvm_debug("WRPGPR[%d][%d] = %#lx\n", pss, rd, |
| 1298 | vcpu->arch.gprs[rt]); |
| 1299 | vcpu->arch.gprs[rd] = vcpu->arch.gprs[rt]; |
| 1300 | } |
| 1301 | break; |
| 1302 | default: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1303 | kvm_err("[%#lx]MachEmulateCP0: unsupported COP0, copz: 0x%x\n", |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1304 | vcpu->arch.pc, inst.c0r_format.rs); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1305 | er = EMULATE_FAIL; |
| 1306 | break; |
| 1307 | } |
| 1308 | } |
| 1309 | |
| 1310 | done: |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1311 | /* Rollback PC only if emulation was unsuccessful */ |
| 1312 | if (er == EMULATE_FAIL) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1313 | vcpu->arch.pc = curr_pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1314 | |
| 1315 | dont_update_pc: |
| 1316 | /* |
| 1317 | * This is for special instructions whose emulation |
| 1318 | * updates the PC, so do not overwrite the PC under |
| 1319 | * any circumstances |
| 1320 | */ |
| 1321 | |
| 1322 | return er; |
| 1323 | } |
| 1324 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1325 | enum emulation_result kvm_mips_emulate_store(union mips_instruction inst, |
| 1326 | u32 cause, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1327 | struct kvm_run *run, |
| 1328 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1329 | { |
| 1330 | enum emulation_result er = EMULATE_DO_MMIO; |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1331 | u32 rt; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1332 | u32 bytes; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1333 | void *data = run->mmio.data; |
| 1334 | unsigned long curr_pc; |
| 1335 | |
| 1336 | /* |
| 1337 | * Update PC and hold onto current PC in case there is |
| 1338 | * an error and we want to rollback the PC |
| 1339 | */ |
| 1340 | curr_pc = vcpu->arch.pc; |
| 1341 | er = update_pc(vcpu, cause); |
| 1342 | if (er == EMULATE_FAIL) |
| 1343 | return er; |
| 1344 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1345 | rt = inst.i_format.rt; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1346 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1347 | switch (inst.i_format.opcode) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1348 | case sb_op: |
| 1349 | bytes = 1; |
| 1350 | if (bytes > sizeof(run->mmio.data)) { |
| 1351 | kvm_err("%s: bad MMIO length: %d\n", __func__, |
| 1352 | run->mmio.len); |
| 1353 | } |
| 1354 | run->mmio.phys_addr = |
| 1355 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. |
| 1356 | host_cp0_badvaddr); |
| 1357 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { |
| 1358 | er = EMULATE_FAIL; |
| 1359 | break; |
| 1360 | } |
| 1361 | run->mmio.len = bytes; |
| 1362 | run->mmio.is_write = 1; |
| 1363 | vcpu->mmio_needed = 1; |
| 1364 | vcpu->mmio_is_write = 1; |
| 1365 | *(u8 *) data = vcpu->arch.gprs[rt]; |
| 1366 | kvm_debug("OP_SB: eaddr: %#lx, gpr: %#lx, data: %#x\n", |
| 1367 | vcpu->arch.host_cp0_badvaddr, vcpu->arch.gprs[rt], |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1368 | *(u8 *) data); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1369 | |
| 1370 | break; |
| 1371 | |
| 1372 | case sw_op: |
| 1373 | bytes = 4; |
| 1374 | if (bytes > sizeof(run->mmio.data)) { |
| 1375 | kvm_err("%s: bad MMIO length: %d\n", __func__, |
| 1376 | run->mmio.len); |
| 1377 | } |
| 1378 | run->mmio.phys_addr = |
| 1379 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. |
| 1380 | host_cp0_badvaddr); |
| 1381 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { |
| 1382 | er = EMULATE_FAIL; |
| 1383 | break; |
| 1384 | } |
| 1385 | |
| 1386 | run->mmio.len = bytes; |
| 1387 | run->mmio.is_write = 1; |
| 1388 | vcpu->mmio_needed = 1; |
| 1389 | vcpu->mmio_is_write = 1; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1390 | *(u32 *) data = vcpu->arch.gprs[rt]; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1391 | |
| 1392 | kvm_debug("[%#lx] OP_SW: eaddr: %#lx, gpr: %#lx, data: %#x\n", |
| 1393 | vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1394 | vcpu->arch.gprs[rt], *(u32 *) data); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1395 | break; |
| 1396 | |
| 1397 | case sh_op: |
| 1398 | bytes = 2; |
| 1399 | if (bytes > sizeof(run->mmio.data)) { |
| 1400 | kvm_err("%s: bad MMIO length: %d\n", __func__, |
| 1401 | run->mmio.len); |
| 1402 | } |
| 1403 | run->mmio.phys_addr = |
| 1404 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. |
| 1405 | host_cp0_badvaddr); |
| 1406 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { |
| 1407 | er = EMULATE_FAIL; |
| 1408 | break; |
| 1409 | } |
| 1410 | |
| 1411 | run->mmio.len = bytes; |
| 1412 | run->mmio.is_write = 1; |
| 1413 | vcpu->mmio_needed = 1; |
| 1414 | vcpu->mmio_is_write = 1; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1415 | *(u16 *) data = vcpu->arch.gprs[rt]; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1416 | |
| 1417 | kvm_debug("[%#lx] OP_SH: eaddr: %#lx, gpr: %#lx, data: %#x\n", |
| 1418 | vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1419 | vcpu->arch.gprs[rt], *(u32 *) data); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1420 | break; |
| 1421 | |
| 1422 | default: |
James Hogan | d86c1eb | 2016-06-14 09:40:17 +0100 | [diff] [blame] | 1423 | kvm_err("Store not yet supported (inst=0x%08x)\n", |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1424 | inst.word); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1425 | er = EMULATE_FAIL; |
| 1426 | break; |
| 1427 | } |
| 1428 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1429 | /* Rollback PC if emulation was unsuccessful */ |
| 1430 | if (er == EMULATE_FAIL) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1431 | vcpu->arch.pc = curr_pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1432 | |
| 1433 | return er; |
| 1434 | } |
| 1435 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1436 | enum emulation_result kvm_mips_emulate_load(union mips_instruction inst, |
| 1437 | u32 cause, struct kvm_run *run, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1438 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1439 | { |
| 1440 | enum emulation_result er = EMULATE_DO_MMIO; |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1441 | u32 op, rt; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1442 | u32 bytes; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1443 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1444 | rt = inst.i_format.rt; |
| 1445 | op = inst.i_format.opcode; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1446 | |
| 1447 | vcpu->arch.pending_load_cause = cause; |
| 1448 | vcpu->arch.io_gpr = rt; |
| 1449 | |
| 1450 | switch (op) { |
| 1451 | case lw_op: |
| 1452 | bytes = 4; |
| 1453 | if (bytes > sizeof(run->mmio.data)) { |
| 1454 | kvm_err("%s: bad MMIO length: %d\n", __func__, |
| 1455 | run->mmio.len); |
| 1456 | er = EMULATE_FAIL; |
| 1457 | break; |
| 1458 | } |
| 1459 | run->mmio.phys_addr = |
| 1460 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. |
| 1461 | host_cp0_badvaddr); |
| 1462 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { |
| 1463 | er = EMULATE_FAIL; |
| 1464 | break; |
| 1465 | } |
| 1466 | |
| 1467 | run->mmio.len = bytes; |
| 1468 | run->mmio.is_write = 0; |
| 1469 | vcpu->mmio_needed = 1; |
| 1470 | vcpu->mmio_is_write = 0; |
| 1471 | break; |
| 1472 | |
| 1473 | case lh_op: |
| 1474 | case lhu_op: |
| 1475 | bytes = 2; |
| 1476 | if (bytes > sizeof(run->mmio.data)) { |
| 1477 | kvm_err("%s: bad MMIO length: %d\n", __func__, |
| 1478 | run->mmio.len); |
| 1479 | er = EMULATE_FAIL; |
| 1480 | break; |
| 1481 | } |
| 1482 | run->mmio.phys_addr = |
| 1483 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. |
| 1484 | host_cp0_badvaddr); |
| 1485 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { |
| 1486 | er = EMULATE_FAIL; |
| 1487 | break; |
| 1488 | } |
| 1489 | |
| 1490 | run->mmio.len = bytes; |
| 1491 | run->mmio.is_write = 0; |
| 1492 | vcpu->mmio_needed = 1; |
| 1493 | vcpu->mmio_is_write = 0; |
| 1494 | |
| 1495 | if (op == lh_op) |
| 1496 | vcpu->mmio_needed = 2; |
| 1497 | else |
| 1498 | vcpu->mmio_needed = 1; |
| 1499 | |
| 1500 | break; |
| 1501 | |
| 1502 | case lbu_op: |
| 1503 | case lb_op: |
| 1504 | bytes = 1; |
| 1505 | if (bytes > sizeof(run->mmio.data)) { |
| 1506 | kvm_err("%s: bad MMIO length: %d\n", __func__, |
| 1507 | run->mmio.len); |
| 1508 | er = EMULATE_FAIL; |
| 1509 | break; |
| 1510 | } |
| 1511 | run->mmio.phys_addr = |
| 1512 | kvm_mips_callbacks->gva_to_gpa(vcpu->arch. |
| 1513 | host_cp0_badvaddr); |
| 1514 | if (run->mmio.phys_addr == KVM_INVALID_ADDR) { |
| 1515 | er = EMULATE_FAIL; |
| 1516 | break; |
| 1517 | } |
| 1518 | |
| 1519 | run->mmio.len = bytes; |
| 1520 | run->mmio.is_write = 0; |
| 1521 | vcpu->mmio_is_write = 0; |
| 1522 | |
| 1523 | if (op == lb_op) |
| 1524 | vcpu->mmio_needed = 2; |
| 1525 | else |
| 1526 | vcpu->mmio_needed = 1; |
| 1527 | |
| 1528 | break; |
| 1529 | |
| 1530 | default: |
James Hogan | d86c1eb | 2016-06-14 09:40:17 +0100 | [diff] [blame] | 1531 | kvm_err("Load not yet supported (inst=0x%08x)\n", |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1532 | inst.word); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1533 | er = EMULATE_FAIL; |
| 1534 | break; |
| 1535 | } |
| 1536 | |
| 1537 | return er; |
| 1538 | } |
| 1539 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1540 | enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst, |
| 1541 | u32 *opc, u32 cause, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1542 | struct kvm_run *run, |
| 1543 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1544 | { |
| 1545 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1546 | enum emulation_result er = EMULATE_DONE; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 1547 | u32 cache, op_inst, op, base; |
| 1548 | s16 offset; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1549 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 1550 | unsigned long va; |
| 1551 | unsigned long curr_pc; |
| 1552 | |
| 1553 | /* |
| 1554 | * Update PC and hold onto current PC in case there is |
| 1555 | * an error and we want to rollback the PC |
| 1556 | */ |
| 1557 | curr_pc = vcpu->arch.pc; |
| 1558 | er = update_pc(vcpu, cause); |
| 1559 | if (er == EMULATE_FAIL) |
| 1560 | return er; |
| 1561 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1562 | base = inst.i_format.rs; |
| 1563 | op_inst = inst.i_format.rt; |
| 1564 | offset = inst.i_format.simmediate; |
James Hogan | f4956f6 | 2015-12-16 23:49:37 +0000 | [diff] [blame] | 1565 | cache = op_inst & CacheOp_Cache; |
| 1566 | op = op_inst & CacheOp_Op; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1567 | |
| 1568 | va = arch->gprs[base] + offset; |
| 1569 | |
| 1570 | kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", |
| 1571 | cache, op, base, arch->gprs[base], offset); |
| 1572 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1573 | /* |
| 1574 | * Treat INDEX_INV as a nop, basically issued by Linux on startup to |
| 1575 | * invalidate the caches entirely by stepping through all the |
| 1576 | * ways/indexes |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1577 | */ |
James Hogan | f4956f6 | 2015-12-16 23:49:37 +0000 | [diff] [blame] | 1578 | if (op == Index_Writeback_Inv) { |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1579 | kvm_debug("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", |
| 1580 | vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base, |
| 1581 | arch->gprs[base], offset); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1582 | |
James Hogan | f4956f6 | 2015-12-16 23:49:37 +0000 | [diff] [blame] | 1583 | if (cache == Cache_D) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1584 | r4k_blast_dcache(); |
James Hogan | f4956f6 | 2015-12-16 23:49:37 +0000 | [diff] [blame] | 1585 | else if (cache == Cache_I) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1586 | r4k_blast_icache(); |
| 1587 | else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1588 | kvm_err("%s: unsupported CACHE INDEX operation\n", |
| 1589 | __func__); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1590 | return EMULATE_FAIL; |
| 1591 | } |
| 1592 | |
| 1593 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS |
| 1594 | kvm_mips_trans_cache_index(inst, opc, vcpu); |
| 1595 | #endif |
| 1596 | goto done; |
| 1597 | } |
| 1598 | |
| 1599 | preempt_disable(); |
| 1600 | if (KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG0) { |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1601 | if (kvm_mips_host_tlb_lookup(vcpu, va) < 0) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1602 | kvm_mips_handle_kseg0_tlb_fault(va, vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1603 | } else if ((KVM_GUEST_KSEGX(va) < KVM_GUEST_KSEG0) || |
| 1604 | KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG23) { |
| 1605 | int index; |
| 1606 | |
| 1607 | /* If an entry already exists then skip */ |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1608 | if (kvm_mips_host_tlb_lookup(vcpu, va) >= 0) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1609 | goto skip_fault; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1610 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1611 | /* |
| 1612 | * If address not in the guest TLB, then give the guest a fault, |
| 1613 | * the resulting handler will do the right thing |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1614 | */ |
| 1615 | index = kvm_mips_guest_tlb_lookup(vcpu, (va & VPN2_MASK) | |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 1616 | (kvm_read_c0_guest_entryhi |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1617 | (cop0) & KVM_ENTRYHI_ASID)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1618 | |
| 1619 | if (index < 0) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1620 | vcpu->arch.host_cp0_badvaddr = va; |
James Hogan | 6df82a7 | 2016-06-09 10:50:46 +0100 | [diff] [blame] | 1621 | vcpu->arch.pc = curr_pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1622 | er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run, |
| 1623 | vcpu); |
| 1624 | preempt_enable(); |
| 1625 | goto dont_update_pc; |
| 1626 | } else { |
| 1627 | struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index]; |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1628 | /* |
| 1629 | * Check if the entry is valid, if not then setup a TLB |
| 1630 | * invalid exception to the guest |
| 1631 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1632 | if (!TLB_IS_VALID(*tlb, va)) { |
James Hogan | 6df82a7 | 2016-06-09 10:50:46 +0100 | [diff] [blame] | 1633 | vcpu->arch.host_cp0_badvaddr = va; |
| 1634 | vcpu->arch.pc = curr_pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1635 | er = kvm_mips_emulate_tlbinv_ld(cause, NULL, |
| 1636 | run, vcpu); |
| 1637 | preempt_enable(); |
| 1638 | goto dont_update_pc; |
| 1639 | } else { |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1640 | /* |
| 1641 | * We fault an entry from the guest tlb to the |
| 1642 | * shadow host TLB |
| 1643 | */ |
James Hogan | 26ee17f | 2016-06-09 14:19:13 +0100 | [diff] [blame] | 1644 | kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1645 | } |
| 1646 | } |
| 1647 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1648 | kvm_err("INVALID CACHE INDEX/ADDRESS (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", |
| 1649 | cache, op, base, arch->gprs[base], offset); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1650 | er = EMULATE_FAIL; |
| 1651 | preempt_enable(); |
James Hogan | cc81e94 | 2016-06-09 10:50:45 +0100 | [diff] [blame] | 1652 | goto done; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1653 | |
| 1654 | } |
| 1655 | |
| 1656 | skip_fault: |
| 1657 | /* XXXKYMA: Only a subset of cache ops are supported, used by Linux */ |
James Hogan | f4956f6 | 2015-12-16 23:49:37 +0000 | [diff] [blame] | 1658 | if (op_inst == Hit_Writeback_Inv_D || op_inst == Hit_Invalidate_D) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1659 | flush_dcache_line(va); |
| 1660 | |
| 1661 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1662 | /* |
| 1663 | * Replace the CACHE instruction, with a SYNCI, not the same, |
| 1664 | * but avoids a trap |
| 1665 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1666 | kvm_mips_trans_cache_va(inst, opc, vcpu); |
| 1667 | #endif |
James Hogan | f4956f6 | 2015-12-16 23:49:37 +0000 | [diff] [blame] | 1668 | } else if (op_inst == Hit_Invalidate_I) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1669 | flush_dcache_line(va); |
| 1670 | flush_icache_line(va); |
| 1671 | |
| 1672 | #ifdef CONFIG_KVM_MIPS_DYN_TRANS |
| 1673 | /* Replace the CACHE instruction, with a SYNCI */ |
| 1674 | kvm_mips_trans_cache_va(inst, opc, vcpu); |
| 1675 | #endif |
| 1676 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1677 | kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", |
| 1678 | cache, op, base, arch->gprs[base], offset); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1679 | er = EMULATE_FAIL; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1680 | } |
| 1681 | |
| 1682 | preempt_enable(); |
James Hogan | cc81e94 | 2016-06-09 10:50:45 +0100 | [diff] [blame] | 1683 | done: |
| 1684 | /* Rollback PC only if emulation was unsuccessful */ |
| 1685 | if (er == EMULATE_FAIL) |
| 1686 | vcpu->arch.pc = curr_pc; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1687 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1688 | dont_update_pc: |
James Hogan | cc81e94 | 2016-06-09 10:50:45 +0100 | [diff] [blame] | 1689 | /* |
| 1690 | * This is for exceptions whose emulation updates the PC, so do not |
| 1691 | * overwrite the PC under any circumstances |
| 1692 | */ |
| 1693 | |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1694 | return er; |
| 1695 | } |
| 1696 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1697 | enum emulation_result kvm_mips_emulate_inst(u32 cause, u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1698 | struct kvm_run *run, |
| 1699 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1700 | { |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1701 | union mips_instruction inst; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1702 | enum emulation_result er = EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1703 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1704 | /* Fetch the instruction. */ |
| 1705 | if (cause & CAUSEF_BD) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1706 | opc += 1; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1707 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1708 | inst.word = kvm_get_inst(opc, vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1709 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1710 | switch (inst.r_format.opcode) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1711 | case cop0_op: |
| 1712 | er = kvm_mips_emulate_CP0(inst, opc, cause, run, vcpu); |
| 1713 | break; |
| 1714 | case sb_op: |
| 1715 | case sh_op: |
| 1716 | case sw_op: |
| 1717 | er = kvm_mips_emulate_store(inst, cause, run, vcpu); |
| 1718 | break; |
| 1719 | case lb_op: |
| 1720 | case lbu_op: |
| 1721 | case lhu_op: |
| 1722 | case lh_op: |
| 1723 | case lw_op: |
| 1724 | er = kvm_mips_emulate_load(inst, cause, run, vcpu); |
| 1725 | break; |
| 1726 | |
| 1727 | case cache_op: |
| 1728 | ++vcpu->stat.cache_exits; |
James Hogan | 1e09e86 | 2016-06-14 09:40:12 +0100 | [diff] [blame] | 1729 | trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1730 | er = kvm_mips_emulate_cache(inst, opc, cause, run, vcpu); |
| 1731 | break; |
| 1732 | |
| 1733 | default: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1734 | kvm_err("Instruction emulation not supported (%p/%#x)\n", opc, |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 1735 | inst.word); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1736 | kvm_arch_vcpu_dump_regs(vcpu); |
| 1737 | er = EMULATE_FAIL; |
| 1738 | break; |
| 1739 | } |
| 1740 | |
| 1741 | return er; |
| 1742 | } |
| 1743 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1744 | enum emulation_result kvm_mips_emulate_syscall(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 1745 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1746 | struct kvm_run *run, |
| 1747 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1748 | { |
| 1749 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 1750 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 1751 | enum emulation_result er = EMULATE_DONE; |
| 1752 | |
| 1753 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 1754 | /* save old pc */ |
| 1755 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 1756 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 1757 | |
| 1758 | if (cause & CAUSEF_BD) |
| 1759 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 1760 | else |
| 1761 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 1762 | |
| 1763 | kvm_debug("Delivering SYSCALL @ pc %#lx\n", arch->pc); |
| 1764 | |
| 1765 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 1766 | (EXCCODE_SYS << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1767 | |
| 1768 | /* Set PC to the exception entry point */ |
| 1769 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 1770 | |
| 1771 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 1772 | kvm_err("Trying to deliver SYSCALL when EXL is already set\n"); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1773 | er = EMULATE_FAIL; |
| 1774 | } |
| 1775 | |
| 1776 | return er; |
| 1777 | } |
| 1778 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1779 | enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 1780 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1781 | struct kvm_run *run, |
| 1782 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1783 | { |
| 1784 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 1785 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1786 | unsigned long entryhi = (vcpu->arch. host_cp0_badvaddr & VPN2_MASK) | |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1787 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1788 | |
| 1789 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 1790 | /* save old pc */ |
| 1791 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 1792 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 1793 | |
| 1794 | if (cause & CAUSEF_BD) |
| 1795 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 1796 | else |
| 1797 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 1798 | |
| 1799 | kvm_debug("[EXL == 0] delivering TLB MISS @ pc %#lx\n", |
| 1800 | arch->pc); |
| 1801 | |
| 1802 | /* set pc to the exception entry point */ |
| 1803 | arch->pc = KVM_GUEST_KSEG0 + 0x0; |
| 1804 | |
| 1805 | } else { |
| 1806 | kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n", |
| 1807 | arch->pc); |
| 1808 | |
| 1809 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 1810 | } |
| 1811 | |
| 1812 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 1813 | (EXCCODE_TLBL << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1814 | |
| 1815 | /* setup badvaddr, context and entryhi registers for the guest */ |
| 1816 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); |
| 1817 | /* XXXKYMA: is the context register used by linux??? */ |
| 1818 | kvm_write_c0_guest_entryhi(cop0, entryhi); |
| 1819 | /* Blow away the shadow host TLBs */ |
| 1820 | kvm_mips_flush_host_tlb(1); |
| 1821 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 1822 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1823 | } |
| 1824 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1825 | enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 1826 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1827 | struct kvm_run *run, |
| 1828 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1829 | { |
| 1830 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 1831 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1832 | unsigned long entryhi = |
| 1833 | (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1834 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1835 | |
| 1836 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 1837 | /* save old pc */ |
| 1838 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 1839 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 1840 | |
| 1841 | if (cause & CAUSEF_BD) |
| 1842 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 1843 | else |
| 1844 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 1845 | |
| 1846 | kvm_debug("[EXL == 0] delivering TLB INV @ pc %#lx\n", |
| 1847 | arch->pc); |
| 1848 | |
| 1849 | /* set pc to the exception entry point */ |
| 1850 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 1851 | |
| 1852 | } else { |
| 1853 | kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n", |
| 1854 | arch->pc); |
| 1855 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 1856 | } |
| 1857 | |
| 1858 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 1859 | (EXCCODE_TLBL << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1860 | |
| 1861 | /* setup badvaddr, context and entryhi registers for the guest */ |
| 1862 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); |
| 1863 | /* XXXKYMA: is the context register used by linux??? */ |
| 1864 | kvm_write_c0_guest_entryhi(cop0, entryhi); |
| 1865 | /* Blow away the shadow host TLBs */ |
| 1866 | kvm_mips_flush_host_tlb(1); |
| 1867 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 1868 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1869 | } |
| 1870 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1871 | enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 1872 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1873 | struct kvm_run *run, |
| 1874 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1875 | { |
| 1876 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 1877 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1878 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1879 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1880 | |
| 1881 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 1882 | /* save old pc */ |
| 1883 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 1884 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 1885 | |
| 1886 | if (cause & CAUSEF_BD) |
| 1887 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 1888 | else |
| 1889 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 1890 | |
| 1891 | kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n", |
| 1892 | arch->pc); |
| 1893 | |
| 1894 | /* Set PC to the exception entry point */ |
| 1895 | arch->pc = KVM_GUEST_KSEG0 + 0x0; |
| 1896 | } else { |
| 1897 | kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n", |
| 1898 | arch->pc); |
| 1899 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 1900 | } |
| 1901 | |
| 1902 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 1903 | (EXCCODE_TLBS << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1904 | |
| 1905 | /* setup badvaddr, context and entryhi registers for the guest */ |
| 1906 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); |
| 1907 | /* XXXKYMA: is the context register used by linux??? */ |
| 1908 | kvm_write_c0_guest_entryhi(cop0, entryhi); |
| 1909 | /* Blow away the shadow host TLBs */ |
| 1910 | kvm_mips_flush_host_tlb(1); |
| 1911 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 1912 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1913 | } |
| 1914 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1915 | enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 1916 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1917 | struct kvm_run *run, |
| 1918 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1919 | { |
| 1920 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 1921 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1922 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1923 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1924 | |
| 1925 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 1926 | /* save old pc */ |
| 1927 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 1928 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 1929 | |
| 1930 | if (cause & CAUSEF_BD) |
| 1931 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 1932 | else |
| 1933 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 1934 | |
| 1935 | kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n", |
| 1936 | arch->pc); |
| 1937 | |
| 1938 | /* Set PC to the exception entry point */ |
| 1939 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 1940 | } else { |
| 1941 | kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n", |
| 1942 | arch->pc); |
| 1943 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 1944 | } |
| 1945 | |
| 1946 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 1947 | (EXCCODE_TLBS << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1948 | |
| 1949 | /* setup badvaddr, context and entryhi registers for the guest */ |
| 1950 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); |
| 1951 | /* XXXKYMA: is the context register used by linux??? */ |
| 1952 | kvm_write_c0_guest_entryhi(cop0, entryhi); |
| 1953 | /* Blow away the shadow host TLBs */ |
| 1954 | kvm_mips_flush_host_tlb(1); |
| 1955 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 1956 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1957 | } |
| 1958 | |
| 1959 | /* TLBMOD: store into address matching TLB with Dirty bit off */ |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1960 | enum emulation_result kvm_mips_handle_tlbmod(u32 cause, u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1961 | struct kvm_run *run, |
| 1962 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1963 | { |
| 1964 | enum emulation_result er = EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1965 | #ifdef DEBUG |
James Hogan | 3d65483 | 2014-05-29 10:16:41 +0100 | [diff] [blame] | 1966 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 1967 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1968 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
James Hogan | 3d65483 | 2014-05-29 10:16:41 +0100 | [diff] [blame] | 1969 | int index; |
| 1970 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1971 | /* If address not in the guest TLB, then we are in trouble */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1972 | index = kvm_mips_guest_tlb_lookup(vcpu, entryhi); |
| 1973 | if (index < 0) { |
| 1974 | /* XXXKYMA Invalidate and retry */ |
| 1975 | kvm_mips_host_tlb_inv(vcpu, vcpu->arch.host_cp0_badvaddr); |
| 1976 | kvm_err("%s: host got TLBMOD for %#lx but entry not present in Guest TLB\n", |
| 1977 | __func__, entryhi); |
| 1978 | kvm_mips_dump_guest_tlbs(vcpu); |
| 1979 | kvm_mips_dump_host_tlbs(); |
| 1980 | return EMULATE_FAIL; |
| 1981 | } |
| 1982 | #endif |
| 1983 | |
| 1984 | er = kvm_mips_emulate_tlbmod(cause, opc, run, vcpu); |
| 1985 | return er; |
| 1986 | } |
| 1987 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 1988 | enum emulation_result kvm_mips_emulate_tlbmod(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 1989 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 1990 | struct kvm_run *run, |
| 1991 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1992 | { |
| 1993 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 1994 | unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) | |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 1995 | (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1996 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 1997 | |
| 1998 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 1999 | /* save old pc */ |
| 2000 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2001 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2002 | |
| 2003 | if (cause & CAUSEF_BD) |
| 2004 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2005 | else |
| 2006 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2007 | |
| 2008 | kvm_debug("[EXL == 0] Delivering TLB MOD @ pc %#lx\n", |
| 2009 | arch->pc); |
| 2010 | |
| 2011 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2012 | } else { |
| 2013 | kvm_debug("[EXL == 1] Delivering TLB MOD @ pc %#lx\n", |
| 2014 | arch->pc); |
| 2015 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2016 | } |
| 2017 | |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2018 | kvm_change_c0_guest_cause(cop0, (0xff), |
| 2019 | (EXCCODE_MOD << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2020 | |
| 2021 | /* setup badvaddr, context and entryhi registers for the guest */ |
| 2022 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); |
| 2023 | /* XXXKYMA: is the context register used by linux??? */ |
| 2024 | kvm_write_c0_guest_entryhi(cop0, entryhi); |
| 2025 | /* Blow away the shadow host TLBs */ |
| 2026 | kvm_mips_flush_host_tlb(1); |
| 2027 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 2028 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2029 | } |
| 2030 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2031 | enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2032 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2033 | struct kvm_run *run, |
| 2034 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2035 | { |
| 2036 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2037 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2038 | |
| 2039 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2040 | /* save old pc */ |
| 2041 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2042 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2043 | |
| 2044 | if (cause & CAUSEF_BD) |
| 2045 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2046 | else |
| 2047 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2048 | |
| 2049 | } |
| 2050 | |
| 2051 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2052 | |
| 2053 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2054 | (EXCCODE_CPU << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2055 | kvm_change_c0_guest_cause(cop0, (CAUSEF_CE), (0x1 << CAUSEB_CE)); |
| 2056 | |
Deng-Cheng Zhu | d98403a | 2014-06-26 12:11:36 -0700 | [diff] [blame] | 2057 | return EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2058 | } |
| 2059 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2060 | enum emulation_result kvm_mips_emulate_ri_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2061 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2062 | struct kvm_run *run, |
| 2063 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2064 | { |
| 2065 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2066 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2067 | enum emulation_result er = EMULATE_DONE; |
| 2068 | |
| 2069 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2070 | /* save old pc */ |
| 2071 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2072 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2073 | |
| 2074 | if (cause & CAUSEF_BD) |
| 2075 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2076 | else |
| 2077 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2078 | |
| 2079 | kvm_debug("Delivering RI @ pc %#lx\n", arch->pc); |
| 2080 | |
| 2081 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2082 | (EXCCODE_RI << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2083 | |
| 2084 | /* Set PC to the exception entry point */ |
| 2085 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2086 | |
| 2087 | } else { |
| 2088 | kvm_err("Trying to deliver RI when EXL is already set\n"); |
| 2089 | er = EMULATE_FAIL; |
| 2090 | } |
| 2091 | |
| 2092 | return er; |
| 2093 | } |
| 2094 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2095 | enum emulation_result kvm_mips_emulate_bp_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2096 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2097 | struct kvm_run *run, |
| 2098 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2099 | { |
| 2100 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2101 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2102 | enum emulation_result er = EMULATE_DONE; |
| 2103 | |
| 2104 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2105 | /* save old pc */ |
| 2106 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2107 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2108 | |
| 2109 | if (cause & CAUSEF_BD) |
| 2110 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2111 | else |
| 2112 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2113 | |
| 2114 | kvm_debug("Delivering BP @ pc %#lx\n", arch->pc); |
| 2115 | |
| 2116 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2117 | (EXCCODE_BP << CAUSEB_EXCCODE)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2118 | |
| 2119 | /* Set PC to the exception entry point */ |
| 2120 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2121 | |
| 2122 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2123 | kvm_err("Trying to deliver BP when EXL is already set\n"); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2124 | er = EMULATE_FAIL; |
| 2125 | } |
| 2126 | |
| 2127 | return er; |
| 2128 | } |
| 2129 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2130 | enum emulation_result kvm_mips_emulate_trap_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2131 | u32 *opc, |
James Hogan | 0a56042 | 2015-02-06 16:03:57 +0000 | [diff] [blame] | 2132 | struct kvm_run *run, |
| 2133 | struct kvm_vcpu *vcpu) |
| 2134 | { |
| 2135 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2136 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2137 | enum emulation_result er = EMULATE_DONE; |
| 2138 | |
| 2139 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2140 | /* save old pc */ |
| 2141 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2142 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2143 | |
| 2144 | if (cause & CAUSEF_BD) |
| 2145 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2146 | else |
| 2147 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2148 | |
| 2149 | kvm_debug("Delivering TRAP @ pc %#lx\n", arch->pc); |
| 2150 | |
| 2151 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2152 | (EXCCODE_TR << CAUSEB_EXCCODE)); |
James Hogan | 0a56042 | 2015-02-06 16:03:57 +0000 | [diff] [blame] | 2153 | |
| 2154 | /* Set PC to the exception entry point */ |
| 2155 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2156 | |
| 2157 | } else { |
| 2158 | kvm_err("Trying to deliver TRAP when EXL is already set\n"); |
| 2159 | er = EMULATE_FAIL; |
| 2160 | } |
| 2161 | |
| 2162 | return er; |
| 2163 | } |
| 2164 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2165 | enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2166 | u32 *opc, |
James Hogan | c2537ed | 2015-02-06 10:56:27 +0000 | [diff] [blame] | 2167 | struct kvm_run *run, |
| 2168 | struct kvm_vcpu *vcpu) |
| 2169 | { |
| 2170 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2171 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2172 | enum emulation_result er = EMULATE_DONE; |
| 2173 | |
| 2174 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2175 | /* save old pc */ |
| 2176 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2177 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2178 | |
| 2179 | if (cause & CAUSEF_BD) |
| 2180 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2181 | else |
| 2182 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2183 | |
| 2184 | kvm_debug("Delivering MSAFPE @ pc %#lx\n", arch->pc); |
| 2185 | |
| 2186 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2187 | (EXCCODE_MSAFPE << CAUSEB_EXCCODE)); |
James Hogan | c2537ed | 2015-02-06 10:56:27 +0000 | [diff] [blame] | 2188 | |
| 2189 | /* Set PC to the exception entry point */ |
| 2190 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2191 | |
| 2192 | } else { |
| 2193 | kvm_err("Trying to deliver MSAFPE when EXL is already set\n"); |
| 2194 | er = EMULATE_FAIL; |
| 2195 | } |
| 2196 | |
| 2197 | return er; |
| 2198 | } |
| 2199 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2200 | enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2201 | u32 *opc, |
James Hogan | 1c0cd66 | 2015-02-06 10:56:27 +0000 | [diff] [blame] | 2202 | struct kvm_run *run, |
| 2203 | struct kvm_vcpu *vcpu) |
| 2204 | { |
| 2205 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2206 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2207 | enum emulation_result er = EMULATE_DONE; |
| 2208 | |
| 2209 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2210 | /* save old pc */ |
| 2211 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2212 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2213 | |
| 2214 | if (cause & CAUSEF_BD) |
| 2215 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2216 | else |
| 2217 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2218 | |
| 2219 | kvm_debug("Delivering FPE @ pc %#lx\n", arch->pc); |
| 2220 | |
| 2221 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2222 | (EXCCODE_FPE << CAUSEB_EXCCODE)); |
James Hogan | 1c0cd66 | 2015-02-06 10:56:27 +0000 | [diff] [blame] | 2223 | |
| 2224 | /* Set PC to the exception entry point */ |
| 2225 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2226 | |
| 2227 | } else { |
| 2228 | kvm_err("Trying to deliver FPE when EXL is already set\n"); |
| 2229 | er = EMULATE_FAIL; |
| 2230 | } |
| 2231 | |
| 2232 | return er; |
| 2233 | } |
| 2234 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2235 | enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2236 | u32 *opc, |
James Hogan | c2537ed | 2015-02-06 10:56:27 +0000 | [diff] [blame] | 2237 | struct kvm_run *run, |
| 2238 | struct kvm_vcpu *vcpu) |
| 2239 | { |
| 2240 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2241 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2242 | enum emulation_result er = EMULATE_DONE; |
| 2243 | |
| 2244 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2245 | /* save old pc */ |
| 2246 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2247 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2248 | |
| 2249 | if (cause & CAUSEF_BD) |
| 2250 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2251 | else |
| 2252 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2253 | |
| 2254 | kvm_debug("Delivering MSADIS @ pc %#lx\n", arch->pc); |
| 2255 | |
| 2256 | kvm_change_c0_guest_cause(cop0, (0xff), |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2257 | (EXCCODE_MSADIS << CAUSEB_EXCCODE)); |
James Hogan | c2537ed | 2015-02-06 10:56:27 +0000 | [diff] [blame] | 2258 | |
| 2259 | /* Set PC to the exception entry point */ |
| 2260 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2261 | |
| 2262 | } else { |
| 2263 | kvm_err("Trying to deliver MSADIS when EXL is already set\n"); |
| 2264 | er = EMULATE_FAIL; |
| 2265 | } |
| 2266 | |
| 2267 | return er; |
| 2268 | } |
| 2269 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2270 | enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2271 | struct kvm_run *run, |
| 2272 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2273 | { |
| 2274 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2275 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2276 | enum emulation_result er = EMULATE_DONE; |
| 2277 | unsigned long curr_pc; |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 2278 | union mips_instruction inst; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2279 | |
| 2280 | /* |
| 2281 | * Update PC and hold onto current PC in case there is |
| 2282 | * an error and we want to rollback the PC |
| 2283 | */ |
| 2284 | curr_pc = vcpu->arch.pc; |
| 2285 | er = update_pc(vcpu, cause); |
| 2286 | if (er == EMULATE_FAIL) |
| 2287 | return er; |
| 2288 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2289 | /* Fetch the instruction. */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2290 | if (cause & CAUSEF_BD) |
| 2291 | opc += 1; |
| 2292 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 2293 | inst.word = kvm_get_inst(opc, vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2294 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 2295 | if (inst.word == KVM_INVALID_INST) { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2296 | kvm_err("%s: Cannot get inst @ %p\n", __func__, opc); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2297 | return EMULATE_FAIL; |
| 2298 | } |
| 2299 | |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 2300 | if (inst.r_format.opcode == spec3_op && |
| 2301 | inst.r_format.func == rdhwr_op) { |
James Hogan | 26f4f3b | 2014-03-14 13:06:09 +0000 | [diff] [blame] | 2302 | int usermode = !KVM_GUEST_KERNEL_MODE(vcpu); |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 2303 | int rd = inst.r_format.rd; |
| 2304 | int rt = inst.r_format.rt; |
| 2305 | int sel = inst.r_format.re & 0x7; |
James Hogan | 6398da1 | 2016-06-14 09:40:15 +0100 | [diff] [blame] | 2306 | |
James Hogan | 26f4f3b | 2014-03-14 13:06:09 +0000 | [diff] [blame] | 2307 | /* If usermode, check RDHWR rd is allowed by guest HWREna */ |
| 2308 | if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) { |
| 2309 | kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n", |
| 2310 | rd, opc); |
| 2311 | goto emulate_ri; |
| 2312 | } |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2313 | switch (rd) { |
James Hogan | aff565a | 2016-06-15 19:29:52 +0100 | [diff] [blame] | 2314 | case MIPS_HWR_CPUNUM: /* CPU number */ |
James Hogan | cf1fb0f | 2016-06-15 19:29:55 +0100 | [diff] [blame] | 2315 | arch->gprs[rt] = vcpu->vcpu_id; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2316 | break; |
James Hogan | aff565a | 2016-06-15 19:29:52 +0100 | [diff] [blame] | 2317 | case MIPS_HWR_SYNCISTEP: /* SYNCI length */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2318 | arch->gprs[rt] = min(current_cpu_data.dcache.linesz, |
| 2319 | current_cpu_data.icache.linesz); |
| 2320 | break; |
James Hogan | aff565a | 2016-06-15 19:29:52 +0100 | [diff] [blame] | 2321 | case MIPS_HWR_CC: /* Read count register */ |
James Hogan | e30492b | 2014-05-29 10:16:35 +0100 | [diff] [blame] | 2322 | arch->gprs[rt] = kvm_mips_read_count(vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2323 | break; |
James Hogan | aff565a | 2016-06-15 19:29:52 +0100 | [diff] [blame] | 2324 | case MIPS_HWR_CCRES: /* Count register resolution */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2325 | switch (current_cpu_data.cputype) { |
| 2326 | case CPU_20KC: |
| 2327 | case CPU_25KF: |
| 2328 | arch->gprs[rt] = 1; |
| 2329 | break; |
| 2330 | default: |
| 2331 | arch->gprs[rt] = 2; |
| 2332 | } |
| 2333 | break; |
James Hogan | aff565a | 2016-06-15 19:29:52 +0100 | [diff] [blame] | 2334 | case MIPS_HWR_ULR: /* Read UserLocal register */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2335 | arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2336 | break; |
| 2337 | |
| 2338 | default: |
James Hogan | 1550567 | 2014-03-14 13:06:07 +0000 | [diff] [blame] | 2339 | kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc); |
James Hogan | 26f4f3b | 2014-03-14 13:06:09 +0000 | [diff] [blame] | 2340 | goto emulate_ri; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2341 | } |
James Hogan | 6398da1 | 2016-06-14 09:40:15 +0100 | [diff] [blame] | 2342 | |
| 2343 | trace_kvm_hwr(vcpu, KVM_TRACE_RDHWR, KVM_TRACE_HWR(rd, sel), |
| 2344 | vcpu->arch.gprs[rt]); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2345 | } else { |
James Hogan | 258f3a2 | 2016-06-15 19:29:47 +0100 | [diff] [blame] | 2346 | kvm_debug("Emulate RI not supported @ %p: %#x\n", |
| 2347 | opc, inst.word); |
James Hogan | 26f4f3b | 2014-03-14 13:06:09 +0000 | [diff] [blame] | 2348 | goto emulate_ri; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2349 | } |
| 2350 | |
James Hogan | 26f4f3b | 2014-03-14 13:06:09 +0000 | [diff] [blame] | 2351 | return EMULATE_DONE; |
| 2352 | |
| 2353 | emulate_ri: |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2354 | /* |
James Hogan | 26f4f3b | 2014-03-14 13:06:09 +0000 | [diff] [blame] | 2355 | * Rollback PC (if in branch delay slot then the PC already points to |
| 2356 | * branch target), and pass the RI exception to the guest OS. |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2357 | */ |
James Hogan | 26f4f3b | 2014-03-14 13:06:09 +0000 | [diff] [blame] | 2358 | vcpu->arch.pc = curr_pc; |
| 2359 | return kvm_mips_emulate_ri_exc(cause, opc, run, vcpu); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2360 | } |
| 2361 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2362 | enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu, |
| 2363 | struct kvm_run *run) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2364 | { |
| 2365 | unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr]; |
| 2366 | enum emulation_result er = EMULATE_DONE; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2367 | |
| 2368 | if (run->mmio.len > sizeof(*gpr)) { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2369 | kvm_err("Bad MMIO length: %d", run->mmio.len); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2370 | er = EMULATE_FAIL; |
| 2371 | goto done; |
| 2372 | } |
| 2373 | |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2374 | er = update_pc(vcpu, vcpu->arch.pending_load_cause); |
| 2375 | if (er == EMULATE_FAIL) |
| 2376 | return er; |
| 2377 | |
| 2378 | switch (run->mmio.len) { |
| 2379 | case 4: |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 2380 | *gpr = *(s32 *) run->mmio.data; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2381 | break; |
| 2382 | |
| 2383 | case 2: |
| 2384 | if (vcpu->mmio_needed == 2) |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 2385 | *gpr = *(s16 *) run->mmio.data; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2386 | else |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 2387 | *gpr = *(u16 *)run->mmio.data; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2388 | |
| 2389 | break; |
| 2390 | case 1: |
| 2391 | if (vcpu->mmio_needed == 2) |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 2392 | *gpr = *(s8 *) run->mmio.data; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2393 | else |
| 2394 | *gpr = *(u8 *) run->mmio.data; |
| 2395 | break; |
| 2396 | } |
| 2397 | |
| 2398 | if (vcpu->arch.pending_load_cause & CAUSEF_BD) |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2399 | kvm_debug("[%#lx] Completing %d byte BD Load to gpr %d (0x%08lx) type %d\n", |
| 2400 | vcpu->arch.pc, run->mmio.len, vcpu->arch.io_gpr, *gpr, |
| 2401 | vcpu->mmio_needed); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2402 | |
| 2403 | done: |
| 2404 | return er; |
| 2405 | } |
| 2406 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2407 | static enum emulation_result kvm_mips_emulate_exc(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2408 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2409 | struct kvm_run *run, |
| 2410 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2411 | { |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 2412 | u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2413 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
| 2414 | struct kvm_vcpu_arch *arch = &vcpu->arch; |
| 2415 | enum emulation_result er = EMULATE_DONE; |
| 2416 | |
| 2417 | if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) { |
| 2418 | /* save old pc */ |
| 2419 | kvm_write_c0_guest_epc(cop0, arch->pc); |
| 2420 | kvm_set_c0_guest_status(cop0, ST0_EXL); |
| 2421 | |
| 2422 | if (cause & CAUSEF_BD) |
| 2423 | kvm_set_c0_guest_cause(cop0, CAUSEF_BD); |
| 2424 | else |
| 2425 | kvm_clear_c0_guest_cause(cop0, CAUSEF_BD); |
| 2426 | |
| 2427 | kvm_change_c0_guest_cause(cop0, (0xff), |
| 2428 | (exccode << CAUSEB_EXCCODE)); |
| 2429 | |
| 2430 | /* Set PC to the exception entry point */ |
| 2431 | arch->pc = KVM_GUEST_KSEG0 + 0x180; |
| 2432 | kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr); |
| 2433 | |
| 2434 | kvm_debug("Delivering EXC %d @ pc %#lx, badVaddr: %#lx\n", |
| 2435 | exccode, kvm_read_c0_guest_epc(cop0), |
| 2436 | kvm_read_c0_guest_badvaddr(cop0)); |
| 2437 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2438 | kvm_err("Trying to deliver EXC when EXL is already set\n"); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2439 | er = EMULATE_FAIL; |
| 2440 | } |
| 2441 | |
| 2442 | return er; |
| 2443 | } |
| 2444 | |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2445 | enum emulation_result kvm_mips_check_privilege(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2446 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2447 | struct kvm_run *run, |
| 2448 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2449 | { |
| 2450 | enum emulation_result er = EMULATE_DONE; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 2451 | u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2452 | unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; |
| 2453 | |
| 2454 | int usermode = !KVM_GUEST_KERNEL_MODE(vcpu); |
| 2455 | |
| 2456 | if (usermode) { |
| 2457 | switch (exccode) { |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2458 | case EXCCODE_INT: |
| 2459 | case EXCCODE_SYS: |
| 2460 | case EXCCODE_BP: |
| 2461 | case EXCCODE_RI: |
| 2462 | case EXCCODE_TR: |
| 2463 | case EXCCODE_MSAFPE: |
| 2464 | case EXCCODE_FPE: |
| 2465 | case EXCCODE_MSADIS: |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2466 | break; |
| 2467 | |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2468 | case EXCCODE_CPU: |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2469 | if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 0) |
| 2470 | er = EMULATE_PRIV_FAIL; |
| 2471 | break; |
| 2472 | |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2473 | case EXCCODE_MOD: |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2474 | break; |
| 2475 | |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2476 | case EXCCODE_TLBL: |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2477 | /* |
| 2478 | * We we are accessing Guest kernel space, then send an |
| 2479 | * address error exception to the guest |
| 2480 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2481 | if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2482 | kvm_debug("%s: LD MISS @ %#lx\n", __func__, |
| 2483 | badvaddr); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2484 | cause &= ~0xff; |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2485 | cause |= (EXCCODE_ADEL << CAUSEB_EXCCODE); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2486 | er = EMULATE_PRIV_FAIL; |
| 2487 | } |
| 2488 | break; |
| 2489 | |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2490 | case EXCCODE_TLBS: |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2491 | /* |
| 2492 | * We we are accessing Guest kernel space, then send an |
| 2493 | * address error exception to the guest |
| 2494 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2495 | if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2496 | kvm_debug("%s: ST MISS @ %#lx\n", __func__, |
| 2497 | badvaddr); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2498 | cause &= ~0xff; |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2499 | cause |= (EXCCODE_ADES << CAUSEB_EXCCODE); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2500 | er = EMULATE_PRIV_FAIL; |
| 2501 | } |
| 2502 | break; |
| 2503 | |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2504 | case EXCCODE_ADES: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2505 | kvm_debug("%s: address error ST @ %#lx\n", __func__, |
| 2506 | badvaddr); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2507 | if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) { |
| 2508 | cause &= ~0xff; |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2509 | cause |= (EXCCODE_TLBS << CAUSEB_EXCCODE); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2510 | } |
| 2511 | er = EMULATE_PRIV_FAIL; |
| 2512 | break; |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2513 | case EXCCODE_ADEL: |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2514 | kvm_debug("%s: address error LD @ %#lx\n", __func__, |
| 2515 | badvaddr); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2516 | if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) { |
| 2517 | cause &= ~0xff; |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2518 | cause |= (EXCCODE_TLBL << CAUSEB_EXCCODE); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2519 | } |
| 2520 | er = EMULATE_PRIV_FAIL; |
| 2521 | break; |
| 2522 | default: |
| 2523 | er = EMULATE_PRIV_FAIL; |
| 2524 | break; |
| 2525 | } |
| 2526 | } |
| 2527 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2528 | if (er == EMULATE_PRIV_FAIL) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2529 | kvm_mips_emulate_exc(cause, opc, run, vcpu); |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2530 | |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2531 | return er; |
| 2532 | } |
| 2533 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2534 | /* |
| 2535 | * User Address (UA) fault, this could happen if |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2536 | * (1) TLB entry not present/valid in both Guest and shadow host TLBs, in this |
| 2537 | * case we pass on the fault to the guest kernel and let it handle it. |
| 2538 | * (2) TLB entry is present in the Guest TLB but not in the shadow, in this |
| 2539 | * case we inject the TLB from the Guest TLB into the shadow host TLB |
| 2540 | */ |
James Hogan | 31cf749 | 2016-06-09 14:19:09 +0100 | [diff] [blame] | 2541 | enum emulation_result kvm_mips_handle_tlbmiss(u32 cause, |
James Hogan | bdb7ed8 | 2016-06-09 14:19:07 +0100 | [diff] [blame] | 2542 | u32 *opc, |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2543 | struct kvm_run *run, |
| 2544 | struct kvm_vcpu *vcpu) |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2545 | { |
| 2546 | enum emulation_result er = EMULATE_DONE; |
James Hogan | 8cffd19 | 2016-06-09 14:19:08 +0100 | [diff] [blame] | 2547 | u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2548 | unsigned long va = vcpu->arch.host_cp0_badvaddr; |
| 2549 | int index; |
| 2550 | |
James Hogan | e4e94c0 | 2016-06-09 14:19:05 +0100 | [diff] [blame] | 2551 | kvm_debug("kvm_mips_handle_tlbmiss: badvaddr: %#lx\n", |
| 2552 | vcpu->arch.host_cp0_badvaddr); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2553 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2554 | /* |
| 2555 | * KVM would not have got the exception if this entry was valid in the |
| 2556 | * shadow host TLB. Check the Guest TLB, if the entry is not there then |
| 2557 | * send the guest an exception. The guest exc handler should then inject |
| 2558 | * an entry into the guest TLB. |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2559 | */ |
| 2560 | index = kvm_mips_guest_tlb_lookup(vcpu, |
James Hogan | caa1faa | 2015-12-16 23:49:26 +0000 | [diff] [blame] | 2561 | (va & VPN2_MASK) | |
Paul Burton | ca64c2b | 2016-05-06 14:36:20 +0100 | [diff] [blame] | 2562 | (kvm_read_c0_guest_entryhi(vcpu->arch.cop0) & |
| 2563 | KVM_ENTRYHI_ASID)); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2564 | if (index < 0) { |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2565 | if (exccode == EXCCODE_TLBL) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2566 | er = kvm_mips_emulate_tlbmiss_ld(cause, opc, run, vcpu); |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2567 | } else if (exccode == EXCCODE_TLBS) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2568 | er = kvm_mips_emulate_tlbmiss_st(cause, opc, run, vcpu); |
| 2569 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2570 | kvm_err("%s: invalid exc code: %d\n", __func__, |
| 2571 | exccode); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2572 | er = EMULATE_FAIL; |
| 2573 | } |
| 2574 | } else { |
| 2575 | struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index]; |
| 2576 | |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2577 | /* |
| 2578 | * Check if the entry is valid, if not then setup a TLB invalid |
| 2579 | * exception to the guest |
| 2580 | */ |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2581 | if (!TLB_IS_VALID(*tlb, va)) { |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2582 | if (exccode == EXCCODE_TLBL) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2583 | er = kvm_mips_emulate_tlbinv_ld(cause, opc, run, |
| 2584 | vcpu); |
James Hogan | 16d100db | 2015-12-16 23:49:33 +0000 | [diff] [blame] | 2585 | } else if (exccode == EXCCODE_TLBS) { |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2586 | er = kvm_mips_emulate_tlbinv_st(cause, opc, run, |
| 2587 | vcpu); |
| 2588 | } else { |
Deng-Cheng Zhu | 6ad78a5 | 2014-06-26 12:11:35 -0700 | [diff] [blame] | 2589 | kvm_err("%s: invalid exc code: %d\n", __func__, |
| 2590 | exccode); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2591 | er = EMULATE_FAIL; |
| 2592 | } |
| 2593 | } else { |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2594 | kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n", |
James Hogan | 9fbfb06 | 2016-06-09 14:19:17 +0100 | [diff] [blame] | 2595 | tlb->tlb_hi, tlb->tlb_lo[0], tlb->tlb_lo[1]); |
Deng-Cheng Zhu | d116e81 | 2014-06-26 12:11:34 -0700 | [diff] [blame] | 2596 | /* |
| 2597 | * OK we have a Guest TLB entry, now inject it into the |
| 2598 | * shadow host TLB |
| 2599 | */ |
James Hogan | 26ee17f | 2016-06-09 14:19:13 +0100 | [diff] [blame] | 2600 | kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb); |
Sanjay Lal | e685c68 | 2012-11-21 18:34:04 -0800 | [diff] [blame] | 2601 | } |
| 2602 | } |
| 2603 | |
| 2604 | return er; |
| 2605 | } |