blob: 6dbdad2b8f88693ffe9f31a9885f9e49059f19bc [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 */
8
9#ifndef _T3_H
10#define _T3_H
11
12#define TG3_64BIT_REG_HIGH 0x00UL
13#define TG3_64BIT_REG_LOW 0x04UL
14
15/* Descriptor block info. */
16#define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
17#define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
18#define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
19#define BDINFO_FLAGS_DISABLED 0x00000002
20#define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
21#define BDINFO_FLAGS_MAXLEN_SHIFT 16
22#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
23#define TG3_BDINFO_SIZE 0x10UL
24
25#define RX_COPY_THRESHOLD 256
26
Michael Chanb5d37722006-09-27 16:06:21 -070027#define TG3_RX_INTERNAL_RING_SZ_5906 32
28
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#define RX_STD_MAX_SIZE 1536
30#define RX_STD_MAX_SIZE_5705 512
31#define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
32
33/* First 256 bytes are a mirror of PCI config space. */
34#define TG3PCI_VENDOR 0x00000000
35#define TG3PCI_VENDOR_BROADCOM 0x14e4
36#define TG3PCI_DEVICE 0x00000002
37#define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
38#define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
39#define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
40#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
41#define TG3PCI_COMMAND 0x00000004
42#define TG3PCI_STATUS 0x00000006
43#define TG3PCI_CCREVID 0x00000008
44#define TG3PCI_CACHELINESZ 0x0000000c
45#define TG3PCI_LATTIMER 0x0000000d
46#define TG3PCI_HEADERTYPE 0x0000000e
47#define TG3PCI_BIST 0x0000000f
48#define TG3PCI_BASE0_LOW 0x00000010
49#define TG3PCI_BASE0_HIGH 0x00000014
50/* 0x18 --> 0x2c unused */
51#define TG3PCI_SUBSYSVENID 0x0000002c
52#define TG3PCI_SUBSYSID 0x0000002e
53#define TG3PCI_ROMADDR 0x00000030
54#define TG3PCI_CAPLIST 0x00000034
55/* 0x35 --> 0x3c unused */
56#define TG3PCI_IRQ_LINE 0x0000003c
57#define TG3PCI_IRQ_PIN 0x0000003d
58#define TG3PCI_MIN_GNT 0x0000003e
59#define TG3PCI_MAX_LAT 0x0000003f
Matt Carlson9974a352007-10-07 23:27:28 -070060/* 0x40 --> 0x64 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -070061#define TG3PCI_MSI_DATA 0x00000064
62/* 0x66 --> 0x68 unused */
63#define TG3PCI_MISC_HOST_CTRL 0x00000068
64#define MISC_HOST_CTRL_CLEAR_INT 0x00000001
65#define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
66#define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
67#define MISC_HOST_CTRL_WORD_SWAP 0x00000008
68#define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
69#define MISC_HOST_CTRL_CLKREG_RW 0x00000020
70#define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
71#define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
72#define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
73#define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
74#define MISC_HOST_CTRL_CHIPREV 0xffff0000
75#define MISC_HOST_CTRL_CHIPREV_SHIFT 16
76#define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
77 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
78 MISC_HOST_CTRL_CHIPREV_SHIFT)
79#define CHIPREV_ID_5700_A0 0x7000
80#define CHIPREV_ID_5700_A1 0x7001
81#define CHIPREV_ID_5700_B0 0x7100
82#define CHIPREV_ID_5700_B1 0x7101
83#define CHIPREV_ID_5700_B3 0x7102
84#define CHIPREV_ID_5700_ALTIMA 0x7104
85#define CHIPREV_ID_5700_C0 0x7200
86#define CHIPREV_ID_5701_A0 0x0000
87#define CHIPREV_ID_5701_B0 0x0100
88#define CHIPREV_ID_5701_B2 0x0102
89#define CHIPREV_ID_5701_B5 0x0105
90#define CHIPREV_ID_5703_A0 0x1000
91#define CHIPREV_ID_5703_A1 0x1001
92#define CHIPREV_ID_5703_A2 0x1002
93#define CHIPREV_ID_5703_A3 0x1003
94#define CHIPREV_ID_5704_A0 0x2000
95#define CHIPREV_ID_5704_A1 0x2001
96#define CHIPREV_ID_5704_A2 0x2002
97#define CHIPREV_ID_5704_A3 0x2003
98#define CHIPREV_ID_5705_A0 0x3000
99#define CHIPREV_ID_5705_A1 0x3001
100#define CHIPREV_ID_5705_A2 0x3002
101#define CHIPREV_ID_5705_A3 0x3003
102#define CHIPREV_ID_5750_A0 0x4000
103#define CHIPREV_ID_5750_A1 0x4001
104#define CHIPREV_ID_5750_A3 0x4003
Michael Chan52c0fd82006-06-29 20:15:54 -0700105#define CHIPREV_ID_5750_C2 0x4202
Michael Chanff645be2005-04-21 17:09:53 -0700106#define CHIPREV_ID_5752_A0_HW 0x5000
107#define CHIPREV_ID_5752_A0 0x6000
John W. Linville053d7802005-04-21 17:03:52 -0700108#define CHIPREV_ID_5752_A1 0x6001
Michael Chan7544b092007-05-05 13:08:32 -0700109#define CHIPREV_ID_5714_A2 0x9002
Michael Chanb5d37722006-09-27 16:06:21 -0700110#define CHIPREV_ID_5906_A1 0xc001
Matt Carlsond30cdd22007-10-07 23:28:35 -0700111#define CHIPREV_ID_5784_A0 0x5784000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
113#define ASIC_REV_5700 0x07
114#define ASIC_REV_5701 0x00
115#define ASIC_REV_5703 0x01
116#define ASIC_REV_5704 0x02
117#define ASIC_REV_5705 0x03
118#define ASIC_REV_5750 0x04
Michael Chanff645be2005-04-21 17:09:53 -0700119#define ASIC_REV_5752 0x06
Michael Chan4cf78e42005-07-25 12:29:19 -0700120#define ASIC_REV_5780 0x08
Michael Chana4e2b342005-10-26 15:46:52 -0700121#define ASIC_REV_5714 0x09
Michael Chanaf36e6b2006-03-23 01:28:06 -0800122#define ASIC_REV_5755 0x0a
Michael Chand9ab5ad2006-03-20 22:27:35 -0800123#define ASIC_REV_5787 0x0b
Michael Chanb5d37722006-09-27 16:06:21 -0700124#define ASIC_REV_5906 0x0c
Matt Carlson795d01c2007-10-07 23:28:17 -0700125#define ASIC_REV_USE_PROD_ID_REG 0x0f
Matt Carlsond30cdd22007-10-07 23:28:35 -0700126#define ASIC_REV_5784 0x5784
Matt Carlson6b91fa02007-10-10 18:01:09 -0700127#define ASIC_REV_5761 0x5761
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
129#define CHIPREV_5700_AX 0x70
130#define CHIPREV_5700_BX 0x71
131#define CHIPREV_5700_CX 0x72
132#define CHIPREV_5701_AX 0x00
133#define CHIPREV_5703_AX 0x10
134#define CHIPREV_5704_AX 0x20
135#define CHIPREV_5704_BX 0x21
136#define CHIPREV_5750_AX 0x40
137#define CHIPREV_5750_BX 0x41
138#define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
139#define METAL_REV_A0 0x00
140#define METAL_REV_A1 0x01
141#define METAL_REV_B0 0x00
142#define METAL_REV_B1 0x01
143#define METAL_REV_B2 0x02
144#define TG3PCI_DMA_RW_CTRL 0x0000006c
145#define DMA_RWCTRL_MIN_DMA 0x000000ff
146#define DMA_RWCTRL_MIN_DMA_SHIFT 0
147#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
148#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
149#define DMA_RWCTRL_READ_BNDRY_16 0x00000100
150#define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
151#define DMA_RWCTRL_READ_BNDRY_32 0x00000200
152#define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
153#define DMA_RWCTRL_READ_BNDRY_64 0x00000300
154#define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
155#define DMA_RWCTRL_READ_BNDRY_128 0x00000400
156#define DMA_RWCTRL_READ_BNDRY_256 0x00000500
157#define DMA_RWCTRL_READ_BNDRY_512 0x00000600
158#define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
159#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
160#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
161#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
162#define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
163#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
164#define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
165#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
166#define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
167#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
168#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
169#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
170#define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
171#define DMA_RWCTRL_ONE_DMA 0x00004000
172#define DMA_RWCTRL_READ_WATER 0x00070000
173#define DMA_RWCTRL_READ_WATER_SHIFT 16
174#define DMA_RWCTRL_WRITE_WATER 0x00380000
175#define DMA_RWCTRL_WRITE_WATER_SHIFT 19
176#define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
177#define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
178#define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
179#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
180#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
181#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
182#define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
183#define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
184#define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
185#define TG3PCI_PCISTATE 0x00000070
186#define PCISTATE_FORCE_RESET 0x00000001
187#define PCISTATE_INT_NOT_ACTIVE 0x00000002
188#define PCISTATE_CONV_PCI_MODE 0x00000004
189#define PCISTATE_BUS_SPEED_HIGH 0x00000008
190#define PCISTATE_BUS_32BIT 0x00000010
191#define PCISTATE_ROM_ENABLE 0x00000020
192#define PCISTATE_ROM_RETRY_ENABLE 0x00000040
193#define PCISTATE_FLAT_VIEW 0x00000100
194#define PCISTATE_RETRY_SAME_DMA 0x00002000
Matt Carlson0d3031d2007-10-10 18:02:43 -0700195#define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
196#define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197#define TG3PCI_CLOCK_CTRL 0x00000074
198#define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
199#define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
200#define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
201#define CLOCK_CTRL_ALTCLK 0x00001000
202#define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
203#define CLOCK_CTRL_44MHZ_CORE 0x00040000
204#define CLOCK_CTRL_625_CORE 0x00100000
205#define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
206#define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
207#define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
208#define TG3PCI_REG_BASE_ADDR 0x00000078
209#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
210#define TG3PCI_REG_DATA 0x00000080
211#define TG3PCI_MEM_WIN_DATA 0x00000084
212#define TG3PCI_MODE_CTRL 0x00000088
213#define TG3PCI_MISC_CFG 0x0000008c
214#define TG3PCI_MISC_LOCAL_CTRL 0x00000090
215/* 0x94 --> 0x98 unused */
216#define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
217#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
218#define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */
219/* 0xb0 --> 0xb8 unused */
220#define TG3PCI_DUAL_MAC_CTRL 0x000000b8
221#define DUAL_MAC_CTRL_CH_MASK 0x00000003
222#define DUAL_MAC_CTRL_ID 0x00000004
Matt Carlson795d01c2007-10-07 23:28:17 -0700223#define TG3PCI_PRODID_ASICREV 0x000000bc
224#define PROD_ID_ASIC_REV_MASK 0x0fffffff
225/* 0xc0 --> 0x100 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226
227/* 0x100 --> 0x200 unused */
228
229/* Mailbox registers */
230#define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
231#define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
232#define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
233#define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
234#define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
235#define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
236#define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
237#define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
238#define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
239#define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
240#define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
241#define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
242#define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
243#define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
244#define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
245#define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
246#define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
247#define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
248#define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
249#define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
250#define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
251#define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
252#define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
253#define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
254#define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
255#define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
256#define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
257#define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
258#define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
259#define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
260#define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
261#define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
262#define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
263#define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
264#define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
265#define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
266#define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
267#define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
268#define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
269#define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
270#define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
271#define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
272#define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
273#define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
274#define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
275#define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
276#define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
277#define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
278#define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
279#define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
280#define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
281#define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
282#define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
283#define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
284#define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
285#define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
286#define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
287#define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
288#define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
289#define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
290#define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
291#define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
292#define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
293#define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
294
295/* MAC control registers */
296#define MAC_MODE 0x00000400
297#define MAC_MODE_RESET 0x00000001
298#define MAC_MODE_HALF_DUPLEX 0x00000002
299#define MAC_MODE_PORT_MODE_MASK 0x0000000c
300#define MAC_MODE_PORT_MODE_TBI 0x0000000c
301#define MAC_MODE_PORT_MODE_GMII 0x00000008
302#define MAC_MODE_PORT_MODE_MII 0x00000004
303#define MAC_MODE_PORT_MODE_NONE 0x00000000
304#define MAC_MODE_PORT_INT_LPBACK 0x00000010
305#define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
306#define MAC_MODE_TX_BURSTING 0x00000100
307#define MAC_MODE_MAX_DEFER 0x00000200
308#define MAC_MODE_LINK_POLARITY 0x00000400
309#define MAC_MODE_RXSTAT_ENABLE 0x00000800
310#define MAC_MODE_RXSTAT_CLEAR 0x00001000
311#define MAC_MODE_RXSTAT_FLUSH 0x00002000
312#define MAC_MODE_TXSTAT_ENABLE 0x00004000
313#define MAC_MODE_TXSTAT_CLEAR 0x00008000
314#define MAC_MODE_TXSTAT_FLUSH 0x00010000
315#define MAC_MODE_SEND_CONFIGS 0x00020000
316#define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
317#define MAC_MODE_ACPI_ENABLE 0x00080000
318#define MAC_MODE_MIP_ENABLE 0x00100000
319#define MAC_MODE_TDE_ENABLE 0x00200000
320#define MAC_MODE_RDE_ENABLE 0x00400000
321#define MAC_MODE_FHDE_ENABLE 0x00800000
322#define MAC_STATUS 0x00000404
323#define MAC_STATUS_PCS_SYNCED 0x00000001
324#define MAC_STATUS_SIGNAL_DET 0x00000002
325#define MAC_STATUS_RCVD_CFG 0x00000004
326#define MAC_STATUS_CFG_CHANGED 0x00000008
327#define MAC_STATUS_SYNC_CHANGED 0x00000010
328#define MAC_STATUS_PORT_DEC_ERR 0x00000400
329#define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
330#define MAC_STATUS_MI_COMPLETION 0x00400000
331#define MAC_STATUS_MI_INTERRUPT 0x00800000
332#define MAC_STATUS_AP_ERROR 0x01000000
333#define MAC_STATUS_ODI_ERROR 0x02000000
334#define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
335#define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
336#define MAC_EVENT 0x00000408
337#define MAC_EVENT_PORT_DECODE_ERR 0x00000400
338#define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
339#define MAC_EVENT_MI_COMPLETION 0x00400000
340#define MAC_EVENT_MI_INTERRUPT 0x00800000
341#define MAC_EVENT_AP_ERROR 0x01000000
342#define MAC_EVENT_ODI_ERROR 0x02000000
343#define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
344#define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
345#define MAC_LED_CTRL 0x0000040c
346#define LED_CTRL_LNKLED_OVERRIDE 0x00000001
347#define LED_CTRL_1000MBPS_ON 0x00000002
348#define LED_CTRL_100MBPS_ON 0x00000004
349#define LED_CTRL_10MBPS_ON 0x00000008
350#define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
351#define LED_CTRL_TRAFFIC_BLINK 0x00000020
352#define LED_CTRL_TRAFFIC_LED 0x00000040
353#define LED_CTRL_1000MBPS_STATUS 0x00000080
354#define LED_CTRL_100MBPS_STATUS 0x00000100
355#define LED_CTRL_10MBPS_STATUS 0x00000200
356#define LED_CTRL_TRAFFIC_STATUS 0x00000400
357#define LED_CTRL_MODE_MAC 0x00000000
358#define LED_CTRL_MODE_PHY_1 0x00000800
359#define LED_CTRL_MODE_PHY_2 0x00001000
360#define LED_CTRL_MODE_SHASTA_MAC 0x00002000
361#define LED_CTRL_MODE_SHARED 0x00004000
362#define LED_CTRL_MODE_COMBO 0x00008000
363#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
364#define LED_CTRL_BLINK_RATE_SHIFT 19
365#define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
366#define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
367#define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
368#define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
369#define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
370#define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
371#define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
372#define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
373#define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
374#define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
375#define MAC_ACPI_MBUF_PTR 0x00000430
376#define MAC_ACPI_LEN_OFFSET 0x00000434
377#define ACPI_LENOFF_LEN_MASK 0x0000ffff
378#define ACPI_LENOFF_LEN_SHIFT 0
379#define ACPI_LENOFF_OFF_MASK 0x0fff0000
380#define ACPI_LENOFF_OFF_SHIFT 16
381#define MAC_TX_BACKOFF_SEED 0x00000438
382#define TX_BACKOFF_SEED_MASK 0x000003ff
383#define MAC_RX_MTU_SIZE 0x0000043c
384#define RX_MTU_SIZE_MASK 0x0000ffff
385#define MAC_PCS_TEST 0x00000440
386#define PCS_TEST_PATTERN_MASK 0x000fffff
387#define PCS_TEST_PATTERN_SHIFT 0
388#define PCS_TEST_ENABLE 0x00100000
389#define MAC_TX_AUTO_NEG 0x00000444
390#define TX_AUTO_NEG_MASK 0x0000ffff
391#define TX_AUTO_NEG_SHIFT 0
392#define MAC_RX_AUTO_NEG 0x00000448
393#define RX_AUTO_NEG_MASK 0x0000ffff
394#define RX_AUTO_NEG_SHIFT 0
395#define MAC_MI_COM 0x0000044c
396#define MI_COM_CMD_MASK 0x0c000000
397#define MI_COM_CMD_WRITE 0x04000000
398#define MI_COM_CMD_READ 0x08000000
399#define MI_COM_READ_FAILED 0x10000000
400#define MI_COM_START 0x20000000
401#define MI_COM_BUSY 0x20000000
402#define MI_COM_PHY_ADDR_MASK 0x03e00000
403#define MI_COM_PHY_ADDR_SHIFT 21
404#define MI_COM_REG_ADDR_MASK 0x001f0000
405#define MI_COM_REG_ADDR_SHIFT 16
406#define MI_COM_DATA_MASK 0x0000ffff
407#define MAC_MI_STAT 0x00000450
408#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
409#define MAC_MI_MODE 0x00000454
410#define MAC_MI_MODE_CLK_10MHZ 0x00000001
411#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
412#define MAC_MI_MODE_AUTO_POLL 0x00000010
413#define MAC_MI_MODE_CORE_CLK_62MHZ 0x00008000
414#define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
415#define MAC_AUTO_POLL_STATUS 0x00000458
416#define MAC_AUTO_POLL_ERROR 0x00000001
417#define MAC_TX_MODE 0x0000045c
418#define TX_MODE_RESET 0x00000001
419#define TX_MODE_ENABLE 0x00000002
420#define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
421#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
422#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
423#define MAC_TX_STATUS 0x00000460
424#define TX_STATUS_XOFFED 0x00000001
425#define TX_STATUS_SENT_XOFF 0x00000002
426#define TX_STATUS_SENT_XON 0x00000004
427#define TX_STATUS_LINK_UP 0x00000008
428#define TX_STATUS_ODI_UNDERRUN 0x00000010
429#define TX_STATUS_ODI_OVERRUN 0x00000020
430#define MAC_TX_LENGTHS 0x00000464
431#define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
432#define TX_LENGTHS_SLOT_TIME_SHIFT 0
433#define TX_LENGTHS_IPG_MASK 0x00000f00
434#define TX_LENGTHS_IPG_SHIFT 8
435#define TX_LENGTHS_IPG_CRS_MASK 0x00003000
436#define TX_LENGTHS_IPG_CRS_SHIFT 12
437#define MAC_RX_MODE 0x00000468
438#define RX_MODE_RESET 0x00000001
439#define RX_MODE_ENABLE 0x00000002
440#define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
441#define RX_MODE_KEEP_MAC_CTRL 0x00000008
442#define RX_MODE_KEEP_PAUSE 0x00000010
443#define RX_MODE_ACCEPT_OVERSIZED 0x00000020
444#define RX_MODE_ACCEPT_RUNTS 0x00000040
445#define RX_MODE_LEN_CHECK 0x00000080
446#define RX_MODE_PROMISC 0x00000100
447#define RX_MODE_NO_CRC_CHECK 0x00000200
448#define RX_MODE_KEEP_VLAN_TAG 0x00000400
Michael Chanaf36e6b2006-03-23 01:28:06 -0800449#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450#define MAC_RX_STATUS 0x0000046c
451#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
452#define RX_STATUS_XOFF_RCVD 0x00000002
453#define RX_STATUS_XON_RCVD 0x00000004
454#define MAC_HASH_REG_0 0x00000470
455#define MAC_HASH_REG_1 0x00000474
456#define MAC_HASH_REG_2 0x00000478
457#define MAC_HASH_REG_3 0x0000047c
458#define MAC_RCV_RULE_0 0x00000480
459#define MAC_RCV_VALUE_0 0x00000484
460#define MAC_RCV_RULE_1 0x00000488
461#define MAC_RCV_VALUE_1 0x0000048c
462#define MAC_RCV_RULE_2 0x00000490
463#define MAC_RCV_VALUE_2 0x00000494
464#define MAC_RCV_RULE_3 0x00000498
465#define MAC_RCV_VALUE_3 0x0000049c
466#define MAC_RCV_RULE_4 0x000004a0
467#define MAC_RCV_VALUE_4 0x000004a4
468#define MAC_RCV_RULE_5 0x000004a8
469#define MAC_RCV_VALUE_5 0x000004ac
470#define MAC_RCV_RULE_6 0x000004b0
471#define MAC_RCV_VALUE_6 0x000004b4
472#define MAC_RCV_RULE_7 0x000004b8
473#define MAC_RCV_VALUE_7 0x000004bc
474#define MAC_RCV_RULE_8 0x000004c0
475#define MAC_RCV_VALUE_8 0x000004c4
476#define MAC_RCV_RULE_9 0x000004c8
477#define MAC_RCV_VALUE_9 0x000004cc
478#define MAC_RCV_RULE_10 0x000004d0
479#define MAC_RCV_VALUE_10 0x000004d4
480#define MAC_RCV_RULE_11 0x000004d8
481#define MAC_RCV_VALUE_11 0x000004dc
482#define MAC_RCV_RULE_12 0x000004e0
483#define MAC_RCV_VALUE_12 0x000004e4
484#define MAC_RCV_RULE_13 0x000004e8
485#define MAC_RCV_VALUE_13 0x000004ec
486#define MAC_RCV_RULE_14 0x000004f0
487#define MAC_RCV_VALUE_14 0x000004f4
488#define MAC_RCV_RULE_15 0x000004f8
489#define MAC_RCV_VALUE_15 0x000004fc
490#define RCV_RULE_DISABLE_MASK 0x7fffffff
491#define MAC_RCV_RULE_CFG 0x00000500
492#define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
493#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
494/* 0x508 --> 0x520 unused */
495#define MAC_HASHREGU_0 0x00000520
496#define MAC_HASHREGU_1 0x00000524
497#define MAC_HASHREGU_2 0x00000528
498#define MAC_HASHREGU_3 0x0000052c
499#define MAC_EXTADDR_0_HIGH 0x00000530
500#define MAC_EXTADDR_0_LOW 0x00000534
501#define MAC_EXTADDR_1_HIGH 0x00000538
502#define MAC_EXTADDR_1_LOW 0x0000053c
503#define MAC_EXTADDR_2_HIGH 0x00000540
504#define MAC_EXTADDR_2_LOW 0x00000544
505#define MAC_EXTADDR_3_HIGH 0x00000548
506#define MAC_EXTADDR_3_LOW 0x0000054c
507#define MAC_EXTADDR_4_HIGH 0x00000550
508#define MAC_EXTADDR_4_LOW 0x00000554
509#define MAC_EXTADDR_5_HIGH 0x00000558
510#define MAC_EXTADDR_5_LOW 0x0000055c
511#define MAC_EXTADDR_6_HIGH 0x00000560
512#define MAC_EXTADDR_6_LOW 0x00000564
513#define MAC_EXTADDR_7_HIGH 0x00000568
514#define MAC_EXTADDR_7_LOW 0x0000056c
515#define MAC_EXTADDR_8_HIGH 0x00000570
516#define MAC_EXTADDR_8_LOW 0x00000574
517#define MAC_EXTADDR_9_HIGH 0x00000578
518#define MAC_EXTADDR_9_LOW 0x0000057c
519#define MAC_EXTADDR_10_HIGH 0x00000580
520#define MAC_EXTADDR_10_LOW 0x00000584
521#define MAC_EXTADDR_11_HIGH 0x00000588
522#define MAC_EXTADDR_11_LOW 0x0000058c
523#define MAC_SERDES_CFG 0x00000590
524#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
525#define MAC_SERDES_STAT 0x00000594
526/* 0x598 --> 0x5b0 unused */
Michael Chana4e2b342005-10-26 15:46:52 -0700527#define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
528#define SERDES_RX_SIG_DETECT 0x00000400
Linus Torvalds1da177e2005-04-16 15:20:36 -0700529#define SG_DIG_CTRL 0x000005b0
530#define SG_DIG_USING_HW_AUTONEG 0x80000000
531#define SG_DIG_SOFT_RESET 0x40000000
532#define SG_DIG_DISABLE_LINKRDY 0x20000000
533#define SG_DIG_CRC16_CLEAR_N 0x01000000
534#define SG_DIG_EN10B 0x00800000
535#define SG_DIG_CLEAR_STATUS 0x00400000
536#define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
537#define SG_DIG_LOCAL_LINK_STATUS 0x00100000
538#define SG_DIG_SPEED_STATUS_MASK 0x000c0000
539#define SG_DIG_SPEED_STATUS_SHIFT 18
540#define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
541#define SG_DIG_RESTART_AUTONEG 0x00010000
542#define SG_DIG_FIBER_MODE 0x00008000
543#define SG_DIG_REMOTE_FAULT_MASK 0x00006000
544#define SG_DIG_PAUSE_MASK 0x00001800
545#define SG_DIG_GBIC_ENABLE 0x00000400
546#define SG_DIG_CHECK_END_ENABLE 0x00000200
547#define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
548#define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
549#define SG_DIG_GMII_INPUT_SELECT 0x00000040
550#define SG_DIG_MRADV_CRC16_SELECT 0x00000020
551#define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
552#define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
553#define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
554#define SG_DIG_REMOTE_LOOPBACK 0x00000002
555#define SG_DIG_LOOPBACK 0x00000001
556#define SG_DIG_STATUS 0x000005b4
557#define SG_DIG_CRC16_BUS_MASK 0xffff0000
558#define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
559#define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
560#define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
561#define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
562#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
563#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
564#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
565#define SG_DIG_COMMA_DETECTOR 0x00000008
566#define SG_DIG_MAC_ACK_STATUS 0x00000004
567#define SG_DIG_AUTONEG_COMPLETE 0x00000002
568#define SG_DIG_AUTONEG_ERROR 0x00000001
569/* 0x5b8 --> 0x600 unused */
570#define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
571#define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
572/* 0x624 --> 0x800 unused */
573#define MAC_TX_STATS_OCTETS 0x00000800
574#define MAC_TX_STATS_RESV1 0x00000804
575#define MAC_TX_STATS_COLLISIONS 0x00000808
576#define MAC_TX_STATS_XON_SENT 0x0000080c
577#define MAC_TX_STATS_XOFF_SENT 0x00000810
578#define MAC_TX_STATS_RESV2 0x00000814
579#define MAC_TX_STATS_MAC_ERRORS 0x00000818
580#define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
581#define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
582#define MAC_TX_STATS_DEFERRED 0x00000824
583#define MAC_TX_STATS_RESV3 0x00000828
584#define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
585#define MAC_TX_STATS_LATE_COL 0x00000830
586#define MAC_TX_STATS_RESV4_1 0x00000834
587#define MAC_TX_STATS_RESV4_2 0x00000838
588#define MAC_TX_STATS_RESV4_3 0x0000083c
589#define MAC_TX_STATS_RESV4_4 0x00000840
590#define MAC_TX_STATS_RESV4_5 0x00000844
591#define MAC_TX_STATS_RESV4_6 0x00000848
592#define MAC_TX_STATS_RESV4_7 0x0000084c
593#define MAC_TX_STATS_RESV4_8 0x00000850
594#define MAC_TX_STATS_RESV4_9 0x00000854
595#define MAC_TX_STATS_RESV4_10 0x00000858
596#define MAC_TX_STATS_RESV4_11 0x0000085c
597#define MAC_TX_STATS_RESV4_12 0x00000860
598#define MAC_TX_STATS_RESV4_13 0x00000864
599#define MAC_TX_STATS_RESV4_14 0x00000868
600#define MAC_TX_STATS_UCAST 0x0000086c
601#define MAC_TX_STATS_MCAST 0x00000870
602#define MAC_TX_STATS_BCAST 0x00000874
603#define MAC_TX_STATS_RESV5_1 0x00000878
604#define MAC_TX_STATS_RESV5_2 0x0000087c
605#define MAC_RX_STATS_OCTETS 0x00000880
606#define MAC_RX_STATS_RESV1 0x00000884
607#define MAC_RX_STATS_FRAGMENTS 0x00000888
608#define MAC_RX_STATS_UCAST 0x0000088c
609#define MAC_RX_STATS_MCAST 0x00000890
610#define MAC_RX_STATS_BCAST 0x00000894
611#define MAC_RX_STATS_FCS_ERRORS 0x00000898
612#define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
613#define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
614#define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
615#define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
616#define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
617#define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
618#define MAC_RX_STATS_JABBERS 0x000008b4
619#define MAC_RX_STATS_UNDERSIZE 0x000008b8
620/* 0x8bc --> 0xc00 unused */
621
622/* Send data initiator control registers */
623#define SNDDATAI_MODE 0x00000c00
624#define SNDDATAI_MODE_RESET 0x00000001
625#define SNDDATAI_MODE_ENABLE 0x00000002
626#define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
627#define SNDDATAI_STATUS 0x00000c04
628#define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
629#define SNDDATAI_STATSCTRL 0x00000c08
630#define SNDDATAI_SCTRL_ENABLE 0x00000001
631#define SNDDATAI_SCTRL_FASTUPD 0x00000002
632#define SNDDATAI_SCTRL_CLEAR 0x00000004
633#define SNDDATAI_SCTRL_FLUSH 0x00000008
634#define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
635#define SNDDATAI_STATSENAB 0x00000c0c
636#define SNDDATAI_STATSINCMASK 0x00000c10
Michael Chanb5d37722006-09-27 16:06:21 -0700637#define ISO_PKT_TX 0x00000c20
638/* 0xc24 --> 0xc80 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639#define SNDDATAI_COS_CNT_0 0x00000c80
640#define SNDDATAI_COS_CNT_1 0x00000c84
641#define SNDDATAI_COS_CNT_2 0x00000c88
642#define SNDDATAI_COS_CNT_3 0x00000c8c
643#define SNDDATAI_COS_CNT_4 0x00000c90
644#define SNDDATAI_COS_CNT_5 0x00000c94
645#define SNDDATAI_COS_CNT_6 0x00000c98
646#define SNDDATAI_COS_CNT_7 0x00000c9c
647#define SNDDATAI_COS_CNT_8 0x00000ca0
648#define SNDDATAI_COS_CNT_9 0x00000ca4
649#define SNDDATAI_COS_CNT_10 0x00000ca8
650#define SNDDATAI_COS_CNT_11 0x00000cac
651#define SNDDATAI_COS_CNT_12 0x00000cb0
652#define SNDDATAI_COS_CNT_13 0x00000cb4
653#define SNDDATAI_COS_CNT_14 0x00000cb8
654#define SNDDATAI_COS_CNT_15 0x00000cbc
655#define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
656#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
657#define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
658#define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
659#define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
660#define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
661#define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
662#define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
663/* 0xce0 --> 0x1000 unused */
664
665/* Send data completion control registers */
666#define SNDDATAC_MODE 0x00001000
667#define SNDDATAC_MODE_RESET 0x00000001
668#define SNDDATAC_MODE_ENABLE 0x00000002
Matt Carlson9936bcf2007-10-10 18:03:07 -0700669#define SNDDATAC_MODE_CDELAY 0x00000010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670/* 0x1004 --> 0x1400 unused */
671
672/* Send BD ring selector */
673#define SNDBDS_MODE 0x00001400
674#define SNDBDS_MODE_RESET 0x00000001
675#define SNDBDS_MODE_ENABLE 0x00000002
676#define SNDBDS_MODE_ATTN_ENABLE 0x00000004
677#define SNDBDS_STATUS 0x00001404
678#define SNDBDS_STATUS_ERROR_ATTN 0x00000004
679#define SNDBDS_HWDIAG 0x00001408
680/* 0x140c --> 0x1440 */
681#define SNDBDS_SEL_CON_IDX_0 0x00001440
682#define SNDBDS_SEL_CON_IDX_1 0x00001444
683#define SNDBDS_SEL_CON_IDX_2 0x00001448
684#define SNDBDS_SEL_CON_IDX_3 0x0000144c
685#define SNDBDS_SEL_CON_IDX_4 0x00001450
686#define SNDBDS_SEL_CON_IDX_5 0x00001454
687#define SNDBDS_SEL_CON_IDX_6 0x00001458
688#define SNDBDS_SEL_CON_IDX_7 0x0000145c
689#define SNDBDS_SEL_CON_IDX_8 0x00001460
690#define SNDBDS_SEL_CON_IDX_9 0x00001464
691#define SNDBDS_SEL_CON_IDX_10 0x00001468
692#define SNDBDS_SEL_CON_IDX_11 0x0000146c
693#define SNDBDS_SEL_CON_IDX_12 0x00001470
694#define SNDBDS_SEL_CON_IDX_13 0x00001474
695#define SNDBDS_SEL_CON_IDX_14 0x00001478
696#define SNDBDS_SEL_CON_IDX_15 0x0000147c
697/* 0x1480 --> 0x1800 unused */
698
699/* Send BD initiator control registers */
700#define SNDBDI_MODE 0x00001800
701#define SNDBDI_MODE_RESET 0x00000001
702#define SNDBDI_MODE_ENABLE 0x00000002
703#define SNDBDI_MODE_ATTN_ENABLE 0x00000004
704#define SNDBDI_STATUS 0x00001804
705#define SNDBDI_STATUS_ERROR_ATTN 0x00000004
706#define SNDBDI_IN_PROD_IDX_0 0x00001808
707#define SNDBDI_IN_PROD_IDX_1 0x0000180c
708#define SNDBDI_IN_PROD_IDX_2 0x00001810
709#define SNDBDI_IN_PROD_IDX_3 0x00001814
710#define SNDBDI_IN_PROD_IDX_4 0x00001818
711#define SNDBDI_IN_PROD_IDX_5 0x0000181c
712#define SNDBDI_IN_PROD_IDX_6 0x00001820
713#define SNDBDI_IN_PROD_IDX_7 0x00001824
714#define SNDBDI_IN_PROD_IDX_8 0x00001828
715#define SNDBDI_IN_PROD_IDX_9 0x0000182c
716#define SNDBDI_IN_PROD_IDX_10 0x00001830
717#define SNDBDI_IN_PROD_IDX_11 0x00001834
718#define SNDBDI_IN_PROD_IDX_12 0x00001838
719#define SNDBDI_IN_PROD_IDX_13 0x0000183c
720#define SNDBDI_IN_PROD_IDX_14 0x00001840
721#define SNDBDI_IN_PROD_IDX_15 0x00001844
722/* 0x1848 --> 0x1c00 unused */
723
724/* Send BD completion control registers */
725#define SNDBDC_MODE 0x00001c00
726#define SNDBDC_MODE_RESET 0x00000001
727#define SNDBDC_MODE_ENABLE 0x00000002
728#define SNDBDC_MODE_ATTN_ENABLE 0x00000004
729/* 0x1c04 --> 0x2000 unused */
730
731/* Receive list placement control registers */
732#define RCVLPC_MODE 0x00002000
733#define RCVLPC_MODE_RESET 0x00000001
734#define RCVLPC_MODE_ENABLE 0x00000002
735#define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
736#define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
737#define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
738#define RCVLPC_STATUS 0x00002004
739#define RCVLPC_STATUS_CLASS0 0x00000004
740#define RCVLPC_STATUS_MAPOOR 0x00000008
741#define RCVLPC_STATUS_STAT_OFLOW 0x00000010
742#define RCVLPC_LOCK 0x00002008
743#define RCVLPC_LOCK_REQ_MASK 0x0000ffff
744#define RCVLPC_LOCK_REQ_SHIFT 0
745#define RCVLPC_LOCK_GRANT_MASK 0xffff0000
746#define RCVLPC_LOCK_GRANT_SHIFT 16
747#define RCVLPC_NON_EMPTY_BITS 0x0000200c
748#define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
749#define RCVLPC_CONFIG 0x00002010
750#define RCVLPC_STATSCTRL 0x00002014
751#define RCVLPC_STATSCTRL_ENABLE 0x00000001
752#define RCVLPC_STATSCTRL_FASTUPD 0x00000002
753#define RCVLPC_STATS_ENABLE 0x00002018
Michael Chan16613942006-06-29 20:15:13 -0700754#define RCVLPC_STATSENAB_DACK_FIX 0x00040000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700755#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
756#define RCVLPC_STATS_INCMASK 0x0000201c
757/* 0x2020 --> 0x2100 unused */
758#define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
759#define SELLST_TAIL 0x00000004
760#define SELLST_CONT 0x00000008
761#define SELLST_UNUSED 0x0000000c
762#define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
763#define RCVLPC_DROP_FILTER_CNT 0x00002240
764#define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
765#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
766#define RCVLPC_NO_RCV_BD_CNT 0x0000224c
767#define RCVLPC_IN_DISCARDS_CNT 0x00002250
768#define RCVLPC_IN_ERRORS_CNT 0x00002254
769#define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
770/* 0x225c --> 0x2400 unused */
771
772/* Receive Data and Receive BD Initiator Control */
773#define RCVDBDI_MODE 0x00002400
774#define RCVDBDI_MODE_RESET 0x00000001
775#define RCVDBDI_MODE_ENABLE 0x00000002
776#define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
777#define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
778#define RCVDBDI_MODE_INV_RING_SZ 0x00000010
779#define RCVDBDI_STATUS 0x00002404
780#define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
781#define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
782#define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
783#define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
784/* 0x240c --> 0x2440 unused */
785#define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
786#define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
787#define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
788#define RCVDBDI_JUMBO_CON_IDX 0x00002470
789#define RCVDBDI_STD_CON_IDX 0x00002474
790#define RCVDBDI_MINI_CON_IDX 0x00002478
791/* 0x247c --> 0x2480 unused */
792#define RCVDBDI_BD_PROD_IDX_0 0x00002480
793#define RCVDBDI_BD_PROD_IDX_1 0x00002484
794#define RCVDBDI_BD_PROD_IDX_2 0x00002488
795#define RCVDBDI_BD_PROD_IDX_3 0x0000248c
796#define RCVDBDI_BD_PROD_IDX_4 0x00002490
797#define RCVDBDI_BD_PROD_IDX_5 0x00002494
798#define RCVDBDI_BD_PROD_IDX_6 0x00002498
799#define RCVDBDI_BD_PROD_IDX_7 0x0000249c
800#define RCVDBDI_BD_PROD_IDX_8 0x000024a0
801#define RCVDBDI_BD_PROD_IDX_9 0x000024a4
802#define RCVDBDI_BD_PROD_IDX_10 0x000024a8
803#define RCVDBDI_BD_PROD_IDX_11 0x000024ac
804#define RCVDBDI_BD_PROD_IDX_12 0x000024b0
805#define RCVDBDI_BD_PROD_IDX_13 0x000024b4
806#define RCVDBDI_BD_PROD_IDX_14 0x000024b8
807#define RCVDBDI_BD_PROD_IDX_15 0x000024bc
808#define RCVDBDI_HWDIAG 0x000024c0
809/* 0x24c4 --> 0x2800 unused */
810
811/* Receive Data Completion Control */
812#define RCVDCC_MODE 0x00002800
813#define RCVDCC_MODE_RESET 0x00000001
814#define RCVDCC_MODE_ENABLE 0x00000002
815#define RCVDCC_MODE_ATTN_ENABLE 0x00000004
816/* 0x2804 --> 0x2c00 unused */
817
818/* Receive BD Initiator Control Registers */
819#define RCVBDI_MODE 0x00002c00
820#define RCVBDI_MODE_RESET 0x00000001
821#define RCVBDI_MODE_ENABLE 0x00000002
822#define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
823#define RCVBDI_STATUS 0x00002c04
824#define RCVBDI_STATUS_RCB_ATTN 0x00000004
825#define RCVBDI_JUMBO_PROD_IDX 0x00002c08
826#define RCVBDI_STD_PROD_IDX 0x00002c0c
827#define RCVBDI_MINI_PROD_IDX 0x00002c10
828#define RCVBDI_MINI_THRESH 0x00002c14
829#define RCVBDI_STD_THRESH 0x00002c18
830#define RCVBDI_JUMBO_THRESH 0x00002c1c
831/* 0x2c20 --> 0x3000 unused */
832
833/* Receive BD Completion Control Registers */
834#define RCVCC_MODE 0x00003000
835#define RCVCC_MODE_RESET 0x00000001
836#define RCVCC_MODE_ENABLE 0x00000002
837#define RCVCC_MODE_ATTN_ENABLE 0x00000004
838#define RCVCC_STATUS 0x00003004
839#define RCVCC_STATUS_ERROR_ATTN 0x00000004
840#define RCVCC_JUMP_PROD_IDX 0x00003008
841#define RCVCC_STD_PROD_IDX 0x0000300c
842#define RCVCC_MINI_PROD_IDX 0x00003010
843/* 0x3014 --> 0x3400 unused */
844
845/* Receive list selector control registers */
846#define RCVLSC_MODE 0x00003400
847#define RCVLSC_MODE_RESET 0x00000001
848#define RCVLSC_MODE_ENABLE 0x00000002
849#define RCVLSC_MODE_ATTN_ENABLE 0x00000004
850#define RCVLSC_STATUS 0x00003404
851#define RCVLSC_STATUS_ERROR_ATTN 0x00000004
Matt Carlsond30cdd22007-10-07 23:28:35 -0700852/* 0x3408 --> 0x3600 unused */
853
854/* CPMU registers */
855#define TG3_CPMU_CTRL 0x00003600
856#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
857#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
Matt Carlson9936bcf2007-10-10 18:03:07 -0700858#define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
859/* 0x3604 --> 0x365c unused */
860
861#define TG3_CPMU_MUTEX_REQ 0x0000365c
862#define CPMU_MUTEX_REQ_DRIVER 0x00001000
863#define TG3_CPMU_MUTEX_GNT 0x00003660
864#define CPMU_MUTEX_GNT_DRIVER 0x00001000
865/* 0x3664 --> 0x3800 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700866
867/* Mbuf cluster free registers */
868#define MBFREE_MODE 0x00003800
869#define MBFREE_MODE_RESET 0x00000001
870#define MBFREE_MODE_ENABLE 0x00000002
871#define MBFREE_STATUS 0x00003804
872/* 0x3808 --> 0x3c00 unused */
873
874/* Host coalescing control registers */
875#define HOSTCC_MODE 0x00003c00
876#define HOSTCC_MODE_RESET 0x00000001
877#define HOSTCC_MODE_ENABLE 0x00000002
878#define HOSTCC_MODE_ATTN 0x00000004
879#define HOSTCC_MODE_NOW 0x00000008
880#define HOSTCC_MODE_FULL_STATUS 0x00000000
881#define HOSTCC_MODE_64BYTE 0x00000080
882#define HOSTCC_MODE_32BYTE 0x00000100
883#define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
884#define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
885#define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
886#define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
887#define HOSTCC_STATUS 0x00003c04
888#define HOSTCC_STATUS_ERROR_ATTN 0x00000004
889#define HOSTCC_RXCOL_TICKS 0x00003c08
890#define LOW_RXCOL_TICKS 0x00000032
David S. Miller15f98502005-05-18 22:49:26 -0700891#define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892#define DEFAULT_RXCOL_TICKS 0x00000048
893#define HIGH_RXCOL_TICKS 0x00000096
Michael Chand244c892005-07-05 14:42:33 -0700894#define MAX_RXCOL_TICKS 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700895#define HOSTCC_TXCOL_TICKS 0x00003c0c
896#define LOW_TXCOL_TICKS 0x00000096
David S. Miller15f98502005-05-18 22:49:26 -0700897#define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
Linus Torvalds1da177e2005-04-16 15:20:36 -0700898#define DEFAULT_TXCOL_TICKS 0x0000012c
899#define HIGH_TXCOL_TICKS 0x00000145
Michael Chand244c892005-07-05 14:42:33 -0700900#define MAX_TXCOL_TICKS 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901#define HOSTCC_RXMAX_FRAMES 0x00003c10
902#define LOW_RXMAX_FRAMES 0x00000005
903#define DEFAULT_RXMAX_FRAMES 0x00000008
904#define HIGH_RXMAX_FRAMES 0x00000012
Michael Chand244c892005-07-05 14:42:33 -0700905#define MAX_RXMAX_FRAMES 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700906#define HOSTCC_TXMAX_FRAMES 0x00003c14
907#define LOW_TXMAX_FRAMES 0x00000035
908#define DEFAULT_TXMAX_FRAMES 0x0000004b
909#define HIGH_TXMAX_FRAMES 0x00000052
Michael Chand244c892005-07-05 14:42:33 -0700910#define MAX_TXMAX_FRAMES 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700911#define HOSTCC_RXCOAL_TICK_INT 0x00003c18
912#define DEFAULT_RXCOAL_TICK_INT 0x00000019
David S. Miller15f98502005-05-18 22:49:26 -0700913#define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
Michael Chand244c892005-07-05 14:42:33 -0700914#define MAX_RXCOAL_TICK_INT 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700915#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
916#define DEFAULT_TXCOAL_TICK_INT 0x00000019
David S. Miller15f98502005-05-18 22:49:26 -0700917#define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
Michael Chand244c892005-07-05 14:42:33 -0700918#define MAX_TXCOAL_TICK_INT 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700919#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
920#define DEFAULT_RXCOAL_MAXF_INT 0x00000005
Michael Chand244c892005-07-05 14:42:33 -0700921#define MAX_RXCOAL_MAXF_INT 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
923#define DEFAULT_TXCOAL_MAXF_INT 0x00000005
Michael Chand244c892005-07-05 14:42:33 -0700924#define MAX_TXCOAL_MAXF_INT 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925#define HOSTCC_STAT_COAL_TICKS 0x00003c28
926#define DEFAULT_STAT_COAL_TICKS 0x000f4240
Michael Chand244c892005-07-05 14:42:33 -0700927#define MAX_STAT_COAL_TICKS 0xd693d400
928#define MIN_STAT_COAL_TICKS 0x00000064
Linus Torvalds1da177e2005-04-16 15:20:36 -0700929/* 0x3c2c --> 0x3c30 unused */
930#define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
931#define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
932#define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
933#define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
934#define HOSTCC_FLOW_ATTN 0x00003c48
935/* 0x3c4c --> 0x3c50 unused */
936#define HOSTCC_JUMBO_CON_IDX 0x00003c50
937#define HOSTCC_STD_CON_IDX 0x00003c54
938#define HOSTCC_MINI_CON_IDX 0x00003c58
939/* 0x3c5c --> 0x3c80 unused */
940#define HOSTCC_RET_PROD_IDX_0 0x00003c80
941#define HOSTCC_RET_PROD_IDX_1 0x00003c84
942#define HOSTCC_RET_PROD_IDX_2 0x00003c88
943#define HOSTCC_RET_PROD_IDX_3 0x00003c8c
944#define HOSTCC_RET_PROD_IDX_4 0x00003c90
945#define HOSTCC_RET_PROD_IDX_5 0x00003c94
946#define HOSTCC_RET_PROD_IDX_6 0x00003c98
947#define HOSTCC_RET_PROD_IDX_7 0x00003c9c
948#define HOSTCC_RET_PROD_IDX_8 0x00003ca0
949#define HOSTCC_RET_PROD_IDX_9 0x00003ca4
950#define HOSTCC_RET_PROD_IDX_10 0x00003ca8
951#define HOSTCC_RET_PROD_IDX_11 0x00003cac
952#define HOSTCC_RET_PROD_IDX_12 0x00003cb0
953#define HOSTCC_RET_PROD_IDX_13 0x00003cb4
954#define HOSTCC_RET_PROD_IDX_14 0x00003cb8
955#define HOSTCC_RET_PROD_IDX_15 0x00003cbc
956#define HOSTCC_SND_CON_IDX_0 0x00003cc0
957#define HOSTCC_SND_CON_IDX_1 0x00003cc4
958#define HOSTCC_SND_CON_IDX_2 0x00003cc8
959#define HOSTCC_SND_CON_IDX_3 0x00003ccc
960#define HOSTCC_SND_CON_IDX_4 0x00003cd0
961#define HOSTCC_SND_CON_IDX_5 0x00003cd4
962#define HOSTCC_SND_CON_IDX_6 0x00003cd8
963#define HOSTCC_SND_CON_IDX_7 0x00003cdc
964#define HOSTCC_SND_CON_IDX_8 0x00003ce0
965#define HOSTCC_SND_CON_IDX_9 0x00003ce4
966#define HOSTCC_SND_CON_IDX_10 0x00003ce8
967#define HOSTCC_SND_CON_IDX_11 0x00003cec
968#define HOSTCC_SND_CON_IDX_12 0x00003cf0
969#define HOSTCC_SND_CON_IDX_13 0x00003cf4
970#define HOSTCC_SND_CON_IDX_14 0x00003cf8
971#define HOSTCC_SND_CON_IDX_15 0x00003cfc
972/* 0x3d00 --> 0x4000 unused */
973
974/* Memory arbiter control registers */
975#define MEMARB_MODE 0x00004000
976#define MEMARB_MODE_RESET 0x00000001
977#define MEMARB_MODE_ENABLE 0x00000002
978#define MEMARB_STATUS 0x00004004
979#define MEMARB_TRAP_ADDR_LOW 0x00004008
980#define MEMARB_TRAP_ADDR_HIGH 0x0000400c
981/* 0x4010 --> 0x4400 unused */
982
983/* Buffer manager control registers */
984#define BUFMGR_MODE 0x00004400
985#define BUFMGR_MODE_RESET 0x00000001
986#define BUFMGR_MODE_ENABLE 0x00000002
987#define BUFMGR_MODE_ATTN_ENABLE 0x00000004
988#define BUFMGR_MODE_BM_TEST 0x00000008
989#define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
990#define BUFMGR_STATUS 0x00004404
991#define BUFMGR_STATUS_ERROR 0x00000004
992#define BUFMGR_STATUS_MBLOW 0x00000010
993#define BUFMGR_MB_POOL_ADDR 0x00004408
994#define BUFMGR_MB_POOL_SIZE 0x0000440c
995#define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
996#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
997#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
998#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
Michael Chanfdfec1722005-07-25 12:31:48 -0700999#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001000#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
1001#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
1002#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
Michael Chanb5d37722006-09-27 16:06:21 -07001003#define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
Michael Chanfdfec1722005-07-25 12:31:48 -07001005#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006#define BUFMGR_MB_HIGH_WATER 0x00004418
1007#define DEFAULT_MB_HIGH_WATER 0x00000060
1008#define DEFAULT_MB_HIGH_WATER_5705 0x00000060
Michael Chanb5d37722006-09-27 16:06:21 -07001009#define DEFAULT_MB_HIGH_WATER_5906 0x00000010
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
Michael Chanfdfec1722005-07-25 12:31:48 -07001011#define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
Linus Torvalds1da177e2005-04-16 15:20:36 -07001012#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1013#define BUFMGR_MB_ALLOC_BIT 0x10000000
1014#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1015#define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1016#define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1017#define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1018#define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1019#define BUFMGR_DMA_LOW_WATER 0x00004434
1020#define DEFAULT_DMA_LOW_WATER 0x00000005
1021#define BUFMGR_DMA_HIGH_WATER 0x00004438
1022#define DEFAULT_DMA_HIGH_WATER 0x0000000a
1023#define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1024#define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1025#define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1026#define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1027#define BUFMGR_HWDIAG_0 0x0000444c
1028#define BUFMGR_HWDIAG_1 0x00004450
1029#define BUFMGR_HWDIAG_2 0x00004454
1030/* 0x4458 --> 0x4800 unused */
1031
1032/* Read DMA control registers */
1033#define RDMAC_MODE 0x00004800
1034#define RDMAC_MODE_RESET 0x00000001
1035#define RDMAC_MODE_ENABLE 0x00000002
1036#define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1037#define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1038#define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1039#define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1040#define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1041#define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1042#define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1043#define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1044#define RDMAC_MODE_SPLIT_ENABLE 0x00000800
Matt Carlsond30cdd22007-10-07 23:28:35 -07001045#define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046#define RDMAC_MODE_SPLIT_RESET 0x00001000
Matt Carlsond30cdd22007-10-07 23:28:35 -07001047#define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
1048#define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049#define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1050#define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
1051#define RDMAC_STATUS 0x00004804
1052#define RDMAC_STATUS_TGTABORT 0x00000004
1053#define RDMAC_STATUS_MSTABORT 0x00000008
1054#define RDMAC_STATUS_PARITYERR 0x00000010
1055#define RDMAC_STATUS_ADDROFLOW 0x00000020
1056#define RDMAC_STATUS_FIFOOFLOW 0x00000040
1057#define RDMAC_STATUS_FIFOURUN 0x00000080
1058#define RDMAC_STATUS_FIFOOREAD 0x00000100
1059#define RDMAC_STATUS_LNGREAD 0x00000200
1060/* 0x4808 --> 0x4c00 unused */
1061
1062/* Write DMA control registers */
1063#define WDMAC_MODE 0x00004c00
1064#define WDMAC_MODE_RESET 0x00000001
1065#define WDMAC_MODE_ENABLE 0x00000002
1066#define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1067#define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1068#define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1069#define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1070#define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1071#define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1072#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1073#define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1074#define WDMAC_MODE_RX_ACCEL 0x00000400
1075#define WDMAC_STATUS 0x00004c04
1076#define WDMAC_STATUS_TGTABORT 0x00000004
1077#define WDMAC_STATUS_MSTABORT 0x00000008
1078#define WDMAC_STATUS_PARITYERR 0x00000010
1079#define WDMAC_STATUS_ADDROFLOW 0x00000020
1080#define WDMAC_STATUS_FIFOOFLOW 0x00000040
1081#define WDMAC_STATUS_FIFOURUN 0x00000080
1082#define WDMAC_STATUS_FIFOOREAD 0x00000100
1083#define WDMAC_STATUS_LNGREAD 0x00000200
1084/* 0x4c08 --> 0x5000 unused */
1085
1086/* Per-cpu register offsets (arm9) */
1087#define CPU_MODE 0x00000000
1088#define CPU_MODE_RESET 0x00000001
1089#define CPU_MODE_HALT 0x00000400
1090#define CPU_STATE 0x00000004
1091#define CPU_EVTMASK 0x00000008
1092/* 0xc --> 0x1c reserved */
1093#define CPU_PC 0x0000001c
1094#define CPU_INSN 0x00000020
1095#define CPU_SPAD_UFLOW 0x00000024
1096#define CPU_WDOG_CLEAR 0x00000028
1097#define CPU_WDOG_VECTOR 0x0000002c
1098#define CPU_WDOG_PC 0x00000030
1099#define CPU_HW_BP 0x00000034
1100/* 0x38 --> 0x44 unused */
1101#define CPU_WDOG_SAVED_STATE 0x00000044
1102#define CPU_LAST_BRANCH_ADDR 0x00000048
1103#define CPU_SPAD_UFLOW_SET 0x0000004c
1104/* 0x50 --> 0x200 unused */
1105#define CPU_R0 0x00000200
1106#define CPU_R1 0x00000204
1107#define CPU_R2 0x00000208
1108#define CPU_R3 0x0000020c
1109#define CPU_R4 0x00000210
1110#define CPU_R5 0x00000214
1111#define CPU_R6 0x00000218
1112#define CPU_R7 0x0000021c
1113#define CPU_R8 0x00000220
1114#define CPU_R9 0x00000224
1115#define CPU_R10 0x00000228
1116#define CPU_R11 0x0000022c
1117#define CPU_R12 0x00000230
1118#define CPU_R13 0x00000234
1119#define CPU_R14 0x00000238
1120#define CPU_R15 0x0000023c
1121#define CPU_R16 0x00000240
1122#define CPU_R17 0x00000244
1123#define CPU_R18 0x00000248
1124#define CPU_R19 0x0000024c
1125#define CPU_R20 0x00000250
1126#define CPU_R21 0x00000254
1127#define CPU_R22 0x00000258
1128#define CPU_R23 0x0000025c
1129#define CPU_R24 0x00000260
1130#define CPU_R25 0x00000264
1131#define CPU_R26 0x00000268
1132#define CPU_R27 0x0000026c
1133#define CPU_R28 0x00000270
1134#define CPU_R29 0x00000274
1135#define CPU_R30 0x00000278
1136#define CPU_R31 0x0000027c
1137/* 0x280 --> 0x400 unused */
1138
1139#define RX_CPU_BASE 0x00005000
Chris Elmquist091465d2005-12-20 13:25:19 -08001140#define RX_CPU_MODE 0x00005000
1141#define RX_CPU_STATE 0x00005004
1142#define RX_CPU_PGMCTR 0x0000501c
1143#define RX_CPU_HWBKPT 0x00005034
Linus Torvalds1da177e2005-04-16 15:20:36 -07001144#define TX_CPU_BASE 0x00005400
Chris Elmquist091465d2005-12-20 13:25:19 -08001145#define TX_CPU_MODE 0x00005400
1146#define TX_CPU_STATE 0x00005404
1147#define TX_CPU_PGMCTR 0x0000541c
Linus Torvalds1da177e2005-04-16 15:20:36 -07001148
Michael Chanb5d37722006-09-27 16:06:21 -07001149#define VCPU_STATUS 0x00005100
1150#define VCPU_STATUS_INIT_DONE 0x04000000
1151#define VCPU_STATUS_DRV_RESET 0x08000000
1152
Matt Carlson8ed5d972007-05-07 00:25:49 -07001153#define VCPU_CFGSHDW 0x00005104
Matt Carlson0527ba32007-10-10 18:03:30 -07001154#define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
1155#define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
Matt Carlson8ed5d972007-05-07 00:25:49 -07001156#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
1157
Linus Torvalds1da177e2005-04-16 15:20:36 -07001158/* Mailboxes */
Michael Chanb5d37722006-09-27 16:06:21 -07001159#define GRCMBOX_BASE 0x00005600
Linus Torvalds1da177e2005-04-16 15:20:36 -07001160#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1161#define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1162#define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1163#define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1164#define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1165#define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1166#define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1167#define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1168#define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1169#define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1170#define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1171#define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1172#define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1173#define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1174#define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1175#define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1176#define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1177#define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1178#define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1179#define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1180#define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1181#define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1182#define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1183#define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1184#define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1185#define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1186#define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1187#define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1188#define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1189#define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1190#define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1191#define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1192#define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1193#define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1194#define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1195#define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1196#define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1197#define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1198#define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1199#define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1200#define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1201#define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1202#define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1203#define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1204#define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1205#define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1206#define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1207#define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1208#define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1209#define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1210#define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1211#define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1212#define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1213#define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1214#define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1215#define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1216#define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1217#define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1218#define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1219#define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1220#define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1221#define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1222#define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1223#define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1224#define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1225#define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1226#define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1227#define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1228/* 0x5a10 --> 0x5c00 */
1229
1230/* Flow Through queues */
1231#define FTQ_RESET 0x00005c00
1232/* 0x5c04 --> 0x5c10 unused */
1233#define FTQ_DMA_NORM_READ_CTL 0x00005c10
1234#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1235#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1236#define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1237#define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1238#define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1239#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1240#define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1241#define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1242#define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1243#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1244#define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1245#define FTQ_SEND_BD_COMP_CTL 0x00005c40
1246#define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1247#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1248#define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1249#define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1250#define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1251#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1252#define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1253#define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1254#define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1255#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1256#define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1257#define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1258#define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1259#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1260#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1261#define FTQ_SWTYPE1_CTL 0x00005c80
1262#define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1263#define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1264#define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1265#define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1266#define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1267#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1268#define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1269#define FTQ_HOST_COAL_CTL 0x00005ca0
1270#define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1271#define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1272#define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1273#define FTQ_MAC_TX_CTL 0x00005cb0
1274#define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1275#define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1276#define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1277#define FTQ_MB_FREE_CTL 0x00005cc0
1278#define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1279#define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1280#define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1281#define FTQ_RCVBD_COMP_CTL 0x00005cd0
1282#define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1283#define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1284#define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1285#define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1286#define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1287#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1288#define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1289#define FTQ_RCVDATA_INI_CTL 0x00005cf0
1290#define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1291#define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1292#define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1293#define FTQ_RCVDATA_COMP_CTL 0x00005d00
1294#define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1295#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1296#define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1297#define FTQ_SWTYPE2_CTL 0x00005d10
1298#define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1299#define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1300#define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1301/* 0x5d20 --> 0x6000 unused */
1302
1303/* Message signaled interrupt registers */
1304#define MSGINT_MODE 0x00006000
1305#define MSGINT_MODE_RESET 0x00000001
1306#define MSGINT_MODE_ENABLE 0x00000002
1307#define MSGINT_STATUS 0x00006004
1308#define MSGINT_FIFO 0x00006008
1309/* 0x600c --> 0x6400 unused */
1310
1311/* DMA completion registers */
1312#define DMAC_MODE 0x00006400
1313#define DMAC_MODE_RESET 0x00000001
1314#define DMAC_MODE_ENABLE 0x00000002
1315/* 0x6404 --> 0x6800 unused */
1316
1317/* GRC registers */
1318#define GRC_MODE 0x00006800
1319#define GRC_MODE_UPD_ON_COAL 0x00000001
1320#define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1321#define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1322#define GRC_MODE_BSWAP_DATA 0x00000010
1323#define GRC_MODE_WSWAP_DATA 0x00000020
1324#define GRC_MODE_SPLITHDR 0x00000100
1325#define GRC_MODE_NOFRM_CRACKING 0x00000200
1326#define GRC_MODE_INCL_CRC 0x00000400
1327#define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1328#define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1329#define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1330#define GRC_MODE_FORCE_PCI32BIT 0x00008000
1331#define GRC_MODE_HOST_STACKUP 0x00010000
1332#define GRC_MODE_HOST_SENDBDS 0x00020000
1333#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1334#define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1335#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1336#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1337#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1338#define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1339#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1340#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1341#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1342#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1343#define GRC_MISC_CFG 0x00006804
1344#define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1345#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1346#define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1347#define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1348#define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1349#define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1350#define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1351#define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1352#define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1353#define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1354#define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1355#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1356#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1357#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1358#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
Michael Chan60189dd2006-12-17 17:08:07 -08001359#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001360#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1361#define GRC_LOCAL_CTRL 0x00006808
1362#define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1363#define GRC_LCLCTRL_CLEARINT 0x00000002
1364#define GRC_LCLCTRL_SETINT 0x00000004
1365#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
Michael Chanaf36e6b2006-03-23 01:28:06 -08001366#define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
Michael Chana4e2b342005-10-26 15:46:52 -07001367#define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
1368#define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
Michael Chan3e7d83b2005-04-21 17:10:36 -07001369#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1370#define GRC_LCLCTRL_GPIO_OE3 0x00000040
1371#define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
Linus Torvalds1da177e2005-04-16 15:20:36 -07001372#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1373#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1374#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1375#define GRC_LCLCTRL_GPIO_OE0 0x00000800
1376#define GRC_LCLCTRL_GPIO_OE1 0x00001000
1377#define GRC_LCLCTRL_GPIO_OE2 0x00002000
1378#define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1379#define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1380#define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1381#define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1382#define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1383#define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1384#define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1385#define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1386#define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1387#define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1388#define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1389#define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1390#define GRC_LCLCTRL_BANK_SELECT 0x00200000
1391#define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1392#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1393#define GRC_TIMER 0x0000680c
1394#define GRC_RX_CPU_EVENT 0x00006810
1395#define GRC_RX_TIMER_REF 0x00006814
1396#define GRC_RX_CPU_SEM 0x00006818
1397#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1398#define GRC_TX_CPU_EVENT 0x00006820
1399#define GRC_TX_TIMER_REF 0x00006824
1400#define GRC_TX_CPU_SEM 0x00006828
1401#define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1402#define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1403#define GRC_EEPROM_ADDR 0x00006838
1404#define EEPROM_ADDR_WRITE 0x00000000
1405#define EEPROM_ADDR_READ 0x80000000
1406#define EEPROM_ADDR_COMPLETE 0x40000000
1407#define EEPROM_ADDR_FSM_RESET 0x20000000
1408#define EEPROM_ADDR_DEVID_MASK 0x1c000000
1409#define EEPROM_ADDR_DEVID_SHIFT 26
1410#define EEPROM_ADDR_START 0x02000000
1411#define EEPROM_ADDR_CLKPERD_SHIFT 16
1412#define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1413#define EEPROM_ADDR_ADDR_SHIFT 0
1414#define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1415#define EEPROM_CHIP_SIZE (64 * 1024)
1416#define GRC_EEPROM_DATA 0x0000683c
1417#define GRC_EEPROM_CTRL 0x00006840
1418#define GRC_MDI_CTRL 0x00006844
1419#define GRC_SEEPROM_DELAY 0x00006848
Michael Chanb5d37722006-09-27 16:06:21 -07001420/* 0x684c --> 0x6890 unused */
1421#define GRC_VCPU_EXT_CTRL 0x00006890
1422#define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1423#define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
Michael Chand9ab5ad2006-03-20 22:27:35 -08001424#define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001425
1426/* 0x6c00 --> 0x7000 unused */
1427
1428/* NVRAM Control registers */
1429#define NVRAM_CMD 0x00007000
1430#define NVRAM_CMD_RESET 0x00000001
1431#define NVRAM_CMD_DONE 0x00000008
1432#define NVRAM_CMD_GO 0x00000010
1433#define NVRAM_CMD_WR 0x00000020
1434#define NVRAM_CMD_RD 0x00000000
1435#define NVRAM_CMD_ERASE 0x00000040
1436#define NVRAM_CMD_FIRST 0x00000080
1437#define NVRAM_CMD_LAST 0x00000100
1438#define NVRAM_CMD_WREN 0x00010000
1439#define NVRAM_CMD_WRDI 0x00020000
1440#define NVRAM_STAT 0x00007004
1441#define NVRAM_WRDATA 0x00007008
1442#define NVRAM_ADDR 0x0000700c
1443#define NVRAM_ADDR_MSK 0x00ffffff
1444#define NVRAM_RDDATA 0x00007010
1445#define NVRAM_CFG1 0x00007014
1446#define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1447#define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1448#define NVRAM_CFG1_PASS_THRU 0x00000004
1449#define NVRAM_CFG1_STATUS_BITS 0x00000070
1450#define NVRAM_CFG1_BIT_BANG 0x00000008
1451#define NVRAM_CFG1_FLASH_SIZE 0x02000000
1452#define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1453#define NVRAM_CFG1_VENDOR_MASK 0x03000003
1454#define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1455#define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1456#define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1457#define FLASH_VENDOR_ST 0x03000001
1458#define FLASH_VENDOR_SAIFUN 0x01000003
1459#define FLASH_VENDOR_SST_SMALL 0x00000001
1460#define FLASH_VENDOR_SST_LARGE 0x02000001
Michael Chan361b4ac2005-04-21 17:11:21 -07001461#define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1462#define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1463#define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1464#define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1465#define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1466#define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1467#define FLASH_5752VENDOR_ST_M45PE40 0x02400001
Michael Chan1b277772006-03-20 22:27:48 -08001468#define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1469#define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1470#define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
Michael Chand3c7b882006-03-23 01:28:25 -08001471#define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
Matt Carlson70b65a22007-07-11 19:48:50 -07001472#define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003
Michael Chand3c7b882006-03-23 01:28:25 -08001473#define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1474#define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
Michael Chan1b277772006-03-20 22:27:48 -08001475#define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1476#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1477#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1478#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
Matt Carlson6b91fa02007-10-10 18:01:09 -07001479#define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
1480#define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
1481#define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
1482#define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
1483#define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
1484#define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
1485#define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
1486#define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
1487#define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
1488#define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
1489#define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
1490#define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
1491#define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
1492#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1493#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1494#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
Michael Chan361b4ac2005-04-21 17:11:21 -07001495#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1496#define FLASH_5752PAGE_SIZE_256 0x00000000
1497#define FLASH_5752PAGE_SIZE_512 0x10000000
1498#define FLASH_5752PAGE_SIZE_1K 0x20000000
1499#define FLASH_5752PAGE_SIZE_2K 0x30000000
1500#define FLASH_5752PAGE_SIZE_4K 0x40000000
1501#define FLASH_5752PAGE_SIZE_264 0x50000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001502#define NVRAM_CFG2 0x00007018
1503#define NVRAM_CFG3 0x0000701c
1504#define NVRAM_SWARB 0x00007020
1505#define SWARB_REQ_SET0 0x00000001
1506#define SWARB_REQ_SET1 0x00000002
1507#define SWARB_REQ_SET2 0x00000004
1508#define SWARB_REQ_SET3 0x00000008
1509#define SWARB_REQ_CLR0 0x00000010
1510#define SWARB_REQ_CLR1 0x00000020
1511#define SWARB_REQ_CLR2 0x00000040
1512#define SWARB_REQ_CLR3 0x00000080
1513#define SWARB_GNT0 0x00000100
1514#define SWARB_GNT1 0x00000200
1515#define SWARB_GNT2 0x00000400
1516#define SWARB_GNT3 0x00000800
1517#define SWARB_REQ0 0x00001000
1518#define SWARB_REQ1 0x00002000
1519#define SWARB_REQ2 0x00004000
1520#define SWARB_REQ3 0x00008000
1521#define NVRAM_ACCESS 0x00007024
1522#define ACCESS_ENABLE 0x00000001
1523#define ACCESS_WR_ENABLE 0x00000002
1524#define NVRAM_WRITE1 0x00007028
Matt Carlson6b91fa02007-10-10 18:01:09 -07001525/* 0x702c unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526
Matt Carlson6b91fa02007-10-10 18:01:09 -07001527#define NVRAM_ADDR_LOCKOUT 0x00007030
1528/* 0x7034 --> 0x7c00 unused */
1529
Michael Chanb5d37722006-09-27 16:06:21 -07001530#define PCIE_TRANSACTION_CFG 0x00007c04
1531#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
1532#define PCIE_TRANS_CFG_LOM 0x00000020
1533
Matt Carlson8ed5d972007-05-07 00:25:49 -07001534#define PCIE_PWR_MGMT_THRESH 0x00007d28
1535#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
Linus Torvalds1da177e2005-04-16 15:20:36 -07001536
1537#define TG3_EEPROM_MAGIC 0x669955aa
Michael Chanb16250e2006-09-27 16:10:14 -07001538#define TG3_EEPROM_MAGIC_FW 0xa5000000
1539#define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
1540#define TG3_EEPROM_MAGIC_HW 0xabcd
1541#define TG3_EEPROM_MAGIC_HW_MSK 0xffff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001542
1543/* 32K Window into NIC internal memory */
1544#define NIC_SRAM_WIN_BASE 0x00008000
1545
1546/* Offsets into first 32k of NIC internal memory. */
1547#define NIC_SRAM_PAGE_ZERO 0x00000000
1548#define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
1549#define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
1550#define NIC_SRAM_STATS_BLK 0x00000300
1551#define NIC_SRAM_STATUS_BLK 0x00000b00
1552
1553#define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
1554#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
1555#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
1556
1557#define NIC_SRAM_DATA_SIG 0x00000b54
1558#define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
1559
1560#define NIC_SRAM_DATA_CFG 0x00000b58
1561#define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
1562#define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
1563#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
1564#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
1565#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
1566#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
1567#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
1568#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
1569#define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
1570#define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
1571#define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
1572#define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
1573#define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
1574#define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
Matt Carlson0d3031d2007-10-10 18:02:43 -07001575#define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001576
1577#define NIC_SRAM_DATA_VER 0x00000b5c
1578#define NIC_SRAM_DATA_VER_SHIFT 16
1579
1580#define NIC_SRAM_DATA_PHY_ID 0x00000b74
1581#define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
1582#define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
1583
1584#define NIC_SRAM_FW_CMD_MBOX 0x00000b78
1585#define FWCMD_NICDRV_ALIVE 0x00000001
1586#define FWCMD_NICDRV_PAUSE_FW 0x00000002
1587#define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
1588#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
1589#define FWCMD_NICDRV_FIX_DMAR 0x00000005
1590#define FWCMD_NICDRV_FIX_DMAW 0x00000006
Michael Chan28fbef72005-10-26 15:48:35 -07001591#define FWCMD_NICDRV_ALIVE2 0x0000000d
Michael Chan130b8e42006-09-27 16:00:40 -07001592#define FWCMD_NICDRV_ALIVE3 0x0000000e
Linus Torvalds1da177e2005-04-16 15:20:36 -07001593#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
1594#define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
1595#define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
1596#define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
1597#define DRV_STATE_START 0x00000001
1598#define DRV_STATE_START_DONE 0x80000001
1599#define DRV_STATE_UNLOAD 0x00000002
1600#define DRV_STATE_UNLOAD_DONE 0x80000002
1601#define DRV_STATE_WOL 0x00000003
1602#define DRV_STATE_SUSPEND 0x00000004
1603
1604#define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
1605
1606#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
1607#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
1608
Michael Chan6921d202005-12-13 21:15:53 -08001609#define NIC_SRAM_WOL_MBOX 0x00000d30
1610#define WOL_SIGNATURE 0x474c0000
1611#define WOL_DRV_STATE_SHUTDOWN 0x00000001
1612#define WOL_DRV_WOL 0x00000002
1613#define WOL_SET_MAGIC_PKT 0x00000004
1614
Linus Torvalds1da177e2005-04-16 15:20:36 -07001615#define NIC_SRAM_DATA_CFG_2 0x00000d38
1616
1617#define SHASTA_EXT_LED_MODE_MASK 0x00018000
1618#define SHASTA_EXT_LED_LEGACY 0x00000000
1619#define SHASTA_EXT_LED_SHARED 0x00008000
1620#define SHASTA_EXT_LED_MAC 0x00010000
1621#define SHASTA_EXT_LED_COMBO 0x00018000
1622
Matt Carlson8ed5d972007-05-07 00:25:49 -07001623#define NIC_SRAM_DATA_CFG_3 0x00000d3c
1624#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
1625
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
1627
1628#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
1629#define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
1630#define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
1631#define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
1632#define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
1633#define NIC_SRAM_MBUF_POOL_BASE 0x00008000
1634#define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
1635#define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
1636#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
1637#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
1638
1639/* Currently this is fixed. */
1640#define PHY_ADDR 0x01
1641
1642/* Tigon3 specific PHY MII registers. */
1643#define TG3_BMCR_SPEED1000 0x0040
1644
1645#define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
1646#define MII_TG3_CTRL_ADV_1000_HALF 0x0100
1647#define MII_TG3_CTRL_ADV_1000_FULL 0x0200
1648#define MII_TG3_CTRL_AS_MASTER 0x0800
1649#define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
1650
1651#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
1652#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
1653#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
Michael Chan6921d202005-12-13 21:15:53 -08001654#define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
Linus Torvalds1da177e2005-04-16 15:20:36 -07001655#define MII_TG3_EXT_CTRL_TBI 0x8000
1656
1657#define MII_TG3_EXT_STAT 0x11 /* Extended status register */
1658#define MII_TG3_EXT_STAT_LPASS 0x0100
1659
1660#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
1661
1662#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
Michael Chan715116a2006-09-27 16:09:25 -07001663#define MII_TG3_EPHY_PTEST 0x17 /* 5906 PHY register */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001664
1665#define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
1666
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001667#define MII_TG3_AUXCTL_MISC_WREN 0x8000
1668#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
1669#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
1670#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
1671
Linus Torvalds1da177e2005-04-16 15:20:36 -07001672#define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
1673#define MII_TG3_AUX_STAT_LPASS 0x0004
1674#define MII_TG3_AUX_STAT_SPDMASK 0x0700
1675#define MII_TG3_AUX_STAT_10HALF 0x0100
1676#define MII_TG3_AUX_STAT_10FULL 0x0200
1677#define MII_TG3_AUX_STAT_100HALF 0x0300
1678#define MII_TG3_AUX_STAT_100_4 0x0400
1679#define MII_TG3_AUX_STAT_100FULL 0x0500
1680#define MII_TG3_AUX_STAT_1000HALF 0x0600
1681#define MII_TG3_AUX_STAT_1000FULL 0x0700
Michael Chan715116a2006-09-27 16:09:25 -07001682#define MII_TG3_AUX_STAT_100 0x0008
1683#define MII_TG3_AUX_STAT_FULL 0x0001
Linus Torvalds1da177e2005-04-16 15:20:36 -07001684
1685#define MII_TG3_ISTAT 0x1a /* IRQ status register */
1686#define MII_TG3_IMASK 0x1b /* IRQ mask register */
1687
1688/* ISTAT/IMASK event bits */
1689#define MII_TG3_INT_LINKCHG 0x0002
1690#define MII_TG3_INT_SPEEDCHG 0x0004
1691#define MII_TG3_INT_DUPLEXCHG 0x0008
1692#define MII_TG3_INT_ANEG_PAGE_RX 0x0400
1693
Michael Chan715116a2006-09-27 16:09:25 -07001694#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */
1695#define MII_TG3_EPHY_SHADOW_EN 0x80
1696
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001697#define MII_TG3_EPHYTST_MISCCTRL 0x10 /* 5906 EPHY misc ctrl shadow register */
1698#define MII_TG3_EPHYTST_MISCCTRL_MDIX 0x4000
1699
Michael Chanc1d2a192007-01-08 19:57:20 -08001700#define MII_TG3_TEST1 0x1e
1701#define MII_TG3_TEST1_TRIM_EN 0x0010
Michael Chan569a5df2007-02-13 12:18:15 -08001702#define MII_TG3_TEST1_CRC_EN 0x8000
Michael Chanc1d2a192007-01-08 19:57:20 -08001703
Matt Carlson0d3031d2007-10-10 18:02:43 -07001704/* APE registers. Accessible through BAR1 */
1705#define TG3_APE_EVENT 0x000c
1706#define APE_EVENT_1 0x00000001
1707#define TG3_APE_LOCK_REQ 0x002c
1708#define APE_LOCK_REQ_DRIVER 0x00001000
1709#define TG3_APE_LOCK_GRANT 0x004c
1710#define APE_LOCK_GRANT_DRIVER 0x00001000
1711#define TG3_APE_SEG_SIG 0x4000
1712#define APE_SEG_SIG_MAGIC 0x41504521
1713
1714/* APE shared memory. Accessible through BAR1 */
1715#define TG3_APE_FW_STATUS 0x400c
1716#define APE_FW_STATUS_READY 0x00000100
1717#define TG3_APE_HOST_SEG_SIG 0x4200
1718#define APE_HOST_SEG_SIG_MAGIC 0x484f5354
1719#define TG3_APE_HOST_SEG_LEN 0x4204
1720#define APE_HOST_SEG_LEN_MAGIC 0x0000001c
1721#define TG3_APE_HOST_INIT_COUNT 0x4208
1722#define TG3_APE_HOST_DRIVER_ID 0x420c
1723#define APE_HOST_DRIVER_ID_MAGIC 0xf0035100
1724#define TG3_APE_HOST_BEHAVIOR 0x4210
1725#define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
1726#define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214
1727#define APE_HOST_HEARTBEAT_INT_DISABLE 0
1728#define APE_HOST_HEARTBEAT_INT_5SEC 5000
1729#define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
1730
1731#define TG3_APE_EVENT_STATUS 0x4300
1732
1733#define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
1734#define APE_EVENT_STATUS_STATE_CHNGE 0x00000500
1735#define APE_EVENT_STATUS_STATE_START 0x00010000
1736#define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
1737#define APE_EVENT_STATUS_STATE_WOL 0x00030000
1738#define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
1739#define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
1740
1741/* APE convenience enumerations. */
1742#define TG3_APE_LOCK_MEM 4
1743
1744
Linus Torvalds1da177e2005-04-16 15:20:36 -07001745/* There are two ways to manage the TX descriptors on the tigon3.
1746 * Either the descriptors are in host DMA'able memory, or they
1747 * exist only in the cards on-chip SRAM. All 16 send bds are under
1748 * the same mode, they may not be configured individually.
1749 *
1750 * This driver always uses host memory TX descriptors.
1751 *
1752 * To use host memory TX descriptors:
1753 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
1754 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
1755 * 2) Allocate DMA'able memory.
1756 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1757 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
1758 * obtained in step 2
1759 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
1760 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
1761 * of TX descriptors. Leave flags field clear.
1762 * 4) Access TX descriptors via host memory. The chip
1763 * will refetch into local SRAM as needed when producer
1764 * index mailboxes are updated.
1765 *
1766 * To use on-chip TX descriptors:
1767 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
1768 * Make sure GRC_MODE_HOST_SENDBDS is clear.
1769 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1770 * a) Set TG3_BDINFO_HOST_ADDR to zero.
1771 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
1772 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
1773 * 3) Access TX descriptors directly in on-chip SRAM
1774 * using normal {read,write}l(). (and not using
1775 * pointer dereferencing of ioremap()'d memory like
1776 * the broken Broadcom driver does)
1777 *
1778 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
1779 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
1780 */
1781struct tg3_tx_buffer_desc {
1782 u32 addr_hi;
1783 u32 addr_lo;
1784
1785 u32 len_flags;
1786#define TXD_FLAG_TCPUDP_CSUM 0x0001
1787#define TXD_FLAG_IP_CSUM 0x0002
1788#define TXD_FLAG_END 0x0004
1789#define TXD_FLAG_IP_FRAG 0x0008
1790#define TXD_FLAG_IP_FRAG_END 0x0010
1791#define TXD_FLAG_VLAN 0x0040
1792#define TXD_FLAG_COAL_NOW 0x0080
1793#define TXD_FLAG_CPU_PRE_DMA 0x0100
1794#define TXD_FLAG_CPU_POST_DMA 0x0200
1795#define TXD_FLAG_ADD_SRC_ADDR 0x1000
1796#define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
1797#define TXD_FLAG_NO_CRC 0x8000
1798#define TXD_LEN_SHIFT 16
1799
1800 u32 vlan_tag;
1801#define TXD_VLAN_TAG_SHIFT 0
1802#define TXD_MSS_SHIFT 16
1803};
1804
1805#define TXD_ADDR 0x00UL /* 64-bit */
1806#define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
1807#define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
1808#define TXD_SIZE 0x10UL
1809
1810struct tg3_rx_buffer_desc {
1811 u32 addr_hi;
1812 u32 addr_lo;
1813
1814 u32 idx_len;
1815#define RXD_IDX_MASK 0xffff0000
1816#define RXD_IDX_SHIFT 16
1817#define RXD_LEN_MASK 0x0000ffff
1818#define RXD_LEN_SHIFT 0
1819
1820 u32 type_flags;
1821#define RXD_TYPE_SHIFT 16
1822#define RXD_FLAGS_SHIFT 0
1823
1824#define RXD_FLAG_END 0x0004
1825#define RXD_FLAG_MINI 0x0800
1826#define RXD_FLAG_JUMBO 0x0020
1827#define RXD_FLAG_VLAN 0x0040
1828#define RXD_FLAG_ERROR 0x0400
1829#define RXD_FLAG_IP_CSUM 0x1000
1830#define RXD_FLAG_TCPUDP_CSUM 0x2000
1831#define RXD_FLAG_IS_TCP 0x4000
1832
1833 u32 ip_tcp_csum;
1834#define RXD_IPCSUM_MASK 0xffff0000
1835#define RXD_IPCSUM_SHIFT 16
1836#define RXD_TCPCSUM_MASK 0x0000ffff
1837#define RXD_TCPCSUM_SHIFT 0
1838
1839 u32 err_vlan;
1840
1841#define RXD_VLAN_MASK 0x0000ffff
1842
1843#define RXD_ERR_BAD_CRC 0x00010000
1844#define RXD_ERR_COLLISION 0x00020000
1845#define RXD_ERR_LINK_LOST 0x00040000
1846#define RXD_ERR_PHY_DECODE 0x00080000
1847#define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
1848#define RXD_ERR_MAC_ABRT 0x00200000
1849#define RXD_ERR_TOO_SMALL 0x00400000
1850#define RXD_ERR_NO_RESOURCES 0x00800000
1851#define RXD_ERR_HUGE_FRAME 0x01000000
1852#define RXD_ERR_MASK 0xffff0000
1853
1854 u32 reserved;
1855 u32 opaque;
1856#define RXD_OPAQUE_INDEX_MASK 0x0000ffff
1857#define RXD_OPAQUE_INDEX_SHIFT 0
1858#define RXD_OPAQUE_RING_STD 0x00010000
1859#define RXD_OPAQUE_RING_JUMBO 0x00020000
1860#define RXD_OPAQUE_RING_MINI 0x00040000
1861#define RXD_OPAQUE_RING_MASK 0x00070000
1862};
1863
1864struct tg3_ext_rx_buffer_desc {
1865 struct {
1866 u32 addr_hi;
1867 u32 addr_lo;
1868 } addrlist[3];
1869 u32 len2_len1;
1870 u32 resv_len3;
1871 struct tg3_rx_buffer_desc std;
1872};
1873
1874/* We only use this when testing out the DMA engine
1875 * at probe time. This is the internal format of buffer
1876 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
1877 */
1878struct tg3_internal_buffer_desc {
1879 u32 addr_hi;
1880 u32 addr_lo;
1881 u32 nic_mbuf;
1882 /* XXX FIX THIS */
1883#ifdef __BIG_ENDIAN
1884 u16 cqid_sqid;
1885 u16 len;
1886#else
1887 u16 len;
1888 u16 cqid_sqid;
1889#endif
1890 u32 flags;
1891 u32 __cookie1;
1892 u32 __cookie2;
1893 u32 __cookie3;
1894};
1895
1896#define TG3_HW_STATUS_SIZE 0x50
1897struct tg3_hw_status {
1898 u32 status;
1899#define SD_STATUS_UPDATED 0x00000001
1900#define SD_STATUS_LINK_CHG 0x00000002
1901#define SD_STATUS_ERROR 0x00000004
1902
1903 u32 status_tag;
1904
1905#ifdef __BIG_ENDIAN
1906 u16 rx_consumer;
1907 u16 rx_jumbo_consumer;
1908#else
1909 u16 rx_jumbo_consumer;
1910 u16 rx_consumer;
1911#endif
1912
1913#ifdef __BIG_ENDIAN
1914 u16 reserved;
1915 u16 rx_mini_consumer;
1916#else
1917 u16 rx_mini_consumer;
1918 u16 reserved;
1919#endif
1920 struct {
1921#ifdef __BIG_ENDIAN
1922 u16 tx_consumer;
1923 u16 rx_producer;
1924#else
1925 u16 rx_producer;
1926 u16 tx_consumer;
1927#endif
1928 } idx[16];
1929};
1930
1931typedef struct {
1932 u32 high, low;
1933} tg3_stat64_t;
1934
1935struct tg3_hw_stats {
1936 u8 __reserved0[0x400-0x300];
1937
1938 /* Statistics maintained by Receive MAC. */
1939 tg3_stat64_t rx_octets;
1940 u64 __reserved1;
1941 tg3_stat64_t rx_fragments;
1942 tg3_stat64_t rx_ucast_packets;
1943 tg3_stat64_t rx_mcast_packets;
1944 tg3_stat64_t rx_bcast_packets;
1945 tg3_stat64_t rx_fcs_errors;
1946 tg3_stat64_t rx_align_errors;
1947 tg3_stat64_t rx_xon_pause_rcvd;
1948 tg3_stat64_t rx_xoff_pause_rcvd;
1949 tg3_stat64_t rx_mac_ctrl_rcvd;
1950 tg3_stat64_t rx_xoff_entered;
1951 tg3_stat64_t rx_frame_too_long_errors;
1952 tg3_stat64_t rx_jabbers;
1953 tg3_stat64_t rx_undersize_packets;
1954 tg3_stat64_t rx_in_length_errors;
1955 tg3_stat64_t rx_out_length_errors;
1956 tg3_stat64_t rx_64_or_less_octet_packets;
1957 tg3_stat64_t rx_65_to_127_octet_packets;
1958 tg3_stat64_t rx_128_to_255_octet_packets;
1959 tg3_stat64_t rx_256_to_511_octet_packets;
1960 tg3_stat64_t rx_512_to_1023_octet_packets;
1961 tg3_stat64_t rx_1024_to_1522_octet_packets;
1962 tg3_stat64_t rx_1523_to_2047_octet_packets;
1963 tg3_stat64_t rx_2048_to_4095_octet_packets;
1964 tg3_stat64_t rx_4096_to_8191_octet_packets;
1965 tg3_stat64_t rx_8192_to_9022_octet_packets;
1966
1967 u64 __unused0[37];
1968
1969 /* Statistics maintained by Transmit MAC. */
1970 tg3_stat64_t tx_octets;
1971 u64 __reserved2;
1972 tg3_stat64_t tx_collisions;
1973 tg3_stat64_t tx_xon_sent;
1974 tg3_stat64_t tx_xoff_sent;
1975 tg3_stat64_t tx_flow_control;
1976 tg3_stat64_t tx_mac_errors;
1977 tg3_stat64_t tx_single_collisions;
1978 tg3_stat64_t tx_mult_collisions;
1979 tg3_stat64_t tx_deferred;
1980 u64 __reserved3;
1981 tg3_stat64_t tx_excessive_collisions;
1982 tg3_stat64_t tx_late_collisions;
1983 tg3_stat64_t tx_collide_2times;
1984 tg3_stat64_t tx_collide_3times;
1985 tg3_stat64_t tx_collide_4times;
1986 tg3_stat64_t tx_collide_5times;
1987 tg3_stat64_t tx_collide_6times;
1988 tg3_stat64_t tx_collide_7times;
1989 tg3_stat64_t tx_collide_8times;
1990 tg3_stat64_t tx_collide_9times;
1991 tg3_stat64_t tx_collide_10times;
1992 tg3_stat64_t tx_collide_11times;
1993 tg3_stat64_t tx_collide_12times;
1994 tg3_stat64_t tx_collide_13times;
1995 tg3_stat64_t tx_collide_14times;
1996 tg3_stat64_t tx_collide_15times;
1997 tg3_stat64_t tx_ucast_packets;
1998 tg3_stat64_t tx_mcast_packets;
1999 tg3_stat64_t tx_bcast_packets;
2000 tg3_stat64_t tx_carrier_sense_errors;
2001 tg3_stat64_t tx_discards;
2002 tg3_stat64_t tx_errors;
2003
2004 u64 __unused1[31];
2005
2006 /* Statistics maintained by Receive List Placement. */
2007 tg3_stat64_t COS_rx_packets[16];
2008 tg3_stat64_t COS_rx_filter_dropped;
2009 tg3_stat64_t dma_writeq_full;
2010 tg3_stat64_t dma_write_prioq_full;
2011 tg3_stat64_t rxbds_empty;
2012 tg3_stat64_t rx_discards;
2013 tg3_stat64_t rx_errors;
2014 tg3_stat64_t rx_threshold_hit;
2015
2016 u64 __unused2[9];
2017
2018 /* Statistics maintained by Send Data Initiator. */
2019 tg3_stat64_t COS_out_packets[16];
2020 tg3_stat64_t dma_readq_full;
2021 tg3_stat64_t dma_read_prioq_full;
2022 tg3_stat64_t tx_comp_queue_full;
2023
2024 /* Statistics maintained by Host Coalescing. */
2025 tg3_stat64_t ring_set_send_prod_index;
2026 tg3_stat64_t ring_status_update;
2027 tg3_stat64_t nic_irqs;
2028 tg3_stat64_t nic_avoided_irqs;
2029 tg3_stat64_t nic_tx_threshold_hit;
2030
2031 u8 __reserved4[0xb00-0x9c0];
2032};
2033
2034/* 'mapping' is superfluous as the chip does not write into
2035 * the tx/rx post rings so we could just fetch it from there.
2036 * But the cache behavior is better how we are doing it now.
2037 */
2038struct ring_info {
2039 struct sk_buff *skb;
2040 DECLARE_PCI_UNMAP_ADDR(mapping)
2041};
2042
2043struct tx_ring_info {
2044 struct sk_buff *skb;
2045 DECLARE_PCI_UNMAP_ADDR(mapping)
2046 u32 prev_vlan_tag;
2047};
2048
2049struct tg3_config_info {
2050 u32 flags;
2051};
2052
2053struct tg3_link_config {
2054 /* Describes what we're trying to get. */
2055 u32 advertising;
2056 u16 speed;
2057 u8 duplex;
2058 u8 autoneg;
2059
2060 /* Describes what we actually have. */
2061 u16 active_speed;
2062 u8 active_duplex;
2063#define SPEED_INVALID 0xffff
2064#define DUPLEX_INVALID 0xff
2065#define AUTONEG_INVALID 0xff
2066
2067 /* When we go in and out of low power mode we need
2068 * to swap with this state.
2069 */
2070 int phy_is_low_power;
2071 u16 orig_speed;
2072 u8 orig_duplex;
2073 u8 orig_autoneg;
2074};
2075
2076struct tg3_bufmgr_config {
2077 u32 mbuf_read_dma_low_water;
2078 u32 mbuf_mac_rx_low_water;
2079 u32 mbuf_high_water;
2080
2081 u32 mbuf_read_dma_low_water_jumbo;
2082 u32 mbuf_mac_rx_low_water_jumbo;
2083 u32 mbuf_high_water_jumbo;
2084
2085 u32 dma_low_water;
2086 u32 dma_high_water;
2087};
2088
2089struct tg3_ethtool_stats {
2090 /* Statistics maintained by Receive MAC. */
2091 u64 rx_octets;
2092 u64 rx_fragments;
2093 u64 rx_ucast_packets;
2094 u64 rx_mcast_packets;
2095 u64 rx_bcast_packets;
2096 u64 rx_fcs_errors;
2097 u64 rx_align_errors;
2098 u64 rx_xon_pause_rcvd;
2099 u64 rx_xoff_pause_rcvd;
2100 u64 rx_mac_ctrl_rcvd;
2101 u64 rx_xoff_entered;
2102 u64 rx_frame_too_long_errors;
2103 u64 rx_jabbers;
2104 u64 rx_undersize_packets;
2105 u64 rx_in_length_errors;
2106 u64 rx_out_length_errors;
2107 u64 rx_64_or_less_octet_packets;
2108 u64 rx_65_to_127_octet_packets;
2109 u64 rx_128_to_255_octet_packets;
2110 u64 rx_256_to_511_octet_packets;
2111 u64 rx_512_to_1023_octet_packets;
2112 u64 rx_1024_to_1522_octet_packets;
2113 u64 rx_1523_to_2047_octet_packets;
2114 u64 rx_2048_to_4095_octet_packets;
2115 u64 rx_4096_to_8191_octet_packets;
2116 u64 rx_8192_to_9022_octet_packets;
2117
2118 /* Statistics maintained by Transmit MAC. */
2119 u64 tx_octets;
2120 u64 tx_collisions;
2121 u64 tx_xon_sent;
2122 u64 tx_xoff_sent;
2123 u64 tx_flow_control;
2124 u64 tx_mac_errors;
2125 u64 tx_single_collisions;
2126 u64 tx_mult_collisions;
2127 u64 tx_deferred;
2128 u64 tx_excessive_collisions;
2129 u64 tx_late_collisions;
2130 u64 tx_collide_2times;
2131 u64 tx_collide_3times;
2132 u64 tx_collide_4times;
2133 u64 tx_collide_5times;
2134 u64 tx_collide_6times;
2135 u64 tx_collide_7times;
2136 u64 tx_collide_8times;
2137 u64 tx_collide_9times;
2138 u64 tx_collide_10times;
2139 u64 tx_collide_11times;
2140 u64 tx_collide_12times;
2141 u64 tx_collide_13times;
2142 u64 tx_collide_14times;
2143 u64 tx_collide_15times;
2144 u64 tx_ucast_packets;
2145 u64 tx_mcast_packets;
2146 u64 tx_bcast_packets;
2147 u64 tx_carrier_sense_errors;
2148 u64 tx_discards;
2149 u64 tx_errors;
2150
2151 /* Statistics maintained by Receive List Placement. */
2152 u64 dma_writeq_full;
2153 u64 dma_write_prioq_full;
2154 u64 rxbds_empty;
2155 u64 rx_discards;
2156 u64 rx_errors;
2157 u64 rx_threshold_hit;
2158
2159 /* Statistics maintained by Send Data Initiator. */
2160 u64 dma_readq_full;
2161 u64 dma_read_prioq_full;
2162 u64 tx_comp_queue_full;
2163
2164 /* Statistics maintained by Host Coalescing. */
2165 u64 ring_set_send_prod_index;
2166 u64 ring_status_update;
2167 u64 nic_irqs;
2168 u64 nic_avoided_irqs;
2169 u64 nic_tx_threshold_hit;
2170};
2171
2172struct tg3 {
2173 /* begin "general, frequently-used members" cacheline section */
2174
David S. Millerf47c11e2005-06-24 20:18:35 -07002175 /* If the IRQ handler (which runs lockless) needs to be
2176 * quiesced, the following bitmask state is used. The
2177 * SYNC flag is set by non-IRQ context code to initiate
2178 * the quiescence.
2179 *
2180 * When the IRQ handler notices that SYNC is set, it
2181 * disables interrupts and returns.
2182 *
2183 * When all outstanding IRQ handlers have returned after
2184 * the SYNC flag has been set, the setter can be assured
2185 * that interrupts will no longer get run.
2186 *
2187 * In this way all SMP driver locks are never acquired
2188 * in hw IRQ context, only sw IRQ context or lower.
2189 */
2190 unsigned int irq_sync;
2191
Linus Torvalds1da177e2005-04-16 15:20:36 -07002192 /* SMP locking strategy:
2193 *
Michael Chan00b70502006-06-17 21:58:45 -07002194 * lock: Held during reset, PHY access, timer, and when
2195 * updating tg3_flags and tg3_flags2.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002196 *
Michael Chan1b2a7202006-08-07 21:46:02 -07002197 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
2198 * netif_tx_lock when it needs to call
2199 * netif_wake_queue.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002200 *
David S. Millerf47c11e2005-06-24 20:18:35 -07002201 * Both of these locks are to be held with BH safety.
Michael Chan00b70502006-06-17 21:58:45 -07002202 *
2203 * Because the IRQ handler, tg3_poll, and tg3_start_xmit
2204 * are running lockless, it is necessary to completely
2205 * quiesce the chip with tg3_netif_stop and tg3_full_lock
2206 * before reconfiguring the device.
2207 *
2208 * indirect_lock: Held when accessing registers indirectly
2209 * with IRQ disabling.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002210 */
2211 spinlock_t lock;
2212 spinlock_t indirect_lock;
2213
Michael Chan20094932005-08-09 20:16:32 -07002214 u32 (*read32) (struct tg3 *, u32);
2215 void (*write32) (struct tg3 *, u32, u32);
Michael Chan09ee9292005-08-09 20:17:00 -07002216 u32 (*read32_mbox) (struct tg3 *, u32);
Michael Chan20094932005-08-09 20:16:32 -07002217 void (*write32_mbox) (struct tg3 *, u32,
2218 u32);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002219 void __iomem *regs;
Matt Carlson0d3031d2007-10-10 18:02:43 -07002220 void __iomem *aperegs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002221 struct net_device *dev;
2222 struct pci_dev *pdev;
2223
2224 struct tg3_hw_status *hw_status;
2225 dma_addr_t status_mapping;
David S. Millerfac9b832005-05-18 22:46:34 -07002226 u32 last_tag;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002227
2228 u32 msg_enable;
2229
2230 /* begin "tx thread" cacheline section */
Michael Chan20094932005-08-09 20:16:32 -07002231 void (*write32_tx_mbox) (struct tg3 *, u32,
2232 u32);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002233 u32 tx_prod;
2234 u32 tx_cons;
2235 u32 tx_pending;
2236
Linus Torvalds1da177e2005-04-16 15:20:36 -07002237 struct tg3_tx_buffer_desc *tx_ring;
2238 struct tx_ring_info *tx_buffers;
2239 dma_addr_t tx_desc_mapping;
2240
2241 /* begin "rx thread" cacheline section */
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002242 struct napi_struct napi;
Michael Chan20094932005-08-09 20:16:32 -07002243 void (*write32_rx_mbox) (struct tg3 *, u32,
2244 u32);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002245 u32 rx_rcb_ptr;
2246 u32 rx_std_ptr;
2247 u32 rx_jumbo_ptr;
2248 u32 rx_pending;
2249 u32 rx_jumbo_pending;
2250#if TG3_VLAN_TAG_USED
2251 struct vlan_group *vlgrp;
2252#endif
2253
2254 struct tg3_rx_buffer_desc *rx_std;
2255 struct ring_info *rx_std_buffers;
2256 dma_addr_t rx_std_mapping;
Michael Chanf92905d2006-06-29 20:14:29 -07002257 u32 rx_std_max_post;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002258
2259 struct tg3_rx_buffer_desc *rx_jumbo;
2260 struct ring_info *rx_jumbo_buffers;
2261 dma_addr_t rx_jumbo_mapping;
2262
2263 struct tg3_rx_buffer_desc *rx_rcb;
2264 dma_addr_t rx_rcb_mapping;
2265
Michael Chan7e72aad2005-07-25 12:31:17 -07002266 u32 rx_pkt_buf_sz;
2267
Linus Torvalds1da177e2005-04-16 15:20:36 -07002268 /* begin "everything else" cacheline(s) section */
2269 struct net_device_stats net_stats;
2270 struct net_device_stats net_stats_prev;
2271 struct tg3_ethtool_stats estats;
2272 struct tg3_ethtool_stats estats_prev;
2273
2274 unsigned long phy_crc_errors;
2275
2276 u32 rx_offset;
2277 u32 tg3_flags;
David S. Millerfac9b832005-05-18 22:46:34 -07002278#define TG3_FLAG_TAGGED_STATUS 0x00000001
Linus Torvalds1da177e2005-04-16 15:20:36 -07002279#define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
2280#define TG3_FLAG_RX_CHECKSUMS 0x00000004
2281#define TG3_FLAG_USE_LINKCHG_REG 0x00000008
2282#define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
2283#define TG3_FLAG_ENABLE_ASF 0x00000020
Matt Carlson8ed5d972007-05-07 00:25:49 -07002284#define TG3_FLAG_ASPM_WORKAROUND 0x00000040
Linus Torvalds1da177e2005-04-16 15:20:36 -07002285#define TG3_FLAG_POLL_SERDES 0x00000080
Linus Torvalds1da177e2005-04-16 15:20:36 -07002286#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
Linus Torvalds1da177e2005-04-16 15:20:36 -07002287#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
2288#define TG3_FLAG_WOL_SPEED_100MB 0x00000400
2289#define TG3_FLAG_WOL_ENABLE 0x00000800
2290#define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
2291#define TG3_FLAG_NVRAM 0x00002000
2292#define TG3_FLAG_NVRAM_BUFFERED 0x00004000
2293#define TG3_FLAG_RX_PAUSE 0x00008000
2294#define TG3_FLAG_TX_PAUSE 0x00010000
2295#define TG3_FLAG_PCIX_MODE 0x00020000
2296#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
2297#define TG3_FLAG_PCI_32BIT 0x00080000
Michael Chanbbadf502006-04-06 21:46:34 -07002298#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
Michael Chandf3e6542006-05-26 17:48:07 -07002299#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
Gary Zambranoa85feb82007-05-05 11:52:19 -07002300#define TG3_FLAG_WOL_CAP 0x00400000
Michael Chan0f893dc2005-07-25 12:30:38 -07002301#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002302#define TG3_FLAG_10_100_ONLY 0x01000000
2303#define TG3_FLAG_PAUSE_AUTONEG 0x02000000
Matt Carlson795d01c2007-10-07 23:28:17 -07002304#define TG3_FLAG_CPMU_PRESENT 0x04000000
Michael Chan4a29cc22006-03-19 13:21:12 -08002305#define TG3_FLAG_40BIT_DMA_BUG 0x08000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002306#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
Michael Chan7544b092007-05-05 13:08:32 -07002307#define TG3_FLAG_SUPPORT_MSI 0x20000000
Michael Chand18edcb2007-03-24 20:57:11 -07002308#define TG3_FLAG_CHIP_RESETTING 0x40000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002309#define TG3_FLAG_INIT_COMPLETE 0x80000000
2310 u32 tg3_flags2;
2311#define TG3_FLG2_RESTART_TIMER 0x00000001
Michael Chan7f62ad52007-02-20 23:25:40 -08002312#define TG3_FLG2_TSO_BUG 0x00000002
Linus Torvalds1da177e2005-04-16 15:20:36 -07002313#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
2314#define TG3_FLG2_IS_5788 0x00000008
2315#define TG3_FLG2_MAX_RXPEND_64 0x00000010
2316#define TG3_FLG2_TSO_CAPABLE 0x00000020
2317#define TG3_FLG2_PHY_ADC_BUG 0x00000040
2318#define TG3_FLG2_PHY_5704_A0_BUG 0x00000080
2319#define TG3_FLG2_PHY_BER_BUG 0x00000100
2320#define TG3_FLG2_PCI_EXPRESS 0x00000200
2321#define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
2322#define TG3_FLG2_HW_AUTONEG 0x00000800
Michael Chan9d26e212006-12-07 00:21:14 -08002323#define TG3_FLG2_IS_NIC 0x00001000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002324#define TG3_FLG2_PHY_SERDES 0x00002000
2325#define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
2326#define TG3_FLG2_FLASH 0x00008000
Michael Chan5a6f3072006-03-20 22:28:05 -08002327#define TG3_FLG2_HW_TSO_1 0x00010000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002328#define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
2329#define TG3_FLG2_5705_PLUS 0x00040000
John W. Linville6708e5c2005-04-21 17:00:52 -07002330#define TG3_FLG2_5750_PLUS 0x00080000
Michael Chane6af3012005-04-21 17:12:05 -07002331#define TG3_FLG2_PROTECTED_NVRAM 0x00100000
Michael Chan88b06bc22005-04-21 17:13:25 -07002332#define TG3_FLG2_USING_MSI 0x00200000
Michael Chan0f893dc2005-07-25 12:30:38 -07002333#define TG3_FLG2_JUMBO_CAPABLE 0x00400000
Michael Chan747e8f82005-07-25 12:33:22 -07002334#define TG3_FLG2_MII_SERDES 0x00800000
2335#define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \
2336 TG3_FLG2_MII_SERDES)
2337#define TG3_FLG2_PARALLEL_DETECT 0x01000000
Michael Chan68929142005-08-09 20:17:14 -07002338#define TG3_FLG2_ICH_WORKAROUND 0x02000000
Michael Chana4e2b342005-10-26 15:46:52 -07002339#define TG3_FLG2_5780_CLASS 0x04000000
Michael Chan5a6f3072006-03-20 22:28:05 -08002340#define TG3_FLG2_HW_TSO_2 0x08000000
2341#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
Michael Chanfcfa0a32006-03-20 22:28:41 -08002342#define TG3_FLG2_1SHOT_MSI 0x10000000
Michael Chanc424cb22006-04-29 18:56:34 -07002343#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
David S. Millerf49639e2006-06-09 11:58:36 -07002344#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
Michael Chanc1d2a192007-01-08 19:57:20 -08002345#define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000
Matt Carlson6b91fa02007-10-10 18:01:09 -07002346 u32 tg3_flags3;
2347#define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001
Matt Carlson0d3031d2007-10-10 18:02:43 -07002348#define TG3_FLG3_ENABLE_APE 0x00000002
Linus Torvalds1da177e2005-04-16 15:20:36 -07002349
Linus Torvalds1da177e2005-04-16 15:20:36 -07002350 struct timer_list timer;
2351 u16 timer_counter;
2352 u16 timer_multiplier;
2353 u32 timer_offset;
2354 u16 asf_counter;
2355 u16 asf_multiplier;
2356
Michael Chan3d3ebe72006-09-27 15:59:15 -07002357 /* 1 second counter for transient serdes link events */
2358 u32 serdes_counter;
2359#define SERDES_AN_TIMEOUT_5704S 2
2360#define SERDES_PARALLEL_DET_TIMEOUT 1
2361#define SERDES_AN_TIMEOUT_5714S 1
2362
Linus Torvalds1da177e2005-04-16 15:20:36 -07002363 struct tg3_link_config link_config;
2364 struct tg3_bufmgr_config bufmgr_config;
2365
2366 /* cache h/w values, often passed straight to h/w */
2367 u32 rx_mode;
2368 u32 tx_mode;
2369 u32 mac_mode;
2370 u32 mi_mode;
2371 u32 misc_host_ctrl;
2372 u32 grc_mode;
2373 u32 grc_local_ctrl;
2374 u32 dma_rwctrl;
2375 u32 coalesce_mode;
Matt Carlson8ed5d972007-05-07 00:25:49 -07002376 u32 pwrmgmt_thresh;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002377
2378 /* PCI block */
Matt Carlson795d01c2007-10-07 23:28:17 -07002379 u32 pci_chip_rev_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002380 u8 pci_cacheline_sz;
2381 u8 pci_lat_timer;
2382 u8 pci_hdr_type;
2383 u8 pci_bist;
2384
2385 int pm_cap;
Michael Chan4cf78e42005-07-25 12:29:19 -07002386 int msi_cap;
Matt Carlson9974a352007-10-07 23:27:28 -07002387 int pcix_cap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002388
2389 /* PHY info */
2390 u32 phy_id;
2391#define PHY_ID_MASK 0xfffffff0
2392#define PHY_ID_BCM5400 0x60008040
2393#define PHY_ID_BCM5401 0x60008050
2394#define PHY_ID_BCM5411 0x60008070
2395#define PHY_ID_BCM5701 0x60008110
2396#define PHY_ID_BCM5703 0x60008160
2397#define PHY_ID_BCM5704 0x60008190
2398#define PHY_ID_BCM5705 0x600081a0
2399#define PHY_ID_BCM5750 0x60008180
Michael Chan85e94ce2005-04-21 17:05:28 -07002400#define PHY_ID_BCM5752 0x60008100
Michael Chana4e2b342005-10-26 15:46:52 -07002401#define PHY_ID_BCM5714 0x60008340
Michael Chan4cf78e42005-07-25 12:29:19 -07002402#define PHY_ID_BCM5780 0x60008350
Michael Chanaf36e6b2006-03-23 01:28:06 -08002403#define PHY_ID_BCM5755 0xbc050cc0
Michael Chand9ab5ad2006-03-20 22:27:35 -08002404#define PHY_ID_BCM5787 0xbc050ce0
Michael Chan126a3362006-09-27 16:03:07 -07002405#define PHY_ID_BCM5756 0xbc050ed0
Matt Carlsond30cdd22007-10-07 23:28:35 -07002406#define PHY_ID_BCM5784 0xbc050fa0
Matt Carlson9936bcf2007-10-10 18:03:07 -07002407#define PHY_ID_BCM5761 0xbc050fd0
Michael Chanb5d37722006-09-27 16:06:21 -07002408#define PHY_ID_BCM5906 0xdc00ac40
Linus Torvalds1da177e2005-04-16 15:20:36 -07002409#define PHY_ID_BCM8002 0x60010140
2410#define PHY_ID_INVALID 0xffffffff
2411#define PHY_ID_REV_MASK 0x0000000f
2412#define PHY_REV_BCM5401_B0 0x1
2413#define PHY_REV_BCM5401_B2 0x3
2414#define PHY_REV_BCM5401_C0 0x6
2415#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
2416
2417 u32 led_ctrl;
Michael Chanee6a99b2007-07-18 21:49:10 -07002418 u32 pci_cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002419
2420 char board_part_number[24];
Michael Chanc4e65752006-03-20 22:29:32 -08002421 char fw_ver[16];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002422 u32 nic_sram_data_cfg;
2423 u32 pci_clock_ctrl;
2424 struct pci_dev *pdev_peer;
2425
2426 /* This macro assumes the passed PHY ID is already masked
2427 * with PHY_ID_MASK.
2428 */
2429#define KNOWN_PHY_ID(X) \
2430 ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2431 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2432 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2433 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
Michael Chana4e2b342005-10-26 15:46:52 -07002434 (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
Michael Chand9ab5ad2006-03-20 22:27:35 -08002435 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
Michael Chan126a3362006-09-27 16:03:07 -07002436 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
Matt Carlson9936bcf2007-10-10 18:03:07 -07002437 (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
2438 (X) == PHY_ID_BCM8002)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002439
2440 struct tg3_hw_stats *hw_stats;
2441 dma_addr_t stats_mapping;
2442 struct work_struct reset_task;
2443
Michael Chanec41c7d2006-01-17 02:40:55 -08002444 int nvram_lock_cnt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002445 u32 nvram_size;
2446 u32 nvram_pagesize;
2447 u32 nvram_jedecnum;
2448
2449#define JEDEC_ATMEL 0x1f
2450#define JEDEC_ST 0x20
2451#define JEDEC_SAIFUN 0x4f
2452#define JEDEC_SST 0xbf
2453
2454#define ATMEL_AT24C64_CHIP_SIZE (64 * 1024)
2455#define ATMEL_AT24C64_PAGE_SIZE (32)
2456
2457#define ATMEL_AT24C512_CHIP_SIZE (512 * 1024)
2458#define ATMEL_AT24C512_PAGE_SIZE (128)
2459
2460#define ATMEL_AT45DB0X1B_PAGE_POS 9
2461#define ATMEL_AT45DB0X1B_PAGE_SIZE 264
2462
2463#define ATMEL_AT25F512_PAGE_SIZE 256
2464
2465#define ST_M45PEX0_PAGE_SIZE 256
2466
2467#define SAIFUN_SA25F0XX_PAGE_SIZE 256
2468
2469#define SST_25VF0X0_PAGE_SIZE 4098
2470
David S. Miller15f98502005-05-18 22:49:26 -07002471 struct ethtool_coalesce coal;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002472};
2473
2474#endif /* !(_T3_H) */