Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2001-2002 by David Brownell |
David Brownell | 53bd6a6 | 2006-08-30 14:50:06 -0700 | [diff] [blame] | 3 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms of the GNU General Public License as published by the |
| 6 | * Free Software Foundation; either version 2 of the License, or (at your |
| 7 | * option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but |
| 10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 12 | * for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software Foundation, |
| 16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 17 | */ |
| 18 | |
| 19 | #ifndef __LINUX_EHCI_HCD_H |
| 20 | #define __LINUX_EHCI_HCD_H |
| 21 | |
| 22 | /* definitions used for the EHCI driver */ |
| 23 | |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 24 | /* |
| 25 | * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to |
| 26 | * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on |
| 27 | * the host controller implementation. |
| 28 | * |
| 29 | * To facilitate the strongest possible byte-order checking from "sparse" |
| 30 | * and so on, we use __leXX unless that's not practical. |
| 31 | */ |
| 32 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC |
| 33 | typedef __u32 __bitwise __hc32; |
| 34 | typedef __u16 __bitwise __hc16; |
| 35 | #else |
| 36 | #define __hc32 __le32 |
| 37 | #define __hc16 __le16 |
| 38 | #endif |
| 39 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | /* statistics can be kept for for tuning/monitoring */ |
| 41 | struct ehci_stats { |
| 42 | /* irq usage */ |
| 43 | unsigned long normal; |
| 44 | unsigned long error; |
| 45 | unsigned long reclaim; |
| 46 | unsigned long lost_iaa; |
| 47 | |
| 48 | /* termination of urbs from core */ |
| 49 | unsigned long complete; |
| 50 | unsigned long unlink; |
| 51 | }; |
| 52 | |
| 53 | /* ehci_hcd->lock guards shared data against other CPUs: |
| 54 | * ehci_hcd: async, reclaim, periodic (and shadow), ... |
| 55 | * usb_host_endpoint: hcpriv |
| 56 | * ehci_qh: qh_next, qtd_list |
| 57 | * ehci_qtd: qtd_list |
| 58 | * |
| 59 | * Also, hold this lock when talking to HC registers or |
| 60 | * when updating hw_* fields in shared qh/qtd/... structures. |
| 61 | */ |
| 62 | |
| 63 | #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ |
| 64 | |
| 65 | struct ehci_hcd { /* one per controller */ |
David Brownell | 56c1e26 | 2005-04-09 09:00:29 -0700 | [diff] [blame] | 66 | /* glue to PCI and HCD framework */ |
| 67 | struct ehci_caps __iomem *caps; |
| 68 | struct ehci_regs __iomem *regs; |
| 69 | struct ehci_dbg_port __iomem *debug; |
| 70 | |
| 71 | __u32 hcs_params; /* cached register copy */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | spinlock_t lock; |
| 73 | |
| 74 | /* async schedule support */ |
| 75 | struct ehci_qh *async; |
| 76 | struct ehci_qh *reclaim; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | unsigned scanning : 1; |
| 78 | |
| 79 | /* periodic schedule support */ |
| 80 | #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ |
| 81 | unsigned periodic_size; |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 82 | __hc32 *periodic; /* hw periodic table */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | dma_addr_t periodic_dma; |
| 84 | unsigned i_thresh; /* uframes HC might cache */ |
| 85 | |
| 86 | union ehci_shadow *pshadow; /* mirror hw periodic table */ |
| 87 | int next_uframe; /* scan periodic, start here */ |
| 88 | unsigned periodic_sched; /* periodic activity count */ |
| 89 | |
| 90 | /* per root hub port */ |
| 91 | unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; |
Alan Stern | 383975d | 2007-05-04 11:52:40 -0400 | [diff] [blame] | 92 | |
Alan Stern | 57e06c1 | 2007-01-16 11:59:45 -0500 | [diff] [blame] | 93 | /* bit vectors (one bit per port) */ |
| 94 | unsigned long bus_suspended; /* which ports were |
| 95 | already suspended at the start of a bus suspend */ |
| 96 | unsigned long companion_ports; /* which ports are |
| 97 | dedicated to the companion controller */ |
Alan Stern | 383975d | 2007-05-04 11:52:40 -0400 | [diff] [blame] | 98 | unsigned long owned_ports; /* which ports are |
| 99 | owned by the companion during a bus suspend */ |
Alan Stern | d1f114d | 2008-05-20 16:58:58 -0400 | [diff] [blame] | 100 | unsigned long port_c_suspend; /* which ports have |
| 101 | the change-suspend feature turned on */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | |
| 103 | /* per-HC memory pools (could be per-bus, but ...) */ |
| 104 | struct dma_pool *qh_pool; /* qh per active urb */ |
| 105 | struct dma_pool *qtd_pool; /* one or more per qh */ |
| 106 | struct dma_pool *itd_pool; /* itd per iso urb */ |
| 107 | struct dma_pool *sitd_pool; /* sitd per split iso urb */ |
| 108 | |
Alan Stern | 07d29b6 | 2007-12-11 16:05:30 -0500 | [diff] [blame] | 109 | struct timer_list iaa_watchdog; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | struct timer_list watchdog; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | unsigned long actions; |
| 112 | unsigned stamp; |
| 113 | unsigned long next_statechange; |
| 114 | u32 command; |
| 115 | |
Kumar Gala | 8cd42e9 | 2006-01-20 13:57:52 -0800 | [diff] [blame] | 116 | /* SILICON QUIRKS */ |
David Brownell | f8aeb3b | 2006-01-20 13:55:14 -0800 | [diff] [blame] | 117 | unsigned no_selective_suspend:1; |
Kumar Gala | 8cd42e9 | 2006-01-20 13:57:52 -0800 | [diff] [blame] | 118 | unsigned has_fsl_port_bug:1; /* FreeScale */ |
Benjamin Herrenschmidt | 083522d | 2006-12-15 06:54:08 +1100 | [diff] [blame] | 119 | unsigned big_endian_mmio:1; |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 120 | unsigned big_endian_desc:1; |
Kumar Gala | 8cd42e9 | 2006-01-20 13:57:52 -0800 | [diff] [blame] | 121 | |
David Brownell | f8aeb3b | 2006-01-20 13:55:14 -0800 | [diff] [blame] | 122 | u8 sbrn; /* packed release number */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 123 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 124 | /* irq statistics */ |
| 125 | #ifdef EHCI_STATS |
| 126 | struct ehci_stats stats; |
| 127 | # define COUNT(x) do { (x)++; } while (0) |
| 128 | #else |
| 129 | # define COUNT(x) do {} while (0) |
| 130 | #endif |
Tony Jones | 694cc20 | 2007-09-11 14:07:31 -0700 | [diff] [blame] | 131 | |
| 132 | /* debug files */ |
| 133 | #ifdef DEBUG |
| 134 | struct dentry *debug_dir; |
| 135 | struct dentry *debug_async; |
| 136 | struct dentry *debug_periodic; |
| 137 | struct dentry *debug_registers; |
| 138 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | }; |
| 140 | |
David Brownell | 53bd6a6 | 2006-08-30 14:50:06 -0700 | [diff] [blame] | 141 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 142 | static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) |
| 143 | { |
| 144 | return (struct ehci_hcd *) (hcd->hcd_priv); |
| 145 | } |
| 146 | static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) |
| 147 | { |
| 148 | return container_of ((void *) ehci, struct usb_hcd, hcd_priv); |
| 149 | } |
| 150 | |
| 151 | |
Alan Stern | 07d29b6 | 2007-12-11 16:05:30 -0500 | [diff] [blame] | 152 | static inline void |
| 153 | iaa_watchdog_start(struct ehci_hcd *ehci) |
| 154 | { |
| 155 | WARN_ON(timer_pending(&ehci->iaa_watchdog)); |
| 156 | mod_timer(&ehci->iaa_watchdog, |
| 157 | jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); |
| 158 | } |
| 159 | |
| 160 | static inline void iaa_watchdog_done(struct ehci_hcd *ehci) |
| 161 | { |
| 162 | del_timer(&ehci->iaa_watchdog); |
| 163 | } |
| 164 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 165 | enum ehci_timer_action { |
| 166 | TIMER_IO_WATCHDOG, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 167 | TIMER_ASYNC_SHRINK, |
| 168 | TIMER_ASYNC_OFF, |
| 169 | }; |
| 170 | |
| 171 | static inline void |
| 172 | timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) |
| 173 | { |
| 174 | clear_bit (action, &ehci->actions); |
| 175 | } |
| 176 | |
| 177 | static inline void |
| 178 | timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action) |
| 179 | { |
David Brownell | 056761e | 2008-06-13 23:56:48 -0700 | [diff] [blame^] | 180 | /* Don't override timeouts which shrink or (later) disable |
| 181 | * the async ring; just the I/O watchdog. Note that if a |
| 182 | * SHRINK were pending, OFF would never be requested. |
| 183 | */ |
| 184 | if (timer_pending(&ehci->watchdog) |
| 185 | && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) |
| 186 | & ehci->actions)) |
| 187 | return; |
| 188 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 189 | if (!test_and_set_bit (action, &ehci->actions)) { |
| 190 | unsigned long t; |
| 191 | |
| 192 | switch (action) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | case TIMER_IO_WATCHDOG: |
| 194 | t = EHCI_IO_JIFFIES; |
| 195 | break; |
| 196 | case TIMER_ASYNC_OFF: |
| 197 | t = EHCI_ASYNC_JIFFIES; |
| 198 | break; |
| 199 | // case TIMER_ASYNC_SHRINK: |
| 200 | default: |
| 201 | t = EHCI_SHRINK_JIFFIES; |
| 202 | break; |
| 203 | } |
David Brownell | 056761e | 2008-06-13 23:56:48 -0700 | [diff] [blame^] | 204 | mod_timer(&ehci->watchdog, t + jiffies); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | } |
| 206 | } |
| 207 | |
| 208 | /*-------------------------------------------------------------------------*/ |
| 209 | |
| 210 | /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ |
| 211 | |
| 212 | /* Section 2.2 Host Controller Capability Registers */ |
| 213 | struct ehci_caps { |
| 214 | /* these fields are specified as 8 and 16 bit registers, |
| 215 | * but some hosts can't perform 8 or 16 bit PCI accesses. |
| 216 | */ |
David Brownell | 56c1e26 | 2005-04-09 09:00:29 -0700 | [diff] [blame] | 217 | u32 hc_capbase; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ |
| 219 | #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ |
| 220 | u32 hcs_params; /* HCSPARAMS - offset 0x4 */ |
| 221 | #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ |
| 222 | #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ |
| 223 | #define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ |
| 224 | #define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ |
David Brownell | 53bd6a6 | 2006-08-30 14:50:06 -0700 | [diff] [blame] | 225 | #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ |
| 226 | #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 227 | #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ |
| 228 | |
| 229 | u32 hcc_params; /* HCCPARAMS - offset 0x8 */ |
| 230 | #define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ |
| 231 | #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ |
| 232 | #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ |
| 233 | #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ |
| 234 | #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ |
| 235 | #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ |
| 236 | u8 portroute [8]; /* nibbles for routing - offset 0xC */ |
| 237 | } __attribute__ ((packed)); |
| 238 | |
| 239 | |
| 240 | /* Section 2.3 Host Controller Operational Registers */ |
| 241 | struct ehci_regs { |
| 242 | |
| 243 | /* USBCMD: offset 0x00 */ |
| 244 | u32 command; |
| 245 | /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ |
| 246 | #define CMD_PARK (1<<11) /* enable "park" on async qh */ |
| 247 | #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ |
| 248 | #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ |
| 249 | #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ |
| 250 | #define CMD_ASE (1<<5) /* async schedule enable */ |
David Brownell | 53bd6a6 | 2006-08-30 14:50:06 -0700 | [diff] [blame] | 251 | #define CMD_PSE (1<<4) /* periodic schedule enable */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 252 | /* 3:2 is periodic frame list size */ |
| 253 | #define CMD_RESET (1<<1) /* reset HC not bus */ |
| 254 | #define CMD_RUN (1<<0) /* start/stop HC */ |
| 255 | |
| 256 | /* USBSTS: offset 0x04 */ |
| 257 | u32 status; |
| 258 | #define STS_ASS (1<<15) /* Async Schedule Status */ |
| 259 | #define STS_PSS (1<<14) /* Periodic Schedule Status */ |
| 260 | #define STS_RECL (1<<13) /* Reclamation */ |
| 261 | #define STS_HALT (1<<12) /* Not running (any reason) */ |
| 262 | /* some bits reserved */ |
| 263 | /* these STS_* flags are also intr_enable bits (USBINTR) */ |
| 264 | #define STS_IAA (1<<5) /* Interrupted on async advance */ |
| 265 | #define STS_FATAL (1<<4) /* such as some PCI access errors */ |
| 266 | #define STS_FLR (1<<3) /* frame list rolled over */ |
| 267 | #define STS_PCD (1<<2) /* port change detect */ |
| 268 | #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ |
| 269 | #define STS_INT (1<<0) /* "normal" completion (short, ...) */ |
| 270 | |
| 271 | /* USBINTR: offset 0x08 */ |
| 272 | u32 intr_enable; |
| 273 | |
| 274 | /* FRINDEX: offset 0x0C */ |
| 275 | u32 frame_index; /* current microframe number */ |
| 276 | /* CTRLDSSEGMENT: offset 0x10 */ |
David Brownell | 53bd6a6 | 2006-08-30 14:50:06 -0700 | [diff] [blame] | 277 | u32 segment; /* address bits 63:32 if needed */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 278 | /* PERIODICLISTBASE: offset 0x14 */ |
David Brownell | 53bd6a6 | 2006-08-30 14:50:06 -0700 | [diff] [blame] | 279 | u32 frame_list; /* points to periodic list */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 280 | /* ASYNCLISTADDR: offset 0x18 */ |
| 281 | u32 async_next; /* address of next async queue head */ |
| 282 | |
| 283 | u32 reserved [9]; |
| 284 | |
| 285 | /* CONFIGFLAG: offset 0x40 */ |
| 286 | u32 configured_flag; |
| 287 | #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ |
| 288 | |
| 289 | /* PORTSC: offset 0x44 */ |
| 290 | u32 port_status [0]; /* up to N_PORTS */ |
| 291 | /* 31:23 reserved */ |
| 292 | #define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ |
| 293 | #define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ |
| 294 | #define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ |
| 295 | /* 19:16 for port testing */ |
| 296 | #define PORT_LED_OFF (0<<14) |
| 297 | #define PORT_LED_AMBER (1<<14) |
| 298 | #define PORT_LED_GREEN (2<<14) |
| 299 | #define PORT_LED_MASK (3<<14) |
| 300 | #define PORT_OWNER (1<<13) /* true: companion hc owns this port */ |
| 301 | #define PORT_POWER (1<<12) /* true: has power (see PPC) */ |
| 302 | #define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */ |
| 303 | /* 11:10 for detecting lowspeed devices (reset vs release ownership) */ |
| 304 | /* 9 reserved */ |
| 305 | #define PORT_RESET (1<<8) /* reset port */ |
| 306 | #define PORT_SUSPEND (1<<7) /* suspend port */ |
| 307 | #define PORT_RESUME (1<<6) /* resume it */ |
| 308 | #define PORT_OCC (1<<5) /* over current change */ |
| 309 | #define PORT_OC (1<<4) /* over current active */ |
| 310 | #define PORT_PEC (1<<3) /* port enable change */ |
| 311 | #define PORT_PE (1<<2) /* port enable */ |
| 312 | #define PORT_CSC (1<<1) /* connect status change */ |
| 313 | #define PORT_CONNECT (1<<0) /* device connected */ |
David Brownell | 10f6524 | 2005-08-31 10:55:38 -0700 | [diff] [blame] | 314 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | } __attribute__ ((packed)); |
| 316 | |
Vladimir Barinov | d23a137 | 2007-05-23 20:07:48 +0400 | [diff] [blame] | 317 | #define USBMODE 0x68 /* USB Device mode */ |
| 318 | #define USBMODE_SDIS (1<<3) /* Stream disable */ |
| 319 | #define USBMODE_BE (1<<2) /* BE/LE endianness select */ |
| 320 | #define USBMODE_CM_HC (3<<0) /* host controller mode */ |
| 321 | #define USBMODE_CM_IDLE (0<<0) /* idle state */ |
| 322 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 323 | /* Appendix C, Debug port ... intended for use with special "debug devices" |
| 324 | * that can help if there's no serial console. (nonstandard enumeration.) |
| 325 | */ |
| 326 | struct ehci_dbg_port { |
| 327 | u32 control; |
| 328 | #define DBGP_OWNER (1<<30) |
| 329 | #define DBGP_ENABLED (1<<28) |
| 330 | #define DBGP_DONE (1<<16) |
| 331 | #define DBGP_INUSE (1<<10) |
David Brownell | 56c1e26 | 2005-04-09 09:00:29 -0700 | [diff] [blame] | 332 | #define DBGP_ERRCODE(x) (((x)>>7)&0x07) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 333 | # define DBGP_ERR_BAD 1 |
| 334 | # define DBGP_ERR_SIGNAL 2 |
| 335 | #define DBGP_ERROR (1<<6) |
| 336 | #define DBGP_GO (1<<5) |
| 337 | #define DBGP_OUT (1<<4) |
| 338 | #define DBGP_LEN(x) (((x)>>0)&0x0f) |
| 339 | u32 pids; |
| 340 | #define DBGP_PID_GET(x) (((x)>>16)&0xff) |
David Brownell | 56c1e26 | 2005-04-09 09:00:29 -0700 | [diff] [blame] | 341 | #define DBGP_PID_SET(data,tok) (((data)<<8)|(tok)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 342 | u32 data03; |
| 343 | u32 data47; |
| 344 | u32 address; |
David Brownell | 56c1e26 | 2005-04-09 09:00:29 -0700 | [diff] [blame] | 345 | #define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 346 | } __attribute__ ((packed)); |
| 347 | |
| 348 | /*-------------------------------------------------------------------------*/ |
| 349 | |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 350 | #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | |
| 352 | /* |
| 353 | * EHCI Specification 0.95 Section 3.5 |
David Brownell | 53bd6a6 | 2006-08-30 14:50:06 -0700 | [diff] [blame] | 354 | * QTD: describe data transfer components (buffer, direction, ...) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 355 | * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". |
| 356 | * |
| 357 | * These are associated only with "QH" (Queue Head) structures, |
| 358 | * used with control, bulk, and interrupt transfers. |
| 359 | */ |
| 360 | struct ehci_qtd { |
| 361 | /* first part defined by EHCI spec */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 362 | __hc32 hw_next; /* see EHCI 3.5.1 */ |
| 363 | __hc32 hw_alt_next; /* see EHCI 3.5.2 */ |
| 364 | __hc32 hw_token; /* see EHCI 3.5.3 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 365 | #define QTD_TOGGLE (1 << 31) /* data toggle */ |
| 366 | #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) |
| 367 | #define QTD_IOC (1 << 15) /* interrupt on complete */ |
| 368 | #define QTD_CERR(tok) (((tok)>>10) & 0x3) |
| 369 | #define QTD_PID(tok) (((tok)>>8) & 0x3) |
| 370 | #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ |
| 371 | #define QTD_STS_HALT (1 << 6) /* halted on error */ |
| 372 | #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ |
| 373 | #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ |
| 374 | #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ |
| 375 | #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ |
| 376 | #define QTD_STS_STS (1 << 1) /* split transaction state */ |
| 377 | #define QTD_STS_PING (1 << 0) /* issue PING? */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 378 | |
| 379 | #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) |
| 380 | #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) |
| 381 | #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) |
| 382 | |
| 383 | __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ |
| 384 | __hc32 hw_buf_hi [5]; /* Appendix B */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 385 | |
| 386 | /* the rest is HCD-private */ |
| 387 | dma_addr_t qtd_dma; /* qtd address */ |
| 388 | struct list_head qtd_list; /* sw qtd list */ |
| 389 | struct urb *urb; /* qtd's urb */ |
| 390 | size_t length; /* length of buffer */ |
| 391 | } __attribute__ ((aligned (32))); |
| 392 | |
| 393 | /* mask NakCnt+T in qh->hw_alt_next */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 394 | #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | |
| 396 | #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) |
| 397 | |
| 398 | /*-------------------------------------------------------------------------*/ |
| 399 | |
| 400 | /* type tag from {qh,itd,sitd,fstn}->hw_next */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 401 | #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 402 | |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 403 | /* |
| 404 | * Now the following defines are not converted using the |
| 405 | * __constant_cpu_to_le32() macro anymore, since we have to support |
| 406 | * "dynamic" switching between be and le support, so that the driver |
| 407 | * can be used on one system with SoC EHCI controller using big-endian |
| 408 | * descriptors as well as a normal little-endian PCI EHCI controller. |
| 409 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 410 | /* values for that type tag */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 411 | #define Q_TYPE_ITD (0 << 1) |
| 412 | #define Q_TYPE_QH (1 << 1) |
| 413 | #define Q_TYPE_SITD (2 << 1) |
| 414 | #define Q_TYPE_FSTN (3 << 1) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 415 | |
| 416 | /* next async queue entry, or pointer to interrupt/periodic QH */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 417 | #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 418 | |
| 419 | /* for periodic/async schedules and qtd lists, mark end of list */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 420 | #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 421 | |
| 422 | /* |
| 423 | * Entries in periodic shadow table are pointers to one of four kinds |
| 424 | * of data structure. That's dictated by the hardware; a type tag is |
| 425 | * encoded in the low bits of the hardware's periodic schedule. Use |
| 426 | * Q_NEXT_TYPE to get the tag. |
| 427 | * |
| 428 | * For entries in the async schedule, the type tag always says "qh". |
| 429 | */ |
| 430 | union ehci_shadow { |
David Brownell | 53bd6a6 | 2006-08-30 14:50:06 -0700 | [diff] [blame] | 431 | struct ehci_qh *qh; /* Q_TYPE_QH */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 432 | struct ehci_itd *itd; /* Q_TYPE_ITD */ |
| 433 | struct ehci_sitd *sitd; /* Q_TYPE_SITD */ |
| 434 | struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 435 | __hc32 *hw_next; /* (all types) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 436 | void *ptr; |
| 437 | }; |
| 438 | |
| 439 | /*-------------------------------------------------------------------------*/ |
| 440 | |
| 441 | /* |
| 442 | * EHCI Specification 0.95 Section 3.6 |
| 443 | * QH: describes control/bulk/interrupt endpoints |
| 444 | * See Fig 3-7 "Queue Head Structure Layout". |
| 445 | * |
| 446 | * These appear in both the async and (for interrupt) periodic schedules. |
| 447 | */ |
| 448 | |
| 449 | struct ehci_qh { |
| 450 | /* first part defined by EHCI spec */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 451 | __hc32 hw_next; /* see EHCI 3.6.1 */ |
| 452 | __hc32 hw_info1; /* see EHCI 3.6.2 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | #define QH_HEAD 0x00008000 |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 454 | __hc32 hw_info2; /* see EHCI 3.6.2 */ |
David Brownell | 7dedacf | 2005-08-04 18:06:41 -0700 | [diff] [blame] | 455 | #define QH_SMASK 0x000000ff |
| 456 | #define QH_CMASK 0x0000ff00 |
| 457 | #define QH_HUBADDR 0x007f0000 |
| 458 | #define QH_HUBPORT 0x3f800000 |
| 459 | #define QH_MULT 0xc0000000 |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 460 | __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ |
David Brownell | 53bd6a6 | 2006-08-30 14:50:06 -0700 | [diff] [blame] | 461 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 462 | /* qtd overlay (hardware parts of a struct ehci_qtd) */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 463 | __hc32 hw_qtd_next; |
| 464 | __hc32 hw_alt_next; |
| 465 | __hc32 hw_token; |
| 466 | __hc32 hw_buf [5]; |
| 467 | __hc32 hw_buf_hi [5]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 468 | |
| 469 | /* the rest is HCD-private */ |
| 470 | dma_addr_t qh_dma; /* address of qh */ |
| 471 | union ehci_shadow qh_next; /* ptr to qh; or periodic */ |
| 472 | struct list_head qtd_list; /* sw qtd list */ |
| 473 | struct ehci_qtd *dummy; |
| 474 | struct ehci_qh *reclaim; /* next to reclaim */ |
| 475 | |
| 476 | struct ehci_hcd *ehci; |
David Brownell | 9c033e8 | 2007-05-17 12:21:19 -0700 | [diff] [blame] | 477 | |
| 478 | /* |
| 479 | * Do NOT use atomic operations for QH refcounting. On some CPUs |
| 480 | * (PPC7448 for example), atomic operations cannot be performed on |
| 481 | * memory that is cache-inhibited (i.e. being used for DMA). |
| 482 | * Spinlocks are used to protect all QH fields. |
| 483 | */ |
| 484 | u32 refcount; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 485 | unsigned stamp; |
| 486 | |
| 487 | u8 qh_state; |
| 488 | #define QH_STATE_LINKED 1 /* HC sees this */ |
| 489 | #define QH_STATE_UNLINK 2 /* HC may still see this */ |
| 490 | #define QH_STATE_IDLE 3 /* HC doesn't see this */ |
| 491 | #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ |
| 492 | #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ |
| 493 | |
| 494 | /* periodic schedule info */ |
| 495 | u8 usecs; /* intr bandwidth */ |
| 496 | u8 gap_uf; /* uframes split/csplit gap */ |
| 497 | u8 c_usecs; /* ... split completion bw */ |
david-b@pacbell.net | d038420 | 2005-08-13 18:44:58 -0700 | [diff] [blame] | 498 | u16 tt_usecs; /* tt downstream bandwidth */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 499 | unsigned short period; /* polling interval */ |
| 500 | unsigned short start; /* where polling starts */ |
| 501 | #define NO_FRAME ((unsigned short)~0) /* pick new start */ |
| 502 | struct usb_device *dev; /* access to TT */ |
| 503 | } __attribute__ ((aligned (32))); |
| 504 | |
| 505 | /*-------------------------------------------------------------------------*/ |
| 506 | |
| 507 | /* description of one iso transaction (up to 3 KB data if highspeed) */ |
| 508 | struct ehci_iso_packet { |
| 509 | /* These will be copied to iTD when scheduling */ |
| 510 | u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 511 | __hc32 transaction; /* itd->hw_transaction[i] |= */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 512 | u8 cross; /* buf crosses pages */ |
| 513 | /* for full speed OUT splits */ |
| 514 | u32 buf1; |
| 515 | }; |
| 516 | |
| 517 | /* temporary schedule data for packets from iso urbs (both speeds) |
| 518 | * each packet is one logical usb transaction to the device (not TT), |
| 519 | * beginning at stream->next_uframe |
| 520 | */ |
| 521 | struct ehci_iso_sched { |
| 522 | struct list_head td_list; |
| 523 | unsigned span; |
| 524 | struct ehci_iso_packet packet [0]; |
| 525 | }; |
| 526 | |
| 527 | /* |
| 528 | * ehci_iso_stream - groups all (s)itds for this endpoint. |
| 529 | * acts like a qh would, if EHCI had them for ISO. |
| 530 | */ |
| 531 | struct ehci_iso_stream { |
| 532 | /* first two fields match QH, but info1 == 0 */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 533 | __hc32 hw_next; |
| 534 | __hc32 hw_info1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 535 | |
| 536 | u32 refcount; |
| 537 | u8 bEndpointAddress; |
| 538 | u8 highspeed; |
| 539 | u16 depth; /* depth in uframes */ |
| 540 | struct list_head td_list; /* queued itds/sitds */ |
| 541 | struct list_head free_list; /* list of unused itds/sitds */ |
| 542 | struct usb_device *udev; |
David Brownell | 53bd6a6 | 2006-08-30 14:50:06 -0700 | [diff] [blame] | 543 | struct usb_host_endpoint *ep; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 544 | |
| 545 | /* output of (re)scheduling */ |
| 546 | unsigned long start; /* jiffies */ |
| 547 | unsigned long rescheduled; |
| 548 | int next_uframe; |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 549 | __hc32 splits; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 550 | |
| 551 | /* the rest is derived from the endpoint descriptor, |
| 552 | * trusting urb->interval == f(epdesc->bInterval) and |
| 553 | * including the extra info for hw_bufp[0..2] |
| 554 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 555 | u8 usecs, c_usecs; |
David Brownell | c06d4dc | 2008-01-24 12:30:34 -0800 | [diff] [blame] | 556 | u16 interval; |
david-b@pacbell.net | d038420 | 2005-08-13 18:44:58 -0700 | [diff] [blame] | 557 | u16 tt_usecs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 558 | u16 maxp; |
| 559 | u16 raw_mask; |
| 560 | unsigned bandwidth; |
| 561 | |
| 562 | /* This is used to initialize iTD's hw_bufp fields */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 563 | __hc32 buf0; |
| 564 | __hc32 buf1; |
| 565 | __hc32 buf2; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 566 | |
| 567 | /* this is used to initialize sITD's tt info */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 568 | __hc32 address; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 569 | }; |
| 570 | |
| 571 | /*-------------------------------------------------------------------------*/ |
| 572 | |
| 573 | /* |
| 574 | * EHCI Specification 0.95 Section 3.3 |
| 575 | * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" |
| 576 | * |
| 577 | * Schedule records for high speed iso xfers |
| 578 | */ |
| 579 | struct ehci_itd { |
| 580 | /* first part defined by EHCI spec */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 581 | __hc32 hw_next; /* see EHCI 3.3.1 */ |
| 582 | __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 583 | #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ |
| 584 | #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ |
| 585 | #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ |
| 586 | #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ |
| 587 | #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) |
| 588 | #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ |
| 589 | |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 590 | #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 591 | |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 592 | __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ |
| 593 | __hc32 hw_bufp_hi [7]; /* Appendix B */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 594 | |
| 595 | /* the rest is HCD-private */ |
| 596 | dma_addr_t itd_dma; /* for this itd */ |
| 597 | union ehci_shadow itd_next; /* ptr to periodic q entry */ |
| 598 | |
| 599 | struct urb *urb; |
| 600 | struct ehci_iso_stream *stream; /* endpoint's queue */ |
| 601 | struct list_head itd_list; /* list of stream's itds */ |
| 602 | |
| 603 | /* any/all hw_transactions here may be used by that urb */ |
| 604 | unsigned frame; /* where scheduled */ |
| 605 | unsigned pg; |
| 606 | unsigned index[8]; /* in urb->iso_frame_desc */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 607 | } __attribute__ ((aligned (32))); |
| 608 | |
| 609 | /*-------------------------------------------------------------------------*/ |
| 610 | |
| 611 | /* |
David Brownell | 53bd6a6 | 2006-08-30 14:50:06 -0700 | [diff] [blame] | 612 | * EHCI Specification 0.95 Section 3.4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 613 | * siTD, aka split-transaction isochronous Transfer Descriptor |
| 614 | * ... describe full speed iso xfers through TT in hubs |
| 615 | * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) |
| 616 | */ |
| 617 | struct ehci_sitd { |
| 618 | /* first part defined by EHCI spec */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 619 | __hc32 hw_next; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 621 | __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ |
| 622 | __hc32 hw_uframe; /* EHCI table 3-10 */ |
| 623 | __hc32 hw_results; /* EHCI table 3-11 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 624 | #define SITD_IOC (1 << 31) /* interrupt on completion */ |
| 625 | #define SITD_PAGE (1 << 30) /* buffer 0/1 */ |
| 626 | #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) |
| 627 | #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ |
| 628 | #define SITD_STS_ERR (1 << 6) /* error from TT */ |
| 629 | #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ |
| 630 | #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ |
| 631 | #define SITD_STS_XACT (1 << 3) /* illegal IN response */ |
| 632 | #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ |
| 633 | #define SITD_STS_STS (1 << 1) /* split transaction state */ |
| 634 | |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 635 | #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 636 | |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 637 | __hc32 hw_buf [2]; /* EHCI table 3-12 */ |
| 638 | __hc32 hw_backpointer; /* EHCI table 3-13 */ |
| 639 | __hc32 hw_buf_hi [2]; /* Appendix B */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 640 | |
| 641 | /* the rest is HCD-private */ |
| 642 | dma_addr_t sitd_dma; |
| 643 | union ehci_shadow sitd_next; /* ptr to periodic q entry */ |
| 644 | |
| 645 | struct urb *urb; |
| 646 | struct ehci_iso_stream *stream; /* endpoint's queue */ |
| 647 | struct list_head sitd_list; /* list of stream's sitds */ |
| 648 | unsigned frame; |
| 649 | unsigned index; |
| 650 | } __attribute__ ((aligned (32))); |
| 651 | |
| 652 | /*-------------------------------------------------------------------------*/ |
| 653 | |
| 654 | /* |
| 655 | * EHCI Specification 0.96 Section 3.7 |
| 656 | * Periodic Frame Span Traversal Node (FSTN) |
| 657 | * |
| 658 | * Manages split interrupt transactions (using TT) that span frame boundaries |
| 659 | * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN |
| 660 | * makes the HC jump (back) to a QH to scan for fs/ls QH completions until |
| 661 | * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. |
| 662 | */ |
| 663 | struct ehci_fstn { |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 664 | __hc32 hw_next; /* any periodic q entry */ |
| 665 | __hc32 hw_prev; /* qh or EHCI_LIST_END */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 666 | |
| 667 | /* the rest is HCD-private */ |
| 668 | dma_addr_t fstn_dma; |
| 669 | union ehci_shadow fstn_next; /* ptr to periodic q entry */ |
| 670 | } __attribute__ ((aligned (32))); |
| 671 | |
| 672 | /*-------------------------------------------------------------------------*/ |
| 673 | |
| 674 | #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT |
| 675 | |
| 676 | /* |
| 677 | * Some EHCI controllers have a Transaction Translator built into the |
| 678 | * root hub. This is a non-standard feature. Each controller will need |
| 679 | * to add code to the following inline functions, and call them as |
| 680 | * needed (mostly in root hub code). |
| 681 | */ |
| 682 | |
Alan Stern | a8e5177 | 2008-05-20 16:58:11 -0400 | [diff] [blame] | 683 | #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 684 | |
| 685 | /* Returns the speed of a device attached to a port on the root hub. */ |
| 686 | static inline unsigned int |
| 687 | ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) |
| 688 | { |
| 689 | if (ehci_is_TDI(ehci)) { |
| 690 | switch ((portsc>>26)&3) { |
| 691 | case 0: |
| 692 | return 0; |
| 693 | case 1: |
| 694 | return (1<<USB_PORT_FEAT_LOWSPEED); |
| 695 | case 2: |
| 696 | default: |
| 697 | return (1<<USB_PORT_FEAT_HIGHSPEED); |
| 698 | } |
| 699 | } |
| 700 | return (1<<USB_PORT_FEAT_HIGHSPEED); |
| 701 | } |
| 702 | |
| 703 | #else |
| 704 | |
| 705 | #define ehci_is_TDI(e) (0) |
| 706 | |
| 707 | #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED) |
| 708 | #endif |
| 709 | |
| 710 | /*-------------------------------------------------------------------------*/ |
| 711 | |
Kumar Gala | 8cd42e9 | 2006-01-20 13:57:52 -0800 | [diff] [blame] | 712 | #ifdef CONFIG_PPC_83xx |
| 713 | /* Some Freescale processors have an erratum in which the TT |
| 714 | * port number in the queue head was 0..N-1 instead of 1..N. |
| 715 | */ |
| 716 | #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) |
| 717 | #else |
| 718 | #define ehci_has_fsl_portno_bug(e) (0) |
| 719 | #endif |
| 720 | |
Benjamin Herrenschmidt | 083522d | 2006-12-15 06:54:08 +1100 | [diff] [blame] | 721 | /* |
| 722 | * While most USB host controllers implement their registers in |
| 723 | * little-endian format, a minority (celleb companion chip) implement |
| 724 | * them in big endian format. |
| 725 | * |
| 726 | * This attempts to support either format at compile time without a |
| 727 | * runtime penalty, or both formats with the additional overhead |
| 728 | * of checking a flag bit. |
| 729 | */ |
| 730 | |
| 731 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
| 732 | #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) |
| 733 | #else |
| 734 | #define ehci_big_endian_mmio(e) 0 |
| 735 | #endif |
| 736 | |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 737 | /* |
| 738 | * Big-endian read/write functions are arch-specific. |
| 739 | * Other arches can be added if/when they're needed. |
| 740 | * |
| 741 | * REVISIT: arch/powerpc now has readl/writel_be, so the |
| 742 | * definition below can die once the 4xx support is |
| 743 | * finally ported over. |
| 744 | */ |
Valentine Barshak | da0e8fb | 2007-12-30 15:28:50 -0800 | [diff] [blame] | 745 | #if defined(CONFIG_PPC) && !defined(CONFIG_PPC_MERGE) |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 746 | #define readl_be(addr) in_be32((__force unsigned *)addr) |
| 747 | #define writel_be(val, addr) out_be32((__force unsigned *)addr, val) |
| 748 | #endif |
| 749 | |
Vladimir Barinov | 91bc4d3 | 2007-12-30 15:21:11 -0800 | [diff] [blame] | 750 | #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) |
| 751 | #define readl_be(addr) __raw_readl((__force unsigned *)addr) |
| 752 | #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) |
| 753 | #endif |
| 754 | |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 755 | static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, |
| 756 | __u32 __iomem * regs) |
Benjamin Herrenschmidt | 083522d | 2006-12-15 06:54:08 +1100 | [diff] [blame] | 757 | { |
Benjamin Herrenschmidt | d728e32 | 2006-12-28 15:27:27 +1100 | [diff] [blame] | 758 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
Benjamin Herrenschmidt | 083522d | 2006-12-15 06:54:08 +1100 | [diff] [blame] | 759 | return ehci_big_endian_mmio(ehci) ? |
Al Viro | 68f50e5 | 2007-02-09 16:40:00 +0000 | [diff] [blame] | 760 | readl_be(regs) : |
| 761 | readl(regs); |
Benjamin Herrenschmidt | d728e32 | 2006-12-28 15:27:27 +1100 | [diff] [blame] | 762 | #else |
Al Viro | 68f50e5 | 2007-02-09 16:40:00 +0000 | [diff] [blame] | 763 | return readl(regs); |
Benjamin Herrenschmidt | d728e32 | 2006-12-28 15:27:27 +1100 | [diff] [blame] | 764 | #endif |
Benjamin Herrenschmidt | 083522d | 2006-12-15 06:54:08 +1100 | [diff] [blame] | 765 | } |
| 766 | |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 767 | static inline void ehci_writel(const struct ehci_hcd *ehci, |
| 768 | const unsigned int val, __u32 __iomem *regs) |
Benjamin Herrenschmidt | 083522d | 2006-12-15 06:54:08 +1100 | [diff] [blame] | 769 | { |
Benjamin Herrenschmidt | d728e32 | 2006-12-28 15:27:27 +1100 | [diff] [blame] | 770 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
Benjamin Herrenschmidt | 083522d | 2006-12-15 06:54:08 +1100 | [diff] [blame] | 771 | ehci_big_endian_mmio(ehci) ? |
Al Viro | 68f50e5 | 2007-02-09 16:40:00 +0000 | [diff] [blame] | 772 | writel_be(val, regs) : |
| 773 | writel(val, regs); |
Benjamin Herrenschmidt | d728e32 | 2006-12-28 15:27:27 +1100 | [diff] [blame] | 774 | #else |
Al Viro | 68f50e5 | 2007-02-09 16:40:00 +0000 | [diff] [blame] | 775 | writel(val, regs); |
Benjamin Herrenschmidt | d728e32 | 2006-12-28 15:27:27 +1100 | [diff] [blame] | 776 | #endif |
Benjamin Herrenschmidt | 083522d | 2006-12-15 06:54:08 +1100 | [diff] [blame] | 777 | } |
Kumar Gala | 8cd42e9 | 2006-01-20 13:57:52 -0800 | [diff] [blame] | 778 | |
| 779 | /*-------------------------------------------------------------------------*/ |
| 780 | |
Stefan Roese | 6dbd682 | 2007-05-01 09:29:37 -0700 | [diff] [blame] | 781 | /* |
| 782 | * The AMCC 440EPx not only implements its EHCI registers in big-endian |
| 783 | * format, but also its DMA data structures (descriptors). |
| 784 | * |
| 785 | * EHCI controllers accessed through PCI work normally (little-endian |
| 786 | * everywhere), so we won't bother supporting a BE-only mode for now. |
| 787 | */ |
| 788 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC |
| 789 | #define ehci_big_endian_desc(e) ((e)->big_endian_desc) |
| 790 | |
| 791 | /* cpu to ehci */ |
| 792 | static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) |
| 793 | { |
| 794 | return ehci_big_endian_desc(ehci) |
| 795 | ? (__force __hc32)cpu_to_be32(x) |
| 796 | : (__force __hc32)cpu_to_le32(x); |
| 797 | } |
| 798 | |
| 799 | /* ehci to cpu */ |
| 800 | static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) |
| 801 | { |
| 802 | return ehci_big_endian_desc(ehci) |
| 803 | ? be32_to_cpu((__force __be32)x) |
| 804 | : le32_to_cpu((__force __le32)x); |
| 805 | } |
| 806 | |
| 807 | static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) |
| 808 | { |
| 809 | return ehci_big_endian_desc(ehci) |
| 810 | ? be32_to_cpup((__force __be32 *)x) |
| 811 | : le32_to_cpup((__force __le32 *)x); |
| 812 | } |
| 813 | |
| 814 | #else |
| 815 | |
| 816 | /* cpu to ehci */ |
| 817 | static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) |
| 818 | { |
| 819 | return cpu_to_le32(x); |
| 820 | } |
| 821 | |
| 822 | /* ehci to cpu */ |
| 823 | static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) |
| 824 | { |
| 825 | return le32_to_cpu(x); |
| 826 | } |
| 827 | |
| 828 | static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) |
| 829 | { |
| 830 | return le32_to_cpup(x); |
| 831 | } |
| 832 | |
| 833 | #endif |
| 834 | |
| 835 | /*-------------------------------------------------------------------------*/ |
| 836 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 837 | #ifndef DEBUG |
| 838 | #define STUB_DEBUG_FILES |
| 839 | #endif /* DEBUG */ |
| 840 | |
| 841 | /*-------------------------------------------------------------------------*/ |
| 842 | |
| 843 | #endif /* __LINUX_EHCI_HCD_H */ |