Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 3 | #include "tegra30.dtsi" |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 4 | |
| 5 | / { |
| 6 | model = "NVIDIA Tegra30 Beaver evaluation board"; |
| 7 | compatible = "nvidia,beaver", "nvidia,tegra30"; |
| 8 | |
Stephen Warren | 553c0a2 | 2013-12-09 14:43:59 -0700 | [diff] [blame] | 9 | aliases { |
| 10 | rtc0 = "/i2c@7000d000/tps65911@2d"; |
| 11 | rtc1 = "/rtc@7000e000"; |
Olof Johansson | c4574aa | 2014-11-11 12:49:30 -0800 | [diff] [blame] | 12 | serial0 = &uarta; |
Stephen Warren | 553c0a2 | 2013-12-09 14:43:59 -0700 | [diff] [blame] | 13 | }; |
| 14 | |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 15 | memory { |
Stephen Warren | 30022bb | 2013-05-13 09:47:31 +0000 | [diff] [blame] | 16 | reg = <0x80000000 0x7ff00000>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 17 | }; |
| 18 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 19 | pcie-controller@00003000 { |
Thierry Reding | bb034cb | 2013-08-09 16:49:28 +0200 | [diff] [blame] | 20 | status = "okay"; |
Thierry Reding | cca8614 | 2014-05-28 16:49:12 +0200 | [diff] [blame] | 21 | |
| 22 | avdd-pexa-supply = <&ldo1_reg>; |
| 23 | vdd-pexa-supply = <&ldo1_reg>; |
| 24 | avdd-pexb-supply = <&ldo1_reg>; |
| 25 | vdd-pexb-supply = <&ldo1_reg>; |
| 26 | avdd-pex-pll-supply = <&ldo1_reg>; |
| 27 | avdd-plle-supply = <&ldo1_reg>; |
| 28 | vddio-pex-ctl-supply = <&sys_3v3_reg>; |
| 29 | hvdd-pex-supply = <&sys_3v3_pexs_reg>; |
| 30 | |
Thierry Reding | bb034cb | 2013-08-09 16:49:28 +0200 | [diff] [blame] | 31 | pci@1,0 { |
| 32 | status = "okay"; |
Stephen Warren | 44fefab | 2013-08-09 16:49:29 +0200 | [diff] [blame] | 33 | nvidia,num-lanes = <2>; |
Thierry Reding | bb034cb | 2013-08-09 16:49:28 +0200 | [diff] [blame] | 34 | }; |
| 35 | |
| 36 | pci@2,0 { |
Stephen Warren | 44fefab | 2013-08-09 16:49:29 +0200 | [diff] [blame] | 37 | nvidia,num-lanes = <2>; |
Thierry Reding | bb034cb | 2013-08-09 16:49:28 +0200 | [diff] [blame] | 38 | }; |
| 39 | |
| 40 | pci@3,0 { |
Stephen Warren | 44fefab | 2013-08-09 16:49:29 +0200 | [diff] [blame] | 41 | status = "okay"; |
| 42 | nvidia,num-lanes = <2>; |
Thierry Reding | bb034cb | 2013-08-09 16:49:28 +0200 | [diff] [blame] | 43 | }; |
| 44 | }; |
| 45 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 46 | host1x@50000000 { |
| 47 | hdmi@54280000 { |
Thierry Reding | 9bd80b4 | 2013-08-12 17:49:03 +0200 | [diff] [blame] | 48 | status = "okay"; |
| 49 | |
Thierry Reding | 597eb8e | 2014-04-25 17:44:49 +0200 | [diff] [blame] | 50 | hdmi-supply = <&vdd_5v0_hdmi>; |
Thierry Reding | 9bd80b4 | 2013-08-12 17:49:03 +0200 | [diff] [blame] | 51 | vdd-supply = <&sys_3v3_reg>; |
| 52 | pll-supply = <&vio_reg>; |
| 53 | |
| 54 | nvidia,hpd-gpio = |
| 55 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; |
| 56 | nvidia,ddc-i2c-bus = <&hdmiddc>; |
| 57 | }; |
| 58 | }; |
| 59 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 60 | pinmux@70000868 { |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 61 | pinctrl-names = "default"; |
| 62 | pinctrl-0 = <&state_default>; |
| 63 | |
| 64 | state_default: pinmux { |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 65 | clk_32k_out_pa0 { |
| 66 | nvidia,pins = "clk_32k_out_pa0"; |
| 67 | nvidia,function = "blink"; |
Laxman Dewangan | a47c662 | 2013-12-05 16:14:09 +0530 | [diff] [blame] | 68 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 69 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 70 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 71 | }; |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 72 | uart3_cts_n_pa1 { |
| 73 | nvidia,pins = "uart3_cts_n_pa1"; |
| 74 | nvidia,function = "uartc"; |
| 75 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Laxman Dewangan | a47c662 | 2013-12-05 16:14:09 +0530 | [diff] [blame] | 76 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 77 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 78 | }; |
| 79 | dap2_fs_pa2 { |
| 80 | nvidia,pins = "dap2_fs_pa2"; |
| 81 | nvidia,function = "i2s1"; |
| 82 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 83 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 84 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 85 | }; |
| 86 | dap2_sclk_pa3 { |
| 87 | nvidia,pins = "dap2_sclk_pa3"; |
| 88 | nvidia,function = "i2s1"; |
| 89 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 90 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 91 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 92 | }; |
| 93 | dap2_din_pa4 { |
| 94 | nvidia,pins = "dap2_din_pa4"; |
| 95 | nvidia,function = "i2s1"; |
| 96 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 97 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 98 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 99 | }; |
| 100 | dap2_dout_pa5 { |
| 101 | nvidia,pins = "dap2_dout_pa5"; |
| 102 | nvidia,function = "i2s1"; |
| 103 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 104 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 105 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 106 | }; |
| 107 | sdmmc3_clk_pa6 { |
| 108 | nvidia,pins = "sdmmc3_clk_pa6"; |
| 109 | nvidia,function = "sdmmc3"; |
Laxman Dewangan | a47c662 | 2013-12-05 16:14:09 +0530 | [diff] [blame] | 110 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 111 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 112 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 113 | }; |
| 114 | sdmmc3_cmd_pa7 { |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 115 | nvidia,pins = "sdmmc3_cmd_pa7"; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 116 | nvidia,function = "sdmmc3"; |
Laxman Dewangan | a47c662 | 2013-12-05 16:14:09 +0530 | [diff] [blame] | 117 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 118 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 119 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 120 | }; |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 121 | gmi_a17_pb0 { |
| 122 | nvidia,pins = "gmi_a17_pb0"; |
| 123 | nvidia,function = "spi4"; |
Laxman Dewangan | a47c662 | 2013-12-05 16:14:09 +0530 | [diff] [blame] | 124 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 125 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 126 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 127 | }; |
| 128 | gmi_a18_pb1 { |
| 129 | nvidia,pins = "gmi_a18_pb1"; |
| 130 | nvidia,function = "spi4"; |
| 131 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 132 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 133 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 134 | }; |
| 135 | lcd_pwr0_pb2 { |
| 136 | nvidia,pins = "lcd_pwr0_pb2"; |
| 137 | nvidia,function = "displaya"; |
| 138 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 139 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 140 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 141 | }; |
| 142 | lcd_pclk_pb3 { |
| 143 | nvidia,pins = "lcd_pclk_pb3"; |
| 144 | nvidia,function = "displaya"; |
| 145 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 146 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 147 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 148 | }; |
| 149 | sdmmc3_dat3_pb4 { |
| 150 | nvidia,pins = "sdmmc3_dat3_pb4"; |
| 151 | nvidia,function = "sdmmc3"; |
| 152 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 153 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 154 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 155 | }; |
| 156 | sdmmc3_dat2_pb5 { |
| 157 | nvidia,pins = "sdmmc3_dat2_pb5"; |
| 158 | nvidia,function = "sdmmc3"; |
| 159 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 160 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 161 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 162 | }; |
| 163 | sdmmc3_dat1_pb6 { |
| 164 | nvidia,pins = "sdmmc3_dat1_pb6"; |
| 165 | nvidia,function = "sdmmc3"; |
| 166 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 167 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 168 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 169 | }; |
| 170 | sdmmc3_dat0_pb7 { |
| 171 | nvidia,pins = "sdmmc3_dat0_pb7"; |
| 172 | nvidia,function = "sdmmc3"; |
| 173 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 174 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 175 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 176 | }; |
| 177 | uart3_rts_n_pc0 { |
| 178 | nvidia,pins = "uart3_rts_n_pc0"; |
| 179 | nvidia,function = "uartc"; |
| 180 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 181 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 182 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 183 | }; |
| 184 | lcd_pwr1_pc1 { |
| 185 | nvidia,pins = "lcd_pwr1_pc1"; |
| 186 | nvidia,function = "displaya"; |
| 187 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 188 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 189 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 190 | }; |
| 191 | uart2_txd_pc2 { |
| 192 | nvidia,pins = "uart2_txd_pc2"; |
| 193 | nvidia,function = "uartb"; |
| 194 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 195 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 196 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 197 | }; |
| 198 | uart2_rxd_pc3 { |
| 199 | nvidia,pins = "uart2_rxd_pc3"; |
| 200 | nvidia,function = "uartb"; |
| 201 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 202 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 203 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 204 | }; |
| 205 | gen1_i2c_scl_pc4 { |
| 206 | nvidia,pins = "gen1_i2c_scl_pc4"; |
| 207 | nvidia,function = "i2c1"; |
| 208 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 209 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 210 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 211 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 212 | }; |
| 213 | gen1_i2c_sda_pc5 { |
| 214 | nvidia,pins = "gen1_i2c_sda_pc5"; |
| 215 | nvidia,function = "i2c1"; |
| 216 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 217 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 218 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 219 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 220 | }; |
| 221 | lcd_pwr2_pc6 { |
| 222 | nvidia,pins = "lcd_pwr2_pc6"; |
| 223 | nvidia,function = "displaya"; |
| 224 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 225 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 226 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 227 | }; |
| 228 | gmi_wp_n_pc7 { |
| 229 | nvidia,pins = "gmi_wp_n_pc7"; |
| 230 | nvidia,function = "gmi"; |
| 231 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 232 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 233 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 234 | }; |
| 235 | sdmmc3_dat5_pd0 { |
| 236 | nvidia,pins = "sdmmc3_dat5_pd0"; |
| 237 | nvidia,function = "sdmmc3"; |
| 238 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 239 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 240 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 241 | }; |
| 242 | sdmmc3_dat4_pd1 { |
| 243 | nvidia,pins = "sdmmc3_dat4_pd1"; |
| 244 | nvidia,function = "sdmmc3"; |
| 245 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 246 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 247 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 248 | }; |
| 249 | lcd_dc1_pd2 { |
| 250 | nvidia,pins = "lcd_dc1_pd2"; |
| 251 | nvidia,function = "displaya"; |
| 252 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 253 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 254 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 255 | }; |
| 256 | sdmmc3_dat6_pd3 { |
| 257 | nvidia,pins = "sdmmc3_dat6_pd3"; |
| 258 | nvidia,function = "rsvd1"; |
| 259 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 260 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 261 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 262 | }; |
| 263 | sdmmc3_dat7_pd4 { |
| 264 | nvidia,pins = "sdmmc3_dat7_pd4"; |
| 265 | nvidia,function = "rsvd1"; |
| 266 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 267 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 268 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 269 | }; |
| 270 | vi_d1_pd5 { |
| 271 | nvidia,pins = "vi_d1_pd5"; |
| 272 | nvidia,function = "sdmmc2"; |
| 273 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 274 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 275 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 276 | }; |
| 277 | vi_vsync_pd6 { |
| 278 | nvidia,pins = "vi_vsync_pd6"; |
| 279 | nvidia,function = "rsvd1"; |
| 280 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 281 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 282 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 283 | }; |
| 284 | vi_hsync_pd7 { |
| 285 | nvidia,pins = "vi_hsync_pd7"; |
| 286 | nvidia,function = "rsvd1"; |
| 287 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 288 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 289 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 290 | }; |
| 291 | lcd_d0_pe0 { |
| 292 | nvidia,pins = "lcd_d0_pe0"; |
| 293 | nvidia,function = "displaya"; |
| 294 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 295 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 296 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 297 | }; |
| 298 | lcd_d1_pe1 { |
| 299 | nvidia,pins = "lcd_d1_pe1"; |
| 300 | nvidia,function = "displaya"; |
| 301 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 302 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 303 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 304 | }; |
| 305 | lcd_d2_pe2 { |
| 306 | nvidia,pins = "lcd_d2_pe2"; |
| 307 | nvidia,function = "displaya"; |
| 308 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 309 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 310 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 311 | }; |
| 312 | lcd_d3_pe3 { |
| 313 | nvidia,pins = "lcd_d3_pe3"; |
| 314 | nvidia,function = "displaya"; |
| 315 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 316 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 317 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 318 | }; |
| 319 | lcd_d4_pe4 { |
| 320 | nvidia,pins = "lcd_d4_pe4"; |
| 321 | nvidia,function = "displaya"; |
| 322 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 323 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 324 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 325 | }; |
| 326 | lcd_d5_pe5 { |
| 327 | nvidia,pins = "lcd_d5_pe5"; |
| 328 | nvidia,function = "displaya"; |
| 329 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 330 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 331 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 332 | }; |
| 333 | lcd_d6_pe6 { |
| 334 | nvidia,pins = "lcd_d6_pe6"; |
| 335 | nvidia,function = "displaya"; |
| 336 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 337 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 338 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 339 | }; |
| 340 | lcd_d7_pe7 { |
| 341 | nvidia,pins = "lcd_d7_pe7"; |
| 342 | nvidia,function = "displaya"; |
| 343 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 344 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 345 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 346 | }; |
| 347 | lcd_d8_pf0 { |
| 348 | nvidia,pins = "lcd_d8_pf0"; |
| 349 | nvidia,function = "displaya"; |
| 350 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 351 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 352 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 353 | }; |
| 354 | lcd_d9_pf1 { |
| 355 | nvidia,pins = "lcd_d9_pf1"; |
| 356 | nvidia,function = "displaya"; |
| 357 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 358 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 359 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 360 | }; |
| 361 | lcd_d10_pf2 { |
| 362 | nvidia,pins = "lcd_d10_pf2"; |
| 363 | nvidia,function = "displaya"; |
| 364 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 365 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 366 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 367 | }; |
| 368 | lcd_d11_pf3 { |
| 369 | nvidia,pins = "lcd_d11_pf3"; |
| 370 | nvidia,function = "displaya"; |
| 371 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 372 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 373 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 374 | }; |
| 375 | lcd_d12_pf4 { |
| 376 | nvidia,pins = "lcd_d12_pf4"; |
| 377 | nvidia,function = "displaya"; |
| 378 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 379 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 380 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 381 | }; |
| 382 | lcd_d13_pf5 { |
| 383 | nvidia,pins = "lcd_d13_pf5"; |
| 384 | nvidia,function = "displaya"; |
| 385 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 386 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 387 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 388 | }; |
| 389 | lcd_d14_pf6 { |
| 390 | nvidia,pins = "lcd_d14_pf6"; |
| 391 | nvidia,function = "displaya"; |
| 392 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 393 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 394 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 395 | }; |
| 396 | lcd_d15_pf7 { |
| 397 | nvidia,pins = "lcd_d15_pf7"; |
| 398 | nvidia,function = "displaya"; |
| 399 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 400 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 401 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 402 | }; |
| 403 | gmi_ad0_pg0 { |
| 404 | nvidia,pins = "gmi_ad0_pg0"; |
| 405 | nvidia,function = "nand"; |
| 406 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 407 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 408 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 409 | }; |
| 410 | gmi_ad1_pg1 { |
| 411 | nvidia,pins = "gmi_ad1_pg1"; |
| 412 | nvidia,function = "nand"; |
| 413 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 414 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 415 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 416 | }; |
| 417 | gmi_ad2_pg2 { |
| 418 | nvidia,pins = "gmi_ad2_pg2"; |
| 419 | nvidia,function = "nand"; |
| 420 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 421 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 422 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 423 | }; |
| 424 | gmi_ad3_pg3 { |
| 425 | nvidia,pins = "gmi_ad3_pg3"; |
| 426 | nvidia,function = "nand"; |
| 427 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 428 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 429 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 430 | }; |
| 431 | gmi_ad4_pg4 { |
| 432 | nvidia,pins = "gmi_ad4_pg4"; |
| 433 | nvidia,function = "nand"; |
| 434 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 435 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 436 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 437 | }; |
| 438 | gmi_ad5_pg5 { |
| 439 | nvidia,pins = "gmi_ad5_pg5"; |
| 440 | nvidia,function = "nand"; |
| 441 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 442 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 443 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 444 | }; |
| 445 | gmi_ad6_pg6 { |
| 446 | nvidia,pins = "gmi_ad6_pg6"; |
| 447 | nvidia,function = "nand"; |
| 448 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 449 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 450 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 451 | }; |
| 452 | gmi_ad7_pg7 { |
| 453 | nvidia,pins = "gmi_ad7_pg7"; |
| 454 | nvidia,function = "nand"; |
| 455 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 456 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 457 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 458 | }; |
| 459 | gmi_ad8_ph0 { |
| 460 | nvidia,pins = "gmi_ad8_ph0"; |
| 461 | nvidia,function = "pwm0"; |
| 462 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 463 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 464 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 465 | }; |
| 466 | gmi_ad9_ph1 { |
| 467 | nvidia,pins = "gmi_ad9_ph1"; |
| 468 | nvidia,function = "pwm1"; |
| 469 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 470 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 471 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 472 | }; |
| 473 | gmi_ad10_ph2 { |
| 474 | nvidia,pins = "gmi_ad10_ph2"; |
| 475 | nvidia,function = "nand"; |
| 476 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 477 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 478 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 479 | }; |
| 480 | gmi_ad11_ph3 { |
| 481 | nvidia,pins = "gmi_ad11_ph3"; |
| 482 | nvidia,function = "nand"; |
| 483 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 484 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 485 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 486 | }; |
| 487 | gmi_ad12_ph4 { |
| 488 | nvidia,pins = "gmi_ad12_ph4"; |
| 489 | nvidia,function = "nand"; |
| 490 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 491 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 492 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 493 | }; |
| 494 | gmi_ad13_ph5 { |
| 495 | nvidia,pins = "gmi_ad13_ph5"; |
| 496 | nvidia,function = "nand"; |
| 497 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 498 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 499 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 500 | }; |
| 501 | gmi_ad14_ph6 { |
| 502 | nvidia,pins = "gmi_ad14_ph6"; |
| 503 | nvidia,function = "nand"; |
| 504 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 505 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 506 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 507 | }; |
| 508 | gmi_wr_n_pi0 { |
| 509 | nvidia,pins = "gmi_wr_n_pi0"; |
| 510 | nvidia,function = "nand"; |
| 511 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 512 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 513 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 514 | }; |
| 515 | gmi_oe_n_pi1 { |
| 516 | nvidia,pins = "gmi_oe_n_pi1"; |
| 517 | nvidia,function = "nand"; |
| 518 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 519 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 520 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 521 | }; |
| 522 | gmi_dqs_pi2 { |
| 523 | nvidia,pins = "gmi_dqs_pi2"; |
| 524 | nvidia,function = "nand"; |
| 525 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 526 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 527 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 528 | }; |
| 529 | gmi_iordy_pi5 { |
| 530 | nvidia,pins = "gmi_iordy_pi5"; |
| 531 | nvidia,function = "rsvd1"; |
| 532 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 533 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 534 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 535 | }; |
| 536 | gmi_cs7_n_pi6 { |
| 537 | nvidia,pins = "gmi_cs7_n_pi6"; |
| 538 | nvidia,function = "nand"; |
| 539 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 540 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 541 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 542 | }; |
| 543 | gmi_wait_pi7 { |
| 544 | nvidia,pins = "gmi_wait_pi7"; |
| 545 | nvidia,function = "nand"; |
| 546 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 547 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 548 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 549 | }; |
| 550 | lcd_de_pj1 { |
| 551 | nvidia,pins = "lcd_de_pj1"; |
| 552 | nvidia,function = "displaya"; |
| 553 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 554 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 555 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 556 | }; |
| 557 | lcd_hsync_pj3 { |
| 558 | nvidia,pins = "lcd_hsync_pj3"; |
| 559 | nvidia,function = "displaya"; |
| 560 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 561 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 562 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 563 | }; |
| 564 | lcd_vsync_pj4 { |
| 565 | nvidia,pins = "lcd_vsync_pj4"; |
| 566 | nvidia,function = "displaya"; |
| 567 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 568 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 569 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 570 | }; |
| 571 | uart2_cts_n_pj5 { |
| 572 | nvidia,pins = "uart2_cts_n_pj5"; |
| 573 | nvidia,function = "uartb"; |
| 574 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 575 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 576 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 577 | }; |
| 578 | uart2_rts_n_pj6 { |
| 579 | nvidia,pins = "uart2_rts_n_pj6"; |
| 580 | nvidia,function = "uartb"; |
| 581 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 582 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 583 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 584 | }; |
| 585 | gmi_a16_pj7 { |
| 586 | nvidia,pins = "gmi_a16_pj7"; |
| 587 | nvidia,function = "spi4"; |
| 588 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 589 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 590 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 591 | }; |
| 592 | gmi_adv_n_pk0 { |
| 593 | nvidia,pins = "gmi_adv_n_pk0"; |
| 594 | nvidia,function = "nand"; |
| 595 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 596 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 597 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 598 | }; |
| 599 | gmi_clk_pk1 { |
| 600 | nvidia,pins = "gmi_clk_pk1"; |
| 601 | nvidia,function = "nand"; |
| 602 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 603 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 604 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 605 | }; |
| 606 | gmi_cs2_n_pk3 { |
| 607 | nvidia,pins = "gmi_cs2_n_pk3"; |
| 608 | nvidia,function = "rsvd1"; |
| 609 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 610 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 611 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 612 | }; |
| 613 | gmi_cs3_n_pk4 { |
| 614 | nvidia,pins = "gmi_cs3_n_pk4"; |
| 615 | nvidia,function = "nand"; |
| 616 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 617 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 618 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 619 | }; |
| 620 | spdif_out_pk5 { |
| 621 | nvidia,pins = "spdif_out_pk5"; |
| 622 | nvidia,function = "spdif"; |
| 623 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 624 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 625 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 626 | }; |
| 627 | spdif_in_pk6 { |
| 628 | nvidia,pins = "spdif_in_pk6"; |
| 629 | nvidia,function = "spdif"; |
| 630 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 631 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 632 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 633 | }; |
| 634 | gmi_a19_pk7 { |
| 635 | nvidia,pins = "gmi_a19_pk7"; |
| 636 | nvidia,function = "spi4"; |
| 637 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 638 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 639 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 640 | }; |
| 641 | vi_d2_pl0 { |
| 642 | nvidia,pins = "vi_d2_pl0"; |
| 643 | nvidia,function = "sdmmc2"; |
| 644 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 645 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 646 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 647 | }; |
| 648 | vi_d3_pl1 { |
| 649 | nvidia,pins = "vi_d3_pl1"; |
| 650 | nvidia,function = "sdmmc2"; |
| 651 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 652 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 653 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 654 | }; |
| 655 | vi_d4_pl2 { |
| 656 | nvidia,pins = "vi_d4_pl2"; |
| 657 | nvidia,function = "vi"; |
| 658 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 659 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 660 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 661 | }; |
| 662 | vi_d5_pl3 { |
| 663 | nvidia,pins = "vi_d5_pl3"; |
| 664 | nvidia,function = "sdmmc2"; |
| 665 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 666 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 667 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 668 | }; |
| 669 | vi_d6_pl4 { |
| 670 | nvidia,pins = "vi_d6_pl4"; |
| 671 | nvidia,function = "vi"; |
| 672 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 673 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 674 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 675 | }; |
| 676 | vi_d7_pl5 { |
| 677 | nvidia,pins = "vi_d7_pl5"; |
| 678 | nvidia,function = "sdmmc2"; |
| 679 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 680 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 681 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 682 | }; |
| 683 | vi_d8_pl6 { |
| 684 | nvidia,pins = "vi_d8_pl6"; |
| 685 | nvidia,function = "sdmmc2"; |
| 686 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 687 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 688 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 689 | }; |
| 690 | vi_d9_pl7 { |
| 691 | nvidia,pins = "vi_d9_pl7"; |
| 692 | nvidia,function = "sdmmc2"; |
| 693 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 694 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 695 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 696 | }; |
| 697 | lcd_d16_pm0 { |
| 698 | nvidia,pins = "lcd_d16_pm0"; |
| 699 | nvidia,function = "displaya"; |
| 700 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 701 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 702 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 703 | }; |
| 704 | lcd_d17_pm1 { |
| 705 | nvidia,pins = "lcd_d17_pm1"; |
| 706 | nvidia,function = "displaya"; |
| 707 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 708 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 709 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 710 | }; |
| 711 | lcd_d18_pm2 { |
| 712 | nvidia,pins = "lcd_d18_pm2"; |
| 713 | nvidia,function = "displaya"; |
| 714 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 715 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 716 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 717 | }; |
| 718 | lcd_d19_pm3 { |
| 719 | nvidia,pins = "lcd_d19_pm3"; |
| 720 | nvidia,function = "displaya"; |
| 721 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 722 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 723 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 724 | }; |
| 725 | lcd_d20_pm4 { |
| 726 | nvidia,pins = "lcd_d20_pm4"; |
| 727 | nvidia,function = "displaya"; |
| 728 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 729 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 730 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 731 | }; |
| 732 | lcd_d21_pm5 { |
| 733 | nvidia,pins = "lcd_d21_pm5"; |
| 734 | nvidia,function = "displaya"; |
| 735 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 736 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 737 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 738 | }; |
| 739 | lcd_d22_pm6 { |
| 740 | nvidia,pins = "lcd_d22_pm6"; |
| 741 | nvidia,function = "displaya"; |
| 742 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 743 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 744 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 745 | }; |
| 746 | lcd_d23_pm7 { |
| 747 | nvidia,pins = "lcd_d23_pm7"; |
| 748 | nvidia,function = "displaya"; |
| 749 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 750 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 751 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 752 | }; |
| 753 | dap1_fs_pn0 { |
| 754 | nvidia,pins = "dap1_fs_pn0"; |
| 755 | nvidia,function = "i2s0"; |
| 756 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 757 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 758 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 759 | }; |
| 760 | dap1_din_pn1 { |
| 761 | nvidia,pins = "dap1_din_pn1"; |
| 762 | nvidia,function = "i2s0"; |
| 763 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 764 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 765 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 766 | }; |
| 767 | dap1_dout_pn2 { |
| 768 | nvidia,pins = "dap1_dout_pn2"; |
| 769 | nvidia,function = "i2s0"; |
| 770 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 771 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 772 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 773 | }; |
| 774 | dap1_sclk_pn3 { |
| 775 | nvidia,pins = "dap1_sclk_pn3"; |
| 776 | nvidia,function = "i2s0"; |
| 777 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 778 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 779 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 780 | }; |
| 781 | lcd_cs0_n_pn4 { |
| 782 | nvidia,pins = "lcd_cs0_n_pn4"; |
| 783 | nvidia,function = "displaya"; |
| 784 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 785 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 786 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 787 | }; |
| 788 | lcd_sdout_pn5 { |
| 789 | nvidia,pins = "lcd_sdout_pn5"; |
| 790 | nvidia,function = "displaya"; |
| 791 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 792 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 793 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 794 | }; |
| 795 | lcd_dc0_pn6 { |
| 796 | nvidia,pins = "lcd_dc0_pn6"; |
| 797 | nvidia,function = "displaya"; |
| 798 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 799 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 800 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 801 | }; |
| 802 | hdmi_int_pn7 { |
| 803 | nvidia,pins = "hdmi_int_pn7"; |
| 804 | nvidia,function = "rsvd1"; |
| 805 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 806 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 807 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 808 | }; |
| 809 | ulpi_data7_po0 { |
| 810 | nvidia,pins = "ulpi_data7_po0"; |
| 811 | nvidia,function = "uarta"; |
| 812 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 813 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 814 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 815 | }; |
| 816 | ulpi_data0_po1 { |
| 817 | nvidia,pins = "ulpi_data0_po1"; |
| 818 | nvidia,function = "uarta"; |
| 819 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 820 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 821 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 822 | }; |
| 823 | ulpi_data1_po2 { |
| 824 | nvidia,pins = "ulpi_data1_po2"; |
| 825 | nvidia,function = "uarta"; |
| 826 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 827 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 828 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 829 | }; |
| 830 | ulpi_data2_po3 { |
| 831 | nvidia,pins = "ulpi_data2_po3"; |
| 832 | nvidia,function = "uarta"; |
| 833 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 834 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 835 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 836 | }; |
| 837 | ulpi_data3_po4 { |
| 838 | nvidia,pins = "ulpi_data3_po4"; |
| 839 | nvidia,function = "rsvd1"; |
| 840 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 841 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 842 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 843 | }; |
| 844 | ulpi_data4_po5 { |
| 845 | nvidia,pins = "ulpi_data4_po5"; |
| 846 | nvidia,function = "uarta"; |
| 847 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 848 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 849 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 850 | }; |
| 851 | ulpi_data5_po6 { |
| 852 | nvidia,pins = "ulpi_data5_po6"; |
| 853 | nvidia,function = "uarta"; |
| 854 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 855 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 856 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 857 | }; |
| 858 | ulpi_data6_po7 { |
| 859 | nvidia,pins = "ulpi_data6_po7"; |
| 860 | nvidia,function = "uarta"; |
| 861 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 862 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 863 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 864 | }; |
| 865 | dap3_fs_pp0 { |
| 866 | nvidia,pins = "dap3_fs_pp0"; |
| 867 | nvidia,function = "i2s2"; |
| 868 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 869 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 870 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 871 | }; |
| 872 | dap3_din_pp1 { |
| 873 | nvidia,pins = "dap3_din_pp1"; |
| 874 | nvidia,function = "i2s2"; |
| 875 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 876 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 877 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 878 | }; |
| 879 | dap3_dout_pp2 { |
| 880 | nvidia,pins = "dap3_dout_pp2"; |
| 881 | nvidia,function = "i2s2"; |
| 882 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 883 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 884 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 885 | }; |
| 886 | dap3_sclk_pp3 { |
| 887 | nvidia,pins = "dap3_sclk_pp3"; |
| 888 | nvidia,function = "i2s2"; |
| 889 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 890 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 891 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 892 | }; |
| 893 | dap4_fs_pp4 { |
| 894 | nvidia,pins = "dap4_fs_pp4"; |
| 895 | nvidia,function = "i2s3"; |
| 896 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 897 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 898 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 899 | }; |
| 900 | dap4_din_pp5 { |
| 901 | nvidia,pins = "dap4_din_pp5"; |
| 902 | nvidia,function = "i2s3"; |
| 903 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 904 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 905 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 906 | }; |
| 907 | dap4_dout_pp6 { |
| 908 | nvidia,pins = "dap4_dout_pp6"; |
| 909 | nvidia,function = "i2s3"; |
| 910 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 911 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 912 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 913 | }; |
| 914 | dap4_sclk_pp7 { |
| 915 | nvidia,pins = "dap4_sclk_pp7"; |
| 916 | nvidia,function = "i2s3"; |
| 917 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 918 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 919 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 920 | }; |
| 921 | kb_col0_pq0 { |
| 922 | nvidia,pins = "kb_col0_pq0"; |
| 923 | nvidia,function = "kbc"; |
| 924 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 925 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 926 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 927 | }; |
| 928 | kb_col1_pq1 { |
| 929 | nvidia,pins = "kb_col1_pq1"; |
| 930 | nvidia,function = "kbc"; |
| 931 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 932 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 933 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 934 | }; |
| 935 | kb_col2_pq2 { |
| 936 | nvidia,pins = "kb_col2_pq2"; |
| 937 | nvidia,function = "kbc"; |
| 938 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 939 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 940 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 941 | }; |
| 942 | kb_col3_pq3 { |
| 943 | nvidia,pins = "kb_col3_pq3"; |
| 944 | nvidia,function = "kbc"; |
| 945 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 946 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 947 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 948 | }; |
| 949 | kb_col4_pq4 { |
| 950 | nvidia,pins = "kb_col4_pq4"; |
| 951 | nvidia,function = "kbc"; |
| 952 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 953 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 954 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 955 | }; |
| 956 | kb_col5_pq5 { |
| 957 | nvidia,pins = "kb_col5_pq5"; |
| 958 | nvidia,function = "kbc"; |
| 959 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 960 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 961 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 962 | }; |
| 963 | kb_col6_pq6 { |
| 964 | nvidia,pins = "kb_col6_pq6"; |
| 965 | nvidia,function = "kbc"; |
| 966 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 967 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 968 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 969 | }; |
| 970 | kb_col7_pq7 { |
| 971 | nvidia,pins = "kb_col7_pq7"; |
| 972 | nvidia,function = "kbc"; |
| 973 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 974 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 975 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 976 | }; |
| 977 | kb_row0_pr0 { |
| 978 | nvidia,pins = "kb_row0_pr0"; |
| 979 | nvidia,function = "kbc"; |
| 980 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 981 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 982 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 983 | }; |
| 984 | kb_row1_pr1 { |
| 985 | nvidia,pins = "kb_row1_pr1"; |
| 986 | nvidia,function = "kbc"; |
| 987 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 988 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 989 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 990 | }; |
| 991 | kb_row2_pr2 { |
| 992 | nvidia,pins = "kb_row2_pr2"; |
| 993 | nvidia,function = "kbc"; |
| 994 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 995 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 996 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 997 | }; |
| 998 | kb_row3_pr3 { |
| 999 | nvidia,pins = "kb_row3_pr3"; |
| 1000 | nvidia,function = "kbc"; |
| 1001 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1002 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1003 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1004 | }; |
| 1005 | kb_row4_pr4 { |
| 1006 | nvidia,pins = "kb_row4_pr4"; |
| 1007 | nvidia,function = "kbc"; |
| 1008 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1009 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1010 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1011 | }; |
| 1012 | kb_row5_pr5 { |
| 1013 | nvidia,pins = "kb_row5_pr5"; |
| 1014 | nvidia,function = "kbc"; |
| 1015 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1016 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1017 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1018 | }; |
| 1019 | kb_row6_pr6 { |
| 1020 | nvidia,pins = "kb_row6_pr6"; |
| 1021 | nvidia,function = "kbc"; |
| 1022 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1023 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1024 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1025 | }; |
| 1026 | kb_row7_pr7 { |
| 1027 | nvidia,pins = "kb_row7_pr7"; |
| 1028 | nvidia,function = "kbc"; |
| 1029 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1030 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1031 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1032 | }; |
| 1033 | kb_row8_ps0 { |
| 1034 | nvidia,pins = "kb_row8_ps0"; |
| 1035 | nvidia,function = "kbc"; |
| 1036 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1037 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1038 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1039 | }; |
| 1040 | kb_row9_ps1 { |
| 1041 | nvidia,pins = "kb_row9_ps1"; |
| 1042 | nvidia,function = "kbc"; |
| 1043 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1044 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1045 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1046 | }; |
| 1047 | kb_row10_ps2 { |
| 1048 | nvidia,pins = "kb_row10_ps2"; |
| 1049 | nvidia,function = "kbc"; |
| 1050 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1051 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1052 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1053 | }; |
| 1054 | kb_row11_ps3 { |
| 1055 | nvidia,pins = "kb_row11_ps3"; |
| 1056 | nvidia,function = "kbc"; |
| 1057 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1058 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1059 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1060 | }; |
| 1061 | kb_row12_ps4 { |
| 1062 | nvidia,pins = "kb_row12_ps4"; |
| 1063 | nvidia,function = "kbc"; |
| 1064 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1065 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1066 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1067 | }; |
| 1068 | kb_row13_ps5 { |
| 1069 | nvidia,pins = "kb_row13_ps5"; |
| 1070 | nvidia,function = "kbc"; |
| 1071 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1072 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1073 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1074 | }; |
| 1075 | kb_row14_ps6 { |
| 1076 | nvidia,pins = "kb_row14_ps6"; |
| 1077 | nvidia,function = "kbc"; |
| 1078 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1079 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1080 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1081 | }; |
| 1082 | kb_row15_ps7 { |
| 1083 | nvidia,pins = "kb_row15_ps7"; |
| 1084 | nvidia,function = "kbc"; |
| 1085 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1086 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1087 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1088 | }; |
| 1089 | vi_pclk_pt0 { |
| 1090 | nvidia,pins = "vi_pclk_pt0"; |
| 1091 | nvidia,function = "rsvd1"; |
| 1092 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1093 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1094 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1095 | }; |
| 1096 | vi_mclk_pt1 { |
| 1097 | nvidia,pins = "vi_mclk_pt1"; |
| 1098 | nvidia,function = "vi"; |
| 1099 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1100 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1101 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1102 | }; |
| 1103 | vi_d10_pt2 { |
| 1104 | nvidia,pins = "vi_d10_pt2"; |
| 1105 | nvidia,function = "rsvd1"; |
| 1106 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1107 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1108 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1109 | }; |
| 1110 | vi_d11_pt3 { |
| 1111 | nvidia,pins = "vi_d11_pt3"; |
| 1112 | nvidia,function = "rsvd1"; |
| 1113 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1114 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1115 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1116 | }; |
| 1117 | vi_d0_pt4 { |
| 1118 | nvidia,pins = "vi_d0_pt4"; |
| 1119 | nvidia,function = "rsvd1"; |
| 1120 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1121 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1122 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1123 | }; |
| 1124 | gen2_i2c_scl_pt5 { |
| 1125 | nvidia,pins = "gen2_i2c_scl_pt5"; |
| 1126 | nvidia,function = "i2c2"; |
| 1127 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1128 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1129 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1130 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 1131 | }; |
| 1132 | gen2_i2c_sda_pt6 { |
| 1133 | nvidia,pins = "gen2_i2c_sda_pt6"; |
| 1134 | nvidia,function = "i2c2"; |
| 1135 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1136 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1137 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1138 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 1139 | }; |
| 1140 | sdmmc4_cmd_pt7 { |
| 1141 | nvidia,pins = "sdmmc4_cmd_pt7"; |
| 1142 | nvidia,function = "sdmmc4"; |
| 1143 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1144 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1145 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1146 | }; |
| 1147 | pu0 { |
| 1148 | nvidia,pins = "pu0"; |
| 1149 | nvidia,function = "rsvd1"; |
| 1150 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1151 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1152 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1153 | }; |
| 1154 | pu1 { |
| 1155 | nvidia,pins = "pu1"; |
| 1156 | nvidia,function = "rsvd1"; |
| 1157 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1158 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1159 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1160 | }; |
| 1161 | pu2 { |
| 1162 | nvidia,pins = "pu2"; |
| 1163 | nvidia,function = "rsvd1"; |
| 1164 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1165 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1166 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1167 | }; |
| 1168 | pu3 { |
| 1169 | nvidia,pins = "pu3"; |
| 1170 | nvidia,function = "rsvd1"; |
| 1171 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1172 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1173 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1174 | }; |
| 1175 | pu4 { |
| 1176 | nvidia,pins = "pu4"; |
| 1177 | nvidia,function = "pwm1"; |
| 1178 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1179 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1180 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1181 | }; |
| 1182 | pu5 { |
| 1183 | nvidia,pins = "pu5"; |
| 1184 | nvidia,function = "pwm2"; |
| 1185 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1186 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1187 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1188 | }; |
| 1189 | pu6 { |
| 1190 | nvidia,pins = "pu6"; |
| 1191 | nvidia,function = "rsvd1"; |
| 1192 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1193 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1194 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1195 | }; |
| 1196 | jtag_rtck_pu7 { |
| 1197 | nvidia,pins = "jtag_rtck_pu7"; |
| 1198 | nvidia,function = "rtck"; |
| 1199 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1200 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1201 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1202 | }; |
| 1203 | pv0 { |
| 1204 | nvidia,pins = "pv0"; |
| 1205 | nvidia,function = "rsvd1"; |
| 1206 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1207 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1208 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1209 | }; |
| 1210 | pv2 { |
| 1211 | nvidia,pins = "pv2"; |
| 1212 | nvidia,function = "owr"; |
| 1213 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1214 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1215 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1216 | }; |
| 1217 | pv3 { |
| 1218 | nvidia,pins = "pv3"; |
| 1219 | nvidia,function = "rsvd1"; |
| 1220 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1221 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1222 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1223 | }; |
| 1224 | ddc_scl_pv4 { |
| 1225 | nvidia,pins = "ddc_scl_pv4"; |
| 1226 | nvidia,function = "i2c4"; |
| 1227 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1228 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1229 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1230 | }; |
| 1231 | ddc_sda_pv5 { |
| 1232 | nvidia,pins = "ddc_sda_pv5"; |
| 1233 | nvidia,function = "i2c4"; |
| 1234 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1235 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1236 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1237 | }; |
| 1238 | crt_hsync_pv6 { |
| 1239 | nvidia,pins = "crt_hsync_pv6"; |
| 1240 | nvidia,function = "crt"; |
| 1241 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1242 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1243 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1244 | }; |
| 1245 | crt_vsync_pv7 { |
| 1246 | nvidia,pins = "crt_vsync_pv7"; |
| 1247 | nvidia,function = "crt"; |
| 1248 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1249 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1250 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1251 | }; |
| 1252 | lcd_cs1_n_pw0 { |
| 1253 | nvidia,pins = "lcd_cs1_n_pw0"; |
| 1254 | nvidia,function = "displaya"; |
| 1255 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1256 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1257 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1258 | }; |
| 1259 | lcd_m1_pw1 { |
| 1260 | nvidia,pins = "lcd_m1_pw1"; |
| 1261 | nvidia,function = "displaya"; |
| 1262 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1263 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1264 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1265 | }; |
| 1266 | spi2_cs1_n_pw2 { |
| 1267 | nvidia,pins = "spi2_cs1_n_pw2"; |
| 1268 | nvidia,function = "spi2"; |
| 1269 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1270 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1271 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1272 | }; |
| 1273 | clk1_out_pw4 { |
| 1274 | nvidia,pins = "clk1_out_pw4"; |
| 1275 | nvidia,function = "extperiph1"; |
| 1276 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1277 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1278 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1279 | }; |
| 1280 | clk2_out_pw5 { |
| 1281 | nvidia,pins = "clk2_out_pw5"; |
| 1282 | nvidia,function = "extperiph2"; |
| 1283 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1284 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1285 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1286 | }; |
| 1287 | uart3_txd_pw6 { |
| 1288 | nvidia,pins = "uart3_txd_pw6"; |
| 1289 | nvidia,function = "uartc"; |
| 1290 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1291 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1292 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1293 | }; |
| 1294 | uart3_rxd_pw7 { |
| 1295 | nvidia,pins = "uart3_rxd_pw7"; |
| 1296 | nvidia,function = "uartc"; |
| 1297 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1298 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1299 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1300 | }; |
| 1301 | spi2_sck_px2 { |
| 1302 | nvidia,pins = "spi2_sck_px2"; |
| 1303 | nvidia,function = "gmi"; |
| 1304 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1305 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1306 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1307 | }; |
| 1308 | spi1_mosi_px4 { |
| 1309 | nvidia,pins = "spi1_mosi_px4"; |
| 1310 | nvidia,function = "spi1"; |
| 1311 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1312 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1313 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1314 | }; |
| 1315 | spi1_sck_px5 { |
| 1316 | nvidia,pins = "spi1_sck_px5"; |
| 1317 | nvidia,function = "spi1"; |
| 1318 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1319 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1320 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1321 | }; |
| 1322 | spi1_cs0_n_px6 { |
| 1323 | nvidia,pins = "spi1_cs0_n_px6"; |
| 1324 | nvidia,function = "spi1"; |
| 1325 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1326 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1327 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1328 | }; |
| 1329 | spi1_miso_px7 { |
| 1330 | nvidia,pins = "spi1_miso_px7"; |
| 1331 | nvidia,function = "spi1"; |
| 1332 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1333 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1334 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1335 | }; |
| 1336 | ulpi_clk_py0 { |
| 1337 | nvidia,pins = "ulpi_clk_py0"; |
| 1338 | nvidia,function = "uartd"; |
| 1339 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1340 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1341 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1342 | }; |
| 1343 | ulpi_dir_py1 { |
| 1344 | nvidia,pins = "ulpi_dir_py1"; |
| 1345 | nvidia,function = "uartd"; |
| 1346 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1347 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1348 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1349 | }; |
| 1350 | ulpi_nxt_py2 { |
| 1351 | nvidia,pins = "ulpi_nxt_py2"; |
| 1352 | nvidia,function = "uartd"; |
| 1353 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1354 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1355 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1356 | }; |
| 1357 | ulpi_stp_py3 { |
| 1358 | nvidia,pins = "ulpi_stp_py3"; |
| 1359 | nvidia,function = "uartd"; |
| 1360 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1361 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1362 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1363 | }; |
| 1364 | sdmmc1_dat3_py4 { |
| 1365 | nvidia,pins = "sdmmc1_dat3_py4"; |
| 1366 | nvidia,function = "sdmmc1"; |
| 1367 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1368 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1369 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1370 | }; |
| 1371 | sdmmc1_dat2_py5 { |
| 1372 | nvidia,pins = "sdmmc1_dat2_py5"; |
| 1373 | nvidia,function = "sdmmc1"; |
| 1374 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1375 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1376 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1377 | }; |
| 1378 | sdmmc1_dat1_py6 { |
| 1379 | nvidia,pins = "sdmmc1_dat1_py6"; |
| 1380 | nvidia,function = "sdmmc1"; |
| 1381 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1382 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1383 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1384 | }; |
| 1385 | sdmmc1_dat0_py7 { |
| 1386 | nvidia,pins = "sdmmc1_dat0_py7"; |
| 1387 | nvidia,function = "sdmmc1"; |
| 1388 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1389 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1390 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1391 | }; |
| 1392 | sdmmc1_clk_pz0 { |
| 1393 | nvidia,pins = "sdmmc1_clk_pz0"; |
| 1394 | nvidia,function = "sdmmc1"; |
| 1395 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1396 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1397 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1398 | }; |
| 1399 | sdmmc1_cmd_pz1 { |
| 1400 | nvidia,pins = "sdmmc1_cmd_pz1"; |
| 1401 | nvidia,function = "sdmmc1"; |
| 1402 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1403 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1404 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1405 | }; |
| 1406 | lcd_sdin_pz2 { |
| 1407 | nvidia,pins = "lcd_sdin_pz2"; |
| 1408 | nvidia,function = "displaya"; |
| 1409 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1410 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1411 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1412 | }; |
| 1413 | lcd_wr_n_pz3 { |
| 1414 | nvidia,pins = "lcd_wr_n_pz3"; |
| 1415 | nvidia,function = "displaya"; |
| 1416 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1417 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1418 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1419 | }; |
| 1420 | lcd_sck_pz4 { |
| 1421 | nvidia,pins = "lcd_sck_pz4"; |
| 1422 | nvidia,function = "displaya"; |
| 1423 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1424 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1425 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1426 | }; |
| 1427 | sys_clk_req_pz5 { |
| 1428 | nvidia,pins = "sys_clk_req_pz5"; |
| 1429 | nvidia,function = "sysclk"; |
| 1430 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1431 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1432 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1433 | }; |
| 1434 | pwr_i2c_scl_pz6 { |
| 1435 | nvidia,pins = "pwr_i2c_scl_pz6"; |
| 1436 | nvidia,function = "i2cpwr"; |
| 1437 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1438 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1439 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1440 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 1441 | }; |
| 1442 | pwr_i2c_sda_pz7 { |
| 1443 | nvidia,pins = "pwr_i2c_sda_pz7"; |
| 1444 | nvidia,function = "i2cpwr"; |
| 1445 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1446 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1447 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1448 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1449 | }; |
| 1450 | sdmmc4_dat0_paa0 { |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 1451 | nvidia,pins = "sdmmc4_dat0_paa0"; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1452 | nvidia,function = "sdmmc4"; |
Laxman Dewangan | a47c662 | 2013-12-05 16:14:09 +0530 | [diff] [blame] | 1453 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1454 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 1455 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1456 | }; |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 1457 | sdmmc4_dat1_paa1 { |
| 1458 | nvidia,pins = "sdmmc4_dat1_paa1"; |
| 1459 | nvidia,function = "sdmmc4"; |
| 1460 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1461 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1462 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1463 | }; |
| 1464 | sdmmc4_dat2_paa2 { |
| 1465 | nvidia,pins = "sdmmc4_dat2_paa2"; |
| 1466 | nvidia,function = "sdmmc4"; |
| 1467 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1468 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1469 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1470 | }; |
| 1471 | sdmmc4_dat3_paa3 { |
| 1472 | nvidia,pins = "sdmmc4_dat3_paa3"; |
| 1473 | nvidia,function = "sdmmc4"; |
| 1474 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1475 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1476 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1477 | }; |
| 1478 | sdmmc4_dat4_paa4 { |
| 1479 | nvidia,pins = "sdmmc4_dat4_paa4"; |
| 1480 | nvidia,function = "sdmmc4"; |
| 1481 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1482 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1483 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1484 | }; |
| 1485 | sdmmc4_dat5_paa5 { |
| 1486 | nvidia,pins = "sdmmc4_dat5_paa5"; |
| 1487 | nvidia,function = "sdmmc4"; |
| 1488 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1489 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1490 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1491 | }; |
| 1492 | sdmmc4_dat6_paa6 { |
| 1493 | nvidia,pins = "sdmmc4_dat6_paa6"; |
| 1494 | nvidia,function = "sdmmc4"; |
| 1495 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1496 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1497 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1498 | }; |
| 1499 | sdmmc4_dat7_paa7 { |
| 1500 | nvidia,pins = "sdmmc4_dat7_paa7"; |
| 1501 | nvidia,function = "sdmmc4"; |
| 1502 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1503 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1504 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1505 | }; |
| 1506 | pbb0 { |
| 1507 | nvidia,pins = "pbb0"; |
| 1508 | nvidia,function = "rsvd1"; |
Laxman Dewangan | a47c662 | 2013-12-05 16:14:09 +0530 | [diff] [blame] | 1509 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1510 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 1511 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1512 | }; |
| 1513 | cam_i2c_scl_pbb1 { |
| 1514 | nvidia,pins = "cam_i2c_scl_pbb1"; |
| 1515 | nvidia,function = "i2c3"; |
| 1516 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1517 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1518 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1519 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 1520 | }; |
| 1521 | cam_i2c_sda_pbb2 { |
| 1522 | nvidia,pins = "cam_i2c_sda_pbb2"; |
| 1523 | nvidia,function = "i2c3"; |
| 1524 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1525 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1526 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1527 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 1528 | }; |
| 1529 | pbb3 { |
| 1530 | nvidia,pins = "pbb3"; |
| 1531 | nvidia,function = "vgp3"; |
| 1532 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1533 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1534 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1535 | }; |
| 1536 | pbb4 { |
| 1537 | nvidia,pins = "pbb4"; |
| 1538 | nvidia,function = "vgp4"; |
| 1539 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1540 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1541 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1542 | }; |
| 1543 | pbb5 { |
| 1544 | nvidia,pins = "pbb5"; |
| 1545 | nvidia,function = "vgp5"; |
| 1546 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1547 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1548 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1549 | }; |
| 1550 | pbb6 { |
| 1551 | nvidia,pins = "pbb6"; |
| 1552 | nvidia,function = "vgp6"; |
| 1553 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1554 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1555 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1556 | }; |
| 1557 | pbb7 { |
| 1558 | nvidia,pins = "pbb7"; |
| 1559 | nvidia,function = "i2s4"; |
| 1560 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1561 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1562 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1563 | }; |
| 1564 | cam_mclk_pcc0 { |
| 1565 | nvidia,pins = "cam_mclk_pcc0"; |
| 1566 | nvidia,function = "vi_alt3"; |
| 1567 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1568 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1569 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1570 | }; |
| 1571 | pcc1 { |
| 1572 | nvidia,pins = "pcc1"; |
| 1573 | nvidia,function = "rsvd1"; |
| 1574 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1575 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1576 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1577 | }; |
| 1578 | pcc2 { |
| 1579 | nvidia,pins = "pcc2"; |
| 1580 | nvidia,function = "i2s4"; |
| 1581 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1582 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1583 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1584 | }; |
| 1585 | sdmmc4_rst_n_pcc3 { |
| 1586 | nvidia,pins = "sdmmc4_rst_n_pcc3"; |
| 1587 | nvidia,function = "sdmmc4"; |
| 1588 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 1589 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1590 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1591 | }; |
| 1592 | sdmmc4_clk_pcc4 { |
| 1593 | nvidia,pins = "sdmmc4_clk_pcc4"; |
| 1594 | nvidia,function = "sdmmc4"; |
| 1595 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1596 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1597 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1598 | }; |
| 1599 | clk2_req_pcc5 { |
| 1600 | nvidia,pins = "clk2_req_pcc5"; |
| 1601 | nvidia,function = "dap"; |
| 1602 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1603 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1604 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1605 | }; |
| 1606 | pex_l2_rst_n_pcc6 { |
| 1607 | nvidia,pins = "pex_l2_rst_n_pcc6"; |
| 1608 | nvidia,function = "pcie"; |
| 1609 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1610 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1611 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1612 | }; |
| 1613 | pex_l2_clkreq_n_pcc7 { |
| 1614 | nvidia,pins = "pex_l2_clkreq_n_pcc7"; |
| 1615 | nvidia,function = "pcie"; |
| 1616 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1617 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1618 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1619 | }; |
| 1620 | pex_l0_prsnt_n_pdd0 { |
| 1621 | nvidia,pins = "pex_l0_prsnt_n_pdd0"; |
| 1622 | nvidia,function = "pcie"; |
| 1623 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1624 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1625 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1626 | }; |
| 1627 | pex_l0_rst_n_pdd1 { |
| 1628 | nvidia,pins = "pex_l0_rst_n_pdd1"; |
| 1629 | nvidia,function = "pcie"; |
| 1630 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1631 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1632 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1633 | }; |
| 1634 | pex_l0_clkreq_n_pdd2 { |
| 1635 | nvidia,pins = "pex_l0_clkreq_n_pdd2"; |
| 1636 | nvidia,function = "pcie"; |
| 1637 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1638 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1639 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1640 | }; |
| 1641 | pex_wake_n_pdd3 { |
| 1642 | nvidia,pins = "pex_wake_n_pdd3"; |
| 1643 | nvidia,function = "pcie"; |
| 1644 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1645 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1646 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1647 | }; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 1648 | pex_l1_prsnt_n_pdd4 { |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 1649 | nvidia,pins = "pex_l1_prsnt_n_pdd4"; |
| 1650 | nvidia,function = "pcie"; |
Laxman Dewangan | a47c662 | 2013-12-05 16:14:09 +0530 | [diff] [blame] | 1651 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Lucas Stach | 3d03203 | 2015-01-05 22:57:46 +0100 | [diff] [blame] | 1652 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1653 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1654 | }; |
| 1655 | pex_l1_rst_n_pdd5 { |
| 1656 | nvidia,pins = "pex_l1_rst_n_pdd5"; |
| 1657 | nvidia,function = "pcie"; |
| 1658 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1659 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1660 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1661 | }; |
| 1662 | pex_l1_clkreq_n_pdd6 { |
| 1663 | nvidia,pins = "pex_l1_clkreq_n_pdd6"; |
| 1664 | nvidia,function = "pcie"; |
| 1665 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1666 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1667 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1668 | }; |
| 1669 | pex_l2_prsnt_n_pdd7 { |
| 1670 | nvidia,pins = "pex_l2_prsnt_n_pdd7"; |
| 1671 | nvidia,function = "pcie"; |
| 1672 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1673 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1674 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1675 | }; |
| 1676 | clk3_out_pee0 { |
| 1677 | nvidia,pins = "clk3_out_pee0"; |
| 1678 | nvidia,function = "extperiph3"; |
| 1679 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1680 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1681 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1682 | }; |
| 1683 | clk3_req_pee1 { |
| 1684 | nvidia,pins = "clk3_req_pee1"; |
| 1685 | nvidia,function = "dev3"; |
| 1686 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1687 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1688 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1689 | }; |
| 1690 | clk1_req_pee2 { |
| 1691 | nvidia,pins = "clk1_req_pee2"; |
| 1692 | nvidia,function = "dap"; |
| 1693 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1694 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1695 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1696 | }; |
| 1697 | hdmi_cec_pee3 { |
| 1698 | nvidia,pins = "hdmi_cec_pee3"; |
| 1699 | nvidia,function = "cec"; |
| 1700 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1701 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1702 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1703 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 1704 | }; |
| 1705 | owr { |
| 1706 | nvidia,pins = "owr"; |
| 1707 | nvidia,function = "owr"; |
| 1708 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1709 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1710 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 1711 | }; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1712 | sdio3 { |
| 1713 | nvidia,pins = "drive_sdio3"; |
Laxman Dewangan | a47c662 | 2013-12-05 16:14:09 +0530 | [diff] [blame] | 1714 | nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; |
| 1715 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1716 | nvidia,pull-down-strength = <46>; |
| 1717 | nvidia,pull-up-strength = <42>; |
| 1718 | nvidia,slew-rate-rising = <1>; |
| 1719 | nvidia,slew-rate-falling = <1>; |
| 1720 | }; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 1721 | gpv { |
| 1722 | nvidia,pins = "drive_gpv"; |
| 1723 | nvidia,pull-up-strength = <16>; |
| 1724 | }; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1725 | }; |
| 1726 | }; |
| 1727 | |
| 1728 | serial@70006000 { |
| 1729 | status = "okay"; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1730 | }; |
| 1731 | |
| 1732 | i2c@7000c000 { |
| 1733 | status = "okay"; |
| 1734 | clock-frequency = <100000>; |
| 1735 | }; |
| 1736 | |
| 1737 | i2c@7000c400 { |
| 1738 | status = "okay"; |
| 1739 | clock-frequency = <100000>; |
| 1740 | }; |
| 1741 | |
| 1742 | i2c@7000c500 { |
| 1743 | status = "okay"; |
| 1744 | clock-frequency = <100000>; |
| 1745 | }; |
| 1746 | |
Thierry Reding | 9bd80b4 | 2013-08-12 17:49:03 +0200 | [diff] [blame] | 1747 | hdmiddc: i2c@7000c700 { |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1748 | status = "okay"; |
| 1749 | clock-frequency = <100000>; |
| 1750 | }; |
| 1751 | |
| 1752 | i2c@7000d000 { |
| 1753 | status = "okay"; |
| 1754 | clock-frequency = <100000>; |
| 1755 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 1756 | rt5640: rt5640@1c { |
Stephen Warren | 23037bb | 2013-03-27 16:53:20 -0600 | [diff] [blame] | 1757 | compatible = "realtek,rt5640"; |
| 1758 | reg = <0x1c>; |
| 1759 | interrupt-parent = <&gpio>; |
| 1760 | interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>; |
| 1761 | realtek,ldo1-en-gpios = |
| 1762 | <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; |
| 1763 | }; |
| 1764 | |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1765 | pmic: tps65911@2d { |
| 1766 | compatible = "ti,tps65911"; |
| 1767 | reg = <0x2d>; |
| 1768 | |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 1769 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1770 | #interrupt-cells = <2>; |
| 1771 | interrupt-controller; |
| 1772 | |
| 1773 | ti,system-power-controller; |
| 1774 | |
| 1775 | #gpio-cells = <2>; |
| 1776 | gpio-controller; |
| 1777 | |
| 1778 | vcc1-supply = <&vdd_5v_in_reg>; |
| 1779 | vcc2-supply = <&vdd_5v_in_reg>; |
| 1780 | vcc3-supply = <&vio_reg>; |
| 1781 | vcc4-supply = <&vdd_5v_in_reg>; |
| 1782 | vcc5-supply = <&vdd_5v_in_reg>; |
| 1783 | vcc6-supply = <&vdd2_reg>; |
| 1784 | vcc7-supply = <&vdd_5v_in_reg>; |
| 1785 | vccio-supply = <&vdd_5v_in_reg>; |
| 1786 | |
| 1787 | regulators { |
| 1788 | #address-cells = <1>; |
| 1789 | #size-cells = <0>; |
| 1790 | |
| 1791 | vdd1_reg: vdd1 { |
| 1792 | regulator-name = "vddio_ddr_1v2"; |
| 1793 | regulator-min-microvolt = <1200000>; |
| 1794 | regulator-max-microvolt = <1200000>; |
| 1795 | regulator-always-on; |
| 1796 | }; |
| 1797 | |
| 1798 | vdd2_reg: vdd2 { |
| 1799 | regulator-name = "vdd_1v5_gen"; |
| 1800 | regulator-min-microvolt = <1500000>; |
| 1801 | regulator-max-microvolt = <1500000>; |
| 1802 | regulator-always-on; |
| 1803 | }; |
| 1804 | |
| 1805 | vddctrl_reg: vddctrl { |
| 1806 | regulator-name = "vdd_cpu,vdd_sys"; |
| 1807 | regulator-min-microvolt = <1000000>; |
| 1808 | regulator-max-microvolt = <1000000>; |
| 1809 | regulator-always-on; |
| 1810 | }; |
| 1811 | |
| 1812 | vio_reg: vio { |
| 1813 | regulator-name = "vdd_1v8_gen"; |
| 1814 | regulator-min-microvolt = <1800000>; |
| 1815 | regulator-max-microvolt = <1800000>; |
| 1816 | regulator-always-on; |
| 1817 | }; |
| 1818 | |
| 1819 | ldo1_reg: ldo1 { |
| 1820 | regulator-name = "vdd_pexa,vdd_pexb"; |
| 1821 | regulator-min-microvolt = <1050000>; |
| 1822 | regulator-max-microvolt = <1050000>; |
| 1823 | }; |
| 1824 | |
| 1825 | ldo2_reg: ldo2 { |
| 1826 | regulator-name = "vdd_sata,avdd_plle"; |
| 1827 | regulator-min-microvolt = <1050000>; |
| 1828 | regulator-max-microvolt = <1050000>; |
| 1829 | }; |
| 1830 | |
| 1831 | /* LDO3 is not connected to anything */ |
| 1832 | |
| 1833 | ldo4_reg: ldo4 { |
| 1834 | regulator-name = "vdd_rtc"; |
| 1835 | regulator-min-microvolt = <1200000>; |
| 1836 | regulator-max-microvolt = <1200000>; |
| 1837 | regulator-always-on; |
| 1838 | }; |
| 1839 | |
| 1840 | ldo5_reg: ldo5 { |
| 1841 | regulator-name = "vddio_sdmmc,avdd_vdac"; |
| 1842 | regulator-min-microvolt = <3300000>; |
| 1843 | regulator-max-microvolt = <3300000>; |
| 1844 | regulator-always-on; |
| 1845 | }; |
| 1846 | |
| 1847 | ldo6_reg: ldo6 { |
| 1848 | regulator-name = "avdd_dsi_csi,pwrdet_mipi"; |
| 1849 | regulator-min-microvolt = <1200000>; |
| 1850 | regulator-max-microvolt = <1200000>; |
| 1851 | }; |
| 1852 | |
| 1853 | ldo7_reg: ldo7 { |
| 1854 | regulator-name = "vdd_pllm,x,u,a_p_c_s"; |
| 1855 | regulator-min-microvolt = <1200000>; |
| 1856 | regulator-max-microvolt = <1200000>; |
| 1857 | regulator-always-on; |
| 1858 | }; |
| 1859 | |
| 1860 | ldo8_reg: ldo8 { |
| 1861 | regulator-name = "vdd_ddr_hs"; |
| 1862 | regulator-min-microvolt = <1000000>; |
| 1863 | regulator-max-microvolt = <1000000>; |
| 1864 | regulator-always-on; |
| 1865 | }; |
| 1866 | }; |
| 1867 | }; |
Stephen Warren | 5789905 | 2013-11-26 14:43:45 -0700 | [diff] [blame] | 1868 | |
| 1869 | tps62361@60 { |
| 1870 | compatible = "ti,tps62361"; |
| 1871 | reg = <0x60>; |
| 1872 | |
| 1873 | regulator-name = "tps62361-vout"; |
| 1874 | regulator-min-microvolt = <500000>; |
| 1875 | regulator-max-microvolt = <1500000>; |
| 1876 | regulator-boot-on; |
| 1877 | regulator-always-on; |
| 1878 | ti,vsel0-state-high; |
| 1879 | ti,vsel1-state-high; |
| 1880 | }; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1881 | }; |
| 1882 | |
| 1883 | spi@7000da00 { |
| 1884 | status = "okay"; |
| 1885 | spi-max-frequency = <25000000>; |
| 1886 | spi-flash@1 { |
| 1887 | compatible = "winbond,w25q32"; |
| 1888 | reg = <1>; |
| 1889 | spi-max-frequency = <20000000>; |
| 1890 | }; |
| 1891 | }; |
| 1892 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 1893 | pmc@7000e400 { |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1894 | status = "okay"; |
| 1895 | nvidia,invert-interrupt; |
Joseph Lo | 47d2d63 | 2013-08-12 17:40:07 +0800 | [diff] [blame] | 1896 | nvidia,suspend-mode = <1>; |
Joseph Lo | a44a019 | 2013-04-03 19:31:52 +0800 | [diff] [blame] | 1897 | nvidia,cpu-pwr-good-time = <2000>; |
| 1898 | nvidia,cpu-pwr-off-time = <200>; |
| 1899 | nvidia,core-pwr-good-time = <3845 3845>; |
| 1900 | nvidia,core-pwr-off-time = <0>; |
| 1901 | nvidia,core-power-req-active-high; |
| 1902 | nvidia,sys-clock-req-active-high; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1903 | }; |
| 1904 | |
Stephen Warren | 5789905 | 2013-11-26 14:43:45 -0700 | [diff] [blame] | 1905 | ahub@70080000 { |
| 1906 | i2s@70080400 { |
| 1907 | status = "okay"; |
| 1908 | }; |
| 1909 | }; |
| 1910 | |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1911 | sdhci@78000000 { |
| 1912 | status = "okay"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 1913 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
| 1914 | wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; |
| 1915 | power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1916 | bus-width = <4>; |
| 1917 | }; |
| 1918 | |
| 1919 | sdhci@78000600 { |
| 1920 | status = "okay"; |
| 1921 | bus-width = <8>; |
Joseph Lo | 7a2617a | 2013-04-03 14:34:39 -0600 | [diff] [blame] | 1922 | non-removable; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1923 | }; |
| 1924 | |
Eric Brower | 4c69650 | 2013-12-19 18:08:53 -0800 | [diff] [blame] | 1925 | usb@7d004000 { |
| 1926 | status = "okay"; |
| 1927 | }; |
| 1928 | |
| 1929 | phy2: usb-phy@7d004000 { |
| 1930 | vbus-supply = <&sys_3v3_reg>; |
| 1931 | status = "okay"; |
| 1932 | }; |
| 1933 | |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 1934 | usb@7d008000 { |
| 1935 | status = "okay"; |
| 1936 | }; |
| 1937 | |
| 1938 | usb-phy@7d008000 { |
| 1939 | vbus-supply = <&usb3_vbus_reg>; |
| 1940 | status = "okay"; |
| 1941 | }; |
| 1942 | |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 1943 | clocks { |
| 1944 | compatible = "simple-bus"; |
| 1945 | #address-cells = <1>; |
| 1946 | #size-cells = <0>; |
| 1947 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 1948 | clk32k_in: clock@0 { |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 1949 | compatible = "fixed-clock"; |
| 1950 | reg=<0>; |
| 1951 | #clock-cells = <0>; |
| 1952 | clock-frequency = <32768>; |
| 1953 | }; |
| 1954 | }; |
| 1955 | |
Stephen Warren | 5789905 | 2013-11-26 14:43:45 -0700 | [diff] [blame] | 1956 | gpio-leds { |
| 1957 | compatible = "gpio-leds"; |
| 1958 | |
| 1959 | gpled1 { |
| 1960 | label = "LED1"; /* CR5A1 (blue) */ |
| 1961 | gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; |
| 1962 | }; |
| 1963 | gpled2 { |
| 1964 | label = "LED2"; /* CR4A2 (green) */ |
| 1965 | gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; |
| 1966 | }; |
| 1967 | }; |
| 1968 | |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1969 | regulators { |
| 1970 | compatible = "simple-bus"; |
| 1971 | #address-cells = <1>; |
| 1972 | #size-cells = <0>; |
| 1973 | |
| 1974 | vdd_5v_in_reg: regulator@0 { |
| 1975 | compatible = "regulator-fixed"; |
| 1976 | reg = <0>; |
| 1977 | regulator-name = "vdd_5v_in"; |
| 1978 | regulator-min-microvolt = <5000000>; |
| 1979 | regulator-max-microvolt = <5000000>; |
| 1980 | regulator-always-on; |
| 1981 | }; |
| 1982 | |
| 1983 | chargepump_5v_reg: regulator@1 { |
| 1984 | compatible = "regulator-fixed"; |
| 1985 | reg = <1>; |
| 1986 | regulator-name = "chargepump_5v"; |
| 1987 | regulator-min-microvolt = <5000000>; |
| 1988 | regulator-max-microvolt = <5000000>; |
| 1989 | regulator-boot-on; |
| 1990 | regulator-always-on; |
| 1991 | enable-active-high; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 1992 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 1993 | }; |
| 1994 | |
| 1995 | ddr_reg: regulator@2 { |
| 1996 | compatible = "regulator-fixed"; |
| 1997 | reg = <2>; |
| 1998 | regulator-name = "vdd_ddr"; |
| 1999 | regulator-min-microvolt = <1500000>; |
| 2000 | regulator-max-microvolt = <1500000>; |
| 2001 | regulator-always-on; |
| 2002 | regulator-boot-on; |
| 2003 | enable-active-high; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 2004 | gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 2005 | vin-supply = <&vdd_5v_in_reg>; |
| 2006 | }; |
| 2007 | |
| 2008 | vdd_5v_sata_reg: regulator@3 { |
| 2009 | compatible = "regulator-fixed"; |
| 2010 | reg = <3>; |
| 2011 | regulator-name = "vdd_5v_sata"; |
| 2012 | regulator-min-microvolt = <5000000>; |
| 2013 | regulator-max-microvolt = <5000000>; |
| 2014 | regulator-always-on; |
| 2015 | regulator-boot-on; |
| 2016 | enable-active-high; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 2017 | gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 2018 | vin-supply = <&vdd_5v_in_reg>; |
| 2019 | }; |
| 2020 | |
| 2021 | usb1_vbus_reg: regulator@4 { |
| 2022 | compatible = "regulator-fixed"; |
| 2023 | reg = <4>; |
| 2024 | regulator-name = "usb1_vbus"; |
| 2025 | regulator-min-microvolt = <5000000>; |
| 2026 | regulator-max-microvolt = <5000000>; |
| 2027 | enable-active-high; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 2028 | gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 2029 | gpio-open-drain; |
| 2030 | vin-supply = <&vdd_5v_in_reg>; |
| 2031 | }; |
| 2032 | |
| 2033 | usb3_vbus_reg: regulator@5 { |
| 2034 | compatible = "regulator-fixed"; |
| 2035 | reg = <5>; |
| 2036 | regulator-name = "usb3_vbus"; |
| 2037 | regulator-min-microvolt = <5000000>; |
| 2038 | regulator-max-microvolt = <5000000>; |
| 2039 | enable-active-high; |
Tuomas Tynkkynen | cc34c9f | 2013-08-01 18:00:17 +0300 | [diff] [blame] | 2040 | gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 2041 | gpio-open-drain; |
| 2042 | vin-supply = <&vdd_5v_in_reg>; |
| 2043 | }; |
| 2044 | |
| 2045 | sys_3v3_reg: regulator@6 { |
| 2046 | compatible = "regulator-fixed"; |
| 2047 | reg = <6>; |
| 2048 | regulator-name = "sys_3v3,vdd_3v3_alw"; |
| 2049 | regulator-min-microvolt = <3300000>; |
| 2050 | regulator-max-microvolt = <3300000>; |
| 2051 | regulator-always-on; |
| 2052 | regulator-boot-on; |
| 2053 | enable-active-high; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 2054 | gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 2055 | vin-supply = <&vdd_5v_in_reg>; |
| 2056 | }; |
| 2057 | |
| 2058 | sys_3v3_pexs_reg: regulator@7 { |
| 2059 | compatible = "regulator-fixed"; |
| 2060 | reg = <7>; |
| 2061 | regulator-name = "sys_3v3_pexs"; |
| 2062 | regulator-min-microvolt = <3300000>; |
| 2063 | regulator-max-microvolt = <3300000>; |
| 2064 | regulator-always-on; |
| 2065 | regulator-boot-on; |
| 2066 | enable-active-high; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 2067 | gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 2068 | vin-supply = <&sys_3v3_reg>; |
| 2069 | }; |
Thierry Reding | 597eb8e | 2014-04-25 17:44:49 +0200 | [diff] [blame] | 2070 | |
| 2071 | vdd_5v0_hdmi: regulator@8 { |
| 2072 | compatible = "regulator-fixed"; |
| 2073 | reg = <8>; |
| 2074 | regulator-name = "+VDD_5V_HDMI"; |
| 2075 | regulator-min-microvolt = <5000000>; |
| 2076 | regulator-max-microvolt = <5000000>; |
| 2077 | regulator-always-on; |
| 2078 | regulator-boot-on; |
| 2079 | vin-supply = <&sys_3v3_reg>; |
| 2080 | }; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 2081 | }; |
Eric Brower | b4dd3e0 | 2013-05-10 14:40:29 +0000 | [diff] [blame] | 2082 | |
Stephen Warren | 23037bb | 2013-03-27 16:53:20 -0600 | [diff] [blame] | 2083 | sound { |
| 2084 | compatible = "nvidia,tegra-audio-rt5640-beaver", |
| 2085 | "nvidia,tegra-audio-rt5640"; |
| 2086 | nvidia,model = "NVIDIA Tegra Beaver"; |
| 2087 | |
| 2088 | nvidia,audio-routing = |
| 2089 | "Headphones", "HPOR", |
Stephen Warren | ac47228 | 2013-08-14 13:54:24 -0600 | [diff] [blame] | 2090 | "Headphones", "HPOL", |
| 2091 | "Mic Jack", "MICBIAS1", |
| 2092 | "IN2P", "Mic Jack"; |
Stephen Warren | 23037bb | 2013-03-27 16:53:20 -0600 | [diff] [blame] | 2093 | |
| 2094 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 2095 | nvidia,audio-codec = <&rt5640>; |
| 2096 | |
| 2097 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; |
| 2098 | |
| 2099 | clocks = <&tegra_car TEGRA30_CLK_PLL_A>, |
| 2100 | <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, |
| 2101 | <&tegra_car TEGRA30_CLK_EXTERN1>; |
| 2102 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 2103 | }; |
Bryan Wu | d7df69f | 2013-01-02 15:53:51 -0800 | [diff] [blame] | 2104 | }; |