blob: 80dc3334e82f73c5727ed388176c58764e63088a [file] [log] [blame]
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -08001/*
2 * driver/mfd/asic3.c
3 *
4 * Compaq ASIC3 support.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Copyright 2001 Compaq Computer Corporation.
11 * Copyright 2004-2005 Phil Blundell
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020012 * Copyright 2007-2008 OpenedHand Ltd.
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080013 *
14 * Authors: Phil Blundell <pb@handhelds.org>,
15 * Samuel Ortiz <sameo@openedhand.com>
16 *
17 */
18
19#include <linux/version.h>
20#include <linux/kernel.h>
21#include <linux/irq.h>
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020022#include <linux/gpio.h>
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080023#include <linux/io.h>
24#include <linux/spinlock.h>
25#include <linux/platform_device.h>
26
27#include <linux/mfd/asic3.h>
28
Samuel Ortiz6f2384c2008-06-20 11:02:19 +020029struct asic3 {
30 void __iomem *mapping;
31 unsigned int bus_shift;
32 unsigned int irq_nr;
33 unsigned int irq_base;
34 spinlock_t lock;
35 u16 irq_bothedge[4];
36 struct gpio_chip gpio;
37 struct device *dev;
38};
39
40static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
41
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080042static inline void asic3_write_register(struct asic3 *asic,
43 unsigned int reg, u32 value)
44{
Al Virob32661e2008-03-29 03:10:58 +000045 iowrite16(value, asic->mapping +
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080046 (reg >> asic->bus_shift));
47}
48
49static inline u32 asic3_read_register(struct asic3 *asic,
50 unsigned int reg)
51{
Al Virob32661e2008-03-29 03:10:58 +000052 return ioread16(asic->mapping +
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080053 (reg >> asic->bus_shift));
54}
55
56/* IRQs */
57#define MAX_ASIC_ISR_LOOPS 20
Samuel Ortiz3b8139f2008-06-20 11:12:21 +020058#define ASIC3_GPIO_BASE_INCR \
59 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080060
61static void asic3_irq_flip_edge(struct asic3 *asic,
62 u32 base, int bit)
63{
64 u16 edge;
65 unsigned long flags;
66
67 spin_lock_irqsave(&asic->lock, flags);
68 edge = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +020069 base + ASIC3_GPIO_EDGE_TRIGGER);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080070 edge ^= bit;
71 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +020072 base + ASIC3_GPIO_EDGE_TRIGGER, edge);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080073 spin_unlock_irqrestore(&asic->lock, flags);
74}
75
76static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
77{
78 int iter, i;
79 unsigned long flags;
80 struct asic3 *asic;
81
82 desc->chip->ack(irq);
83
84 asic = desc->handler_data;
85
86 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
87 u32 status;
88 int bank;
89
90 spin_lock_irqsave(&asic->lock, flags);
91 status = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +020092 ASIC3_OFFSET(INTR, P_INT_STAT));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -080093 spin_unlock_irqrestore(&asic->lock, flags);
94
95 /* Check all ten register bits */
96 if ((status & 0x3ff) == 0)
97 break;
98
99 /* Handle GPIO IRQs */
100 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
101 if (status & (1 << bank)) {
102 unsigned long base, istat;
103
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200104 base = ASIC3_GPIO_A_BASE
105 + bank * ASIC3_GPIO_BASE_INCR;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800106
107 spin_lock_irqsave(&asic->lock, flags);
108 istat = asic3_read_register(asic,
109 base +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200110 ASIC3_GPIO_INT_STATUS);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800111 /* Clearing IntStatus */
112 asic3_write_register(asic,
113 base +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200114 ASIC3_GPIO_INT_STATUS, 0);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800115 spin_unlock_irqrestore(&asic->lock, flags);
116
117 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
118 int bit = (1 << i);
119 unsigned int irqnr;
120
121 if (!(istat & bit))
122 continue;
123
124 irqnr = asic->irq_base +
125 (ASIC3_GPIOS_PER_BANK * bank)
126 + i;
127 desc = irq_desc + irqnr;
128 desc->handle_irq(irqnr, desc);
129 if (asic->irq_bothedge[bank] & bit)
130 asic3_irq_flip_edge(asic, base,
131 bit);
132 }
133 }
134 }
135
136 /* Handle remaining IRQs in the status register */
137 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
138 /* They start at bit 4 and go up */
139 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
140 desc = irq_desc + + i;
141 desc->handle_irq(asic->irq_base + i,
142 desc);
143 }
144 }
145 }
146
147 if (iter >= MAX_ASIC_ISR_LOOPS)
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200148 dev_err(asic->dev, "interrupt processing overrun\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800149}
150
151static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
152{
153 int n;
154
155 n = (irq - asic->irq_base) >> 4;
156
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200157 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800158}
159
160static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
161{
162 return (irq - asic->irq_base) & 0xf;
163}
164
165static void asic3_mask_gpio_irq(unsigned int irq)
166{
167 struct asic3 *asic = get_irq_chip_data(irq);
168 u32 val, bank, index;
169 unsigned long flags;
170
171 bank = asic3_irq_to_bank(asic, irq);
172 index = asic3_irq_to_index(asic, irq);
173
174 spin_lock_irqsave(&asic->lock, flags);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200175 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800176 val |= 1 << index;
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200177 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800178 spin_unlock_irqrestore(&asic->lock, flags);
179}
180
181static void asic3_mask_irq(unsigned int irq)
182{
183 struct asic3 *asic = get_irq_chip_data(irq);
184 int regval;
185 unsigned long flags;
186
187 spin_lock_irqsave(&asic->lock, flags);
188 regval = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200189 ASIC3_INTR_BASE +
190 ASIC3_INTR_INT_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800191
192 regval &= ~(ASIC3_INTMASK_MASK0 <<
193 (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
194
195 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200196 ASIC3_INTR_BASE +
197 ASIC3_INTR_INT_MASK,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800198 regval);
199 spin_unlock_irqrestore(&asic->lock, flags);
200}
201
202static void asic3_unmask_gpio_irq(unsigned int irq)
203{
204 struct asic3 *asic = get_irq_chip_data(irq);
205 u32 val, bank, index;
206 unsigned long flags;
207
208 bank = asic3_irq_to_bank(asic, irq);
209 index = asic3_irq_to_index(asic, irq);
210
211 spin_lock_irqsave(&asic->lock, flags);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200212 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800213 val &= ~(1 << index);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200214 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800215 spin_unlock_irqrestore(&asic->lock, flags);
216}
217
218static void asic3_unmask_irq(unsigned int irq)
219{
220 struct asic3 *asic = get_irq_chip_data(irq);
221 int regval;
222 unsigned long flags;
223
224 spin_lock_irqsave(&asic->lock, flags);
225 regval = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200226 ASIC3_INTR_BASE +
227 ASIC3_INTR_INT_MASK);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800228
229 regval |= (ASIC3_INTMASK_MASK0 <<
230 (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
231
232 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200233 ASIC3_INTR_BASE +
234 ASIC3_INTR_INT_MASK,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800235 regval);
236 spin_unlock_irqrestore(&asic->lock, flags);
237}
238
239static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
240{
241 struct asic3 *asic = get_irq_chip_data(irq);
242 u32 bank, index;
243 u16 trigger, level, edge, bit;
244 unsigned long flags;
245
246 bank = asic3_irq_to_bank(asic, irq);
247 index = asic3_irq_to_index(asic, irq);
248 bit = 1<<index;
249
250 spin_lock_irqsave(&asic->lock, flags);
251 level = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200252 bank + ASIC3_GPIO_LEVEL_TRIGGER);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800253 edge = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200254 bank + ASIC3_GPIO_EDGE_TRIGGER);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800255 trigger = asic3_read_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200256 bank + ASIC3_GPIO_TRIGGER_TYPE);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800257 asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
258
259 if (type == IRQT_RISING) {
260 trigger |= bit;
261 edge |= bit;
262 } else if (type == IRQT_FALLING) {
263 trigger |= bit;
264 edge &= ~bit;
265 } else if (type == IRQT_BOTHEDGE) {
266 trigger |= bit;
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200267 if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800268 edge &= ~bit;
269 else
270 edge |= bit;
271 asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
272 } else if (type == IRQT_LOW) {
273 trigger &= ~bit;
274 level &= ~bit;
275 } else if (type == IRQT_HIGH) {
276 trigger &= ~bit;
277 level |= bit;
278 } else {
279 /*
280 * if type == IRQT_NOEDGE, we should mask interrupts, but
281 * be careful to not unmask them if mask was also called.
282 * Probably need internal state for mask.
283 */
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200284 dev_notice(asic->dev, "irq type not changed\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800285 }
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200286 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800287 level);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200288 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800289 edge);
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200290 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800291 trigger);
292 spin_unlock_irqrestore(&asic->lock, flags);
293 return 0;
294}
295
296static struct irq_chip asic3_gpio_irq_chip = {
297 .name = "ASIC3-GPIO",
298 .ack = asic3_mask_gpio_irq,
299 .mask = asic3_mask_gpio_irq,
300 .unmask = asic3_unmask_gpio_irq,
301 .set_type = asic3_gpio_irq_type,
302};
303
304static struct irq_chip asic3_irq_chip = {
305 .name = "ASIC3",
306 .ack = asic3_mask_irq,
307 .mask = asic3_mask_irq,
308 .unmask = asic3_unmask_irq,
309};
310
Philipp Zabel065032f2008-06-21 00:51:38 +0200311static int __init asic3_irq_probe(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800312{
313 struct asic3 *asic = platform_get_drvdata(pdev);
314 unsigned long clksel = 0;
315 unsigned int irq, irq_base;
316
317 asic->irq_nr = platform_get_irq(pdev, 0);
318 if (asic->irq_nr < 0)
319 return asic->irq_nr;
320
321 /* turn on clock to IRQ controller */
322 clksel |= CLOCK_SEL_CX;
323 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
324 clksel);
325
326 irq_base = asic->irq_base;
327
328 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
329 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
330 set_irq_chip(irq, &asic3_gpio_irq_chip);
331 else
332 set_irq_chip(irq, &asic3_irq_chip);
333
334 set_irq_chip_data(irq, asic);
335 set_irq_handler(irq, handle_level_irq);
336 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
337 }
338
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200339 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800340 ASIC3_INTMASK_GINTMASK);
341
342 set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
343 set_irq_type(asic->irq_nr, IRQT_RISING);
344 set_irq_data(asic->irq_nr, asic);
345
346 return 0;
347}
348
349static void asic3_irq_remove(struct platform_device *pdev)
350{
351 struct asic3 *asic = platform_get_drvdata(pdev);
352 unsigned int irq, irq_base;
353
354 irq_base = asic->irq_base;
355
356 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
357 set_irq_flags(irq, 0);
358 set_irq_handler(irq, NULL);
359 set_irq_chip(irq, NULL);
360 set_irq_chip_data(irq, NULL);
361 }
362 set_irq_chained_handler(asic->irq_nr, NULL);
363}
364
365/* GPIOs */
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200366static int asic3_gpio_direction(struct gpio_chip *chip,
367 unsigned offset, int out)
368{
369 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
370 unsigned int gpio_base;
371 unsigned long flags;
372 struct asic3 *asic;
373
374 asic = container_of(chip, struct asic3, gpio);
375 gpio_base = ASIC3_GPIO_TO_BASE(offset);
376
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200377 if (gpio_base > ASIC3_GPIO_D_BASE) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200378 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
379 gpio_base, offset);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200380 return -EINVAL;
381 }
382
383 spin_lock_irqsave(&asic->lock, flags);
384
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200385 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200386
387 /* Input is 0, Output is 1 */
388 if (out)
389 out_reg |= mask;
390 else
391 out_reg &= ~mask;
392
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200393 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200394
395 spin_unlock_irqrestore(&asic->lock, flags);
396
397 return 0;
398
399}
400
401static int asic3_gpio_direction_input(struct gpio_chip *chip,
402 unsigned offset)
403{
404 return asic3_gpio_direction(chip, offset, 0);
405}
406
407static int asic3_gpio_direction_output(struct gpio_chip *chip,
408 unsigned offset, int value)
409{
410 return asic3_gpio_direction(chip, offset, 1);
411}
412
413static int asic3_gpio_get(struct gpio_chip *chip,
414 unsigned offset)
415{
416 unsigned int gpio_base;
417 u32 mask = ASIC3_GPIO_TO_MASK(offset);
418 struct asic3 *asic;
419
420 asic = container_of(chip, struct asic3, gpio);
421 gpio_base = ASIC3_GPIO_TO_BASE(offset);
422
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200423 if (gpio_base > ASIC3_GPIO_D_BASE) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200424 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
425 gpio_base, offset);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200426 return -EINVAL;
427 }
428
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200429 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200430}
431
432static void asic3_gpio_set(struct gpio_chip *chip,
433 unsigned offset, int value)
434{
435 u32 mask, out_reg;
436 unsigned int gpio_base;
437 unsigned long flags;
438 struct asic3 *asic;
439
440 asic = container_of(chip, struct asic3, gpio);
441 gpio_base = ASIC3_GPIO_TO_BASE(offset);
442
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200443 if (gpio_base > ASIC3_GPIO_D_BASE) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200444 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
445 gpio_base, offset);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200446 return;
447 }
448
449 mask = ASIC3_GPIO_TO_MASK(offset);
450
451 spin_lock_irqsave(&asic->lock, flags);
452
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200453 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200454
455 if (value)
456 out_reg |= mask;
457 else
458 out_reg &= ~mask;
459
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200460 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200461
462 spin_unlock_irqrestore(&asic->lock, flags);
463
464 return;
465}
466
Philipp Zabel065032f2008-06-21 00:51:38 +0200467static __init int asic3_gpio_probe(struct platform_device *pdev,
468 u16 *gpio_config, int num)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800469{
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800470 struct asic3 *asic = platform_get_drvdata(pdev);
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200471 u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
472 u16 out_reg[ASIC3_NUM_GPIO_BANKS];
473 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
474 int i;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800475
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200476 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS);
477 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS);
478 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS);
479
480 /* Enable all GPIOs */
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200481 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
482 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
483 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
484 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800485
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200486 for (i = 0; i < num; i++) {
487 u8 alt, pin, dir, init, bank_num, bit_num;
488 u16 config = gpio_config[i];
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800489
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200490 pin = ASIC3_CONFIG_GPIO_PIN(config);
491 alt = ASIC3_CONFIG_GPIO_ALT(config);
492 dir = ASIC3_CONFIG_GPIO_DIR(config);
493 init = ASIC3_CONFIG_GPIO_INIT(config);
494
495 bank_num = ASIC3_GPIO_TO_BANK(pin);
496 bit_num = ASIC3_GPIO_TO_BIT(pin);
497
498 alt_reg[bank_num] |= (alt << bit_num);
499 out_reg[bank_num] |= (init << bit_num);
500 dir_reg[bank_num] |= (dir << bit_num);
501 }
502
503 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
504 asic3_write_register(asic,
505 ASIC3_BANK_TO_BASE(i) +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200506 ASIC3_GPIO_DIRECTION,
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200507 dir_reg[i]);
508 asic3_write_register(asic,
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200509 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200510 out_reg[i]);
511 asic3_write_register(asic,
512 ASIC3_BANK_TO_BASE(i) +
Samuel Ortiz3b8139f2008-06-20 11:12:21 +0200513 ASIC3_GPIO_ALT_FUNCTION,
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200514 alt_reg[i]);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800515 }
516
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200517 return gpiochip_add(&asic->gpio);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800518}
519
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200520static int asic3_gpio_remove(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800521{
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200522 struct asic3 *asic = platform_get_drvdata(pdev);
523
524 return gpiochip_remove(&asic->gpio);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800525}
526
527
528/* Core */
Philipp Zabel065032f2008-06-21 00:51:38 +0200529static int __init asic3_probe(struct platform_device *pdev)
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800530{
531 struct asic3_platform_data *pdata = pdev->dev.platform_data;
532 struct asic3 *asic;
533 struct resource *mem;
534 unsigned long clksel;
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200535 int ret = 0;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800536
537 asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200538 if (asic == NULL) {
539 printk(KERN_ERR "kzalloc failed\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800540 return -ENOMEM;
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200541 }
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800542
543 spin_lock_init(&asic->lock);
544 platform_set_drvdata(pdev, asic);
545 asic->dev = &pdev->dev;
546
547 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
548 if (!mem) {
549 ret = -ENOMEM;
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200550 dev_err(asic->dev, "no MEM resource\n");
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200551 goto out_free;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800552 }
553
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200554
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800555 asic->mapping = ioremap(mem->start, PAGE_SIZE);
556 if (!asic->mapping) {
557 ret = -ENOMEM;
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200558 dev_err(asic->dev, "Couldn't ioremap\n");
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200559 goto out_free;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800560 }
561
562 asic->irq_base = pdata->irq_base;
563
564 if (pdata && pdata->bus_shift)
565 asic->bus_shift = 2 - pdata->bus_shift;
566 else
567 asic->bus_shift = 0;
568
569 clksel = 0;
570 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
571
572 ret = asic3_irq_probe(pdev);
573 if (ret < 0) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200574 dev_err(asic->dev, "Couldn't probe IRQs\n");
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200575 goto out_unmap;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800576 }
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200577
578 asic->gpio.base = pdata->gpio_base;
579 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
580 asic->gpio.get = asic3_gpio_get;
581 asic->gpio.set = asic3_gpio_set;
582 asic->gpio.direction_input = asic3_gpio_direction_input;
583 asic->gpio.direction_output = asic3_gpio_direction_output;
584
Samuel Ortiz3b26bf12008-06-20 11:09:51 +0200585 ret = asic3_gpio_probe(pdev,
586 pdata->gpio_config,
587 pdata->gpio_config_num);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200588 if (ret < 0) {
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200589 dev_err(asic->dev, "GPIO probe failed\n");
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200590 goto out_irq;
591 }
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800592
Samuel Ortiz24f4f2e2008-06-20 11:11:19 +0200593 dev_info(asic->dev, "ASIC3 Core driver\n");
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800594
595 return 0;
596
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200597 out_irq:
598 asic3_irq_remove(pdev);
599
600 out_unmap:
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800601 iounmap(asic->mapping);
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200602
603 out_free:
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800604 kfree(asic);
605
606 return ret;
607}
608
609static int asic3_remove(struct platform_device *pdev)
610{
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200611 int ret;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800612 struct asic3 *asic = platform_get_drvdata(pdev);
613
Samuel Ortiz6f2384c2008-06-20 11:02:19 +0200614 ret = asic3_gpio_remove(pdev);
615 if (ret < 0)
616 return ret;
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800617 asic3_irq_remove(pdev);
618
619 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
620
621 iounmap(asic->mapping);
622
623 kfree(asic);
624
625 return 0;
626}
627
628static void asic3_shutdown(struct platform_device *pdev)
629{
630}
631
632static struct platform_driver asic3_device_driver = {
633 .driver = {
634 .name = "asic3",
635 },
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800636 .remove = __devexit_p(asic3_remove),
637 .shutdown = asic3_shutdown,
638};
639
640static int __init asic3_init(void)
641{
642 int retval = 0;
Philipp Zabel065032f2008-06-21 00:51:38 +0200643 retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
Samuel Ortizfa9ff4b2008-02-07 00:14:49 -0800644 return retval;
645}
646
647subsys_initcall(asic3_init);