Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-pxa/gpio.c |
| 3 | * |
| 4 | * Generic PXA GPIO handling |
| 5 | * |
| 6 | * Author: Nicolas Pitre |
| 7 | * Created: Jun 15, 2001 |
| 8 | * Copyright: MontaVista Software Inc. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/module.h> |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 17 | #include <linux/irq.h> |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 18 | #include <linux/sysdev.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 19 | #include <linux/io.h> |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 20 | |
| 21 | #include <asm/gpio.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 22 | #include <mach/hardware.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 23 | #include <mach/pxa-regs.h> |
| 24 | #include <mach/pxa2xx-gpio.h> |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 25 | |
| 26 | #include "generic.h" |
| 27 | |
| 28 | |
| 29 | struct pxa_gpio_chip { |
| 30 | struct gpio_chip chip; |
| 31 | void __iomem *regbase; |
| 32 | }; |
| 33 | |
| 34 | int pxa_last_gpio; |
| 35 | |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame^] | 36 | #ifdef CONFIG_CPU_PXA26x |
| 37 | /* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, |
| 38 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. |
| 39 | */ |
| 40 | static int __gpio_is_inverted(unsigned gpio) |
| 41 | { |
| 42 | return cpu_is_pxa25x() && gpio > 85; |
| 43 | } |
| 44 | #else |
| 45 | #define __gpio_is_inverted(gpio) (0) |
| 46 | #endif |
| 47 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 48 | /* |
| 49 | * Configure pins for GPIO or other functions |
| 50 | */ |
| 51 | int pxa_gpio_mode(int gpio_mode) |
| 52 | { |
| 53 | unsigned long flags; |
| 54 | int gpio = gpio_mode & GPIO_MD_MASK_NR; |
| 55 | int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; |
| 56 | int gafr; |
| 57 | |
| 58 | if (gpio > pxa_last_gpio) |
| 59 | return -EINVAL; |
| 60 | |
| 61 | local_irq_save(flags); |
| 62 | if (gpio_mode & GPIO_DFLT_LOW) |
| 63 | GPCR(gpio) = GPIO_bit(gpio); |
| 64 | else if (gpio_mode & GPIO_DFLT_HIGH) |
| 65 | GPSR(gpio) = GPIO_bit(gpio); |
| 66 | if (gpio_mode & GPIO_MD_MASK_DIR) |
| 67 | GPDR(gpio) |= GPIO_bit(gpio); |
| 68 | else |
| 69 | GPDR(gpio) &= ~GPIO_bit(gpio); |
| 70 | gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); |
| 71 | GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); |
| 72 | local_irq_restore(flags); |
| 73 | |
| 74 | return 0; |
| 75 | } |
| 76 | EXPORT_SYMBOL(pxa_gpio_mode); |
| 77 | |
| 78 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 79 | { |
| 80 | unsigned long flags; |
| 81 | u32 mask = 1 << offset; |
| 82 | u32 value; |
| 83 | struct pxa_gpio_chip *pxa; |
| 84 | void __iomem *gpdr; |
| 85 | |
| 86 | pxa = container_of(chip, struct pxa_gpio_chip, chip); |
| 87 | gpdr = pxa->regbase + GPDR_OFFSET; |
| 88 | local_irq_save(flags); |
| 89 | value = __raw_readl(gpdr); |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame^] | 90 | if (__gpio_is_inverted(chip->base + offset)) |
| 91 | value |= mask; |
| 92 | else |
| 93 | value &= ~mask; |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 94 | __raw_writel(value, gpdr); |
| 95 | local_irq_restore(flags); |
| 96 | |
| 97 | return 0; |
| 98 | } |
| 99 | |
| 100 | static int pxa_gpio_direction_output(struct gpio_chip *chip, |
| 101 | unsigned offset, int value) |
| 102 | { |
| 103 | unsigned long flags; |
| 104 | u32 mask = 1 << offset; |
| 105 | u32 tmp; |
| 106 | struct pxa_gpio_chip *pxa; |
| 107 | void __iomem *gpdr; |
| 108 | |
| 109 | pxa = container_of(chip, struct pxa_gpio_chip, chip); |
| 110 | __raw_writel(mask, |
| 111 | pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET)); |
| 112 | gpdr = pxa->regbase + GPDR_OFFSET; |
| 113 | local_irq_save(flags); |
| 114 | tmp = __raw_readl(gpdr); |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame^] | 115 | if (__gpio_is_inverted(chip->base + offset)) |
| 116 | tmp &= ~mask; |
| 117 | else |
| 118 | tmp |= mask; |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 119 | __raw_writel(tmp, gpdr); |
| 120 | local_irq_restore(flags); |
| 121 | |
| 122 | return 0; |
| 123 | } |
| 124 | |
| 125 | /* |
| 126 | * Return GPIO level |
| 127 | */ |
| 128 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 129 | { |
| 130 | u32 mask = 1 << offset; |
| 131 | struct pxa_gpio_chip *pxa; |
| 132 | |
| 133 | pxa = container_of(chip, struct pxa_gpio_chip, chip); |
| 134 | return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask; |
| 135 | } |
| 136 | |
| 137 | /* |
| 138 | * Set output GPIO level |
| 139 | */ |
| 140 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 141 | { |
| 142 | u32 mask = 1 << offset; |
| 143 | struct pxa_gpio_chip *pxa; |
| 144 | |
| 145 | pxa = container_of(chip, struct pxa_gpio_chip, chip); |
| 146 | |
| 147 | if (value) |
| 148 | __raw_writel(mask, pxa->regbase + GPSR_OFFSET); |
| 149 | else |
| 150 | __raw_writel(mask, pxa->regbase + GPCR_OFFSET); |
| 151 | } |
| 152 | |
eric miao | 0e037bb | 2008-03-03 13:20:20 +0800 | [diff] [blame] | 153 | #define GPIO_CHIP(_n) \ |
| 154 | [_n] = { \ |
| 155 | .regbase = GPIO##_n##_BASE, \ |
| 156 | .chip = { \ |
| 157 | .label = "gpio-" #_n, \ |
| 158 | .direction_input = pxa_gpio_direction_input, \ |
| 159 | .direction_output = pxa_gpio_direction_output, \ |
| 160 | .get = pxa_gpio_get, \ |
| 161 | .set = pxa_gpio_set, \ |
| 162 | .base = (_n) * 32, \ |
| 163 | .ngpio = 32, \ |
| 164 | }, \ |
| 165 | } |
| 166 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 167 | static struct pxa_gpio_chip pxa_gpio_chip[] = { |
eric miao | 0e037bb | 2008-03-03 13:20:20 +0800 | [diff] [blame] | 168 | GPIO_CHIP(0), |
| 169 | GPIO_CHIP(1), |
| 170 | GPIO_CHIP(2), |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 171 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
eric miao | 0e037bb | 2008-03-03 13:20:20 +0800 | [diff] [blame] | 172 | GPIO_CHIP(3), |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 173 | #endif |
| 174 | }; |
| 175 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 176 | /* |
| 177 | * PXA GPIO edge detection for IRQs: |
| 178 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. |
| 179 | * Use this instead of directly setting GRER/GFER. |
| 180 | */ |
| 181 | |
Dmitry Baryshkov | d8a42fc | 2008-04-19 10:42:18 +0100 | [diff] [blame] | 182 | static unsigned long GPIO_IRQ_rising_edge[4]; |
| 183 | static unsigned long GPIO_IRQ_falling_edge[4]; |
| 184 | static unsigned long GPIO_IRQ_mask[4]; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 185 | |
eric miao | 689c04a | 2008-03-04 17:18:38 +0800 | [diff] [blame] | 186 | /* |
| 187 | * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate |
| 188 | * function of a GPIO, and GPDRx cannot be altered once configured. It |
| 189 | * is attributed as "occupied" here (I know this terminology isn't |
| 190 | * accurate, you are welcome to propose a better one :-) |
| 191 | */ |
| 192 | static int __gpio_is_occupied(unsigned gpio) |
| 193 | { |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame^] | 194 | if (cpu_is_pxa27x() || cpu_is_pxa25x()) { |
| 195 | int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3; |
| 196 | int dir = GPDR(gpio) & GPIO_bit(gpio); |
| 197 | |
| 198 | if (__gpio_is_inverted(gpio)) |
| 199 | return af != 1 || dir == 0; |
| 200 | else |
| 201 | return af != 0 || dir != 0; |
| 202 | } |
| 203 | |
| 204 | return 0; |
eric miao | 689c04a | 2008-03-04 17:18:38 +0800 | [diff] [blame] | 205 | } |
| 206 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 207 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) |
| 208 | { |
| 209 | int gpio, idx; |
| 210 | |
| 211 | gpio = IRQ_TO_GPIO(irq); |
| 212 | idx = gpio >> 5; |
| 213 | |
| 214 | if (type == IRQ_TYPE_PROBE) { |
| 215 | /* Don't mess with enabled GPIOs using preconfigured edges or |
| 216 | * GPIOs set to alternate function or to output during probe |
| 217 | */ |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame^] | 218 | if ((GPIO_IRQ_rising_edge[idx] & GPIO_bit(gpio)) || |
| 219 | (GPIO_IRQ_falling_edge[idx] & GPIO_bit(gpio))) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 220 | return 0; |
eric miao | 689c04a | 2008-03-04 17:18:38 +0800 | [diff] [blame] | 221 | |
| 222 | if (__gpio_is_occupied(gpio)) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 223 | return 0; |
eric miao | 689c04a | 2008-03-04 17:18:38 +0800 | [diff] [blame] | 224 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 225 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 226 | } |
| 227 | |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame^] | 228 | if (__gpio_is_inverted(gpio)) |
| 229 | GPDR(gpio) |= GPIO_bit(gpio); |
| 230 | else |
| 231 | GPDR(gpio) &= ~GPIO_bit(gpio); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 232 | |
| 233 | if (type & IRQ_TYPE_EDGE_RISING) |
| 234 | __set_bit(gpio, GPIO_IRQ_rising_edge); |
| 235 | else |
| 236 | __clear_bit(gpio, GPIO_IRQ_rising_edge); |
| 237 | |
| 238 | if (type & IRQ_TYPE_EDGE_FALLING) |
| 239 | __set_bit(gpio, GPIO_IRQ_falling_edge); |
| 240 | else |
| 241 | __clear_bit(gpio, GPIO_IRQ_falling_edge); |
| 242 | |
| 243 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; |
| 244 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; |
| 245 | |
| 246 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, |
| 247 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), |
| 248 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); |
| 249 | return 0; |
| 250 | } |
| 251 | |
| 252 | /* |
| 253 | * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. |
| 254 | */ |
| 255 | |
| 256 | static void pxa_ack_low_gpio(unsigned int irq) |
| 257 | { |
| 258 | GEDR0 = (1 << (irq - IRQ_GPIO0)); |
| 259 | } |
| 260 | |
| 261 | static void pxa_mask_low_gpio(unsigned int irq) |
| 262 | { |
| 263 | ICMR &= ~(1 << (irq - PXA_IRQ(0))); |
| 264 | } |
| 265 | |
| 266 | static void pxa_unmask_low_gpio(unsigned int irq) |
| 267 | { |
| 268 | ICMR |= 1 << (irq - PXA_IRQ(0)); |
| 269 | } |
| 270 | |
| 271 | static struct irq_chip pxa_low_gpio_chip = { |
| 272 | .name = "GPIO-l", |
| 273 | .ack = pxa_ack_low_gpio, |
| 274 | .mask = pxa_mask_low_gpio, |
| 275 | .unmask = pxa_unmask_low_gpio, |
| 276 | .set_type = pxa_gpio_irq_type, |
| 277 | }; |
| 278 | |
| 279 | /* |
| 280 | * Demux handler for GPIO>=2 edge detect interrupts |
| 281 | */ |
| 282 | |
| 283 | #define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE) |
| 284 | |
| 285 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) |
| 286 | { |
| 287 | int loop, bit, n; |
| 288 | unsigned long gedr[4]; |
| 289 | |
| 290 | do { |
| 291 | gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3; |
| 292 | gedr[1] = GEDR1 & GPIO_IRQ_mask[1]; |
| 293 | gedr[2] = GEDR2 & GPIO_IRQ_mask[2]; |
| 294 | gedr[3] = GEDR3 & GPIO_IRQ_mask[3]; |
| 295 | |
| 296 | GEDR0 = gedr[0]; GEDR1 = gedr[1]; |
| 297 | GEDR2 = gedr[2]; GEDR3 = gedr[3]; |
| 298 | |
| 299 | loop = 0; |
| 300 | bit = find_first_bit(gedr, GEDR_BITS); |
| 301 | while (bit < GEDR_BITS) { |
| 302 | loop = 1; |
| 303 | |
| 304 | n = PXA_GPIO_IRQ_BASE + bit; |
Dmitry Baryshkov | d8aa025 | 2008-10-09 13:36:24 +0100 | [diff] [blame] | 305 | generic_handle_irq(n); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 306 | |
| 307 | bit = find_next_bit(gedr, GEDR_BITS, bit + 1); |
| 308 | } |
| 309 | } while (loop); |
| 310 | } |
| 311 | |
| 312 | static void pxa_ack_muxed_gpio(unsigned int irq) |
| 313 | { |
| 314 | int gpio = irq - IRQ_GPIO(2) + 2; |
| 315 | GEDR(gpio) = GPIO_bit(gpio); |
| 316 | } |
| 317 | |
| 318 | static void pxa_mask_muxed_gpio(unsigned int irq) |
| 319 | { |
| 320 | int gpio = irq - IRQ_GPIO(2) + 2; |
| 321 | __clear_bit(gpio, GPIO_IRQ_mask); |
| 322 | GRER(gpio) &= ~GPIO_bit(gpio); |
| 323 | GFER(gpio) &= ~GPIO_bit(gpio); |
| 324 | } |
| 325 | |
| 326 | static void pxa_unmask_muxed_gpio(unsigned int irq) |
| 327 | { |
| 328 | int gpio = irq - IRQ_GPIO(2) + 2; |
| 329 | int idx = gpio >> 5; |
| 330 | __set_bit(gpio, GPIO_IRQ_mask); |
| 331 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; |
| 332 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; |
| 333 | } |
| 334 | |
| 335 | static struct irq_chip pxa_muxed_gpio_chip = { |
| 336 | .name = "GPIO", |
| 337 | .ack = pxa_ack_muxed_gpio, |
| 338 | .mask = pxa_mask_muxed_gpio, |
| 339 | .unmask = pxa_unmask_muxed_gpio, |
| 340 | .set_type = pxa_gpio_irq_type, |
| 341 | }; |
| 342 | |
eric miao | b9e25ac | 2008-03-04 14:19:58 +0800 | [diff] [blame] | 343 | void __init pxa_init_gpio(int gpio_nr, set_wake_t fn) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 344 | { |
eric miao | b9e25ac | 2008-03-04 14:19:58 +0800 | [diff] [blame] | 345 | int irq, i, gpio; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 346 | |
| 347 | pxa_last_gpio = gpio_nr - 1; |
| 348 | |
| 349 | /* clear all GPIO edge detects */ |
| 350 | for (i = 0; i < gpio_nr; i += 32) { |
| 351 | GFER(i) = 0; |
| 352 | GRER(i) = 0; |
| 353 | GEDR(i) = GEDR(i); |
| 354 | } |
| 355 | |
| 356 | /* GPIO 0 and 1 must have their mask bit always set */ |
| 357 | GPIO_IRQ_mask[0] = 3; |
| 358 | |
| 359 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { |
| 360 | set_irq_chip(irq, &pxa_low_gpio_chip); |
| 361 | set_irq_handler(irq, handle_edge_irq); |
| 362 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
| 363 | } |
| 364 | |
| 365 | for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) { |
| 366 | set_irq_chip(irq, &pxa_muxed_gpio_chip); |
| 367 | set_irq_handler(irq, handle_edge_irq); |
| 368 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
| 369 | } |
| 370 | |
| 371 | /* Install handler for GPIO>=2 edge detect interrupts */ |
| 372 | set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); |
| 373 | |
eric miao | b9e25ac | 2008-03-04 14:19:58 +0800 | [diff] [blame] | 374 | pxa_low_gpio_chip.set_wake = fn; |
| 375 | pxa_muxed_gpio_chip.set_wake = fn; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 376 | |
eric miao | b9e25ac | 2008-03-04 14:19:58 +0800 | [diff] [blame] | 377 | /* add a GPIO chip for each register bank. |
| 378 | * the last PXA25x register only contains 21 GPIOs |
| 379 | */ |
| 380 | for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) { |
| 381 | if (gpio + 32 > gpio_nr) |
| 382 | pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio; |
| 383 | gpiochip_add(&pxa_gpio_chip[i].chip); |
| 384 | } |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 385 | } |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 386 | |
| 387 | #ifdef CONFIG_PM |
| 388 | |
| 389 | static unsigned long saved_gplr[4]; |
| 390 | static unsigned long saved_gpdr[4]; |
| 391 | static unsigned long saved_grer[4]; |
| 392 | static unsigned long saved_gfer[4]; |
| 393 | |
| 394 | static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) |
| 395 | { |
| 396 | int i, gpio; |
| 397 | |
| 398 | for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) { |
| 399 | saved_gplr[i] = GPLR(gpio); |
| 400 | saved_gpdr[i] = GPDR(gpio); |
| 401 | saved_grer[i] = GRER(gpio); |
| 402 | saved_gfer[i] = GFER(gpio); |
| 403 | |
| 404 | /* Clear GPIO transition detect bits */ |
| 405 | GEDR(gpio) = GEDR(gpio); |
| 406 | } |
| 407 | return 0; |
| 408 | } |
| 409 | |
| 410 | static int pxa_gpio_resume(struct sys_device *dev) |
| 411 | { |
| 412 | int i, gpio; |
| 413 | |
| 414 | for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) { |
| 415 | /* restore level with set/clear */ |
| 416 | GPSR(gpio) = saved_gplr[i]; |
| 417 | GPCR(gpio) = ~saved_gplr[i]; |
| 418 | |
| 419 | GRER(gpio) = saved_grer[i]; |
| 420 | GFER(gpio) = saved_gfer[i]; |
| 421 | GPDR(gpio) = saved_gpdr[i]; |
| 422 | } |
| 423 | return 0; |
| 424 | } |
| 425 | #else |
| 426 | #define pxa_gpio_suspend NULL |
| 427 | #define pxa_gpio_resume NULL |
| 428 | #endif |
| 429 | |
| 430 | struct sysdev_class pxa_gpio_sysclass = { |
| 431 | .name = "gpio", |
| 432 | .suspend = pxa_gpio_suspend, |
| 433 | .resume = pxa_gpio_resume, |
| 434 | }; |
| 435 | |
| 436 | static int __init pxa_gpio_init(void) |
| 437 | { |
| 438 | return sysdev_class_register(&pxa_gpio_sysclass); |
| 439 | } |
| 440 | |
| 441 | core_initcall(pxa_gpio_init); |