Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #include <linux/seq_file.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 30 | #include "drmP.h" |
| 31 | #include "radeon_drm.h" |
| 32 | #include "radeon_reg.h" |
| 33 | #include "radeon.h" |
| 34 | #include "atom.h" |
| 35 | |
| 36 | int radeon_debugfs_ib_init(struct radeon_device *rdev); |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 37 | int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 38 | |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 39 | u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
| 40 | { |
| 41 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
| 42 | u32 pg_idx, pg_offset; |
| 43 | u32 idx_value = 0; |
| 44 | int new_page; |
| 45 | |
| 46 | pg_idx = (idx * 4) / PAGE_SIZE; |
| 47 | pg_offset = (idx * 4) % PAGE_SIZE; |
| 48 | |
| 49 | if (ibc->kpage_idx[0] == pg_idx) |
| 50 | return ibc->kpage[0][pg_offset/4]; |
| 51 | if (ibc->kpage_idx[1] == pg_idx) |
| 52 | return ibc->kpage[1][pg_offset/4]; |
| 53 | |
| 54 | new_page = radeon_cs_update_pages(p, pg_idx); |
| 55 | if (new_page < 0) { |
| 56 | p->parser_error = new_page; |
| 57 | return 0; |
| 58 | } |
| 59 | |
| 60 | idx_value = ibc->kpage[new_page][pg_offset/4]; |
| 61 | return idx_value; |
| 62 | } |
| 63 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 64 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 65 | { |
| 66 | #if DRM_DEBUG_CODE |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 67 | if (ring->count_dw <= 0) { |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 68 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
| 69 | } |
| 70 | #endif |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 71 | ring->ring[ring->wptr++] = v; |
| 72 | ring->wptr &= ring->ptr_mask; |
| 73 | ring->count_dw--; |
| 74 | ring->ring_free_dw--; |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 75 | } |
| 76 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 77 | /* |
| 78 | * IB. |
| 79 | */ |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 80 | bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib) |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 81 | { |
| 82 | bool done = false; |
| 83 | |
| 84 | /* only free ib which have been emited */ |
| 85 | if (ib->fence && ib->fence->emitted) { |
| 86 | if (radeon_fence_signaled(ib->fence)) { |
| 87 | radeon_fence_unref(&ib->fence); |
| 88 | radeon_sa_bo_free(rdev, &ib->sa_bo); |
| 89 | done = true; |
| 90 | } |
| 91 | } |
| 92 | return done; |
| 93 | } |
| 94 | |
Jerome Glisse | 69e130a | 2011-12-21 12:13:46 -0500 | [diff] [blame] | 95 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
| 96 | struct radeon_ib **ib, unsigned size) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 97 | { |
| 98 | struct radeon_fence *fence; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 99 | unsigned cretry = 0; |
| 100 | int r = 0, i, idx; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 101 | |
| 102 | *ib = NULL; |
Jerome Glisse | 69e130a | 2011-12-21 12:13:46 -0500 | [diff] [blame] | 103 | /* align size on 256 bytes */ |
| 104 | size = ALIGN(size, 256); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 105 | |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 106 | r = radeon_fence_create(rdev, &fence, ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 107 | if (r) { |
Jerome Glisse | 91cb91b | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 108 | dev_err(rdev->dev, "failed to create fence for new IB\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 109 | return r; |
| 110 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 111 | |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 112 | radeon_mutex_lock(&rdev->ib_pool.mutex); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 113 | idx = rdev->ib_pool.head_id; |
| 114 | retry: |
| 115 | if (cretry > 5) { |
| 116 | dev_err(rdev->dev, "failed to get an ib after 5 retry\n"); |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 117 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
Jerome Glisse | 91cb91b | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 118 | radeon_fence_unref(&fence); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 119 | return -ENOMEM; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 120 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 121 | cretry++; |
| 122 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
| 123 | radeon_ib_try_free(rdev, &rdev->ib_pool.ibs[idx]); |
| 124 | if (rdev->ib_pool.ibs[idx].fence == NULL) { |
| 125 | r = radeon_sa_bo_new(rdev, &rdev->ib_pool.sa_manager, |
| 126 | &rdev->ib_pool.ibs[idx].sa_bo, |
Jerome Glisse | 69e130a | 2011-12-21 12:13:46 -0500 | [diff] [blame] | 127 | size, 256); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 128 | if (!r) { |
| 129 | *ib = &rdev->ib_pool.ibs[idx]; |
| 130 | (*ib)->ptr = rdev->ib_pool.sa_manager.cpu_ptr; |
| 131 | (*ib)->ptr += ((*ib)->sa_bo.offset >> 2); |
| 132 | (*ib)->gpu_addr = rdev->ib_pool.sa_manager.gpu_addr; |
| 133 | (*ib)->gpu_addr += (*ib)->sa_bo.offset; |
| 134 | (*ib)->fence = fence; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 135 | (*ib)->vm_id = 0; |
Alex Deucher | dfcf5f3 | 2012-03-20 17:18:14 -0400 | [diff] [blame] | 136 | (*ib)->is_const_ib = false; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 137 | /* ib are most likely to be allocated in a ring fashion |
| 138 | * thus rdev->ib_pool.head_id should be the id of the |
| 139 | * oldest ib |
| 140 | */ |
| 141 | rdev->ib_pool.head_id = (1 + idx); |
| 142 | rdev->ib_pool.head_id &= (RADEON_IB_POOL_SIZE - 1); |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 143 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 144 | return 0; |
| 145 | } |
Jerome Glisse | 91cb91b | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 146 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 147 | idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 148 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 149 | /* this should be rare event, ie all ib scheduled none signaled yet. |
| 150 | */ |
| 151 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
Jerome Glisse | c1341e5 | 2011-12-21 12:13:47 -0500 | [diff] [blame] | 152 | if (rdev->ib_pool.ibs[idx].fence && rdev->ib_pool.ibs[idx].fence->emitted) { |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 153 | r = radeon_fence_wait(rdev->ib_pool.ibs[idx].fence, false); |
| 154 | if (!r) { |
| 155 | goto retry; |
| 156 | } |
| 157 | /* an error happened */ |
| 158 | break; |
| 159 | } |
| 160 | idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1); |
| 161 | } |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 162 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 163 | radeon_fence_unref(&fence); |
| 164 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 165 | } |
| 166 | |
| 167 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) |
| 168 | { |
| 169 | struct radeon_ib *tmp = *ib; |
| 170 | |
| 171 | *ib = NULL; |
| 172 | if (tmp == NULL) { |
| 173 | return; |
| 174 | } |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 175 | radeon_mutex_lock(&rdev->ib_pool.mutex); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 176 | if (tmp->fence && !tmp->fence->emitted) { |
| 177 | radeon_sa_bo_free(rdev, &tmp->sa_bo); |
| 178 | radeon_fence_unref(&tmp->fence); |
| 179 | } |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 180 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 181 | } |
| 182 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 183 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) |
| 184 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 185 | struct radeon_ring *ring = &rdev->ring[ib->fence->ring]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 186 | int r = 0; |
| 187 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 188 | if (!ib->length_dw || !ring->ready) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 189 | /* TODO: Nothings in the ib we should report. */ |
Jerome Glisse | 91cb91b | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 190 | DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 191 | return -EINVAL; |
| 192 | } |
Dave Airlie | ecb114a | 2009-09-15 11:12:56 +1000 | [diff] [blame] | 193 | |
Dave Airlie | 6cdf658 | 2009-06-29 18:29:13 +1000 | [diff] [blame] | 194 | /* 64 dwords should be enough for fence too */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 195 | r = radeon_ring_lock(rdev, ring, 64); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 196 | if (r) { |
Paul Bolle | ec4f2ac | 2011-01-28 23:32:04 +0100 | [diff] [blame] | 197 | DRM_ERROR("radeon: scheduling IB failed (%d).\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 198 | return r; |
| 199 | } |
Christian König | 4c87bc2 | 2011-10-19 19:02:21 +0200 | [diff] [blame] | 200 | radeon_ring_ib_execute(rdev, ib->fence->ring, ib); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 201 | radeon_fence_emit(rdev, ib->fence); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 202 | radeon_ring_unlock_commit(rdev, ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 203 | return 0; |
| 204 | } |
| 205 | |
| 206 | int radeon_ib_pool_init(struct radeon_device *rdev) |
| 207 | { |
Jerome Glisse | d54fbd4 | 2012-01-24 12:08:52 -0500 | [diff] [blame] | 208 | struct radeon_sa_manager tmp; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 209 | int i, r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 210 | |
Jerome Glisse | d54fbd4 | 2012-01-24 12:08:52 -0500 | [diff] [blame] | 211 | r = radeon_sa_bo_manager_init(rdev, &tmp, |
| 212 | RADEON_IB_POOL_SIZE*64*1024, |
| 213 | RADEON_GEM_DOMAIN_GTT); |
| 214 | if (r) { |
| 215 | return r; |
| 216 | } |
| 217 | |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 218 | radeon_mutex_lock(&rdev->ib_pool.mutex); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 219 | if (rdev->ib_pool.ready) { |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 220 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
Jerome Glisse | d54fbd4 | 2012-01-24 12:08:52 -0500 | [diff] [blame] | 221 | radeon_sa_bo_manager_fini(rdev, &tmp); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 222 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 223 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 224 | |
Jerome Glisse | d54fbd4 | 2012-01-24 12:08:52 -0500 | [diff] [blame] | 225 | rdev->ib_pool.sa_manager = tmp; |
| 226 | INIT_LIST_HEAD(&rdev->ib_pool.sa_manager.sa_bo); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 227 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
| 228 | rdev->ib_pool.ibs[i].fence = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 229 | rdev->ib_pool.ibs[i].idx = i; |
| 230 | rdev->ib_pool.ibs[i].length_dw = 0; |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 231 | INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].sa_bo.list); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 232 | } |
Jerome Glisse | 91cb91b | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 233 | rdev->ib_pool.head_id = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 234 | rdev->ib_pool.ready = true; |
| 235 | DRM_INFO("radeon: ib pool ready.\n"); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 236 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 237 | if (radeon_debugfs_ib_init(rdev)) { |
| 238 | DRM_ERROR("Failed to register debugfs file for IB !\n"); |
| 239 | } |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 240 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 241 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 242 | } |
| 243 | |
| 244 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
| 245 | { |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 246 | unsigned i; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 247 | |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 248 | radeon_mutex_lock(&rdev->ib_pool.mutex); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 249 | if (rdev->ib_pool.ready) { |
| 250 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
| 251 | radeon_sa_bo_free(rdev, &rdev->ib_pool.ibs[i].sa_bo); |
| 252 | radeon_fence_unref(&rdev->ib_pool.ibs[i].fence); |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 253 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 254 | radeon_sa_bo_manager_fini(rdev, &rdev->ib_pool.sa_manager); |
| 255 | rdev->ib_pool.ready = false; |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 256 | } |
Jerome Glisse | 9fc04b5 | 2012-01-23 11:52:15 -0500 | [diff] [blame] | 257 | radeon_mutex_unlock(&rdev->ib_pool.mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 258 | } |
| 259 | |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 260 | int radeon_ib_pool_start(struct radeon_device *rdev) |
| 261 | { |
| 262 | return radeon_sa_bo_manager_start(rdev, &rdev->ib_pool.sa_manager); |
| 263 | } |
| 264 | |
| 265 | int radeon_ib_pool_suspend(struct radeon_device *rdev) |
| 266 | { |
| 267 | return radeon_sa_bo_manager_suspend(rdev, &rdev->ib_pool.sa_manager); |
| 268 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 269 | |
Christian König | 7bd560e | 2012-05-02 15:11:12 +0200 | [diff] [blame] | 270 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
| 271 | { |
| 272 | unsigned i; |
| 273 | int r; |
| 274 | |
| 275 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 276 | struct radeon_ring *ring = &rdev->ring[i]; |
| 277 | |
| 278 | if (!ring->ready) |
| 279 | continue; |
| 280 | |
| 281 | r = radeon_ib_test(rdev, i, ring); |
| 282 | if (r) { |
| 283 | ring->ready = false; |
| 284 | |
| 285 | if (i == RADEON_RING_TYPE_GFX_INDEX) { |
| 286 | /* oh, oh, that's really bad */ |
| 287 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); |
| 288 | rdev->accel_working = false; |
| 289 | return r; |
| 290 | |
| 291 | } else { |
| 292 | /* still not good, but we can live with it */ |
| 293 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); |
| 294 | } |
| 295 | } |
| 296 | } |
| 297 | return 0; |
| 298 | } |
| 299 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 300 | /* |
| 301 | * Ring. |
| 302 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 303 | int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *ring) |
Christian König | bf85279 | 2011-10-13 13:19:22 +0200 | [diff] [blame] | 304 | { |
| 305 | /* r1xx-r5xx only has CP ring */ |
| 306 | if (rdev->family < CHIP_R600) |
| 307 | return RADEON_RING_TYPE_GFX_INDEX; |
| 308 | |
| 309 | if (rdev->family >= CHIP_CAYMAN) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 310 | if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]) |
Christian König | bf85279 | 2011-10-13 13:19:22 +0200 | [diff] [blame] | 311 | return CAYMAN_RING_TYPE_CP1_INDEX; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 312 | else if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]) |
Christian König | bf85279 | 2011-10-13 13:19:22 +0200 | [diff] [blame] | 313 | return CAYMAN_RING_TYPE_CP2_INDEX; |
| 314 | } |
| 315 | return RADEON_RING_TYPE_GFX_INDEX; |
| 316 | } |
| 317 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 318 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 319 | { |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 320 | u32 rptr; |
| 321 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 322 | if (rdev->wb.enabled) |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 323 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); |
Christian König | 5596a9d | 2011-10-13 12:48:45 +0200 | [diff] [blame] | 324 | else |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 325 | rptr = RREG32(ring->rptr_reg); |
| 326 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 327 | /* This works because ring_size is a power of 2 */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 328 | ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); |
| 329 | ring->ring_free_dw -= ring->wptr; |
| 330 | ring->ring_free_dw &= ring->ptr_mask; |
| 331 | if (!ring->ring_free_dw) { |
| 332 | ring->ring_free_dw = ring->ring_size / 4; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 333 | } |
| 334 | } |
| 335 | |
Christian König | 7b1f248 | 2011-09-23 15:11:23 +0200 | [diff] [blame] | 336 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 337 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 338 | { |
| 339 | int r; |
| 340 | |
| 341 | /* Align requested size with padding so unlock_commit can |
| 342 | * pad safely */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 343 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
| 344 | while (ndw > (ring->ring_free_dw - 1)) { |
| 345 | radeon_ring_free_size(rdev, ring); |
| 346 | if (ndw < ring->ring_free_dw) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 347 | break; |
| 348 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 349 | r = radeon_fence_wait_next(rdev, radeon_ring_index(rdev, ring)); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 350 | if (r) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 351 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 352 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 353 | ring->count_dw = ndw; |
| 354 | ring->wptr_old = ring->wptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 355 | return 0; |
| 356 | } |
| 357 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 358 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 359 | { |
| 360 | int r; |
| 361 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 362 | mutex_lock(&ring->mutex); |
| 363 | r = radeon_ring_alloc(rdev, ring, ndw); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 364 | if (r) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 365 | mutex_unlock(&ring->mutex); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 366 | return r; |
| 367 | } |
| 368 | return 0; |
| 369 | } |
| 370 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 371 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 372 | { |
| 373 | unsigned count_dw_pad; |
| 374 | unsigned i; |
| 375 | |
| 376 | /* We pad to match fetch size */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 377 | count_dw_pad = (ring->align_mask + 1) - |
| 378 | (ring->wptr & ring->align_mask); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 379 | for (i = 0; i < count_dw_pad; i++) { |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 380 | radeon_ring_write(ring, ring->nop); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 381 | } |
| 382 | DRM_MEMORYBARRIER(); |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 383 | WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 384 | (void)RREG32(ring->wptr_reg); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 385 | } |
| 386 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 387 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 388 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 389 | radeon_ring_commit(rdev, ring); |
| 390 | mutex_unlock(&ring->mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 391 | } |
| 392 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 393 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 394 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 395 | ring->wptr = ring->wptr_old; |
| 396 | mutex_unlock(&ring->mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 397 | } |
| 398 | |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame^] | 399 | void radeon_ring_lockup_update(struct radeon_ring *ring) |
| 400 | { |
| 401 | ring->last_rptr = ring->rptr; |
| 402 | ring->last_activity = jiffies; |
| 403 | } |
| 404 | |
| 405 | /** |
| 406 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information |
| 407 | * @rdev: radeon device structure |
| 408 | * @ring: radeon_ring structure holding ring information |
| 409 | * |
| 410 | * We don't need to initialize the lockup tracking information as we will either |
| 411 | * have CP rptr to a different value of jiffies wrap around which will force |
| 412 | * initialization of the lockup tracking informations. |
| 413 | * |
| 414 | * A possible false positivie is if we get call after while and last_cp_rptr == |
| 415 | * the current CP rptr, even if it's unlikely it might happen. To avoid this |
| 416 | * if the elapsed time since last call is bigger than 2 second than we return |
| 417 | * false and update the tracking information. Due to this the caller must call |
| 418 | * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported |
| 419 | * the fencing code should be cautious about that. |
| 420 | * |
| 421 | * Caller should write to the ring to force CP to do something so we don't get |
| 422 | * false positive when CP is just gived nothing to do. |
| 423 | * |
| 424 | **/ |
| 425 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
| 426 | { |
| 427 | unsigned long cjiffies, elapsed; |
| 428 | uint32_t rptr; |
| 429 | |
| 430 | cjiffies = jiffies; |
| 431 | if (!time_after(cjiffies, ring->last_activity)) { |
| 432 | /* likely a wrap around */ |
| 433 | radeon_ring_lockup_update(ring); |
| 434 | return false; |
| 435 | } |
| 436 | rptr = RREG32(ring->rptr_reg); |
| 437 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; |
| 438 | if (ring->rptr != ring->last_rptr) { |
| 439 | /* CP is still working no lockup */ |
| 440 | radeon_ring_lockup_update(ring); |
| 441 | return false; |
| 442 | } |
| 443 | elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); |
| 444 | if (elapsed >= 10000) { |
| 445 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
| 446 | return true; |
| 447 | } |
| 448 | /* give a chance to the GPU ... */ |
| 449 | return false; |
| 450 | } |
| 451 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 452 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 453 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
| 454 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 455 | { |
| 456 | int r; |
| 457 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 458 | ring->ring_size = ring_size; |
| 459 | ring->rptr_offs = rptr_offs; |
| 460 | ring->rptr_reg = rptr_reg; |
| 461 | ring->wptr_reg = wptr_reg; |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 462 | ring->ptr_reg_shift = ptr_reg_shift; |
| 463 | ring->ptr_reg_mask = ptr_reg_mask; |
| 464 | ring->nop = nop; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 465 | /* Allocate ring buffer */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 466 | if (ring->ring_obj == NULL) { |
| 467 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 468 | RADEON_GEM_DOMAIN_GTT, |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 469 | &ring->ring_obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 470 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 471 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 472 | return r; |
| 473 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 474 | r = radeon_bo_reserve(ring->ring_obj, false); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 475 | if (unlikely(r != 0)) |
| 476 | return r; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 477 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
| 478 | &ring->gpu_addr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 479 | if (r) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 480 | radeon_bo_unreserve(ring->ring_obj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 481 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 482 | return r; |
| 483 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 484 | r = radeon_bo_kmap(ring->ring_obj, |
| 485 | (void **)&ring->ring); |
| 486 | radeon_bo_unreserve(ring->ring_obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 487 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 488 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 489 | return r; |
| 490 | } |
| 491 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 492 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
| 493 | ring->ring_free_dw = ring->ring_size / 4; |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 494 | if (radeon_debugfs_ring_init(rdev, ring)) { |
| 495 | DRM_ERROR("Failed to register debugfs file for rings !\n"); |
| 496 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 497 | return 0; |
| 498 | } |
| 499 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 500 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 501 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 502 | int r; |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 503 | struct radeon_bo *ring_obj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 504 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 505 | mutex_lock(&ring->mutex); |
| 506 | ring_obj = ring->ring_obj; |
| 507 | ring->ring = NULL; |
| 508 | ring->ring_obj = NULL; |
| 509 | mutex_unlock(&ring->mutex); |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 510 | |
| 511 | if (ring_obj) { |
| 512 | r = radeon_bo_reserve(ring_obj, false); |
| 513 | if (likely(r == 0)) { |
| 514 | radeon_bo_kunmap(ring_obj); |
| 515 | radeon_bo_unpin(ring_obj); |
| 516 | radeon_bo_unreserve(ring_obj); |
| 517 | } |
| 518 | radeon_bo_unref(&ring_obj); |
| 519 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 520 | } |
| 521 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 522 | /* |
| 523 | * Debugfs info |
| 524 | */ |
| 525 | #if defined(CONFIG_DEBUG_FS) |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 526 | |
| 527 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) |
| 528 | { |
| 529 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 530 | struct drm_device *dev = node->minor->dev; |
| 531 | struct radeon_device *rdev = dev->dev_private; |
| 532 | int ridx = *(int*)node->info_ent->data; |
| 533 | struct radeon_ring *ring = &rdev->ring[ridx]; |
| 534 | unsigned count, i, j; |
| 535 | |
| 536 | radeon_ring_free_size(rdev, ring); |
| 537 | count = (ring->ring_size / 4) - ring->ring_free_dw; |
| 538 | seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg)); |
| 539 | seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg)); |
| 540 | seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr); |
| 541 | seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr); |
| 542 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
| 543 | seq_printf(m, "%u dwords in ring\n", count); |
| 544 | i = ring->rptr; |
| 545 | for (j = 0; j <= count; j++) { |
| 546 | seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); |
| 547 | i = (i + 1) & ring->ptr_mask; |
| 548 | } |
| 549 | return 0; |
| 550 | } |
| 551 | |
| 552 | static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX; |
| 553 | static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; |
| 554 | static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; |
| 555 | |
| 556 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { |
| 557 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index}, |
| 558 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index}, |
| 559 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index}, |
| 560 | }; |
| 561 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 562 | static int radeon_debugfs_ib_info(struct seq_file *m, void *data) |
| 563 | { |
| 564 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
Christian König | 293f9fd | 2012-02-23 15:18:45 +0100 | [diff] [blame] | 565 | struct drm_device *dev = node->minor->dev; |
| 566 | struct radeon_device *rdev = dev->dev_private; |
| 567 | struct radeon_ib *ib = &rdev->ib_pool.ibs[*((unsigned*)node->info_ent->data)]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 568 | unsigned i; |
| 569 | |
| 570 | if (ib == NULL) { |
| 571 | return 0; |
| 572 | } |
Jerome Glisse | 91cb91b | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 573 | seq_printf(m, "IB %04u\n", ib->idx); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 574 | seq_printf(m, "IB fence %p\n", ib->fence); |
| 575 | seq_printf(m, "IB size %05u dwords\n", ib->length_dw); |
| 576 | for (i = 0; i < ib->length_dw; i++) { |
| 577 | seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]); |
| 578 | } |
| 579 | return 0; |
| 580 | } |
| 581 | |
| 582 | static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE]; |
| 583 | static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32]; |
Christian König | 293f9fd | 2012-02-23 15:18:45 +0100 | [diff] [blame] | 584 | static unsigned radeon_debugfs_ib_idx[RADEON_IB_POOL_SIZE]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 585 | #endif |
| 586 | |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 587 | int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 588 | { |
| 589 | #if defined(CONFIG_DEBUG_FS) |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 590 | unsigned i; |
| 591 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { |
| 592 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; |
| 593 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; |
| 594 | unsigned r; |
| 595 | |
| 596 | if (&rdev->ring[ridx] != ring) |
| 597 | continue; |
| 598 | |
| 599 | r = radeon_debugfs_add_files(rdev, info, 1); |
| 600 | if (r) |
| 601 | return r; |
| 602 | } |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 603 | #endif |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 604 | return 0; |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 605 | } |
| 606 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 607 | int radeon_debugfs_ib_init(struct radeon_device *rdev) |
| 608 | { |
| 609 | #if defined(CONFIG_DEBUG_FS) |
| 610 | unsigned i; |
| 611 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 612 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
| 613 | sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i); |
Christian König | 293f9fd | 2012-02-23 15:18:45 +0100 | [diff] [blame] | 614 | radeon_debugfs_ib_idx[i] = i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 615 | radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i]; |
| 616 | radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info; |
| 617 | radeon_debugfs_ib_list[i].driver_features = 0; |
Christian König | 293f9fd | 2012-02-23 15:18:45 +0100 | [diff] [blame] | 618 | radeon_debugfs_ib_list[i].data = &radeon_debugfs_ib_idx[i]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 619 | } |
| 620 | return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list, |
| 621 | RADEON_IB_POOL_SIZE); |
| 622 | #else |
| 623 | return 0; |
| 624 | #endif |
| 625 | } |