blob: 1843725785c90f1f2518bade455af7dead4c6ec8 [file] [log] [blame]
Stephen Warrenc80efba2012-04-20 16:57:38 -06001/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05303#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -06004#include "tegra20.dtsi"
Stephen Warrenc80efba2012-04-20 16:57:38 -06005
6/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +00007 model = "NVIDIA Tegra20 Whistler evaluation board";
Stephen Warrenc80efba2012-04-20 16:57:38 -06008 compatible = "nvidia,whistler", "nvidia,tegra20";
9
Stephen Warren553c0a22013-12-09 14:43:59 -070010 aliases {
11 rtc0 = "/i2c@7000d000/max8907@3c";
12 rtc1 = "/rtc@7000e000";
13 };
14
Stephen Warrenc80efba2012-04-20 16:57:38 -060015 memory {
16 reg = <0x00000000 0x20000000>;
17 };
18
Stephen Warren58ecb232013-11-25 17:53:16 -070019 host1x@50000000 {
20 hdmi@54280000 {
Stephen Warren2658ef12012-11-16 10:53:04 -070021 status = "okay";
22
23 vdd-supply = <&hdmi_vdd_reg>;
24 pll-supply = <&hdmi_pll_reg>;
25
26 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070027 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
28 GPIO_ACTIVE_HIGH>;
Stephen Warren2658ef12012-11-16 10:53:04 -070029 };
30 };
31
Stephen Warren58ecb232013-11-25 17:53:16 -070032 pinmux@70000014 {
Stephen Warrenc80efba2012-04-20 16:57:38 -060033 pinctrl-names = "default";
34 pinctrl-0 = <&state_default>;
35
36 state_default: pinmux {
37 ata {
38 nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
39 "gmc", "gmd", "gpu";
40 nvidia,function = "gmi";
41 };
42 atc {
43 nvidia,pins = "atc", "atd";
44 nvidia,function = "sdio4";
45 };
46 cdev1 {
47 nvidia,pins = "cdev1";
48 nvidia,function = "plla_out";
49 };
50 cdev2 {
51 nvidia,pins = "cdev2";
52 nvidia,function = "osc";
53 };
54 crtp {
55 nvidia,pins = "crtp";
56 nvidia,function = "crt";
57 };
58 csus {
59 nvidia,pins = "csus";
60 nvidia,function = "vi_sensor_clk";
61 };
62 dap1 {
63 nvidia,pins = "dap1";
64 nvidia,function = "dap1";
65 };
66 dap2 {
67 nvidia,pins = "dap2";
68 nvidia,function = "dap2";
69 };
70 dap3 {
71 nvidia,pins = "dap3";
72 nvidia,function = "dap3";
73 };
74 dap4 {
75 nvidia,pins = "dap4";
76 nvidia,function = "dap4";
77 };
78 ddc {
79 nvidia,pins = "ddc";
80 nvidia,function = "i2c2";
81 };
82 dta {
83 nvidia,pins = "dta", "dtb", "dtc", "dtd";
84 nvidia,function = "vi";
85 };
86 dte {
87 nvidia,pins = "dte";
88 nvidia,function = "rsvd1";
89 };
90 dtf {
91 nvidia,pins = "dtf";
92 nvidia,function = "i2c3";
93 };
94 gme {
95 nvidia,pins = "gme";
96 nvidia,function = "dap5";
97 };
98 gpu7 {
99 nvidia,pins = "gpu7";
100 nvidia,function = "rtck";
101 };
102 gpv {
103 nvidia,pins = "gpv";
104 nvidia,function = "pcie";
105 };
106 hdint {
107 nvidia,pins = "hdint", "pta";
108 nvidia,function = "hdmi";
109 };
110 i2cp {
111 nvidia,pins = "i2cp";
112 nvidia,function = "i2cp";
113 };
114 irrx {
115 nvidia,pins = "irrx", "irtx";
116 nvidia,function = "uartb";
117 };
118 kbca {
119 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
120 nvidia,function = "kbc";
121 };
122 kbcb {
123 nvidia,pins = "kbcb", "kbcd";
124 nvidia,function = "sdio2";
125 };
126 lcsn {
127 nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
128 "spia", "spib", "spic";
129 nvidia,function = "spi3";
130 };
131 ld0 {
132 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
133 "ld5", "ld6", "ld7", "ld8", "ld9",
134 "ld10", "ld11", "ld12", "ld13", "ld14",
135 "ld15", "ld16", "ld17", "ldc", "ldi",
136 "lhp0", "lhp1", "lhp2", "lhs", "lm0",
137 "lm1", "lpp", "lpw0", "lpw1", "lpw2",
138 "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
139 "lvs";
140 nvidia,function = "displaya";
141 };
142 owc {
143 nvidia,pins = "owc", "uac";
144 nvidia,function = "owr";
145 };
146 pmc {
147 nvidia,pins = "pmc";
148 nvidia,function = "pwr_on";
149 };
150 rm {
151 nvidia,pins = "rm";
152 nvidia,function = "i2c1";
153 };
154 sdb {
155 nvidia,pins = "sdb", "sdc", "sdd", "slxa",
156 "slxc", "slxd", "slxk";
157 nvidia,function = "sdio3";
158 };
159 sdio1 {
160 nvidia,pins = "sdio1";
161 nvidia,function = "sdio1";
162 };
163 spdi {
164 nvidia,pins = "spdi", "spdo";
165 nvidia,function = "rsvd2";
166 };
167 spid {
168 nvidia,pins = "spid", "spie", "spig", "spih";
169 nvidia,function = "spi2_alt";
170 };
171 spif {
172 nvidia,pins = "spif";
173 nvidia,function = "spi2";
174 };
175 uaa {
176 nvidia,pins = "uaa", "uab";
177 nvidia,function = "uarta";
178 };
179 uad {
180 nvidia,pins = "uad";
181 nvidia,function = "irda";
182 };
183 uca {
184 nvidia,pins = "uca", "ucb";
185 nvidia,function = "uartc";
186 };
187 uda {
188 nvidia,pins = "uda";
189 nvidia,function = "spi1";
190 };
191 conf_ata {
192 nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
193 "gmb", "gmc", "gmd", "irrx", "irtx",
194 "kbca", "kbcb", "kbcc", "kbcd", "kbce",
195 "kbcf", "sdc", "sdd", "spie", "spig",
196 "spih", "uaa", "uab", "uad", "uca",
197 "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530198 nvidia,pull = <TEGRA_PIN_PULL_UP>;
199 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600200 };
201 conf_atd {
202 nvidia,pins = "atd", "ate", "cdev1", "csus",
203 "dap1", "dap2", "dap3", "dap4", "dte",
204 "dtf", "gpu", "gpu7", "gpv", "i2cp",
205 "rm", "sdio1", "slxa", "slxc", "slxd",
206 "slxk", "spdi", "spdo", "uac", "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530207 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
208 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600209 };
210 conf_cdev2 {
211 nvidia,pins = "cdev2", "spia", "spib";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530212 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
213 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600214 };
215 conf_ck32 {
216 nvidia,pins = "ck32", "ddrc", "lc", "pmca",
217 "pmcb", "pmcc", "pmcd", "xm2c",
218 "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530219 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600220 };
221 conf_crtp {
222 nvidia,pins = "crtp";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530223 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
224 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600225 };
226 conf_dta {
227 nvidia,pins = "dta", "dtb", "dtc", "dtd",
228 "spid", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530229 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
230 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600231 };
232 conf_gme {
233 nvidia,pins = "gme", "owc", "pta", "spic";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530234 nvidia,pull = <TEGRA_PIN_PULL_UP>;
235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600236 };
237 conf_ld17_0 {
238 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
239 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530240 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600241 };
242 conf_ls {
243 nvidia,pins = "ls", "pmce";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530244 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600245 };
246 drive_dap1 {
247 nvidia,pins = "drive_dap1";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530248 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
249 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
250 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_8>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600251 nvidia,pull-down-strength = <0>;
252 nvidia,pull-up-strength = <0>;
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530253 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
254 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600255 };
256 };
257 };
258
259 i2s@70002800 {
260 status = "okay";
261 };
262
263 serial@70006000 {
264 status = "okay";
Stephen Warrenc80efba2012-04-20 16:57:38 -0600265 };
266
Stephen Warren2658ef12012-11-16 10:53:04 -0700267 hdmi_ddc: i2c@7000c400 {
268 status = "okay";
269 clock-frequency = <100000>;
270 };
271
Stephen Warrenc80efba2012-04-20 16:57:38 -0600272 i2c@7000d000 {
273 status = "okay";
274 clock-frequency = <100000>;
275
276 codec: codec@1a {
277 compatible = "wlf,wm8753";
278 reg = <0x1a>;
279 };
280
281 tca6416: gpio@20 {
282 compatible = "ti,tca6416";
283 reg = <0x20>;
284 gpio-controller;
285 #gpio-cells = <2>;
286 };
Stephen Warrene7765b32012-06-25 16:41:25 -0600287
288 max8907@3c {
289 compatible = "maxim,max8907";
290 reg = <0x3c>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700291 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warrene7765b32012-06-25 16:41:25 -0600292
Stephen Warrenb37ed4a2012-09-11 13:13:05 -0600293 maxim,system-power-controller;
294
Stephen Warrene7765b32012-06-25 16:41:25 -0600295 mbatt-supply = <&usb0_vbus_reg>;
296 in-v1-supply = <&mbatt_reg>;
297 in-v2-supply = <&mbatt_reg>;
298 in-v3-supply = <&mbatt_reg>;
299 in1-supply = <&mbatt_reg>;
300 in2-supply = <&nvvdd_sv3_reg>;
301 in3-supply = <&mbatt_reg>;
302 in4-supply = <&mbatt_reg>;
303 in5-supply = <&mbatt_reg>;
304 in6-supply = <&mbatt_reg>;
305 in7-supply = <&mbatt_reg>;
306 in8-supply = <&mbatt_reg>;
307 in9-supply = <&mbatt_reg>;
308 in10-supply = <&mbatt_reg>;
309 in11-supply = <&mbatt_reg>;
310 in12-supply = <&mbatt_reg>;
311 in13-supply = <&mbatt_reg>;
312 in14-supply = <&mbatt_reg>;
313 in15-supply = <&mbatt_reg>;
314 in16-supply = <&mbatt_reg>;
315 in17-supply = <&nvvdd_sv3_reg>;
316 in18-supply = <&nvvdd_sv3_reg>;
317 in19-supply = <&mbatt_reg>;
318 in20-supply = <&mbatt_reg>;
319
320 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600321 mbatt_reg: mbatt {
Stephen Warrene7765b32012-06-25 16:41:25 -0600322 regulator-name = "vbat_pmu";
323 regulator-always-on;
324 };
325
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600326 sd1 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600327 regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
328 regulator-min-microvolt = <1000000>;
329 regulator-max-microvolt = <1000000>;
330 regulator-always-on;
331 };
332
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600333 sd2 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600334 regulator-name = "nvvdd_sv2,vdd_core";
335 regulator-min-microvolt = <1200000>;
336 regulator-max-microvolt = <1200000>;
337 regulator-always-on;
338 };
339
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600340 nvvdd_sv3_reg: sd3 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600341 regulator-name = "nvvdd_sv3";
342 regulator-min-microvolt = <1800000>;
343 regulator-max-microvolt = <1800000>;
344 regulator-always-on;
345 };
346
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600347 ldo1 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600348 regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
349 regulator-min-microvolt = <3300000>;
350 regulator-max-microvolt = <3300000>;
351 regulator-always-on;
352 };
353
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600354 ldo2 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600355 regulator-name = "nvvdd_ldo2,avdd_pll*";
356 regulator-min-microvolt = <1100000>;
357 regulator-max-microvolt = <1100000>;
358 regulator-always-on;
359 };
360
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600361 ldo3 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600362 regulator-name = "nvvdd_ldo3,vcom_1v8b";
363 regulator-min-microvolt = <1800000>;
364 regulator-max-microvolt = <1800000>;
365 regulator-always-on;
366 };
367
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600368 ldo4 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600369 regulator-name = "nvvdd_ldo4,avdd_usb*";
370 regulator-min-microvolt = <3300000>;
371 regulator-max-microvolt = <3300000>;
372 regulator-always-on;
373 };
374
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600375 ldo5 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600376 regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
377 regulator-min-microvolt = <2800000>;
378 regulator-max-microvolt = <2800000>;
379 regulator-always-on;
380 };
381
Stephen Warren2658ef12012-11-16 10:53:04 -0700382 hdmi_pll_reg: ldo6 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600383 regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
384 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <1800000>;
386 };
387
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600388 ldo7 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600389 regulator-name = "nvvdd_ldo7,avddio_audio";
390 regulator-min-microvolt = <2800000>;
391 regulator-max-microvolt = <2800000>;
392 regulator-always-on;
393 };
394
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600395 ldo8 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600396 regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
397 regulator-min-microvolt = <3000000>;
398 regulator-max-microvolt = <3000000>;
399 };
400
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600401 ldo9 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600402 regulator-name = "nvvdd_ldo9,avdd_cam*";
403 regulator-min-microvolt = <2800000>;
404 regulator-max-microvolt = <2800000>;
405 };
406
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600407 ldo10 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600408 regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
409 regulator-min-microvolt = <3000000>;
410 regulator-max-microvolt = <3000000>;
411 regulator-always-on;
412 };
413
Stephen Warren2658ef12012-11-16 10:53:04 -0700414 hdmi_vdd_reg: ldo11 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600415 regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
416 regulator-min-microvolt = <3300000>;
417 regulator-max-microvolt = <3300000>;
418 };
419
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600420 ldo12 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600421 regulator-name = "nvvdd_ldo12,vddio_sdio";
422 regulator-min-microvolt = <2800000>;
423 regulator-max-microvolt = <2800000>;
424 regulator-always-on;
425 };
426
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600427 ldo13 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600428 regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
429 regulator-min-microvolt = <2800000>;
430 regulator-max-microvolt = <2800000>;
431 };
432
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600433 ldo14 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600434 regulator-name = "nvvdd_ldo14,avdd_vdac";
435 regulator-min-microvolt = <2800000>;
436 regulator-max-microvolt = <2800000>;
437 };
438
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600439 ldo15 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600440 regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
441 regulator-min-microvolt = <3300000>;
442 regulator-max-microvolt = <3300000>;
443 };
444
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600445 ldo16 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600446 regulator-name = "nvvdd_ldo16,vdd_dbrtr";
447 regulator-min-microvolt = <1300000>;
448 regulator-max-microvolt = <1300000>;
449 };
450
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600451 ldo17 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600452 regulator-name = "nvvdd_ldo17,vddio_mipi";
453 regulator-min-microvolt = <1200000>;
454 regulator-max-microvolt = <1200000>;
455 };
456
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600457 ldo18 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600458 regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
459 regulator-min-microvolt = <1800000>;
460 regulator-max-microvolt = <1800000>;
461 };
462
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600463 ldo19 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600464 regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
465 regulator-min-microvolt = <2800000>;
466 regulator-max-microvolt = <2800000>;
467 };
468
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600469 ldo20 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600470 regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
471 regulator-min-microvolt = <1200000>;
472 regulator-max-microvolt = <1200000>;
473 regulator-always-on;
474 };
475
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600476 out5v {
Stephen Warrene7765b32012-06-25 16:41:25 -0600477 regulator-name = "usb0_vbus_reg";
478 };
479
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600480 out33v {
Stephen Warrene7765b32012-06-25 16:41:25 -0600481 regulator-name = "pmu_out3v3";
482 };
483
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600484 bbat {
Stephen Warrene7765b32012-06-25 16:41:25 -0600485 regulator-name = "pmu_bbat";
486 regulator-min-microvolt = <2400000>;
487 regulator-max-microvolt = <2400000>;
488 regulator-always-on;
489 };
490
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600491 sdby {
Stephen Warrene7765b32012-06-25 16:41:25 -0600492 regulator-name = "vdd_aon";
493 regulator-always-on;
494 };
495
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600496 vrtc {
Stephen Warrene7765b32012-06-25 16:41:25 -0600497 regulator-name = "vrtc,pmu_vccadc";
498 regulator-always-on;
499 };
500 };
501 };
502 };
503
Stephen Warren57899052013-11-26 14:43:45 -0700504 kbc@7000e200 {
505 status = "okay";
506 nvidia,debounce-delay-ms = <20>;
507 nvidia,repeat-delay-ms = <160>;
508 nvidia,kbc-row-pins = <0 1 2>;
509 nvidia,kbc-col-pins = <16 17>;
510 nvidia,wakeup-source;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530511 linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER)
512 MATRIX_KEY(0x01, 0x00, KEY_HOME)
513 MATRIX_KEY(0x01, 0x01, KEY_BACK)
514 MATRIX_KEY(0x02, 0x01, KEY_MENU)>;
Stephen Warren57899052013-11-26 14:43:45 -0700515 };
516
Stephen Warren58ecb232013-11-25 17:53:16 -0700517 pmc@7000e400 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600518 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800519 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800520 nvidia,cpu-pwr-good-time = <2000>;
521 nvidia,cpu-pwr-off-time = <1000>;
522 nvidia,core-pwr-good-time = <0 3845>;
523 nvidia,core-pwr-off-time = <93727>;
524 nvidia,core-power-req-active-high;
525 nvidia,sys-clock-req-active-high;
526 nvidia,combined-power-req;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600527 };
528
529 usb@c5000000 {
530 status = "okay";
Stephen Warrenc80efba2012-04-20 16:57:38 -0600531 };
532
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530533 usb-phy@c5000000 {
534 status = "okay";
535 vbus-supply = <&vbus1_reg>;
536 };
537
Stephen Warrenc80efba2012-04-20 16:57:38 -0600538 usb@c5008000 {
539 status = "okay";
Stephen Warrenc80efba2012-04-20 16:57:38 -0600540 };
541
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530542 usb-phy@c5008000 {
543 status = "okay";
544 vbus-supply = <&vbus3_reg>;
545 };
546
Stephen Warrenc80efba2012-04-20 16:57:38 -0600547 sdhci@c8000400 {
548 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700549 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
550 wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600551 bus-width = <8>;
552 };
553
554 sdhci@c8000600 {
555 status = "okay";
556 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600557 non-removable;
Stephen Warrenc80efba2012-04-20 16:57:38 -0600558 };
559
Joseph Lo7021d122013-04-03 19:31:27 +0800560 clocks {
561 compatible = "simple-bus";
562 #address-cells = <1>;
563 #size-cells = <0>;
564
Stephen Warren58ecb232013-11-25 17:53:16 -0700565 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800566 compatible = "fixed-clock";
567 reg=<0>;
568 #clock-cells = <0>;
569 clock-frequency = <32768>;
570 };
571 };
572
Stephen Warrene7765b32012-06-25 16:41:25 -0600573 regulators {
574 compatible = "simple-bus";
575 #address-cells = <1>;
576 #size-cells = <0>;
577
Stephen Warren58ecb232013-11-25 17:53:16 -0700578 usb0_vbus_reg: regulator@0 {
Stephen Warrene7765b32012-06-25 16:41:25 -0600579 compatible = "regulator-fixed";
580 reg = <0>;
581 regulator-name = "usb0_vbus";
582 regulator-min-microvolt = <5000000>;
583 regulator-max-microvolt = <5000000>;
584 regulator-always-on;
585 };
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530586
587 vbus1_reg: regulator@2 {
588 compatible = "regulator-fixed";
589 reg = <2>;
590 regulator-name = "vbus1";
591 regulator-min-microvolt = <5000000>;
592 regulator-max-microvolt = <5000000>;
Stephen Warren9f310de2013-07-01 15:07:05 -0600593 enable-active-high;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530594 gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
Stephen Warren30ca2222013-08-20 14:00:13 -0600595 regulator-always-on;
596 regulator-boot-on;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530597 };
598
599 vbus3_reg: regulator@3 {
600 compatible = "regulator-fixed";
601 reg = <3>;
602 regulator-name = "vbus3";
603 regulator-min-microvolt = <5000000>;
604 regulator-max-microvolt = <5000000>;
Stephen Warren9f310de2013-07-01 15:07:05 -0600605 enable-active-high;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530606 gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
Stephen Warren30ca2222013-08-20 14:00:13 -0600607 regulator-always-on;
608 regulator-boot-on;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530609 };
Stephen Warrene7765b32012-06-25 16:41:25 -0600610 };
611
Stephen Warrenc80efba2012-04-20 16:57:38 -0600612 sound {
613 compatible = "nvidia,tegra-audio-wm8753-whistler",
614 "nvidia,tegra-audio-wm8753";
615 nvidia,model = "NVIDIA Tegra Whistler";
616
617 nvidia,audio-routing =
618 "Headphone Jack", "LOUT1",
619 "Headphone Jack", "ROUT1",
620 "MIC2", "Mic Jack",
621 "MIC2N", "Mic Jack";
622
623 nvidia,i2s-controller = <&tegra_i2s1>;
624 nvidia,audio-codec = <&codec>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600625
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300626 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
627 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
628 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600629 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenc80efba2012-04-20 16:57:38 -0600630 };
631};