blob: 662fcc065821f3100e55e014b2ce1801966e87e8 [file] [log] [blame]
Changhwan Youn30d8bea2011-03-11 10:39:57 +09001/* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/clockchips.h>
19#include <linux/platform_device.h>
20#include <linux/delay.h>
21#include <linux/percpu.h>
Kukjin Kim2edb36c2012-11-15 15:48:56 +090022#include <linux/of.h>
Thomas Abraham36ba5d52013-03-09 16:01:52 +090023#include <linux/of_irq.h>
24#include <linux/of_address.h>
Thomas Abraham9fbf0c82013-03-09 16:10:03 +090025#include <linux/clocksource.h>
Changhwan Youn30d8bea2011-03-11 10:39:57 +090026
Marc Zyngiera8cb6042012-01-10 19:44:19 +000027#include <asm/localtimer.h>
Changhwan Youn30d8bea2011-03-11 10:39:57 +090028#include <asm/mach/time.h>
29
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090030#define EXYNOS4_MCTREG(x) (x)
31#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
32#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
33#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
34#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
35#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
36#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
37#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
38#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
39#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
40#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
41#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
42#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
43#define EXYNOS4_MCT_L_MASK (0xffffff00)
44
45#define MCT_L_TCNTB_OFFSET (0x00)
46#define MCT_L_ICNTB_OFFSET (0x08)
47#define MCT_L_TCON_OFFSET (0x20)
48#define MCT_L_INT_CSTAT_OFFSET (0x30)
49#define MCT_L_INT_ENB_OFFSET (0x34)
50#define MCT_L_WSTAT_OFFSET (0x40)
51#define MCT_G_TCON_START (1 << 8)
52#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
53#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
54#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
55#define MCT_L_TCON_INT_START (1 << 1)
56#define MCT_L_TCON_TIMER_START (1 << 0)
57
Changhwan Youn4d2e4d72012-03-09 15:09:21 -080058#define TICK_BASE_CNT 1
59
Changhwan Youn3a062282011-10-04 17:02:58 +090060enum {
61 MCT_INT_SPI,
62 MCT_INT_PPI
63};
64
Thomas Abrahamc371dc62013-03-09 16:01:50 +090065enum {
66 MCT_G0_IRQ,
67 MCT_G1_IRQ,
68 MCT_G2_IRQ,
69 MCT_G3_IRQ,
70 MCT_L0_IRQ,
71 MCT_L1_IRQ,
72 MCT_L2_IRQ,
73 MCT_L3_IRQ,
74 MCT_NR_IRQS,
75};
76
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090077static void __iomem *reg_base;
Changhwan Youn30d8bea2011-03-11 10:39:57 +090078static unsigned long clk_rate;
Changhwan Youn3a062282011-10-04 17:02:58 +090079static unsigned int mct_int_type;
Thomas Abrahamc371dc62013-03-09 16:01:50 +090080static int mct_irqs[MCT_NR_IRQS];
Changhwan Youn30d8bea2011-03-11 10:39:57 +090081
82struct mct_clock_event_device {
83 struct clock_event_device *evt;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090084 unsigned long base;
Changhwan Younc8987472011-10-04 17:09:26 +090085 char name[10];
Changhwan Youn30d8bea2011-03-11 10:39:57 +090086};
87
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090088static void exynos4_mct_write(unsigned int value, unsigned long offset)
Changhwan Youn30d8bea2011-03-11 10:39:57 +090089{
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090090 unsigned long stat_addr;
Changhwan Youn30d8bea2011-03-11 10:39:57 +090091 u32 mask;
92 u32 i;
93
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090094 __raw_writel(value, reg_base + offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +090095
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090096 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
97 stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
98 switch (offset & EXYNOS4_MCT_L_MASK) {
99 case MCT_L_TCON_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900100 mask = 1 << 3; /* L_TCON write status */
101 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900102 case MCT_L_ICNTB_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900103 mask = 1 << 1; /* L_ICNTB write status */
104 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900105 case MCT_L_TCNTB_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900106 mask = 1 << 0; /* L_TCNTB write status */
107 break;
108 default:
109 return;
110 }
111 } else {
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900112 switch (offset) {
113 case EXYNOS4_MCT_G_TCON:
Changhwan Younc8987472011-10-04 17:09:26 +0900114 stat_addr = EXYNOS4_MCT_G_WSTAT;
115 mask = 1 << 16; /* G_TCON write status */
116 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900117 case EXYNOS4_MCT_G_COMP0_L:
Changhwan Younc8987472011-10-04 17:09:26 +0900118 stat_addr = EXYNOS4_MCT_G_WSTAT;
119 mask = 1 << 0; /* G_COMP0_L write status */
120 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900121 case EXYNOS4_MCT_G_COMP0_U:
Changhwan Younc8987472011-10-04 17:09:26 +0900122 stat_addr = EXYNOS4_MCT_G_WSTAT;
123 mask = 1 << 1; /* G_COMP0_U write status */
124 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900125 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
Changhwan Younc8987472011-10-04 17:09:26 +0900126 stat_addr = EXYNOS4_MCT_G_WSTAT;
127 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
128 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900129 case EXYNOS4_MCT_G_CNT_L:
Changhwan Younc8987472011-10-04 17:09:26 +0900130 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
131 mask = 1 << 0; /* G_CNT_L write status */
132 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900133 case EXYNOS4_MCT_G_CNT_U:
Changhwan Younc8987472011-10-04 17:09:26 +0900134 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
135 mask = 1 << 1; /* G_CNT_U write status */
136 break;
137 default:
138 return;
139 }
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900140 }
141
142 /* Wait maximum 1 ms until written values are applied */
143 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900144 if (__raw_readl(reg_base + stat_addr) & mask) {
145 __raw_writel(mask, reg_base + stat_addr);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900146 return;
147 }
148
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900149 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900150}
151
152/* Clocksource handling */
153static void exynos4_mct_frc_start(u32 hi, u32 lo)
154{
155 u32 reg;
156
157 exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
158 exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
159
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900160 reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900161 reg |= MCT_G_TCON_START;
162 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
163}
164
165static cycle_t exynos4_frc_read(struct clocksource *cs)
166{
167 unsigned int lo, hi;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900168 u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900169
170 do {
171 hi = hi2;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900172 lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
173 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900174 } while (hi != hi2);
175
176 return ((cycle_t)hi << 32) | lo;
177}
178
Changhwan Younaa421c12011-09-02 14:10:52 +0900179static void exynos4_frc_resume(struct clocksource *cs)
180{
181 exynos4_mct_frc_start(0, 0);
182}
183
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900184struct clocksource mct_frc = {
185 .name = "mct-frc",
186 .rating = 400,
187 .read = exynos4_frc_read,
188 .mask = CLOCKSOURCE_MASK(64),
189 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
Changhwan Younaa421c12011-09-02 14:10:52 +0900190 .resume = exynos4_frc_resume,
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900191};
192
193static void __init exynos4_clocksource_init(void)
194{
195 exynos4_mct_frc_start(0, 0);
196
197 if (clocksource_register_hz(&mct_frc, clk_rate))
198 panic("%s: can't register clocksource\n", mct_frc.name);
199}
200
201static void exynos4_mct_comp0_stop(void)
202{
203 unsigned int tcon;
204
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900205 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900206 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
207
208 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
209 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
210}
211
212static void exynos4_mct_comp0_start(enum clock_event_mode mode,
213 unsigned long cycles)
214{
215 unsigned int tcon;
216 cycle_t comp_cycle;
217
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900218 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900219
220 if (mode == CLOCK_EVT_MODE_PERIODIC) {
221 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
222 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
223 }
224
225 comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
226 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
227 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
228
229 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
230
231 tcon |= MCT_G_TCON_COMP0_ENABLE;
232 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
233}
234
235static int exynos4_comp_set_next_event(unsigned long cycles,
236 struct clock_event_device *evt)
237{
238 exynos4_mct_comp0_start(evt->mode, cycles);
239
240 return 0;
241}
242
243static void exynos4_comp_set_mode(enum clock_event_mode mode,
244 struct clock_event_device *evt)
245{
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800246 unsigned long cycles_per_jiffy;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900247 exynos4_mct_comp0_stop();
248
249 switch (mode) {
250 case CLOCK_EVT_MODE_PERIODIC:
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800251 cycles_per_jiffy =
252 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
253 exynos4_mct_comp0_start(mode, cycles_per_jiffy);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900254 break;
255
256 case CLOCK_EVT_MODE_ONESHOT:
257 case CLOCK_EVT_MODE_UNUSED:
258 case CLOCK_EVT_MODE_SHUTDOWN:
259 case CLOCK_EVT_MODE_RESUME:
260 break;
261 }
262}
263
264static struct clock_event_device mct_comp_device = {
265 .name = "mct-comp",
266 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
267 .rating = 250,
268 .set_next_event = exynos4_comp_set_next_event,
269 .set_mode = exynos4_comp_set_mode,
270};
271
272static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
273{
274 struct clock_event_device *evt = dev_id;
275
276 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
277
278 evt->event_handler(evt);
279
280 return IRQ_HANDLED;
281}
282
283static struct irqaction mct_comp_event_irq = {
284 .name = "mct_comp_irq",
285 .flags = IRQF_TIMER | IRQF_IRQPOLL,
286 .handler = exynos4_mct_comp_isr,
287 .dev_id = &mct_comp_device,
288};
289
290static void exynos4_clockevent_init(void)
291{
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900292 mct_comp_device.cpumask = cpumask_of(0);
Shawn Guo838a2ae2013-01-12 11:50:05 +0000293 clockevents_config_and_register(&mct_comp_device, clk_rate,
294 0xf, 0xffffffff);
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900295 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900296}
297
298#ifdef CONFIG_LOCAL_TIMERS
Kukjin Kim991a6c72011-12-08 10:04:49 +0900299
300static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
301
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900302/* Clock event handling */
303static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
304{
305 unsigned long tmp;
306 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900307 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900308
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900309 tmp = __raw_readl(reg_base + offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900310 if (tmp & mask) {
311 tmp &= ~mask;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900312 exynos4_mct_write(tmp, offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900313 }
314}
315
316static void exynos4_mct_tick_start(unsigned long cycles,
317 struct mct_clock_event_device *mevt)
318{
319 unsigned long tmp;
320
321 exynos4_mct_tick_stop(mevt);
322
323 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
324
325 /* update interrupt count buffer */
326 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
327
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300328 /* enable MCT tick interrupt */
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900329 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
330
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900331 tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900332 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
333 MCT_L_TCON_INTERVAL_MODE;
334 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
335}
336
337static int exynos4_tick_set_next_event(unsigned long cycles,
338 struct clock_event_device *evt)
339{
Marc Zyngiere700e412011-11-03 11:13:12 +0900340 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900341
342 exynos4_mct_tick_start(cycles, mevt);
343
344 return 0;
345}
346
347static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
348 struct clock_event_device *evt)
349{
Marc Zyngiere700e412011-11-03 11:13:12 +0900350 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800351 unsigned long cycles_per_jiffy;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900352
353 exynos4_mct_tick_stop(mevt);
354
355 switch (mode) {
356 case CLOCK_EVT_MODE_PERIODIC:
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800357 cycles_per_jiffy =
358 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
359 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900360 break;
361
362 case CLOCK_EVT_MODE_ONESHOT:
363 case CLOCK_EVT_MODE_UNUSED:
364 case CLOCK_EVT_MODE_SHUTDOWN:
365 case CLOCK_EVT_MODE_RESUME:
366 break;
367 }
368}
369
Changhwan Younc8987472011-10-04 17:09:26 +0900370static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900371{
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900372 struct clock_event_device *evt = mevt->evt;
373
374 /*
375 * This is for supporting oneshot mode.
376 * Mct would generate interrupt periodically
377 * without explicit stopping.
378 */
379 if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
380 exynos4_mct_tick_stop(mevt);
381
382 /* Clear the MCT tick interrupt */
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900383 if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
Changhwan Youn3a062282011-10-04 17:02:58 +0900384 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
385 return 1;
386 } else {
387 return 0;
388 }
389}
390
391static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
392{
393 struct mct_clock_event_device *mevt = dev_id;
394 struct clock_event_device *evt = mevt->evt;
395
396 exynos4_mct_tick_clear(mevt);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900397
398 evt->event_handler(evt);
399
400 return IRQ_HANDLED;
401}
402
403static struct irqaction mct_tick0_event_irq = {
404 .name = "mct_tick0_irq",
405 .flags = IRQF_TIMER | IRQF_NOBALANCING,
406 .handler = exynos4_mct_tick_isr,
407};
408
409static struct irqaction mct_tick1_event_irq = {
410 .name = "mct_tick1_irq",
411 .flags = IRQF_TIMER | IRQF_NOBALANCING,
412 .handler = exynos4_mct_tick_isr,
413};
414
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000415static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900416{
Marc Zyngiere700e412011-11-03 11:13:12 +0900417 struct mct_clock_event_device *mevt;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900418 unsigned int cpu = smp_processor_id();
419
Marc Zyngiere700e412011-11-03 11:13:12 +0900420 mevt = this_cpu_ptr(&percpu_mct_tick);
421 mevt->evt = evt;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900422
Marc Zyngiere700e412011-11-03 11:13:12 +0900423 mevt->base = EXYNOS4_MCT_L_BASE(cpu);
424 sprintf(mevt->name, "mct_tick%d", cpu);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900425
Marc Zyngiere700e412011-11-03 11:13:12 +0900426 evt->name = mevt->name;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900427 evt->cpumask = cpumask_of(cpu);
428 evt->set_next_event = exynos4_tick_set_next_event;
429 evt->set_mode = exynos4_tick_set_mode;
430 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
431 evt->rating = 450;
Shawn Guo838a2ae2013-01-12 11:50:05 +0000432 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
433 0xf, 0x7fffffff);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900434
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800435 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900436
Changhwan Youn3a062282011-10-04 17:02:58 +0900437 if (mct_int_type == MCT_INT_SPI) {
438 if (cpu == 0) {
Marc Zyngiere700e412011-11-03 11:13:12 +0900439 mct_tick0_event_irq.dev_id = mevt;
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900440 evt->irq = mct_irqs[MCT_L0_IRQ];
441 setup_irq(evt->irq, &mct_tick0_event_irq);
Changhwan Youn3a062282011-10-04 17:02:58 +0900442 } else {
Marc Zyngiere700e412011-11-03 11:13:12 +0900443 mct_tick1_event_irq.dev_id = mevt;
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900444 evt->irq = mct_irqs[MCT_L1_IRQ];
445 setup_irq(evt->irq, &mct_tick1_event_irq);
446 irq_set_affinity(evt->irq, cpumask_of(1));
Changhwan Youn3a062282011-10-04 17:02:58 +0900447 }
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900448 } else {
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900449 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900450 }
Kukjin Kim4d487d72011-08-24 16:07:39 +0900451
452 return 0;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900453}
454
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000455static void exynos4_local_timer_stop(struct clock_event_device *evt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900456{
Amit Daniel Kachhape248cd52011-12-08 10:07:08 +0900457 unsigned int cpu = smp_processor_id();
Marc Zyngier28af6902011-07-22 12:52:37 +0100458 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
Marc Zyngiere700e412011-11-03 11:13:12 +0900459 if (mct_int_type == MCT_INT_SPI)
Amit Daniel Kachhape248cd52011-12-08 10:07:08 +0900460 if (cpu == 0)
461 remove_irq(evt->irq, &mct_tick0_event_irq);
462 else
463 remove_irq(evt->irq, &mct_tick1_event_irq);
Marc Zyngiere700e412011-11-03 11:13:12 +0900464 else
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900465 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900466}
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000467
468static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
469 .setup = exynos4_local_timer_setup,
470 .stop = exynos4_local_timer_stop,
471};
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900472#endif /* CONFIG_LOCAL_TIMERS */
473
Arnd Bergmann19ce4f42013-04-09 22:24:06 +0200474static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900475{
Thomas Abrahamca9048e2013-03-09 17:10:37 +0900476 struct clk *mct_clk, *tick_clk;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900477
Thomas Abraham415ac2e2013-03-09 17:10:31 +0900478 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
479 clk_get(NULL, "fin_pll");
480 if (IS_ERR(tick_clk))
481 panic("%s: unable to determine tick clock rate\n", __func__);
482 clk_rate = clk_get_rate(tick_clk);
Marc Zyngiere700e412011-11-03 11:13:12 +0900483
Thomas Abrahamca9048e2013-03-09 17:10:37 +0900484 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
485 if (IS_ERR(mct_clk))
486 panic("%s: unable to retrieve mct clock instance\n", __func__);
487 clk_prepare_enable(mct_clk);
Marc Zyngiere700e412011-11-03 11:13:12 +0900488
Arnd Bergmann228e3022013-04-09 22:07:37 +0200489 reg_base = base;
Thomas Abraham36ba5d52013-03-09 16:01:52 +0900490 if (!reg_base)
491 panic("%s: unable to ioremap mct address space\n", __func__);
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900492
Kukjin Kim991a6c72011-12-08 10:04:49 +0900493#ifdef CONFIG_LOCAL_TIMERS
Marc Zyngiere700e412011-11-03 11:13:12 +0900494 if (mct_int_type == MCT_INT_PPI) {
495 int err;
496
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900497 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
Marc Zyngiere700e412011-11-03 11:13:12 +0900498 exynos4_mct_tick_isr, "MCT",
499 &percpu_mct_tick);
500 WARN(err, "MCT: can't request IRQ %d (%d)\n",
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900501 mct_irqs[MCT_L0_IRQ], err);
Marc Zyngiere700e412011-11-03 11:13:12 +0900502 }
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000503
504 local_timer_register(&exynos4_mct_tick_ops);
Kukjin Kim991a6c72011-12-08 10:04:49 +0900505#endif /* CONFIG_LOCAL_TIMERS */
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900506}
507
Arnd Bergmann034c0972013-04-10 11:35:29 +0200508void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900509{
Arnd Bergmann034c0972013-04-10 11:35:29 +0200510 mct_irqs[MCT_G0_IRQ] = irq_g0;
511 mct_irqs[MCT_L0_IRQ] = irq_l0;
512 mct_irqs[MCT_L1_IRQ] = irq_l1;
513 mct_int_type = MCT_INT_SPI;
Kukjin Kim2edb36c2012-11-15 15:48:56 +0900514
Arnd Bergmann034c0972013-04-10 11:35:29 +0200515 exynos4_timer_resources(NULL, base);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900516 exynos4_clocksource_init();
517 exynos4_clockevent_init();
518}
Arnd Bergmann228e3022013-04-09 22:07:37 +0200519
520static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
521{
522 u32 nr_irqs, i;
523
524 mct_int_type = int_type;
525
526 /* This driver uses only one global timer interrupt */
527 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
528
529 /*
530 * Find out the number of local irqs specified. The local
531 * timer irqs are specified after the four global timer
532 * irqs are specified.
533 */
Arnd Bergmannf4636d02013-04-19 22:00:04 +0200534#ifdef CONFIG_OF
Arnd Bergmann228e3022013-04-09 22:07:37 +0200535 nr_irqs = of_irq_count(np);
Arnd Bergmannf4636d02013-04-19 22:00:04 +0200536#else
537 nr_irqs = 0;
538#endif
Arnd Bergmann228e3022013-04-09 22:07:37 +0200539 for (i = MCT_L0_IRQ; i < nr_irqs; i++)
540 mct_irqs[i] = irq_of_parse_and_map(np, i);
541
Arnd Bergmann19ce4f42013-04-09 22:24:06 +0200542 exynos4_timer_resources(np, of_iomap(np, 0));
Arnd Bergmann228e3022013-04-09 22:07:37 +0200543 exynos4_clocksource_init();
544 exynos4_clockevent_init();
545}
546
547
548static void __init mct_init_spi(struct device_node *np)
549{
550 return mct_init_dt(np, MCT_INT_SPI);
551}
552
553static void __init mct_init_ppi(struct device_node *np)
554{
555 return mct_init_dt(np, MCT_INT_PPI);
556}
557CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
558CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);