Thomas Gleixner | 3f4110a | 2009-08-29 14:54:20 +0200 | [diff] [blame] | 1 | /* |
Kuppuswamy Sathyanarayanan | 05454c2 | 2013-10-17 15:35:27 -0700 | [diff] [blame] | 2 | * intel-mid.c: Intel MID platform setup code |
Thomas Gleixner | 3f4110a | 2009-08-29 14:54:20 +0200 | [diff] [blame] | 3 | * |
Kuppuswamy Sathyanarayanan | 05454c2 | 2013-10-17 15:35:27 -0700 | [diff] [blame] | 4 | * (C) Copyright 2008, 2012 Intel Corporation |
Thomas Gleixner | 3f4110a | 2009-08-29 14:54:20 +0200 | [diff] [blame] | 5 | * Author: Jacob Pan (jacob.jun.pan@intel.com) |
Kuppuswamy Sathyanarayanan | 05454c2 | 2013-10-17 15:35:27 -0700 | [diff] [blame] | 6 | * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com> |
Thomas Gleixner | 3f4110a | 2009-08-29 14:54:20 +0200 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License |
| 10 | * as published by the Free Software Foundation; version 2 |
| 11 | * of the License. |
| 12 | */ |
Feng Tang | 1da4b1c | 2010-11-09 11:22:58 +0000 | [diff] [blame] | 13 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 14 | #define pr_fmt(fmt) "intel_mid: " fmt |
Feng Tang | 1da4b1c | 2010-11-09 11:22:58 +0000 | [diff] [blame] | 15 | |
Thomas Gleixner | 3f4110a | 2009-08-29 14:54:20 +0200 | [diff] [blame] | 16 | #include <linux/init.h> |
Jacob Pan | 16ab539 | 2010-02-12 03:08:30 -0800 | [diff] [blame] | 17 | #include <linux/kernel.h> |
Feng Tang | efe3ed9 | 2011-08-26 11:25:14 +0100 | [diff] [blame] | 18 | #include <linux/interrupt.h> |
Andy Shevchenko | a11836f | 2016-07-09 16:45:29 +0300 | [diff] [blame] | 19 | #include <linux/regulator/machine.h> |
Feng Tang | efe3ed9 | 2011-08-26 11:25:14 +0100 | [diff] [blame] | 20 | #include <linux/scatterlist.h> |
Jacob Pan | 16ab539 | 2010-02-12 03:08:30 -0800 | [diff] [blame] | 21 | #include <linux/sfi.h> |
| 22 | #include <linux/irq.h> |
Paul Gortmaker | cc3ae7b | 2016-07-13 20:18:58 -0400 | [diff] [blame] | 23 | #include <linux/export.h> |
Alan Cox | 42c2544 | 2011-09-07 16:06:51 +0300 | [diff] [blame] | 24 | #include <linux/notifier.h> |
Thomas Gleixner | 3f4110a | 2009-08-29 14:54:20 +0200 | [diff] [blame] | 25 | |
| 26 | #include <asm/setup.h> |
Jacob Pan | 16ab539 | 2010-02-12 03:08:30 -0800 | [diff] [blame] | 27 | #include <asm/mpspec_def.h> |
| 28 | #include <asm/hw_irq.h> |
| 29 | #include <asm/apic.h> |
| 30 | #include <asm/io_apic.h> |
Kuppuswamy Sathyanarayanan | 05454c2 | 2013-10-17 15:35:27 -0700 | [diff] [blame] | 31 | #include <asm/intel-mid.h> |
| 32 | #include <asm/intel_mid_vrtc.h> |
Jacob Pan | 5b78b67 | 2010-02-12 02:29:11 -0800 | [diff] [blame] | 33 | #include <asm/io.h> |
| 34 | #include <asm/i8259.h> |
Feng Tang | 1da4b1c | 2010-11-09 11:22:58 +0000 | [diff] [blame] | 35 | #include <asm/intel_scu_ipc.h> |
Jacob Pan | 3746c6b | 2010-02-12 05:01:12 -0800 | [diff] [blame] | 36 | #include <asm/apb_timer.h> |
Alek Du | cfb505a | 2010-11-10 16:50:08 +0000 | [diff] [blame] | 37 | #include <asm/reboot.h> |
Thomas Gleixner | 3f4110a | 2009-08-29 14:54:20 +0200 | [diff] [blame] | 38 | |
David Cohen | ecd6910 | 2013-12-16 12:07:36 -0800 | [diff] [blame] | 39 | #include "intel_mid_weak_decls.h" |
| 40 | |
Jacob Pan | a875c01 | 2010-05-19 12:01:25 -0700 | [diff] [blame] | 41 | /* |
| 42 | * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock, |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 43 | * cmdline option x86_intel_mid_timer can be used to override the configuration |
Jacob Pan | a875c01 | 2010-05-19 12:01:25 -0700 | [diff] [blame] | 44 | * to prefer one or the other. |
| 45 | * at runtime, there are basically three timer configurations: |
| 46 | * 1. per cpu apbt clock only |
| 47 | * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only |
| 48 | * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast. |
| 49 | * |
| 50 | * by default (without cmdline option), platform code first detects cpu type |
| 51 | * to see if we are on lincroft or penwell, then set up both lapic or apbt |
| 52 | * clocks accordingly. |
| 53 | * i.e. by default, medfield uses configuration #2, moorestown uses #1. |
| 54 | * config #3 is supported but not recommended on medfield. |
| 55 | * |
| 56 | * rating and feature summary: |
| 57 | * lapic (with C3STOP) --------- 100 |
| 58 | * apbt (always-on) ------------ 110 |
| 59 | * lapic (always-on,ARAT) ------ 150 |
| 60 | */ |
| 61 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 62 | enum intel_mid_timer_options intel_mid_timer_options; |
Jacob Pan | a875c01 | 2010-05-19 12:01:25 -0700 | [diff] [blame] | 63 | |
Kuppuswamy Sathyanarayanan | 85611e3 | 2013-12-16 12:07:37 -0800 | [diff] [blame] | 64 | /* intel_mid_ops to store sub arch ops */ |
Andy Shevchenko | d1f0f6c | 2015-10-09 17:25:41 +0300 | [diff] [blame] | 65 | static struct intel_mid_ops *intel_mid_ops; |
Kuppuswamy Sathyanarayanan | 85611e3 | 2013-12-16 12:07:37 -0800 | [diff] [blame] | 66 | /* getter function for sub arch ops*/ |
| 67 | static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT; |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 68 | enum intel_mid_cpu_type __intel_mid_cpu_chip; |
| 69 | EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip); |
Jacob Pan | a0c173b | 2010-05-19 12:01:24 -0700 | [diff] [blame] | 70 | |
Kuppuswamy Sathyanarayanan | 85611e3 | 2013-12-16 12:07:37 -0800 | [diff] [blame] | 71 | static void intel_mid_power_off(void) |
| 72 | { |
Andy Shevchenko | bda7b07 | 2016-09-07 15:39:55 +0300 | [diff] [blame] | 73 | /* Shut down South Complex via PWRMU */ |
| 74 | intel_mid_pwr_power_off(); |
| 75 | |
| 76 | /* Only for Tangier, the rest will ignore this command */ |
| 77 | intel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1); |
Kuppuswamy Sathyanarayanan | 85611e3 | 2013-12-16 12:07:37 -0800 | [diff] [blame] | 78 | }; |
| 79 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 80 | static void intel_mid_reboot(void) |
Jacob Pan | 48bc556 | 2011-11-16 16:07:22 +0000 | [diff] [blame] | 81 | { |
Alan Cox | 1a8359e | 2012-01-26 17:33:30 +0000 | [diff] [blame] | 82 | intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0); |
Jacob Pan | 48bc556 | 2011-11-16 16:07:22 +0000 | [diff] [blame] | 83 | } |
| 84 | |
Kuppuswamy Sathyanarayanan | 85611e3 | 2013-12-16 12:07:37 -0800 | [diff] [blame] | 85 | static unsigned long __init intel_mid_calibrate_tsc(void) |
| 86 | { |
| 87 | return 0; |
| 88 | } |
| 89 | |
Thomas Gleixner | 6648d1b | 2015-04-13 14:11:51 +0800 | [diff] [blame] | 90 | static void __init intel_mid_setup_bp_timer(void) |
| 91 | { |
| 92 | apbt_time_init(); |
| 93 | setup_boot_APIC_clock(); |
| 94 | } |
| 95 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 96 | static void __init intel_mid_time_init(void) |
Jacob Pan | 3746c6b | 2010-02-12 05:01:12 -0800 | [diff] [blame] | 97 | { |
Jacob Pan | 7f05dec | 2010-11-09 11:28:43 +0000 | [diff] [blame] | 98 | sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr); |
Thomas Gleixner | 6648d1b | 2015-04-13 14:11:51 +0800 | [diff] [blame] | 99 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 100 | switch (intel_mid_timer_options) { |
| 101 | case INTEL_MID_TIMER_APBT_ONLY: |
Jacob Pan | a875c01 | 2010-05-19 12:01:25 -0700 | [diff] [blame] | 102 | break; |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 103 | case INTEL_MID_TIMER_LAPIC_APBT: |
Thomas Gleixner | 6648d1b | 2015-04-13 14:11:51 +0800 | [diff] [blame] | 104 | /* Use apbt and local apic */ |
| 105 | x86_init.timers.setup_percpu_clockev = intel_mid_setup_bp_timer; |
Jacob Pan | a875c01 | 2010-05-19 12:01:25 -0700 | [diff] [blame] | 106 | x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; |
Thomas Gleixner | 6648d1b | 2015-04-13 14:11:51 +0800 | [diff] [blame] | 107 | return; |
Jacob Pan | a875c01 | 2010-05-19 12:01:25 -0700 | [diff] [blame] | 108 | default: |
| 109 | if (!boot_cpu_has(X86_FEATURE_ARAT)) |
| 110 | break; |
Thomas Gleixner | 6648d1b | 2015-04-13 14:11:51 +0800 | [diff] [blame] | 111 | /* Lapic only, no apbt */ |
Jacob Pan | a875c01 | 2010-05-19 12:01:25 -0700 | [diff] [blame] | 112 | x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; |
| 113 | x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; |
| 114 | return; |
| 115 | } |
Thomas Gleixner | 6648d1b | 2015-04-13 14:11:51 +0800 | [diff] [blame] | 116 | |
| 117 | x86_init.timers.setup_percpu_clockev = apbt_time_init; |
Jacob Pan | 3746c6b | 2010-02-12 05:01:12 -0800 | [diff] [blame] | 118 | } |
| 119 | |
Paul Gortmaker | aeeca40 | 2013-11-07 13:34:50 -0500 | [diff] [blame] | 120 | static void intel_mid_arch_setup(void) |
Jacob Pan | 3746c6b | 2010-02-12 05:01:12 -0800 | [diff] [blame] | 121 | { |
Kuppuswamy Sathyanarayanan | 85611e3 | 2013-12-16 12:07:37 -0800 | [diff] [blame] | 122 | if (boot_cpu_data.x86 != 6) { |
Alan Cox | 1a8359e | 2012-01-26 17:33:30 +0000 | [diff] [blame] | 123 | pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n", |
Jacob Pan | a0c173b | 2010-05-19 12:01:24 -0700 | [diff] [blame] | 124 | boot_cpu_data.x86, boot_cpu_data.x86_model); |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 125 | __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; |
Kuppuswamy Sathyanarayanan | 85611e3 | 2013-12-16 12:07:37 -0800 | [diff] [blame] | 126 | goto out; |
Jacob Pan | a0c173b | 2010-05-19 12:01:24 -0700 | [diff] [blame] | 127 | } |
Kuppuswamy Sathyanarayanan | 85611e3 | 2013-12-16 12:07:37 -0800 | [diff] [blame] | 128 | |
| 129 | switch (boot_cpu_data.x86_model) { |
| 130 | case 0x35: |
| 131 | __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW; |
| 132 | break; |
David Cohen | bc20aa48 | 2013-12-16 12:07:38 -0800 | [diff] [blame] | 133 | case 0x3C: |
| 134 | case 0x4A: |
| 135 | __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER; |
| 136 | break; |
Kuppuswamy Sathyanarayanan | 85611e3 | 2013-12-16 12:07:37 -0800 | [diff] [blame] | 137 | case 0x27: |
| 138 | default: |
| 139 | __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; |
| 140 | break; |
| 141 | } |
| 142 | |
| 143 | if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops)) |
| 144 | intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip](); |
| 145 | else { |
| 146 | intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL](); |
Andy Shevchenko | b000de5 | 2016-01-15 22:11:08 +0200 | [diff] [blame] | 147 | pr_info("ARCH: Unknown SoC, assuming Penwell!\n"); |
Kuppuswamy Sathyanarayanan | 85611e3 | 2013-12-16 12:07:37 -0800 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | out: |
| 151 | if (intel_mid_ops->arch_setup) |
| 152 | intel_mid_ops->arch_setup(); |
Andy Shevchenko | a11836f | 2016-07-09 16:45:29 +0300 | [diff] [blame] | 153 | |
| 154 | /* |
| 155 | * Intel MID platforms are using explicitly defined regulators. |
| 156 | * |
| 157 | * Let the regulator core know that we do not have any additional |
| 158 | * regulators left. This lets it substitute unprovided regulators with |
| 159 | * dummy ones: |
| 160 | */ |
| 161 | regulator_has_full_constraints(); |
Jacob Pan | a0c173b | 2010-05-19 12:01:24 -0700 | [diff] [blame] | 162 | } |
Jacob Pan | 3746c6b | 2010-02-12 05:01:12 -0800 | [diff] [blame] | 163 | |
Feng Tang | 6d2cce6 | 2010-07-05 23:03:19 +0800 | [diff] [blame] | 164 | /* MID systems don't have i8042 controller */ |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 165 | static int intel_mid_i8042_detect(void) |
Feng Tang | 6d2cce6 | 2010-07-05 23:03:19 +0800 | [diff] [blame] | 166 | { |
| 167 | return 0; |
| 168 | } |
| 169 | |
Jacob Pan | 3746c6b | 2010-02-12 05:01:12 -0800 | [diff] [blame] | 170 | /* |
Jacob Pan | 064a59b | 2011-11-10 13:43:05 +0000 | [diff] [blame] | 171 | * Moorestown does not have external NMI source nor port 0x61 to report |
| 172 | * NMI status. The possible NMI sources are from pmu as a result of NMI |
| 173 | * watchdog or lock debug. Reading io port 0x61 results in 0xff which |
| 174 | * misled NMI handler. |
| 175 | */ |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 176 | static unsigned char intel_mid_get_nmi_reason(void) |
Jacob Pan | 064a59b | 2011-11-10 13:43:05 +0000 | [diff] [blame] | 177 | { |
| 178 | return 0; |
| 179 | } |
| 180 | |
| 181 | /* |
Thomas Gleixner | 3f4110a | 2009-08-29 14:54:20 +0200 | [diff] [blame] | 182 | * Moorestown specific x86_init function overrides and early setup |
| 183 | * calls. |
| 184 | */ |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 185 | void __init x86_intel_mid_early_setup(void) |
Thomas Gleixner | 3f4110a | 2009-08-29 14:54:20 +0200 | [diff] [blame] | 186 | { |
| 187 | x86_init.resources.probe_roms = x86_init_noop; |
| 188 | x86_init.resources.reserve_resources = x86_init_noop; |
Jacob Pan | 5b78b67 | 2010-02-12 02:29:11 -0800 | [diff] [blame] | 189 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 190 | x86_init.timers.timer_init = intel_mid_time_init; |
Jacob Pan | a875c01 | 2010-05-19 12:01:25 -0700 | [diff] [blame] | 191 | x86_init.timers.setup_percpu_clockev = x86_init_noop; |
Jacob Pan | 3746c6b | 2010-02-12 05:01:12 -0800 | [diff] [blame] | 192 | |
| 193 | x86_init.irqs.pre_vector_init = x86_init_noop; |
| 194 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 195 | x86_init.oem.arch_setup = intel_mid_arch_setup; |
Jacob Pan | a0c173b | 2010-05-19 12:01:24 -0700 | [diff] [blame] | 196 | |
Jacob Pan | a875c01 | 2010-05-19 12:01:25 -0700 | [diff] [blame] | 197 | x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock; |
Jacob Pan | 3746c6b | 2010-02-12 05:01:12 -0800 | [diff] [blame] | 198 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 199 | x86_platform.calibrate_tsc = intel_mid_calibrate_tsc; |
| 200 | x86_platform.i8042_detect = intel_mid_i8042_detect; |
| 201 | x86_init.timers.wallclock_init = intel_mid_rtc_init; |
| 202 | x86_platform.get_nmi_reason = intel_mid_get_nmi_reason; |
Jacob Pan | 064a59b | 2011-11-10 13:43:05 +0000 | [diff] [blame] | 203 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 204 | x86_init.pci.init = intel_mid_pci_init; |
Jacob Pan | af2730f | 2010-02-12 10:31:47 -0800 | [diff] [blame] | 205 | x86_init.pci.fixup_irqs = x86_init_noop; |
| 206 | |
Jacob Pan | 5b78b67 | 2010-02-12 02:29:11 -0800 | [diff] [blame] | 207 | legacy_pic = &null_legacy_pic; |
Jacob Pan | fea24e2 | 2010-05-14 14:41:20 -0700 | [diff] [blame] | 208 | |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 209 | pm_power_off = intel_mid_power_off; |
| 210 | machine_ops.emergency_restart = intel_mid_reboot; |
Alek Du | cfb505a | 2010-11-10 16:50:08 +0000 | [diff] [blame] | 211 | |
Jacob Pan | fea24e2 | 2010-05-14 14:41:20 -0700 | [diff] [blame] | 212 | /* Avoid searching for BIOS MP tables */ |
| 213 | x86_init.mpparse.find_smp_config = x86_init_noop; |
| 214 | x86_init.mpparse.get_smp_config = x86_init_uint_noop; |
Jacob Pan | 9d90e49 | 2011-04-08 11:23:00 -0700 | [diff] [blame] | 215 | set_bit(MP_BUS_ISA, mp_bus_not_pci); |
Thomas Gleixner | 3f4110a | 2009-08-29 14:54:20 +0200 | [diff] [blame] | 216 | } |
Jacob Pan | a875c01 | 2010-05-19 12:01:25 -0700 | [diff] [blame] | 217 | |
| 218 | /* |
| 219 | * if user does not want to use per CPU apb timer, just give it a lower rating |
| 220 | * than local apic timer and skip the late per cpu timer init. |
| 221 | */ |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 222 | static inline int __init setup_x86_intel_mid_timer(char *arg) |
Jacob Pan | a875c01 | 2010-05-19 12:01:25 -0700 | [diff] [blame] | 223 | { |
| 224 | if (!arg) |
| 225 | return -EINVAL; |
| 226 | |
| 227 | if (strcmp("apbt_only", arg) == 0) |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 228 | intel_mid_timer_options = INTEL_MID_TIMER_APBT_ONLY; |
Jacob Pan | a875c01 | 2010-05-19 12:01:25 -0700 | [diff] [blame] | 229 | else if (strcmp("lapic_and_apbt", arg) == 0) |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 230 | intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT; |
Jacob Pan | a875c01 | 2010-05-19 12:01:25 -0700 | [diff] [blame] | 231 | else { |
Andy Shevchenko | b000de5 | 2016-01-15 22:11:08 +0200 | [diff] [blame] | 232 | pr_warn("X86 INTEL_MID timer option %s not recognised use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n", |
| 233 | arg); |
Jacob Pan | a875c01 | 2010-05-19 12:01:25 -0700 | [diff] [blame] | 234 | return -EINVAL; |
| 235 | } |
| 236 | return 0; |
| 237 | } |
Kuppuswamy Sathyanarayanan | 712b6aa | 2013-10-17 15:35:29 -0700 | [diff] [blame] | 238 | __setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer); |