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gerrit-public.fairphone.software / kernel / msm-4.9 / 090a80cba39f2763a488b6f7c65e38922d5aa17a / . / arch / arm / mach-spear3xx / include / mach / spear.h
blob: 51eb953148a998733f656670cb24705b03f0fbc9 [file] [log] [blame]
viresh kumara7e9c452010-04-01 12:30:19 +0100[diff] [blame]1/*
2 * arch/arm/mach-spear3xx/include/mach/spear.h
3 *
4 * SPEAr3xx Machine family specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_SPEAR3XX_H
15#define __MACH_SPEAR3XX_H
16
Shiraz Hashim981a95d32011-03-07 05:57:08 +0100[diff] [blame]17#include <asm/memory.h>
viresh kumara7e9c452010-04-01 12:30:19 +0100[diff] [blame]18
19/* ICM1 - Low speed connection */
Shiraz Hashim981a95d32011-03-07 05:57:08 +0100[diff] [blame]20#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]21#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
Shiraz Hashim981a95d32011-03-07 05:57:08 +0100[diff] [blame]22#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]23#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
Shiraz Hashim981a95d32011-03-07 05:57:08 +0100[diff] [blame]24#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
viresh kumara7e9c452010-04-01 12:30:19 +0100[diff] [blame]25
26/* ML1 - Multi Layer CPU Subsystem */
Shiraz Hashim981a95d32011-03-07 05:57:08 +0100[diff] [blame]27#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
Arnd Bergmann5019f0b2012-04-11 17:30:11 +0000[diff] [blame]28#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
viresh kumara7e9c452010-04-01 12:30:19 +0100[diff] [blame]29
30/* ICM3 - Basic Subsystem */
Shiraz Hashim981a95d32011-03-07 05:57:08 +0100[diff] [blame]31#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]32#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
Shiraz Hashim981a95d32011-03-07 05:57:08 +0100[diff] [blame]33#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
Shiraz Hashim981a95d32011-03-07 05:57:08 +0100[diff] [blame]34#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]35#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
Shiraz Hashim981a95d32011-03-07 05:57:08 +0100[diff] [blame]36#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
Viresh Kumarc5fa4fd2012-03-23 00:17:43 +0530[diff] [blame]37#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
viresh kumara7e9c452010-04-01 12:30:19 +0100[diff] [blame]38
39/* Debug uart for linux, will be used for debug and uncompress messages */
40#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
41#define VA_SPEAR_DBG_UART_BASE VA_SPEAR3XX_ICM1_UART_BASE
42
43/* Sysctl base for spear platform */
44#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE
45#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
46
Viresh Kumar5df33a62012-04-10 09:02:35 +0530[diff] [blame]47/* SPEAr320 Macros */
48#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
49#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000)
50#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
51#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
52 #define SPEAR320_UARTX_PCLK_MASK 0x1
53 #define SPEAR320_UART2_PCLK_SHIFT 8
54 #define SPEAR320_UART3_PCLK_SHIFT 9
55 #define SPEAR320_UART4_PCLK_SHIFT 10
56 #define SPEAR320_UART5_PCLK_SHIFT 11
57 #define SPEAR320_UART6_PCLK_SHIFT 12
58 #define SPEAR320_RS485_PCLK_SHIFT 13
59
viresh kumara7e9c452010-04-01 12:30:19 +0100[diff] [blame]60#endif /* __MACH_SPEAR3XX_H */