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PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
Greg Rose096a58f2010-01-09 02:26:26 +000034#include "ixgbe_mbx.h"
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +000035
36#define IXGBE_82599_MAX_TX_QUEUES 128
37#define IXGBE_82599_MAX_RX_QUEUES 128
38#define IXGBE_82599_RAR_ENTRIES 128
39#define IXGBE_82599_MC_TBL_SIZE 128
40#define IXGBE_82599_VFT_TBL_SIZE 128
41
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +000042s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
43 ixgbe_link_speed speed,
44 bool autoneg,
45 bool autoneg_wait_to_complete);
Don Skidmorecd7e1f02009-10-08 15:36:22 +000046static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
48 bool autoneg,
49 bool autoneg_wait_to_complete);
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +000050s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
51 bool autoneg_wait_to_complete);
52s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
53 ixgbe_link_speed speed,
54 bool autoneg,
55 bool autoneg_wait_to_complete);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +000056static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
57 ixgbe_link_speed *speed,
58 bool *autoneg);
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +000059static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed speed,
61 bool autoneg,
62 bool autoneg_wait_to_complete);
Peter P Waskiewicz Jr794caeb2009-06-04 16:02:24 +000063static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +000064
Don Skidmore7b25cdb2009-08-25 04:47:32 +000065static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +000066{
67 struct ixgbe_mac_info *mac = &hw->mac;
68 if (hw->phy.multispeed_fiber) {
69 /* Set up dual speed SFP+ support */
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +000070 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +000071 } else {
Don Skidmorecd7e1f02009-10-08 15:36:22 +000072 if ((mac->ops.get_media_type(hw) ==
73 ixgbe_media_type_backplane) &&
74 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
75 hw->phy.smart_speed == ixgbe_smart_speed_on))
76 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
77 else
78 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +000079 }
80}
81
Don Skidmore7b25cdb2009-08-25 04:47:32 +000082static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +000083{
84 s32 ret_val = 0;
85 u16 list_offset, data_offset, data_value;
86
87 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
88 ixgbe_init_mac_link_ops_82599(hw);
PJ Waskiewicz553b4492009-04-09 22:28:15 +000089
90 hw->phy.ops.reset = NULL;
91
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +000092 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
93 &data_offset);
94
95 if (ret_val != 0)
96 goto setup_sfp_out;
97
Peter P Waskiewicz Jraa5aec82009-05-19 09:18:34 +000098 /* PHY config will finish before releasing the semaphore */
99 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
100 if (ret_val != 0) {
101 ret_val = IXGBE_ERR_SWFW_SYNC;
102 goto setup_sfp_out;
103 }
104
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000105 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
106 while (data_value != 0xffff) {
107 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
108 IXGBE_WRITE_FLUSH(hw);
109 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
110 }
Peter P Waskiewicz Jr1479ad42009-06-04 11:10:17 +0000111 /* Now restart DSP by setting Restart_AN */
112 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
113 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
Peter P Waskiewicz Jraa5aec82009-05-19 09:18:34 +0000114
115 /* Release the semaphore */
116 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
117 /* Delay obtaining semaphore again to allow FW access */
118 msleep(hw->eeprom.semaphore_delay);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000119 }
120
121setup_sfp_out:
122 return ret_val;
123}
124
125/**
126 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
127 * @hw: pointer to hardware structure
128 *
129 * Read PCIe configuration space, and get the MSI-X vector count from
130 * the capabilities table.
131 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +0000132static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000133{
134 struct ixgbe_adapter *adapter = hw->back;
135 u16 msix_count;
136 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
137 &msix_count);
138 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
139
140 /* MSI-X count is zero-based in HW, so increment to give proper value */
141 msix_count++;
142
143 return msix_count;
144}
145
146static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
147{
148 struct ixgbe_mac_info *mac = &hw->mac;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000149
150 ixgbe_init_mac_link_ops_82599(hw);
151
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000152 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
153 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
154 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
155 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
156 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
157 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
158
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000159 return 0;
160}
161
162/**
163 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
164 * @hw: pointer to hardware structure
165 *
166 * Initialize any function pointers that were not able to be
167 * set during get_invariants because the PHY/SFP type was
168 * not known. Perform the SFP init if necessary.
169 *
170 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +0000171static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000172{
173 struct ixgbe_mac_info *mac = &hw->mac;
174 struct ixgbe_phy_info *phy = &hw->phy;
175 s32 ret_val = 0;
176
177 /* Identify the PHY or SFP module */
178 ret_val = phy->ops.identify(hw);
179
180 /* Setup function pointers based on detected SFP module and speeds */
181 ixgbe_init_mac_link_ops_82599(hw);
182
183 /* If copper media, overwrite with copper function pointers */
184 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
185 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000186 mac->ops.get_link_capabilities =
187 &ixgbe_get_copper_link_capabilities_82599;
188 }
189
190 /* Set necessary function pointers based on phy type */
191 switch (hw->phy.type) {
192 case ixgbe_phy_tn:
193 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
194 phy->ops.get_firmware_version =
195 &ixgbe_get_phy_firmware_version_tnx;
196 break;
197 default:
198 break;
199 }
200
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000201 return ret_val;
202}
203
204/**
205 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
206 * @hw: pointer to hardware structure
207 * @speed: pointer to link speed
208 * @negotiation: true when autoneg or autotry is enabled
209 *
210 * Determines the link capabilities by reading the AUTOC register.
211 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +0000212static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
213 ixgbe_link_speed *speed,
214 bool *negotiation)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000215{
216 s32 status = 0;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000217 u32 autoc = 0;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000218
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000219 /*
220 * Determine link capabilities based on the stored value of AUTOC,
221 * which represents EEPROM defaults. If AUTOC value has not been
222 * stored, use the current register value.
223 */
224 if (hw->mac.orig_link_settings_stored)
225 autoc = hw->mac.orig_autoc;
226 else
227 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
228
229 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000230 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
231 *speed = IXGBE_LINK_SPEED_1GB_FULL;
232 *negotiation = false;
233 break;
234
235 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
236 *speed = IXGBE_LINK_SPEED_10GB_FULL;
237 *negotiation = false;
238 break;
239
240 case IXGBE_AUTOC_LMS_1G_AN:
241 *speed = IXGBE_LINK_SPEED_1GB_FULL;
242 *negotiation = true;
243 break;
244
245 case IXGBE_AUTOC_LMS_10G_SERIAL:
246 *speed = IXGBE_LINK_SPEED_10GB_FULL;
247 *negotiation = false;
248 break;
249
250 case IXGBE_AUTOC_LMS_KX4_KX_KR:
251 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
252 *speed = IXGBE_LINK_SPEED_UNKNOWN;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000253 if (autoc & IXGBE_AUTOC_KR_SUPP)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000254 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000255 if (autoc & IXGBE_AUTOC_KX4_SUPP)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000256 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000257 if (autoc & IXGBE_AUTOC_KX_SUPP)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000258 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
259 *negotiation = true;
260 break;
261
262 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
263 *speed = IXGBE_LINK_SPEED_100_FULL;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000264 if (autoc & IXGBE_AUTOC_KR_SUPP)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000265 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000266 if (autoc & IXGBE_AUTOC_KX4_SUPP)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000267 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000268 if (autoc & IXGBE_AUTOC_KX_SUPP)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000269 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
270 *negotiation = true;
271 break;
272
273 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
274 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
275 *negotiation = false;
276 break;
277
278 default:
279 status = IXGBE_ERR_LINK_SETUP;
280 goto out;
281 break;
282 }
283
284 if (hw->phy.multispeed_fiber) {
285 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
286 IXGBE_LINK_SPEED_1GB_FULL;
287 *negotiation = true;
288 }
289
290out:
291 return status;
292}
293
294/**
295 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
296 * @hw: pointer to hardware structure
297 * @speed: pointer to link speed
298 * @autoneg: boolean auto-negotiation value
299 *
300 * Determines the link capabilities by reading the AUTOC register.
301 **/
302static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
303 ixgbe_link_speed *speed,
304 bool *autoneg)
305{
306 s32 status = IXGBE_ERR_LINK_SETUP;
307 u16 speed_ability;
308
309 *speed = 0;
310 *autoneg = true;
311
Ben Hutchings6b73e102009-04-29 08:08:58 +0000312 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000313 &speed_ability);
314
315 if (status == 0) {
Ben Hutchings6b73e102009-04-29 08:08:58 +0000316 if (speed_ability & MDIO_SPEED_10G)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000317 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
Ben Hutchings6b73e102009-04-29 08:08:58 +0000318 if (speed_ability & MDIO_PMA_SPEED_1000)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000319 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
320 }
321
322 return status;
323}
324
325/**
326 * ixgbe_get_media_type_82599 - Get media type
327 * @hw: pointer to hardware structure
328 *
329 * Returns the media type (fiber, copper, backplane)
330 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +0000331static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000332{
333 enum ixgbe_media_type media_type;
334
335 /* Detect if there is a copper PHY attached. */
336 if (hw->phy.type == ixgbe_phy_cu_unknown ||
337 hw->phy.type == ixgbe_phy_tn) {
338 media_type = ixgbe_media_type_copper;
339 goto out;
340 }
341
342 switch (hw->device_id) {
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000343 case IXGBE_DEV_ID_82599_KX4:
Don Skidmoredbfec662009-10-02 08:58:25 +0000344 case IXGBE_DEV_ID_82599_KX4_MEZZ:
Don Skidmore312eb932009-10-02 08:58:04 +0000345 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
Don Skidmore74757d42009-12-08 07:22:23 +0000346 case IXGBE_DEV_ID_82599_KR:
Peter P Waskiewicz Jr1fcf03e2009-05-17 20:58:04 +0000347 case IXGBE_DEV_ID_82599_XAUI_LOM:
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000348 /* Default device ID is mezzanine card KX/KX4 */
349 media_type = ixgbe_media_type_backplane;
350 break;
351 case IXGBE_DEV_ID_82599_SFP:
Don Skidmore38ad1c82009-10-08 15:35:58 +0000352 case IXGBE_DEV_ID_82599_SFP_EM:
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000353 media_type = ixgbe_media_type_fiber;
354 break;
Peter P Waskiewicz Jr89111842009-09-14 07:47:49 +0000355 case IXGBE_DEV_ID_82599_CX4:
Peter P Waskiewicz Jr6b1be192009-09-14 07:48:10 +0000356 media_type = ixgbe_media_type_cx4;
Peter P Waskiewicz Jr89111842009-09-14 07:47:49 +0000357 break;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000358 default:
359 media_type = ixgbe_media_type_unknown;
360 break;
361 }
362out:
363 return media_type;
364}
365
366/**
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000367 * ixgbe_start_mac_link_82599 - Setup MAC link settings
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000368 * @hw: pointer to hardware structure
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000369 * @autoneg_wait_to_complete: true when waiting for completion is needed
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000370 *
371 * Configures link settings based on values in the ixgbe_hw struct.
372 * Restarts the link. Performs autonegotiation if needed.
373 **/
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000374s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
375 bool autoneg_wait_to_complete)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000376{
377 u32 autoc_reg;
378 u32 links_reg;
379 u32 i;
380 s32 status = 0;
381
382 /* Restart link */
383 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
384 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
385 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
386
387 /* Only poll for autoneg to complete if specified to do so */
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000388 if (autoneg_wait_to_complete) {
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000389 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
390 IXGBE_AUTOC_LMS_KX4_KX_KR ||
391 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
392 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
393 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
394 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
395 links_reg = 0; /* Just in case Autoneg time = 0 */
396 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
397 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
398 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
399 break;
400 msleep(100);
401 }
402 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
403 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
404 hw_dbg(hw, "Autoneg did not complete.\n");
405 }
406 }
407 }
408
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000409 /* Add delay to filter out noises during initial link setup */
410 msleep(50);
411
412 return status;
413}
414
415/**
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000416 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000417 * @hw: pointer to hardware structure
418 * @speed: new link speed
419 * @autoneg: true if autonegotiation enabled
420 * @autoneg_wait_to_complete: true when waiting for completion is needed
421 *
422 * Set the link speed in the AUTOC register and restarts link.
423 **/
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000424s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
425 ixgbe_link_speed speed,
426 bool autoneg,
427 bool autoneg_wait_to_complete)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000428{
429 s32 status = 0;
430 ixgbe_link_speed phy_link_speed;
431 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
432 u32 speedcnt = 0;
433 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
434 bool link_up = false;
435 bool negotiation;
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000436 int i;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000437
438 /* Mask off requested but non-supported speeds */
439 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
440 speed &= phy_link_speed;
441
442 /*
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000443 * When the driver changes the link speeds that it can support,
444 * it sets autotry_restart to true to indicate that we need to
445 * initiate a new autotry session with the link partner. To do
446 * so, we set the speed then disable and re-enable the tx laser, to
447 * alert the link partner that it also needs to restart autotry on its
448 * end. This is consistent with true clause 37 autoneg, which also
449 * involves a loss of signal.
450 */
451
452 /*
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000453 * Try each speed one by one, highest priority first. We do this in
454 * software because 10gb fiber doesn't support speed autonegotiation.
455 */
456 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
457 speedcnt++;
458 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
459
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000460 /* If we already have link at this speed, just jump out */
461 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
462
463 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
464 goto out;
465
466 /* Set the module link speed */
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000467 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
468 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
469
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000470 /* Allow module to change analog characteristics (1G->10G) */
471 msleep(40);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000472
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000473 status = ixgbe_setup_mac_link_82599(hw,
474 IXGBE_LINK_SPEED_10GB_FULL,
475 autoneg,
476 autoneg_wait_to_complete);
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000477 if (status != 0)
Mallikarjuna R Chilakalac3c74322009-09-01 13:50:14 +0000478 return status;
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000479
480 /* Flap the tx laser if it has not already been done */
481 if (hw->mac.autotry_restart) {
482 /* Disable tx laser; allow 100us to go dark per spec */
483 esdp_reg |= IXGBE_ESDP_SDP3;
484 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
485 udelay(100);
486
487 /* Enable tx laser; allow 2ms to light up per spec */
488 esdp_reg &= ~IXGBE_ESDP_SDP3;
489 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
490 msleep(2);
491
492 hw->mac.autotry_restart = false;
493 }
494
Don Skidmorecd7e1f02009-10-08 15:36:22 +0000495 /*
496 * Wait for the controller to acquire link. Per IEEE 802.3ap,
497 * Section 73.10.2, we may have to wait up to 500ms if KR is
498 * attempted. 82599 uses the same timing for 10g SFI.
499 */
500
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000501 for (i = 0; i < 5; i++) {
502 /* Wait for the link partner to also set speed */
503 msleep(100);
504
505 /* If we have link, just jump out */
506 hw->mac.ops.check_link(hw, &phy_link_speed,
507 &link_up, false);
508 if (link_up)
509 goto out;
510 }
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000511 }
512
513 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
514 speedcnt++;
515 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
516 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
517
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000518 /* If we already have link at this speed, just jump out */
519 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
520
521 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
522 goto out;
523
524 /* Set the module link speed */
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000525 esdp_reg &= ~IXGBE_ESDP_SDP5;
526 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
527 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
528
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000529 /* Allow module to change analog characteristics (10G->1G) */
530 msleep(40);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000531
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000532 status = ixgbe_setup_mac_link_82599(hw,
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000533 IXGBE_LINK_SPEED_1GB_FULL,
534 autoneg,
535 autoneg_wait_to_complete);
536 if (status != 0)
Mallikarjuna R Chilakalac3c74322009-09-01 13:50:14 +0000537 return status;
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000538
539 /* Flap the tx laser if it has not already been done */
540 if (hw->mac.autotry_restart) {
541 /* Disable tx laser; allow 100us to go dark per spec */
542 esdp_reg |= IXGBE_ESDP_SDP3;
543 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
544 udelay(100);
545
546 /* Enable tx laser; allow 2ms to light up per spec */
547 esdp_reg &= ~IXGBE_ESDP_SDP3;
548 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
549 msleep(2);
550
551 hw->mac.autotry_restart = false;
552 }
553
554 /* Wait for the link partner to also set speed */
555 msleep(100);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000556
557 /* If we have link, just jump out */
558 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
559 if (link_up)
560 goto out;
561 }
562
563 /*
564 * We didn't get link. Configure back to the highest speed we tried,
565 * (if there was more than one). We call ourselves back with just the
566 * single highest speed that the user requested.
567 */
568 if (speedcnt > 1)
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000569 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
570 highest_link_speed,
571 autoneg,
572 autoneg_wait_to_complete);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000573
574out:
Mallikarjuna R Chilakalac3c74322009-09-01 13:50:14 +0000575 /* Set autoneg_advertised value based on input link speed */
576 hw->phy.autoneg_advertised = 0;
577
578 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
579 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
580
581 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
582 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
583
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000584 return status;
585}
586
587/**
Don Skidmorecd7e1f02009-10-08 15:36:22 +0000588 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
589 * @hw: pointer to hardware structure
590 * @speed: new link speed
591 * @autoneg: true if autonegotiation enabled
592 * @autoneg_wait_to_complete: true when waiting for completion is needed
593 *
594 * Implements the Intel SmartSpeed algorithm.
595 **/
596static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
597 ixgbe_link_speed speed, bool autoneg,
598 bool autoneg_wait_to_complete)
599{
600 s32 status = 0;
601 ixgbe_link_speed link_speed;
602 s32 i, j;
603 bool link_up = false;
604 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
605
606 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
607
608 /* Set autoneg_advertised value based on input link speed */
609 hw->phy.autoneg_advertised = 0;
610
611 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
612 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
613
614 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
615 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
616
617 if (speed & IXGBE_LINK_SPEED_100_FULL)
618 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
619
620 /*
621 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
622 * autoneg advertisement if link is unable to be established at the
623 * highest negotiated rate. This can sometimes happen due to integrity
624 * issues with the physical media connection.
625 */
626
627 /* First, try to get link with full advertisement */
628 hw->phy.smart_speed_active = false;
629 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
630 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
631 autoneg_wait_to_complete);
632 if (status)
633 goto out;
634
635 /*
636 * Wait for the controller to acquire link. Per IEEE 802.3ap,
637 * Section 73.10.2, we may have to wait up to 500ms if KR is
638 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
639 * Table 9 in the AN MAS.
640 */
641 for (i = 0; i < 5; i++) {
642 mdelay(100);
643
644 /* If we have link, just jump out */
645 hw->mac.ops.check_link(hw, &link_speed,
646 &link_up, false);
647 if (link_up)
648 goto out;
649 }
650 }
651
652 /*
653 * We didn't get link. If we advertised KR plus one of KX4/KX
654 * (or BX4/BX), then disable KR and try again.
655 */
656 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
657 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
658 goto out;
659
660 /* Turn SmartSpeed on to disable KR support */
661 hw->phy.smart_speed_active = true;
662 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
663 autoneg_wait_to_complete);
664 if (status)
665 goto out;
666
667 /*
668 * Wait for the controller to acquire link. 600ms will allow for
669 * the AN link_fail_inhibit_timer as well for multiple cycles of
670 * parallel detect, both 10g and 1g. This allows for the maximum
671 * connect attempts as defined in the AN MAS table 73-7.
672 */
673 for (i = 0; i < 6; i++) {
674 mdelay(100);
675
676 /* If we have link, just jump out */
677 hw->mac.ops.check_link(hw, &link_speed,
678 &link_up, false);
679 if (link_up)
680 goto out;
681 }
682
683 /* We didn't get link. Turn SmartSpeed back off. */
684 hw->phy.smart_speed_active = false;
685 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
686 autoneg_wait_to_complete);
687
688out:
689 return status;
690}
691
692/**
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000693 * ixgbe_check_mac_link_82599 - Determine link and speed status
694 * @hw: pointer to hardware structure
695 * @speed: pointer to link speed
696 * @link_up: true when link is up
697 * @link_up_wait_to_complete: bool used to wait for link up or not
698 *
699 * Reads the links register to determine if link is up and the current speed
700 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +0000701static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
702 ixgbe_link_speed *speed,
703 bool *link_up,
704 bool link_up_wait_to_complete)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000705{
706 u32 links_reg;
707 u32 i;
708
709 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
710 if (link_up_wait_to_complete) {
711 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
712 if (links_reg & IXGBE_LINKS_UP) {
713 *link_up = true;
714 break;
715 } else {
716 *link_up = false;
717 }
718 msleep(100);
719 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
720 }
721 } else {
722 if (links_reg & IXGBE_LINKS_UP)
723 *link_up = true;
724 else
725 *link_up = false;
726 }
727
728 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
729 IXGBE_LINKS_SPEED_10G_82599)
730 *speed = IXGBE_LINK_SPEED_10GB_FULL;
731 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
732 IXGBE_LINKS_SPEED_1G_82599)
733 *speed = IXGBE_LINK_SPEED_1GB_FULL;
734 else
735 *speed = IXGBE_LINK_SPEED_100_FULL;
736
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +0000737 /* if link is down, zero out the current_mode */
738 if (*link_up == false) {
739 hw->fc.current_mode = ixgbe_fc_none;
740 hw->fc.fc_was_autonegged = false;
741 }
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000742
743 return 0;
744}
745
746/**
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000747 * ixgbe_setup_mac_link_82599 - Set MAC link speed
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000748 * @hw: pointer to hardware structure
749 * @speed: new link speed
750 * @autoneg: true if autonegotiation enabled
751 * @autoneg_wait_to_complete: true when waiting for completion is needed
752 *
753 * Set the link speed in the AUTOC register and restarts link.
754 **/
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000755s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
756 ixgbe_link_speed speed, bool autoneg,
757 bool autoneg_wait_to_complete)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000758{
759 s32 status = 0;
760 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
761 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000762 u32 start_autoc = autoc;
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000763 u32 orig_autoc = 0;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000764 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
765 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
766 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
767 u32 links_reg;
768 u32 i;
769 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
770
771 /* Check to see if speed passed in is supported. */
772 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
773 speed &= link_capabilities;
774
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000775 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
776 status = IXGBE_ERR_LINK_SETUP;
777 goto out;
778 }
779
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000780 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
781 if (hw->mac.orig_link_settings_stored)
782 orig_autoc = hw->mac.orig_autoc;
783 else
784 orig_autoc = autoc;
785
786
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000787 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
788 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
789 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000790 /* Set KX4/KX/KR support according to speed requested */
791 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
792 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
PJ Waskiewicz1eb99d52009-04-09 22:28:33 +0000793 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000794 autoc |= IXGBE_AUTOC_KX4_SUPP;
Don Skidmorecd7e1f02009-10-08 15:36:22 +0000795 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
796 (hw->phy.smart_speed_active == false))
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000797 autoc |= IXGBE_AUTOC_KR_SUPP;
798 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
799 autoc |= IXGBE_AUTOC_KX_SUPP;
800 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
801 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
802 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
803 /* Switch from 1G SFI to 10G SFI if requested */
804 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
805 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
806 autoc &= ~IXGBE_AUTOC_LMS_MASK;
807 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
808 }
809 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
810 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
811 /* Switch from 10G SFI to 1G SFI if requested */
812 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
813 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
814 autoc &= ~IXGBE_AUTOC_LMS_MASK;
815 if (autoneg)
816 autoc |= IXGBE_AUTOC_LMS_1G_AN;
817 else
818 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
819 }
820 }
821
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000822 if (autoc != start_autoc) {
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000823 /* Restart link */
824 autoc |= IXGBE_AUTOC_AN_RESTART;
825 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
826
827 /* Only poll for autoneg to complete if specified to do so */
828 if (autoneg_wait_to_complete) {
829 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
830 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
831 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
832 links_reg = 0; /*Just in case Autoneg time=0*/
833 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
834 links_reg =
835 IXGBE_READ_REG(hw, IXGBE_LINKS);
836 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
837 break;
838 msleep(100);
839 }
840 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
841 status =
842 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
843 hw_dbg(hw, "Autoneg did not "
844 "complete.\n");
845 }
846 }
847 }
848
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000849 /* Add delay to filter out noises during initial link setup */
850 msleep(50);
851 }
852
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +0000853out:
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000854 return status;
855}
856
857/**
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000858 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000859 * @hw: pointer to hardware structure
860 * @speed: new link speed
861 * @autoneg: true if autonegotiation enabled
862 * @autoneg_wait_to_complete: true if waiting is needed to complete
863 *
864 * Restarts link on PHY and MAC based on settings passed in.
865 **/
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000866static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
867 ixgbe_link_speed speed,
868 bool autoneg,
869 bool autoneg_wait_to_complete)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000870{
871 s32 status;
872
873 /* Setup the PHY according to input speed */
874 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
875 autoneg_wait_to_complete);
876 /* Set up MAC */
Mallikarjuna R Chilakala8620a102009-09-01 13:49:35 +0000877 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000878
879 return status;
880}
881
882/**
883 * ixgbe_reset_hw_82599 - Perform hardware reset
884 * @hw: pointer to hardware structure
885 *
886 * Resets the hardware by resetting the transmit and receive units, masks
887 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
888 * reset.
889 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +0000890static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000891{
892 s32 status = 0;
893 u32 ctrl, ctrl_ext;
894 u32 i;
895 u32 autoc;
896 u32 autoc2;
897
898 /* Call adapter stop to disable tx/rx and clear interrupts */
899 hw->mac.ops.stop_adapter(hw);
900
PJ Waskiewicz553b4492009-04-09 22:28:15 +0000901 /* PHY ops must be identified and initialized prior to reset */
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000902
PJ Waskiewicz553b4492009-04-09 22:28:15 +0000903 /* Init PHY and function pointers, perform SFP setup */
904 status = hw->phy.ops.init(hw);
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000905
PJ Waskiewicz553b4492009-04-09 22:28:15 +0000906 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
907 goto reset_hw_out;
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000908
PJ Waskiewicz553b4492009-04-09 22:28:15 +0000909 /* Setup SFP module if there is one present. */
910 if (hw->phy.sfp_setup_needed) {
911 status = hw->mac.ops.setup_sfp(hw);
912 hw->phy.sfp_setup_needed = false;
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000913 }
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000914
PJ Waskiewicz553b4492009-04-09 22:28:15 +0000915 /* Reset PHY */
916 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
917 hw->phy.ops.reset(hw);
918
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000919 /*
920 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
921 * access and verify no pending requests before reset
922 */
PJ Waskiewicz04f165e2009-04-09 22:27:57 +0000923 status = ixgbe_disable_pcie_master(hw);
924 if (status != 0) {
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000925 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
926 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
927 }
928
929 /*
930 * Issue global reset to the MAC. This needs to be a SW reset.
931 * If link reset is used, it might reset the MAC when mng is using it
932 */
933 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
934 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
935 IXGBE_WRITE_FLUSH(hw);
936
937 /* Poll for reset bit to self-clear indicating reset is complete */
938 for (i = 0; i < 10; i++) {
939 udelay(1);
940 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
941 if (!(ctrl & IXGBE_CTRL_RST))
942 break;
943 }
944 if (ctrl & IXGBE_CTRL_RST) {
945 status = IXGBE_ERR_RESET_FAILED;
946 hw_dbg(hw, "Reset polling failed to complete.\n");
947 }
948 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
949 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
950 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
951 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
952
953 msleep(50);
954
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000955 /*
956 * Store the original AUTOC/AUTOC2 values if they have not been
957 * stored off yet. Otherwise restore the stored original
958 * values since the reset operation sets back to defaults.
959 */
960 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
961 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
962 if (hw->mac.orig_link_settings_stored == false) {
963 hw->mac.orig_autoc = autoc;
964 hw->mac.orig_autoc2 = autoc2;
965 hw->mac.orig_link_settings_stored = true;
Jesse Brandeburg4df10462009-03-13 22:15:31 +0000966 } else {
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000967 if (autoc != hw->mac.orig_autoc)
968 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
969 IXGBE_AUTOC_AN_RESTART));
970
971 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
972 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
973 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
974 autoc2 |= (hw->mac.orig_autoc2 &
975 IXGBE_AUTOC2_UPPER_MASK);
976 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
977 }
978 }
979
Waskiewicz Jr, Peter Paca6bee2009-05-17 12:32:48 +0000980 /*
981 * Store MAC address from RAR0, clear receive address registers, and
982 * clear the multicast table. Also reset num_rar_entries to 128,
983 * since we modify this value when programming the SAN MAC address.
984 */
985 hw->mac.num_rar_entries = 128;
986 hw->mac.ops.init_rx_addrs(hw);
987
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000988 /* Store the permanent mac address */
989 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
990
PJ Waskiewicz0365e6e2009-05-17 12:32:25 +0000991 /* Store the permanent SAN mac address */
992 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
993
Waskiewicz Jr, Peter Paca6bee2009-05-17 12:32:48 +0000994 /* Add the SAN MAC address to the RAR only if it's a valid address */
995 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
996 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
997 hw->mac.san_addr, 0, IXGBE_RAH_AV);
998
999 /* Reserve the last RAR for the SAN MAC address */
1000 hw->mac.num_rar_entries--;
1001 }
1002
Yi Zou383ff342009-10-28 18:23:57 +00001003 /* Store the alternative WWNN/WWPN prefix */
1004 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1005 &hw->mac.wwpn_prefix);
1006
PJ Waskiewicz04f165e2009-04-09 22:27:57 +00001007reset_hw_out:
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001008 return status;
1009}
1010
1011/**
1012 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
1013 * @hw: pointer to hardware struct
1014 * @rar: receive address register index to disassociate
1015 * @vmdq: VMDq pool index to remove from the rar
1016 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001017static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001018{
1019 u32 mpsar_lo, mpsar_hi;
1020 u32 rar_entries = hw->mac.num_rar_entries;
1021
1022 if (rar < rar_entries) {
1023 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1024 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1025
1026 if (!mpsar_lo && !mpsar_hi)
1027 goto done;
1028
1029 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
1030 if (mpsar_lo) {
1031 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
1032 mpsar_lo = 0;
1033 }
1034 if (mpsar_hi) {
1035 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
1036 mpsar_hi = 0;
1037 }
1038 } else if (vmdq < 32) {
1039 mpsar_lo &= ~(1 << vmdq);
1040 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
1041 } else {
1042 mpsar_hi &= ~(1 << (vmdq - 32));
1043 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
1044 }
1045
1046 /* was that the last pool using this rar? */
1047 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
1048 hw->mac.ops.clear_rar(hw, rar);
1049 } else {
1050 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1051 }
1052
1053done:
1054 return 0;
1055}
1056
1057/**
1058 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
1059 * @hw: pointer to hardware struct
1060 * @rar: receive address register index to associate with a VMDq index
1061 * @vmdq: VMDq pool index
1062 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001063static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001064{
1065 u32 mpsar;
1066 u32 rar_entries = hw->mac.num_rar_entries;
1067
1068 if (rar < rar_entries) {
1069 if (vmdq < 32) {
1070 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
1071 mpsar |= 1 << vmdq;
1072 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
1073 } else {
1074 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
1075 mpsar |= 1 << (vmdq - 32);
1076 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
1077 }
1078 } else {
1079 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
1080 }
1081 return 0;
1082}
1083
1084/**
1085 * ixgbe_set_vfta_82599 - Set VLAN filter table
1086 * @hw: pointer to hardware structure
1087 * @vlan: VLAN id to write to VLAN filter
1088 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
1089 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
1090 *
1091 * Turn on/off specified VLAN in the VLAN filter table.
1092 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001093static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1094 bool vlan_on)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001095{
1096 u32 regindex;
Greg Rose096a58f2010-01-09 02:26:26 +00001097 u32 vlvf_index;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001098 u32 bitindex;
1099 u32 bits;
1100 u32 first_empty_slot;
Greg Rose096a58f2010-01-09 02:26:26 +00001101 u32 vt_ctl;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001102
1103 if (vlan > 4095)
1104 return IXGBE_ERR_PARAM;
1105
1106 /*
1107 * this is a 2 part operation - first the VFTA, then the
1108 * VLVF and VLVFB if vind is set
1109 */
1110
1111 /* Part 1
1112 * The VFTA is a bitstring made up of 128 32-bit registers
1113 * that enable the particular VLAN id, much like the MTA:
1114 * bits[11-5]: which register
1115 * bits[4-0]: which bit in the register
1116 */
1117 regindex = (vlan >> 5) & 0x7F;
1118 bitindex = vlan & 0x1F;
1119 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1120 if (vlan_on)
1121 bits |= (1 << bitindex);
1122 else
1123 bits &= ~(1 << bitindex);
1124 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1125
1126
1127 /* Part 2
Greg Rose096a58f2010-01-09 02:26:26 +00001128 * If VT mode is set
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001129 * Either vlan_on
1130 * make sure the vlan is in VLVF
1131 * set the vind bit in the matching VLVFB
1132 * Or !vlan_on
1133 * clear the pool bit and possibly the vind
1134 */
Greg Rose096a58f2010-01-09 02:26:26 +00001135 vt_ctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1136 if (!(vt_ctl & IXGBE_VT_CTL_VT_ENABLE))
1137 goto out;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001138
Greg Rose096a58f2010-01-09 02:26:26 +00001139 /* find the vlanid or the first empty slot */
1140 first_empty_slot = 0;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001141
Greg Rose096a58f2010-01-09 02:26:26 +00001142 for (vlvf_index = 1; vlvf_index < IXGBE_VLVF_ENTRIES; vlvf_index++) {
1143 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(vlvf_index));
1144 if (!bits && !first_empty_slot)
1145 first_empty_slot = vlvf_index;
1146 else if ((bits & 0x0FFF) == vlan)
1147 break;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001148 }
1149
Greg Rose096a58f2010-01-09 02:26:26 +00001150 if (vlvf_index >= IXGBE_VLVF_ENTRIES) {
1151 if (first_empty_slot)
1152 vlvf_index = first_empty_slot;
1153 else {
1154 hw_dbg(hw, "No space in VLVF.\n");
1155 goto out;
1156 }
1157 }
1158
1159 if (vlan_on) {
1160 /* set the pool bit */
1161 if (vind < 32) {
1162 bits = IXGBE_READ_REG(hw,
1163 IXGBE_VLVFB(vlvf_index * 2));
1164 bits |= (1 << vind);
1165 IXGBE_WRITE_REG(hw,
1166 IXGBE_VLVFB(vlvf_index * 2), bits);
1167 } else {
1168 bits = IXGBE_READ_REG(hw,
1169 IXGBE_VLVFB((vlvf_index * 2) + 1));
1170 bits |= (1 << (vind - 32));
1171 IXGBE_WRITE_REG(hw,
1172 IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
1173 }
1174 } else {
1175 /* clear the pool bit */
1176 if (vind < 32) {
1177 bits = IXGBE_READ_REG(hw,
1178 IXGBE_VLVFB(vlvf_index * 2));
1179 bits &= ~(1 << vind);
1180 IXGBE_WRITE_REG(hw,
1181 IXGBE_VLVFB(vlvf_index * 2), bits);
1182 bits |= IXGBE_READ_REG(hw,
1183 IXGBE_VLVFB((vlvf_index * 2) + 1));
1184 } else {
1185 bits = IXGBE_READ_REG(hw,
1186 IXGBE_VLVFB((vlvf_index * 2) + 1));
1187 bits &= ~(1 << (vind - 32));
1188 IXGBE_WRITE_REG(hw,
1189 IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
1190 bits |= IXGBE_READ_REG(hw,
1191 IXGBE_VLVFB(vlvf_index * 2));
1192 }
1193 }
1194
1195 if (bits) {
1196 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
1197 (IXGBE_VLVF_VIEN | vlan));
1198 /* if bits is non-zero then some pools/VFs are still
1199 * using this VLAN ID. Force the VFTA entry to on */
1200 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1201 bits |= (1 << bitindex);
1202 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1203 }
1204 else
1205 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
1206
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001207out:
1208 return 0;
1209}
1210
1211/**
1212 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1213 * @hw: pointer to hardware structure
1214 *
1215 * Clears the VLAN filer table, and the VMDq index associated with the filter
1216 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001217static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001218{
1219 u32 offset;
1220
1221 for (offset = 0; offset < hw->mac.vft_size; offset++)
1222 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1223
1224 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1225 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1226 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1227 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1228 }
1229
1230 return 0;
1231}
1232
1233/**
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001234 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1235 * @hw: pointer to hardware structure
1236 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001237static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00001238{
1239 int i;
1240 hw_dbg(hw, " Clearing UTA\n");
1241
1242 for (i = 0; i < 128; i++)
1243 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1244
1245 return 0;
1246}
1247
1248/**
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00001249 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1250 * @hw: pointer to hardware structure
1251 **/
1252s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1253{
1254 int i;
1255 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1256 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1257
1258 /*
1259 * Before starting reinitialization process,
1260 * FDIRCMD.CMD must be zero.
1261 */
1262 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1263 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1264 IXGBE_FDIRCMD_CMD_MASK))
1265 break;
1266 udelay(10);
1267 }
1268 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1269 hw_dbg(hw ,"Flow Director previous command isn't complete, "
1270 "aborting table re-initialization. \n");
1271 return IXGBE_ERR_FDIR_REINIT_FAILED;
1272 }
1273
1274 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1275 IXGBE_WRITE_FLUSH(hw);
1276 /*
1277 * 82599 adapters flow director init flow cannot be restarted,
1278 * Workaround 82599 silicon errata by performing the following steps
1279 * before re-writing the FDIRCTRL control register with the same value.
1280 * - write 1 to bit 8 of FDIRCMD register &
1281 * - write 0 to bit 8 of FDIRCMD register
1282 */
1283 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1284 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1285 IXGBE_FDIRCMD_CLEARHT));
1286 IXGBE_WRITE_FLUSH(hw);
1287 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1288 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1289 ~IXGBE_FDIRCMD_CLEARHT));
1290 IXGBE_WRITE_FLUSH(hw);
1291 /*
1292 * Clear FDIR Hash register to clear any leftover hashes
1293 * waiting to be programmed.
1294 */
1295 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1296 IXGBE_WRITE_FLUSH(hw);
1297
1298 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1299 IXGBE_WRITE_FLUSH(hw);
1300
1301 /* Poll init-done after we write FDIRCTRL register */
1302 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1303 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1304 IXGBE_FDIRCTRL_INIT_DONE)
1305 break;
1306 udelay(10);
1307 }
1308 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1309 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1310 return IXGBE_ERR_FDIR_REINIT_FAILED;
1311 }
1312
1313 /* Clear FDIR statistics registers (read to clear) */
1314 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1315 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1316 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1317 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1318 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1319
1320 return 0;
1321}
1322
1323/**
1324 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1325 * @hw: pointer to hardware structure
1326 * @pballoc: which mode to allocate filters with
1327 **/
1328s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1329{
1330 u32 fdirctrl = 0;
1331 u32 pbsize;
1332 int i;
1333
1334 /*
1335 * Before enabling Flow Director, the Rx Packet Buffer size
1336 * must be reduced. The new value is the current size minus
1337 * flow director memory usage size.
1338 */
1339 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1340 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1341 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1342
1343 /*
1344 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1345 * intialized to zero for non DCB mode otherwise actual total RX PB
1346 * would be bigger than programmed and filter space would run into
1347 * the PB 0 region.
1348 */
1349 for (i = 1; i < 8; i++)
1350 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1351
1352 /* Send interrupt when 64 filters are left */
1353 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1354
1355 /* Set the maximum length per hash bucket to 0xA filters */
1356 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1357
1358 switch (pballoc) {
1359 case IXGBE_FDIR_PBALLOC_64K:
1360 /* 8k - 1 signature filters */
1361 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1362 break;
1363 case IXGBE_FDIR_PBALLOC_128K:
1364 /* 16k - 1 signature filters */
1365 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1366 break;
1367 case IXGBE_FDIR_PBALLOC_256K:
1368 /* 32k - 1 signature filters */
1369 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1370 break;
1371 default:
1372 /* bad value */
1373 return IXGBE_ERR_CONFIG;
1374 };
1375
1376 /* Move the flexible bytes to use the ethertype - shift 6 words */
1377 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1378
1379 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1380
1381 /* Prime the keys for hashing */
1382 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1383 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1384 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1385 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1386
1387 /*
1388 * Poll init-done after we write the register. Estimated times:
1389 * 10G: PBALLOC = 11b, timing is 60us
1390 * 1G: PBALLOC = 11b, timing is 600us
1391 * 100M: PBALLOC = 11b, timing is 6ms
1392 *
1393 * Multiple these timings by 4 if under full Rx load
1394 *
1395 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1396 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1397 * this might not finish in our poll time, but we can live with that
1398 * for now.
1399 */
1400 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1401 IXGBE_WRITE_FLUSH(hw);
1402 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1403 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1404 IXGBE_FDIRCTRL_INIT_DONE)
1405 break;
1406 msleep(1);
1407 }
1408 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1409 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1410
1411 return 0;
1412}
1413
1414/**
1415 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1416 * @hw: pointer to hardware structure
1417 * @pballoc: which mode to allocate filters with
1418 **/
1419s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1420{
1421 u32 fdirctrl = 0;
1422 u32 pbsize;
1423 int i;
1424
1425 /*
1426 * Before enabling Flow Director, the Rx Packet Buffer size
1427 * must be reduced. The new value is the current size minus
1428 * flow director memory usage size.
1429 */
1430 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1431 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1432 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1433
1434 /*
1435 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1436 * intialized to zero for non DCB mode otherwise actual total RX PB
1437 * would be bigger than programmed and filter space would run into
1438 * the PB 0 region.
1439 */
1440 for (i = 1; i < 8; i++)
1441 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1442
1443 /* Send interrupt when 64 filters are left */
1444 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1445
1446 switch (pballoc) {
1447 case IXGBE_FDIR_PBALLOC_64K:
1448 /* 2k - 1 perfect filters */
1449 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1450 break;
1451 case IXGBE_FDIR_PBALLOC_128K:
1452 /* 4k - 1 perfect filters */
1453 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1454 break;
1455 case IXGBE_FDIR_PBALLOC_256K:
1456 /* 8k - 1 perfect filters */
1457 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1458 break;
1459 default:
1460 /* bad value */
1461 return IXGBE_ERR_CONFIG;
1462 };
1463
1464 /* Turn perfect match filtering on */
1465 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1466 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1467
1468 /* Move the flexible bytes to use the ethertype - shift 6 words */
1469 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1470
1471 /* Prime the keys for hashing */
1472 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1473 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1474 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1475 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1476
1477 /*
1478 * Poll init-done after we write the register. Estimated times:
1479 * 10G: PBALLOC = 11b, timing is 60us
1480 * 1G: PBALLOC = 11b, timing is 600us
1481 * 100M: PBALLOC = 11b, timing is 6ms
1482 *
1483 * Multiple these timings by 4 if under full Rx load
1484 *
1485 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1486 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1487 * this might not finish in our poll time, but we can live with that
1488 * for now.
1489 */
1490
1491 /* Set the maximum length per hash bucket to 0xA filters */
1492 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1493
1494 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1495 IXGBE_WRITE_FLUSH(hw);
1496 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1497 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1498 IXGBE_FDIRCTRL_INIT_DONE)
1499 break;
1500 msleep(1);
1501 }
1502 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1503 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1504
1505 return 0;
1506}
1507
1508
1509/**
1510 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1511 * @stream: input bitstream to compute the hash on
1512 * @key: 32-bit hash key
1513 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001514static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1515 u32 key)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00001516{
1517 /*
1518 * The algorithm is as follows:
1519 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1520 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1521 * and A[n] x B[n] is bitwise AND between same length strings
1522 *
1523 * K[n] is 16 bits, defined as:
1524 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1525 * for n modulo 32 < 15, K[n] =
1526 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1527 *
1528 * S[n] is 16 bits, defined as:
1529 * for n >= 15, S[n] = S[n:n - 15]
1530 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1531 *
1532 * To simplify for programming, the algorithm is implemented
1533 * in software this way:
1534 *
1535 * Key[31:0], Stream[335:0]
1536 *
1537 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1538 * int_key[350:0] = tmp_key[351:1]
1539 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1540 *
1541 * hash[15:0] = 0;
1542 * for (i = 0; i < 351; i++) {
1543 * if (int_key[i])
1544 * hash ^= int_stream[(i + 15):i];
1545 * }
1546 */
1547
1548 union {
1549 u64 fill[6];
1550 u32 key[11];
1551 u8 key_stream[44];
1552 } tmp_key;
1553
1554 u8 *stream = (u8 *)atr_input;
1555 u8 int_key[44]; /* upper-most bit unused */
1556 u8 hash_str[46]; /* upper-most 2 bits unused */
1557 u16 hash_result = 0;
1558 int i, j, k, h;
1559
1560 /*
1561 * Initialize the fill member to prevent warnings
1562 * on some compilers
1563 */
1564 tmp_key.fill[0] = 0;
1565
1566 /* First load the temporary key stream */
1567 for (i = 0; i < 6; i++) {
1568 u64 fillkey = ((u64)key << 32) | key;
1569 tmp_key.fill[i] = fillkey;
1570 }
1571
1572 /*
1573 * Set the interim key for the hashing. Bit 352 is unused, so we must
1574 * shift and compensate when building the key.
1575 */
1576
1577 int_key[0] = tmp_key.key_stream[0] >> 1;
1578 for (i = 1, j = 0; i < 44; i++) {
1579 unsigned int this_key = tmp_key.key_stream[j] << 7;
1580 j++;
1581 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1582 }
1583
1584 /*
1585 * Set the interim bit string for the hashing. Bits 368 and 367 are
1586 * unused, so shift and compensate when building the string.
1587 */
1588 hash_str[0] = (stream[40] & 0x7f) >> 1;
1589 for (i = 1, j = 40; i < 46; i++) {
1590 unsigned int this_str = stream[j] << 7;
1591 j++;
1592 if (j > 41)
1593 j = 0;
1594 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1595 }
1596
1597 /*
1598 * Now compute the hash. i is the index into hash_str, j is into our
1599 * key stream, k is counting the number of bits, and h interates within
1600 * each byte.
1601 */
1602 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1603 for (h = 0; h < 8 && k < 351; h++, k++) {
1604 if (int_key[j] & (1 << h)) {
1605 /*
1606 * Key bit is set, XOR in the current 16-bit
1607 * string. Example of processing:
1608 * h = 0,
1609 * tmp = (hash_str[i - 2] & 0 << 16) |
1610 * (hash_str[i - 1] & 0xff << 8) |
1611 * (hash_str[i] & 0xff >> 0)
1612 * So tmp = hash_str[15 + k:k], since the
1613 * i + 2 clause rolls off the 16-bit value
1614 * h = 7,
1615 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1616 * (hash_str[i - 1] & 0xff << 1) |
1617 * (hash_str[i] & 0x80 >> 7)
1618 */
1619 int tmp = (hash_str[i] >> h);
1620 tmp |= (hash_str[i - 1] << (8 - h));
1621 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1622 << (16 - h);
1623 hash_result ^= (u16)tmp;
1624 }
1625 }
1626 }
1627
1628 return hash_result;
1629}
1630
1631/**
1632 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1633 * @input: input stream to modify
1634 * @vlan: the VLAN id to load
1635 **/
1636s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1637{
1638 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1639 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1640
1641 return 0;
1642}
1643
1644/**
1645 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1646 * @input: input stream to modify
1647 * @src_addr: the IP address to load
1648 **/
1649s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1650{
1651 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1652 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1653 (src_addr >> 16) & 0xff;
1654 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1655 (src_addr >> 8) & 0xff;
1656 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1657
1658 return 0;
1659}
1660
1661/**
1662 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1663 * @input: input stream to modify
1664 * @dst_addr: the IP address to load
1665 **/
1666s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1667{
1668 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1669 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1670 (dst_addr >> 16) & 0xff;
1671 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1672 (dst_addr >> 8) & 0xff;
1673 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1674
1675 return 0;
1676}
1677
1678/**
1679 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1680 * @input: input stream to modify
1681 * @src_addr_1: the first 4 bytes of the IP address to load
1682 * @src_addr_2: the second 4 bytes of the IP address to load
1683 * @src_addr_3: the third 4 bytes of the IP address to load
1684 * @src_addr_4: the fourth 4 bytes of the IP address to load
1685 **/
1686s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001687 u32 src_addr_1, u32 src_addr_2,
1688 u32 src_addr_3, u32 src_addr_4)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00001689{
1690 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1691 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1692 (src_addr_4 >> 8) & 0xff;
1693 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1694 (src_addr_4 >> 16) & 0xff;
1695 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1696
1697 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1698 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1699 (src_addr_3 >> 8) & 0xff;
1700 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1701 (src_addr_3 >> 16) & 0xff;
1702 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1703
1704 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1705 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1706 (src_addr_2 >> 8) & 0xff;
1707 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1708 (src_addr_2 >> 16) & 0xff;
1709 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1710
1711 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1712 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1713 (src_addr_1 >> 8) & 0xff;
1714 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1715 (src_addr_1 >> 16) & 0xff;
1716 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1717
1718 return 0;
1719}
1720
1721/**
1722 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1723 * @input: input stream to modify
1724 * @dst_addr_1: the first 4 bytes of the IP address to load
1725 * @dst_addr_2: the second 4 bytes of the IP address to load
1726 * @dst_addr_3: the third 4 bytes of the IP address to load
1727 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1728 **/
1729s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001730 u32 dst_addr_1, u32 dst_addr_2,
1731 u32 dst_addr_3, u32 dst_addr_4)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00001732{
1733 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1734 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1735 (dst_addr_4 >> 8) & 0xff;
1736 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1737 (dst_addr_4 >> 16) & 0xff;
1738 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1739
1740 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1741 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1742 (dst_addr_3 >> 8) & 0xff;
1743 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1744 (dst_addr_3 >> 16) & 0xff;
1745 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1746
1747 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1748 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1749 (dst_addr_2 >> 8) & 0xff;
1750 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1751 (dst_addr_2 >> 16) & 0xff;
1752 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1753
1754 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1755 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1756 (dst_addr_1 >> 8) & 0xff;
1757 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1758 (dst_addr_1 >> 16) & 0xff;
1759 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1760
1761 return 0;
1762}
1763
1764/**
1765 * ixgbe_atr_set_src_port_82599 - Sets the source port
1766 * @input: input stream to modify
1767 * @src_port: the source port to load
1768 **/
1769s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1770{
1771 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1772 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1773
1774 return 0;
1775}
1776
1777/**
1778 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1779 * @input: input stream to modify
1780 * @dst_port: the destination port to load
1781 **/
1782s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1783{
1784 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1785 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1786
1787 return 0;
1788}
1789
1790/**
1791 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1792 * @input: input stream to modify
1793 * @flex_bytes: the flexible bytes to load
1794 **/
1795s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1796{
1797 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1798 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1799
1800 return 0;
1801}
1802
1803/**
1804 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1805 * @input: input stream to modify
1806 * @vm_pool: the Virtual Machine pool to load
1807 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001808s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
1809 u8 vm_pool)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00001810{
1811 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1812
1813 return 0;
1814}
1815
1816/**
1817 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1818 * @input: input stream to modify
1819 * @l4type: the layer 4 type value to load
1820 **/
1821s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1822{
1823 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1824
1825 return 0;
1826}
1827
1828/**
1829 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1830 * @input: input stream to search
1831 * @vlan: the VLAN id to load
1832 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001833static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input,
1834 u16 *vlan)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00001835{
1836 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1837 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1838
1839 return 0;
1840}
1841
1842/**
1843 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1844 * @input: input stream to search
1845 * @src_addr: the IP address to load
1846 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001847static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1848 u32 *src_addr)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00001849{
1850 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1851 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1852 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1853 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1854
1855 return 0;
1856}
1857
1858/**
1859 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1860 * @input: input stream to search
1861 * @dst_addr: the IP address to load
1862 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001863static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1864 u32 *dst_addr)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00001865{
1866 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1867 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1868 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1869 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1870
1871 return 0;
1872}
1873
1874/**
1875 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1876 * @input: input stream to search
1877 * @src_addr_1: the first 4 bytes of the IP address to load
1878 * @src_addr_2: the second 4 bytes of the IP address to load
1879 * @src_addr_3: the third 4 bytes of the IP address to load
1880 * @src_addr_4: the fourth 4 bytes of the IP address to load
1881 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001882static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1883 u32 *src_addr_1, u32 *src_addr_2,
1884 u32 *src_addr_3, u32 *src_addr_4)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00001885{
1886 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1887 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1888 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1889 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1890
1891 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1892 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1893 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1894 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1895
1896 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1897 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1898 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1899 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1900
1901 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1902 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1903 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1904 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1905
1906 return 0;
1907}
1908
1909/**
1910 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1911 * @input: input stream to search
1912 * @dst_addr_1: the first 4 bytes of the IP address to load
1913 * @dst_addr_2: the second 4 bytes of the IP address to load
1914 * @dst_addr_3: the third 4 bytes of the IP address to load
1915 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1916 **/
1917s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001918 u32 *dst_addr_1, u32 *dst_addr_2,
1919 u32 *dst_addr_3, u32 *dst_addr_4)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00001920{
1921 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1922 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1923 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1924 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1925
1926 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1927 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1928 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1929 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1930
1931 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1932 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1933 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1934 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1935
1936 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1937 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1938 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1939 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1940
1941 return 0;
1942}
1943
1944/**
1945 * ixgbe_atr_get_src_port_82599 - Gets the source port
1946 * @input: input stream to modify
1947 * @src_port: the source port to load
1948 *
1949 * Even though the input is given in big-endian, the FDIRPORT registers
1950 * expect the ports to be programmed in little-endian. Hence the need to swap
1951 * endianness when retrieving the data. This can be confusing since the
1952 * internal hash engine expects it to be big-endian.
1953 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001954static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1955 u16 *src_port)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00001956{
1957 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1958 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1959
1960 return 0;
1961}
1962
1963/**
1964 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1965 * @input: input stream to modify
1966 * @dst_port: the destination port to load
1967 *
1968 * Even though the input is given in big-endian, the FDIRPORT registers
1969 * expect the ports to be programmed in little-endian. Hence the need to swap
1970 * endianness when retrieving the data. This can be confusing since the
1971 * internal hash engine expects it to be big-endian.
1972 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001973static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1974 u16 *dst_port)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00001975{
1976 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1977 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1978
1979 return 0;
1980}
1981
1982/**
1983 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1984 * @input: input stream to modify
1985 * @flex_bytes: the flexible bytes to load
1986 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00001987static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1988 u16 *flex_byte)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00001989{
1990 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1991 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1992
1993 return 0;
1994}
1995
1996/**
1997 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1998 * @input: input stream to modify
1999 * @vm_pool: the Virtual Machine pool to load
2000 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00002001s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
2002 u8 *vm_pool)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00002003{
2004 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
2005
2006 return 0;
2007}
2008
2009/**
2010 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
2011 * @input: input stream to modify
2012 * @l4type: the layer 4 type value to load
2013 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00002014static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
2015 u8 *l4type)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00002016{
2017 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
2018
2019 return 0;
2020}
2021
2022/**
2023 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
2024 * @hw: pointer to hardware structure
2025 * @stream: input bitstream
2026 * @queue: queue index to direct traffic to
2027 **/
2028s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
2029 struct ixgbe_atr_input *input,
2030 u8 queue)
2031{
2032 u64 fdirhashcmd;
2033 u64 fdircmd;
2034 u32 fdirhash;
2035 u16 bucket_hash, sig_hash;
2036 u8 l4type;
2037
2038 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2039 IXGBE_ATR_BUCKET_HASH_KEY);
2040
2041 /* bucket_hash is only 15 bits */
2042 bucket_hash &= IXGBE_ATR_HASH_MASK;
2043
2044 sig_hash = ixgbe_atr_compute_hash_82599(input,
2045 IXGBE_ATR_SIGNATURE_HASH_KEY);
2046
2047 /* Get the l4type in order to program FDIRCMD properly */
2048 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
2049 ixgbe_atr_get_l4type_82599(input, &l4type);
2050
2051 /*
2052 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
2053 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
2054 */
2055 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2056
2057 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
2058 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
2059
2060 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2061 case IXGBE_ATR_L4TYPE_TCP:
2062 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2063 break;
2064 case IXGBE_ATR_L4TYPE_UDP:
2065 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2066 break;
2067 case IXGBE_ATR_L4TYPE_SCTP:
2068 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2069 break;
2070 default:
2071 hw_dbg(hw, "Error on l4type input\n");
2072 return IXGBE_ERR_CONFIG;
2073 }
2074
2075 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
2076 fdircmd |= IXGBE_FDIRCMD_IPV6;
2077
2078 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
2079 fdirhashcmd = ((fdircmd << 32) | fdirhash);
2080
2081 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
2082
2083 return 0;
2084}
2085
2086/**
2087 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
2088 * @hw: pointer to hardware structure
2089 * @input: input bitstream
2090 * @queue: queue index to direct traffic to
2091 *
2092 * Note that the caller to this function must lock before calling, since the
2093 * hardware writes must be protected from one another.
2094 **/
2095s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
Don Skidmore7b25cdb2009-08-25 04:47:32 +00002096 struct ixgbe_atr_input *input,
2097 u16 soft_id,
2098 u8 queue)
Peter P Waskiewicz Jrffff4772009-06-04 16:01:25 +00002099{
2100 u32 fdircmd = 0;
2101 u32 fdirhash;
2102 u32 src_ipv4, dst_ipv4;
2103 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
2104 u16 src_port, dst_port, vlan_id, flex_bytes;
2105 u16 bucket_hash;
2106 u8 l4type;
2107
2108 /* Get our input values */
2109 ixgbe_atr_get_l4type_82599(input, &l4type);
2110
2111 /*
2112 * Check l4type formatting, and bail out before we touch the hardware
2113 * if there's a configuration issue
2114 */
2115 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
2116 case IXGBE_ATR_L4TYPE_TCP:
2117 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
2118 break;
2119 case IXGBE_ATR_L4TYPE_UDP:
2120 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
2121 break;
2122 case IXGBE_ATR_L4TYPE_SCTP:
2123 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
2124 break;
2125 default:
2126 hw_dbg(hw, "Error on l4type input\n");
2127 return IXGBE_ERR_CONFIG;
2128 }
2129
2130 bucket_hash = ixgbe_atr_compute_hash_82599(input,
2131 IXGBE_ATR_BUCKET_HASH_KEY);
2132
2133 /* bucket_hash is only 15 bits */
2134 bucket_hash &= IXGBE_ATR_HASH_MASK;
2135
2136 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
2137 ixgbe_atr_get_src_port_82599(input, &src_port);
2138 ixgbe_atr_get_dst_port_82599(input, &dst_port);
2139 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
2140
2141 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2142
2143 /* Now figure out if we're IPv4 or IPv6 */
2144 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
2145 /* IPv6 */
2146 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
2147 &src_ipv6_3, &src_ipv6_4);
2148
2149 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
2150 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
2151 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
2152 /* The last 4 bytes is the same register as IPv4 */
2153 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
2154
2155 fdircmd |= IXGBE_FDIRCMD_IPV6;
2156 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
2157 } else {
2158 /* IPv4 */
2159 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
2160 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
2161
2162 }
2163
2164 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
2165 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
2166
2167 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
2168 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
2169 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
2170 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
2171
2172 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
2173 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
2174 fdircmd |= IXGBE_FDIRCMD_LAST;
2175 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
2176 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2177
2178 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2179 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2180
2181 return 0;
2182}
2183/**
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002184 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2185 * @hw: pointer to hardware structure
2186 * @reg: analog register to read
2187 * @val: read value
2188 *
2189 * Performs read operation to Omer analog register specified.
2190 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00002191static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002192{
2193 u32 core_ctl;
2194
2195 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2196 (reg << 8));
2197 IXGBE_WRITE_FLUSH(hw);
2198 udelay(10);
2199 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2200 *val = (u8)core_ctl;
2201
2202 return 0;
2203}
2204
2205/**
2206 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2207 * @hw: pointer to hardware structure
2208 * @reg: atlas register to write
2209 * @val: value to write
2210 *
2211 * Performs write operation to Omer analog register specified.
2212 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00002213static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002214{
2215 u32 core_ctl;
2216
2217 core_ctl = (reg << 8) | val;
2218 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2219 IXGBE_WRITE_FLUSH(hw);
2220 udelay(10);
2221
2222 return 0;
2223}
2224
2225/**
2226 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2227 * @hw: pointer to hardware structure
2228 *
2229 * Starts the hardware using the generic start_hw function.
2230 * Then performs device-specific:
2231 * Clears the rate limiter registers.
2232 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00002233static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002234{
2235 u32 q_num;
Peter P Waskiewicz Jr794caeb2009-06-04 16:02:24 +00002236 s32 ret_val;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002237
Peter P Waskiewicz Jr794caeb2009-06-04 16:02:24 +00002238 ret_val = ixgbe_start_hw_generic(hw);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002239
2240 /* Clear the rate limiters */
2241 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2242 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2243 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2244 }
2245 IXGBE_WRITE_FLUSH(hw);
2246
Peter P Waskiewicz Jr50ac58b2009-06-04 11:10:53 +00002247 /* We need to run link autotry after the driver loads */
2248 hw->mac.autotry_restart = true;
2249
Peter P Waskiewicz Jr794caeb2009-06-04 16:02:24 +00002250 if (ret_val == 0)
2251 ret_val = ixgbe_verify_fw_version_82599(hw);
2252
2253 return ret_val;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002254}
2255
2256/**
2257 * ixgbe_identify_phy_82599 - Get physical layer module
2258 * @hw: pointer to hardware structure
2259 *
2260 * Determines the physical layer module found on the current adapter.
2261 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00002262static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002263{
2264 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2265 status = ixgbe_identify_phy_generic(hw);
2266 if (status != 0)
2267 status = ixgbe_identify_sfp_module_generic(hw);
2268 return status;
2269}
2270
2271/**
2272 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2273 * @hw: pointer to hardware structure
2274 *
2275 * Determines physical layer capabilities of the current configuration.
2276 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00002277static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002278{
2279 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00002280 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2281 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2282 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2283 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2284 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2285 u16 ext_ability = 0;
PJ Waskiewicz1339b9e2009-03-13 22:12:29 +00002286 u8 comp_codes_10g = 0;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002287
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00002288 hw->phy.ops.identify(hw);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002289
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00002290 if (hw->phy.type == ixgbe_phy_tn ||
2291 hw->phy.type == ixgbe_phy_cu_unknown) {
Ben Hutchings6b73e102009-04-29 08:08:58 +00002292 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2293 &ext_ability);
2294 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00002295 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
Ben Hutchings6b73e102009-04-29 08:08:58 +00002296 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00002297 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
Ben Hutchings6b73e102009-04-29 08:08:58 +00002298 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00002299 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2300 goto out;
2301 }
2302
2303 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2304 case IXGBE_AUTOC_LMS_1G_AN:
2305 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2306 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2307 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2308 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2309 goto out;
2310 } else
2311 /* SFI mode so read SFP module */
2312 goto sfp_check;
2313 break;
2314 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2315 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2316 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2317 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2318 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
Peter P Waskiewicz Jr1fcf03e2009-05-17 20:58:04 +00002319 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2320 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00002321 goto out;
2322 break;
2323 case IXGBE_AUTOC_LMS_10G_SERIAL:
2324 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2325 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2326 goto out;
2327 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2328 goto sfp_check;
2329 break;
2330 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2331 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2332 if (autoc & IXGBE_AUTOC_KX_SUPP)
2333 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2334 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2335 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2336 if (autoc & IXGBE_AUTOC_KR_SUPP)
2337 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2338 goto out;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002339 break;
2340 default:
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00002341 goto out;
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002342 break;
2343 }
2344
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00002345sfp_check:
2346 /* SFP check must be done last since DA modules are sometimes used to
2347 * test KR mode - we need to id KR mode correctly before SFP module.
2348 * Call identify_sfp because the pluggable module may have changed */
2349 hw->phy.ops.identify_sfp(hw);
2350 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2351 goto out;
2352
2353 switch (hw->phy.type) {
2354 case ixgbe_phy_tw_tyco:
2355 case ixgbe_phy_tw_unknown:
2356 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2357 break;
2358 case ixgbe_phy_sfp_avago:
2359 case ixgbe_phy_sfp_ftl:
2360 case ixgbe_phy_sfp_intel:
2361 case ixgbe_phy_sfp_unknown:
2362 hw->phy.ops.read_i2c_eeprom(hw,
2363 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2364 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2365 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2366 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2367 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2368 break;
2369 default:
2370 break;
2371 }
2372
2373out:
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002374 return physical_layer;
2375}
2376
2377/**
2378 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2379 * @hw: pointer to hardware structure
2380 * @regval: register value to write to RXCTRL
2381 *
2382 * Enables the Rx DMA unit for 82599
2383 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00002384static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002385{
2386#define IXGBE_MAX_SECRX_POLL 30
2387 int i;
2388 int secrxreg;
2389
2390 /*
2391 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2392 * If traffic is incoming before we enable the Rx unit, it could hang
2393 * the Rx DMA unit. Therefore, make sure the security engine is
2394 * completely disabled prior to enabling the Rx unit.
2395 */
2396 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2397 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2398 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2399 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2400 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2401 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2402 break;
2403 else
2404 udelay(10);
2405 }
2406
2407 /* For informational purposes only */
2408 if (i >= IXGBE_MAX_SECRX_POLL)
2409 hw_dbg(hw, "Rx unit being enabled before security "
2410 "path fully disabled. Continuing with init.\n");
2411
2412 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2413 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2414 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2415 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2416 IXGBE_WRITE_FLUSH(hw);
2417
2418 return 0;
2419}
2420
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00002421/**
2422 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2423 * @hw: pointer to hardware structure
2424 * @device_caps: the EEPROM word with the extra device capabilities
2425 *
2426 * This function will read the EEPROM location for the device capabilities,
2427 * and return the word through device_caps.
2428 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00002429static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00002430{
2431 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2432
2433 return 0;
2434}
2435
PJ Waskiewicz0365e6e2009-05-17 12:32:25 +00002436/**
2437 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2438 * @hw: pointer to hardware structure
2439 * @san_mac_offset: SAN MAC address offset
2440 *
2441 * This function will read the EEPROM location for the SAN MAC address
2442 * pointer, and returns the value at that location. This is used in both
2443 * get and set mac_addr routines.
2444 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00002445static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2446 u16 *san_mac_offset)
PJ Waskiewicz0365e6e2009-05-17 12:32:25 +00002447{
2448 /*
2449 * First read the EEPROM pointer to see if the MAC addresses are
2450 * available.
2451 */
2452 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2453
2454 return 0;
2455}
2456
2457/**
2458 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2459 * @hw: pointer to hardware structure
2460 * @san_mac_addr: SAN MAC address
2461 *
2462 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2463 * per-port, so set_lan_id() must be called before reading the addresses.
2464 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2465 * upon for non-SFP connections, so we must call it here.
2466 **/
Don Skidmore7b25cdb2009-08-25 04:47:32 +00002467static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
PJ Waskiewicz0365e6e2009-05-17 12:32:25 +00002468{
2469 u16 san_mac_data, san_mac_offset;
2470 u8 i;
2471
2472 /*
2473 * First read the EEPROM pointer to see if the MAC addresses are
2474 * available. If they're not, no point in calling set_lan_id() here.
2475 */
2476 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2477
2478 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2479 /*
2480 * No addresses available in this EEPROM. It's not an
2481 * error though, so just wipe the local address and return.
2482 */
2483 for (i = 0; i < 6; i++)
2484 san_mac_addr[i] = 0xFF;
2485
2486 goto san_mac_addr_out;
2487 }
2488
2489 /* make sure we know which port we need to program */
2490 hw->mac.ops.set_lan_id(hw);
2491 /* apply the port offset to the address offset */
2492 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2493 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2494 for (i = 0; i < 3; i++) {
2495 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2496 san_mac_addr[i * 2] = (u8)(san_mac_data);
2497 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2498 san_mac_offset++;
2499 }
2500
2501san_mac_addr_out:
2502 return 0;
2503}
2504
Peter P Waskiewicz Jr794caeb2009-06-04 16:02:24 +00002505/**
2506 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2507 * @hw: pointer to hardware structure
2508 *
2509 * Verifies that installed the firmware version is 0.6 or higher
2510 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2511 *
2512 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2513 * if the FW version is not supported.
2514 **/
2515static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2516{
2517 s32 status = IXGBE_ERR_EEPROM_VERSION;
2518 u16 fw_offset, fw_ptp_cfg_offset;
2519 u16 fw_version = 0;
2520
2521 /* firmware check is only necessary for SFI devices */
2522 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2523 status = 0;
2524 goto fw_version_out;
2525 }
2526
2527 /* get the offset to the Firmware Module block */
2528 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2529
2530 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2531 goto fw_version_out;
2532
2533 /* get the offset to the Pass Through Patch Configuration block */
2534 hw->eeprom.ops.read(hw, (fw_offset +
2535 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2536 &fw_ptp_cfg_offset);
2537
2538 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2539 goto fw_version_out;
2540
2541 /* get the firmware version */
2542 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2543 IXGBE_FW_PATCH_VERSION_4),
2544 &fw_version);
2545
2546 if (fw_version > 0x5)
2547 status = 0;
2548
2549fw_version_out:
2550 return status;
2551}
2552
Yi Zou383ff342009-10-28 18:23:57 +00002553/**
2554 * ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from
2555 * the EEPROM
2556 * @hw: pointer to hardware structure
2557 * @wwnn_prefix: the alternative WWNN prefix
2558 * @wwpn_prefix: the alternative WWPN prefix
2559 *
2560 * This function will read the EEPROM from the alternative SAN MAC address
2561 * block to check the support for the alternative WWNN/WWPN prefix support.
2562 **/
2563static s32 ixgbe_get_wwn_prefix_82599(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2564 u16 *wwpn_prefix)
2565{
2566 u16 offset, caps;
2567 u16 alt_san_mac_blk_offset;
2568
2569 /* clear output first */
2570 *wwnn_prefix = 0xFFFF;
2571 *wwpn_prefix = 0xFFFF;
2572
2573 /* check if alternative SAN MAC is supported */
2574 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2575 &alt_san_mac_blk_offset);
2576
2577 if ((alt_san_mac_blk_offset == 0) ||
2578 (alt_san_mac_blk_offset == 0xFFFF))
2579 goto wwn_prefix_out;
2580
2581 /* check capability in alternative san mac address block */
2582 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2583 hw->eeprom.ops.read(hw, offset, &caps);
2584 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2585 goto wwn_prefix_out;
2586
2587 /* get the corresponding prefix for WWNN/WWPN */
2588 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2589 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2590
2591 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2592 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2593
2594wwn_prefix_out:
2595 return 0;
2596}
2597
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002598static struct ixgbe_mac_operations mac_ops_82599 = {
2599 .init_hw = &ixgbe_init_hw_generic,
2600 .reset_hw = &ixgbe_reset_hw_82599,
2601 .start_hw = &ixgbe_start_hw_82599,
2602 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2603 .get_media_type = &ixgbe_get_media_type_82599,
2604 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2605 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2606 .get_mac_addr = &ixgbe_get_mac_addr_generic,
PJ Waskiewicz0365e6e2009-05-17 12:32:25 +00002607 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
Peter P Waskiewicz Jr04193052009-04-09 22:28:50 +00002608 .get_device_caps = &ixgbe_get_device_caps_82599,
Yi Zou383ff342009-10-28 18:23:57 +00002609 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599,
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002610 .stop_adapter = &ixgbe_stop_adapter_generic,
2611 .get_bus_info = &ixgbe_get_bus_info_generic,
2612 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2613 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2614 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2615 .setup_link = &ixgbe_setup_mac_link_82599,
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002616 .check_link = &ixgbe_check_mac_link_82599,
2617 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2618 .led_on = &ixgbe_led_on_generic,
2619 .led_off = &ixgbe_led_off_generic,
PJ Waskiewicz87c12012009-04-08 13:20:31 +00002620 .blink_led_start = &ixgbe_blink_led_start_generic,
2621 .blink_led_stop = &ixgbe_blink_led_stop_generic,
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002622 .set_rar = &ixgbe_set_rar_generic,
2623 .clear_rar = &ixgbe_clear_rar_generic,
2624 .set_vmdq = &ixgbe_set_vmdq_82599,
2625 .clear_vmdq = &ixgbe_clear_vmdq_82599,
2626 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2627 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2628 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2629 .enable_mc = &ixgbe_enable_mc_generic,
2630 .disable_mc = &ixgbe_disable_mc_generic,
2631 .clear_vfta = &ixgbe_clear_vfta_82599,
2632 .set_vfta = &ixgbe_set_vfta_82599,
Mallikarjuna R Chilakala620fa032009-06-04 11:11:13 +00002633 .fc_enable = &ixgbe_fc_enable_generic,
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002634 .init_uta_tables = &ixgbe_init_uta_tables_82599,
2635 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2636};
2637
2638static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2639 .init_params = &ixgbe_init_eeprom_params_generic,
2640 .read = &ixgbe_read_eeprom_generic,
2641 .write = &ixgbe_write_eeprom_generic,
2642 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2643 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2644};
2645
2646static struct ixgbe_phy_operations phy_ops_82599 = {
2647 .identify = &ixgbe_identify_phy_82599,
2648 .identify_sfp = &ixgbe_identify_sfp_module_generic,
PJ Waskiewicz04f165e2009-04-09 22:27:57 +00002649 .init = &ixgbe_init_phy_ops_82599,
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002650 .reset = &ixgbe_reset_phy_generic,
2651 .read_reg = &ixgbe_read_phy_reg_generic,
2652 .write_reg = &ixgbe_write_phy_reg_generic,
2653 .setup_link = &ixgbe_setup_phy_link_generic,
2654 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2655 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2656 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2657 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2658 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2659};
2660
2661struct ixgbe_info ixgbe_82599_info = {
2662 .mac = ixgbe_mac_82599EB,
2663 .get_invariants = &ixgbe_get_invariants_82599,
2664 .mac_ops = &mac_ops_82599,
2665 .eeprom_ops = &eeprom_ops_82599,
2666 .phy_ops = &phy_ops_82599,
Greg Rose096a58f2010-01-09 02:26:26 +00002667 .mbx_ops = &mbx_ops_82599,
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +00002668};