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Russell Kinge3887712010-01-14 13:30:16 +00001/*
Sudeep Holla0b7402d2015-05-18 16:29:40 +01002 * linux/drivers/clocksource/timer-sp.c
Russell Kinge3887712010-01-14 13:30:16 +00003 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
Russell King7ff550d2011-05-12 13:31:48 +010021#include <linux/clk.h>
Russell Kinge3887712010-01-14 13:30:16 +000022#include <linux/clocksource.h>
23#include <linux/clockchips.h>
Russell King7ff550d2011-05-12 13:31:48 +010024#include <linux/err.h>
Russell Kinge3887712010-01-14 13:30:16 +000025#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/io.h>
Rob Herring7a0eca72013-03-25 11:23:52 -050028#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070031#include <linux/sched_clock.h>
Russell Kinge3887712010-01-14 13:30:16 +000032
Sudeep Holla0b7402d2015-05-18 16:29:40 +010033#include <clocksource/timer-sp804.h>
34
35#include "timer-sp.h"
Russell Kinge3887712010-01-14 13:30:16 +000036
Rob Herring7a0eca72013-03-25 11:23:52 -050037static long __init sp804_get_clock_rate(struct clk *clk)
Russell King7ff550d2011-05-12 13:31:48 +010038{
Russell King7ff550d2011-05-12 13:31:48 +010039 long rate;
40 int err;
41
Russell King6f5ad962011-09-22 11:38:40 +010042 err = clk_prepare(clk);
43 if (err) {
Rob Herring7a0eca72013-03-25 11:23:52 -050044 pr_err("sp804: clock failed to prepare: %d\n", err);
Russell King6f5ad962011-09-22 11:38:40 +010045 clk_put(clk);
46 return err;
47 }
48
Russell King7ff550d2011-05-12 13:31:48 +010049 err = clk_enable(clk);
50 if (err) {
Rob Herring7a0eca72013-03-25 11:23:52 -050051 pr_err("sp804: clock failed to enable: %d\n", err);
Russell King6f5ad962011-09-22 11:38:40 +010052 clk_unprepare(clk);
Russell King7ff550d2011-05-12 13:31:48 +010053 clk_put(clk);
54 return err;
55 }
56
57 rate = clk_get_rate(clk);
58 if (rate < 0) {
Rob Herring7a0eca72013-03-25 11:23:52 -050059 pr_err("sp804: clock failed to get rate: %ld\n", rate);
Russell King7ff550d2011-05-12 13:31:48 +010060 clk_disable(clk);
Russell King6f5ad962011-09-22 11:38:40 +010061 clk_unprepare(clk);
Russell King7ff550d2011-05-12 13:31:48 +010062 clk_put(clk);
63 }
64
65 return rate;
66}
67
Rob Herringa7bf6162011-12-12 15:29:08 -060068static void __iomem *sched_clock_base;
69
Stephen Boyd9b12f3a2013-11-15 15:26:09 -080070static u64 notrace sp804_read(void)
Rob Herringa7bf6162011-12-12 15:29:08 -060071{
72 return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
73}
74
Sudeep Holla1e5f0512015-05-18 16:29:04 +010075void __init sp804_timer_disable(void __iomem *base)
76{
77 writel(0, base + TIMER_CTRL);
78}
79
Rob Herringa7bf6162011-12-12 15:29:08 -060080void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
81 const char *name,
Rob Herring7a0eca72013-03-25 11:23:52 -050082 struct clk *clk,
Rob Herringa7bf6162011-12-12 15:29:08 -060083 int use_sched_clock)
Russell Kinge3887712010-01-14 13:30:16 +000084{
Rob Herring7a0eca72013-03-25 11:23:52 -050085 long rate;
86
87 if (!clk) {
88 clk = clk_get_sys("sp804", name);
89 if (IS_ERR(clk)) {
90 pr_err("sp804: clock not found: %d\n",
91 (int)PTR_ERR(clk));
92 return;
93 }
94 }
95
96 rate = sp804_get_clock_rate(clk);
Russell King7ff550d2011-05-12 13:31:48 +010097
98 if (rate < 0)
99 return;
100
Russell Kinge3887712010-01-14 13:30:16 +0000101 /* setup timer 0 as free-running clocksource */
Russell Kingbfe45e02011-05-08 15:33:30 +0100102 writel(0, base + TIMER_CTRL);
103 writel(0xffffffff, base + TIMER_LOAD);
104 writel(0xffffffff, base + TIMER_VALUE);
Russell Kinge3887712010-01-14 13:30:16 +0000105 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
Russell Kingbfe45e02011-05-08 15:33:30 +0100106 base + TIMER_CTRL);
Russell Kinge3887712010-01-14 13:30:16 +0000107
Russell Kingfb593cf2011-05-12 12:08:23 +0100108 clocksource_mmio_init(base + TIMER_VALUE, name,
Russell King7ff550d2011-05-12 13:31:48 +0100109 rate, 200, 32, clocksource_mmio_readl_down);
Rob Herringa7bf6162011-12-12 15:29:08 -0600110
111 if (use_sched_clock) {
112 sched_clock_base = base;
Stephen Boyd9b12f3a2013-11-15 15:26:09 -0800113 sched_clock_register(sp804_read, 32, rate);
Rob Herringa7bf6162011-12-12 15:29:08 -0600114 }
Russell Kinge3887712010-01-14 13:30:16 +0000115}
116
117
118static void __iomem *clkevt_base;
Russell King23828a72011-05-12 15:45:16 +0100119static unsigned long clkevt_reload;
Russell Kinge3887712010-01-14 13:30:16 +0000120
121/*
122 * IRQ handler for the timer
123 */
124static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
125{
126 struct clock_event_device *evt = dev_id;
127
128 /* clear the interrupt */
129 writel(1, clkevt_base + TIMER_INTCLR);
130
131 evt->event_handler(evt);
132
133 return IRQ_HANDLED;
134}
135
136static void sp804_set_mode(enum clock_event_mode mode,
137 struct clock_event_device *evt)
138{
139 unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE;
140
141 writel(ctrl, clkevt_base + TIMER_CTRL);
142
143 switch (mode) {
144 case CLOCK_EVT_MODE_PERIODIC:
Russell King23828a72011-05-12 15:45:16 +0100145 writel(clkevt_reload, clkevt_base + TIMER_LOAD);
Russell Kinge3887712010-01-14 13:30:16 +0000146 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
147 break;
148
149 case CLOCK_EVT_MODE_ONESHOT:
150 /* period set, and timer enabled in 'next_event' hook */
151 ctrl |= TIMER_CTRL_ONESHOT;
152 break;
153
154 case CLOCK_EVT_MODE_UNUSED:
155 case CLOCK_EVT_MODE_SHUTDOWN:
156 default:
157 break;
158 }
159
160 writel(ctrl, clkevt_base + TIMER_CTRL);
161}
162
163static int sp804_set_next_event(unsigned long next,
164 struct clock_event_device *evt)
165{
166 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
167
168 writel(next, clkevt_base + TIMER_LOAD);
169 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
170
171 return 0;
172}
173
174static struct clock_event_device sp804_clockevent = {
Viresh Kumar887708f2013-03-02 11:10:13 +0100175 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
176 CLOCK_EVT_FEAT_DYNIRQ,
Russell Kinge3887712010-01-14 13:30:16 +0000177 .set_mode = sp804_set_mode,
178 .set_next_event = sp804_set_next_event,
179 .rating = 300,
Russell Kinge3887712010-01-14 13:30:16 +0000180};
181
182static struct irqaction sp804_timer_irq = {
183 .name = "timer",
Michael Opdenacker728fae62013-10-14 04:42:20 +0100184 .flags = IRQF_TIMER | IRQF_IRQPOLL,
Russell Kinge3887712010-01-14 13:30:16 +0000185 .handler = sp804_timer_interrupt,
186 .dev_id = &sp804_clockevent,
187};
188
Rob Herring7a0eca72013-03-25 11:23:52 -0500189void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name)
Russell Kinge3887712010-01-14 13:30:16 +0000190{
191 struct clock_event_device *evt = &sp804_clockevent;
Rob Herring7a0eca72013-03-25 11:23:52 -0500192 long rate;
Russell King23828a72011-05-12 15:45:16 +0100193
Rob Herring7a0eca72013-03-25 11:23:52 -0500194 if (!clk)
195 clk = clk_get_sys("sp804", name);
196 if (IS_ERR(clk)) {
197 pr_err("sp804: %s clock not found: %d\n", name,
198 (int)PTR_ERR(clk));
199 return;
200 }
201
202 rate = sp804_get_clock_rate(clk);
Russell King23828a72011-05-12 15:45:16 +0100203 if (rate < 0)
204 return;
Russell Kinge3887712010-01-14 13:30:16 +0000205
206 clkevt_base = base;
Russell King23828a72011-05-12 15:45:16 +0100207 clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
Russell King57cc4f72011-05-12 15:31:13 +0100208 evt->name = name;
209 evt->irq = irq;
Will Deaconea3aacf2012-11-23 18:55:30 +0100210 evt->cpumask = cpu_possible_mask;
Russell Kinge3887712010-01-14 13:30:16 +0000211
Rob Herring7a0eca72013-03-25 11:23:52 -0500212 writel(0, base + TIMER_CTRL);
213
Russell King57cc4f72011-05-12 15:31:13 +0100214 setup_irq(irq, &sp804_timer_irq);
Linus Walleij7c324d82011-12-21 13:25:34 +0100215 clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
Russell Kinge3887712010-01-14 13:30:16 +0000216}
Rob Herring7a0eca72013-03-25 11:23:52 -0500217
218static void __init sp804_of_init(struct device_node *np)
219{
220 static bool initialized = false;
221 void __iomem *base;
222 int irq;
223 u32 irq_num = 0;
224 struct clk *clk1, *clk2;
225 const char *name = of_get_property(np, "compatible", NULL);
226
227 base = of_iomap(np, 0);
228 if (WARN_ON(!base))
229 return;
230
231 /* Ensure timers are disabled */
232 writel(0, base + TIMER_CTRL);
233 writel(0, base + TIMER_2_BASE + TIMER_CTRL);
234
235 if (initialized || !of_device_is_available(np))
236 goto err;
237
238 clk1 = of_clk_get(np, 0);
239 if (IS_ERR(clk1))
240 clk1 = NULL;
241
Rob Herring1bde9902014-05-29 16:01:34 -0500242 /* Get the 2nd clock if the timer has 3 timer clocks */
Rob Herring7a0eca72013-03-25 11:23:52 -0500243 if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
244 clk2 = of_clk_get(np, 1);
245 if (IS_ERR(clk2)) {
246 pr_err("sp804: %s clock not found: %d\n", np->name,
247 (int)PTR_ERR(clk2));
Rob Herring1bde9902014-05-29 16:01:34 -0500248 clk2 = NULL;
Rob Herring7a0eca72013-03-25 11:23:52 -0500249 }
250 } else
251 clk2 = clk1;
252
253 irq = irq_of_parse_and_map(np, 0);
254 if (irq <= 0)
255 goto err;
256
257 of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
258 if (irq_num == 2) {
259 __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
260 __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
261 } else {
262 __sp804_clockevents_init(base, irq, clk1 , name);
263 __sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
264 name, clk2, 1);
265 }
266 initialized = true;
267
268 return;
269err:
270 iounmap(base);
271}
272CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
Rob Herring870e2922013-03-13 15:31:12 -0500273
274static void __init integrator_cp_of_init(struct device_node *np)
275{
276 static int init_count = 0;
277 void __iomem *base;
278 int irq;
279 const char *name = of_get_property(np, "compatible", NULL);
Linus Walleij9cf31382014-01-10 15:54:34 +0100280 struct clk *clk;
Rob Herring870e2922013-03-13 15:31:12 -0500281
282 base = of_iomap(np, 0);
283 if (WARN_ON(!base))
284 return;
Linus Walleij9cf31382014-01-10 15:54:34 +0100285 clk = of_clk_get(np, 0);
286 if (WARN_ON(IS_ERR(clk)))
287 return;
Rob Herring870e2922013-03-13 15:31:12 -0500288
289 /* Ensure timer is disabled */
290 writel(0, base + TIMER_CTRL);
291
292 if (init_count == 2 || !of_device_is_available(np))
293 goto err;
294
295 if (!init_count)
Linus Walleij9cf31382014-01-10 15:54:34 +0100296 __sp804_clocksource_and_sched_clock_init(base, name, clk, 0);
Rob Herring870e2922013-03-13 15:31:12 -0500297 else {
298 irq = irq_of_parse_and_map(np, 0);
299 if (irq <= 0)
300 goto err;
301
Linus Walleij9cf31382014-01-10 15:54:34 +0100302 __sp804_clockevents_init(base, irq, clk, name);
Rob Herring870e2922013-03-13 15:31:12 -0500303 }
304
305 init_count++;
306 return;
307err:
308 iounmap(base);
309}
310CLOCKSOURCE_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);