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gerrit-public.fairphone.software / kernel / msm-4.9 / 0c11f655553c84bb695fdd5ea8b19d42b41b7133 / . / sound / soc / codecs / wm8993.c
blob: e246ca07989751abf702241678827ccf6743cb64 [file] [log] [blame]
Mark Brown942c4352009-06-05 16:32:59 +0100[diff] [blame]1/*
2 * wm8993.c -- WM8993 ALSA SoC audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/i2c.h>
19#include <linux/spi/spi.h>
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/tlv.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/wm8993.h>
28
29#include "wm8993.h"
30
31static u16 wm8993_reg_defaults[WM8993_REGISTER_COUNT] = {
32 0x8993, /* R0 - Software Reset */
33 0x0000, /* R1 - Power Management (1) */
34 0x6000, /* R2 - Power Management (2) */
35 0x0000, /* R3 - Power Management (3) */
36 0x4050, /* R4 - Audio Interface (1) */
37 0x4000, /* R5 - Audio Interface (2) */
38 0x01C8, /* R6 - Clocking 1 */
39 0x0000, /* R7 - Clocking 2 */
40 0x0000, /* R8 - Audio Interface (3) */
41 0x0040, /* R9 - Audio Interface (4) */
42 0x0004, /* R10 - DAC CTRL */
43 0x00C0, /* R11 - Left DAC Digital Volume */
44 0x00C0, /* R12 - Right DAC Digital Volume */
45 0x0000, /* R13 - Digital Side Tone */
46 0x0300, /* R14 - ADC CTRL */
47 0x00C0, /* R15 - Left ADC Digital Volume */
48 0x00C0, /* R16 - Right ADC Digital Volume */
49 0x0000, /* R17 */
50 0x0000, /* R18 - GPIO CTRL 1 */
51 0x0010, /* R19 - GPIO1 */
52 0x0000, /* R20 - IRQ_DEBOUNCE */
53 0x0000, /* R21 */
54 0x8000, /* R22 - GPIOCTRL 2 */
55 0x0800, /* R23 - GPIO_POL */
56 0x008B, /* R24 - Left Line Input 1&2 Volume */
57 0x008B, /* R25 - Left Line Input 3&4 Volume */
58 0x008B, /* R26 - Right Line Input 1&2 Volume */
59 0x008B, /* R27 - Right Line Input 3&4 Volume */
60 0x006D, /* R28 - Left Output Volume */
61 0x006D, /* R29 - Right Output Volume */
62 0x0066, /* R30 - Line Outputs Volume */
63 0x0020, /* R31 - HPOUT2 Volume */
64 0x0079, /* R32 - Left OPGA Volume */
65 0x0079, /* R33 - Right OPGA Volume */
66 0x0003, /* R34 - SPKMIXL Attenuation */
67 0x0003, /* R35 - SPKMIXR Attenuation */
68 0x0011, /* R36 - SPKOUT Mixers */
69 0x0100, /* R37 - SPKOUT Boost */
70 0x0079, /* R38 - Speaker Volume Left */
71 0x0079, /* R39 - Speaker Volume Right */
72 0x0000, /* R40 - Input Mixer2 */
73 0x0000, /* R41 - Input Mixer3 */
74 0x0000, /* R42 - Input Mixer4 */
75 0x0000, /* R43 - Input Mixer5 */
76 0x0000, /* R44 - Input Mixer6 */
77 0x0000, /* R45 - Output Mixer1 */
78 0x0000, /* R46 - Output Mixer2 */
79 0x0000, /* R47 - Output Mixer3 */
80 0x0000, /* R48 - Output Mixer4 */
81 0x0000, /* R49 - Output Mixer5 */
82 0x0000, /* R50 - Output Mixer6 */
83 0x0000, /* R51 - HPOUT2 Mixer */
84 0x0000, /* R52 - Line Mixer1 */
85 0x0000, /* R53 - Line Mixer2 */
86 0x0000, /* R54 - Speaker Mixer */
87 0x0000, /* R55 - Additional Control */
88 0x0000, /* R56 - AntiPOP1 */
89 0x0000, /* R57 - AntiPOP2 */
90 0x0000, /* R58 - MICBIAS */
91 0x0000, /* R59 */
92 0x0000, /* R60 - FLL Control 1 */
93 0x0000, /* R61 - FLL Control 2 */
94 0x0000, /* R62 - FLL Control 3 */
95 0x2EE0, /* R63 - FLL Control 4 */
96 0x0002, /* R64 - FLL Control 5 */
97 0x2287, /* R65 - Clocking 3 */
98 0x025F, /* R66 - Clocking 4 */
99 0x0000, /* R67 - MW Slave Control */
100 0x0000, /* R68 */
101 0x0002, /* R69 - Bus Control 1 */
102 0x0000, /* R70 - Write Sequencer 0 */
103 0x0000, /* R71 - Write Sequencer 1 */
104 0x0000, /* R72 - Write Sequencer 2 */
105 0x0000, /* R73 - Write Sequencer 3 */
106 0x0000, /* R74 - Write Sequencer 4 */
107 0x0000, /* R75 - Write Sequencer 5 */
108 0x1F25, /* R76 - Charge Pump 1 */
109 0x0000, /* R77 */
110 0x0000, /* R78 */
111 0x0000, /* R79 */
112 0x0000, /* R80 */
113 0x0000, /* R81 - Class W 0 */
114 0x0000, /* R82 */
115 0x0000, /* R83 */
116 0x0000, /* R84 - DC Servo 0 */
117 0x054A, /* R85 - DC Servo 1 */
118 0x0000, /* R86 */
119 0x0000, /* R87 - DC Servo 3 */
120 0x0000, /* R88 - DC Servo Readback 0 */
121 0x0000, /* R89 - DC Servo Readback 1 */
122 0x0000, /* R90 - DC Servo Readback 2 */
123 0x0000, /* R91 */
124 0x0000, /* R92 */
125 0x0000, /* R93 */
126 0x0000, /* R94 */
127 0x0000, /* R95 */
128 0x0100, /* R96 - Analogue HP 0 */
129 0x0000, /* R97 */
130 0x0000, /* R98 - EQ1 */
131 0x000C, /* R99 - EQ2 */
132 0x000C, /* R100 - EQ3 */
133 0x000C, /* R101 - EQ4 */
134 0x000C, /* R102 - EQ5 */
135 0x000C, /* R103 - EQ6 */
136 0x0FCA, /* R104 - EQ7 */
137 0x0400, /* R105 - EQ8 */
138 0x00D8, /* R106 - EQ9 */
139 0x1EB5, /* R107 - EQ10 */
140 0xF145, /* R108 - EQ11 */
141 0x0B75, /* R109 - EQ12 */
142 0x01C5, /* R110 - EQ13 */
143 0x1C58, /* R111 - EQ14 */
144 0xF373, /* R112 - EQ15 */
145 0x0A54, /* R113 - EQ16 */
146 0x0558, /* R114 - EQ17 */
147 0x168E, /* R115 - EQ18 */
148 0xF829, /* R116 - EQ19 */
149 0x07AD, /* R117 - EQ20 */
150 0x1103, /* R118 - EQ21 */
151 0x0564, /* R119 - EQ22 */
152 0x0559, /* R120 - EQ23 */
153 0x4000, /* R121 - EQ24 */
154 0x0000, /* R122 - Digital Pulls */
155 0x0F08, /* R123 - DRC Control 1 */
156 0x0000, /* R124 - DRC Control 2 */
157 0x0080, /* R125 - DRC Control 3 */
158 0x0000, /* R126 - DRC Control 4 */
159};
160
161static struct {
162 int ratio;
163 int clk_sys_rate;
164} clk_sys_rates[] = {
165 { 64, 0 },
166 { 128, 1 },
167 { 192, 2 },
168 { 256, 3 },
169 { 384, 4 },
170 { 512, 5 },
171 { 768, 6 },
172 { 1024, 7 },
173 { 1408, 8 },
174 { 1536, 9 },
175};
176
177static struct {
178 int rate;
179 int sample_rate;
180} sample_rates[] = {
181 { 8000, 0 },
182 { 11025, 1 },
183 { 12000, 1 },
184 { 16000, 2 },
185 { 22050, 3 },
186 { 24000, 3 },
187 { 32000, 4 },
188 { 44100, 5 },
189 { 48000, 5 },
190};
191
192static struct {
193 int div; /* *10 due to .5s */
194 int bclk_div;
195} bclk_divs[] = {
196 { 10, 0 },
197 { 15, 1 },
198 { 20, 2 },
199 { 30, 3 },
200 { 40, 4 },
201 { 55, 5 },
202 { 60, 6 },
203 { 80, 7 },
204 { 110, 8 },
205 { 120, 9 },
206 { 160, 10 },
207 { 220, 11 },
208 { 240, 12 },
209 { 320, 13 },
210 { 440, 14 },
211 { 480, 15 },
212};
213
214struct wm8993_priv {
215 u16 reg_cache[WM8993_REGISTER_COUNT];
216 struct wm8993_platform_data pdata;
217 struct snd_soc_codec codec;
218 int master;
219 int sysclk_source;
220 unsigned int mclk_rate;
221 unsigned int sysclk_rate;
222 unsigned int fs;
223 unsigned int bclk;
224 int class_w_users;
225 unsigned int fll_fref;
226 unsigned int fll_fout;
227};
228
229static unsigned int wm8993_read_hw(struct snd_soc_codec *codec, u8 reg)
230{
231 struct i2c_msg xfer[2];
232 u16 data;
233 int ret;
234 struct i2c_client *i2c = codec->control_data;
235
236 /* Write register */
237 xfer[0].addr = i2c->addr;
238 xfer[0].flags = 0;
239 xfer[0].len = 1;
240 xfer[0].buf = &reg;
241
242 /* Read data */
243 xfer[1].addr = i2c->addr;
244 xfer[1].flags = I2C_M_RD;
245 xfer[1].len = 2;
246 xfer[1].buf = (u8 *)&data;
247
248 ret = i2c_transfer(i2c->adapter, xfer, 2);
249 if (ret != 2) {
250 dev_err(codec->dev, "Failed to read 0x%x: %d\n", reg, ret);
251 return 0;
252 }
253
254 return (data >> 8) | ((data & 0xff) << 8);
255}
256
257static int wm8993_volatile(unsigned int reg)
258{
259 switch (reg) {
260 case WM8993_SOFTWARE_RESET:
261 case WM8993_DC_SERVO_0:
262 case WM8993_DC_SERVO_READBACK_0:
263 case WM8993_DC_SERVO_READBACK_1:
264 case WM8993_DC_SERVO_READBACK_2:
265 return 1;
266 default:
267 return 0;
268 }
269}
270
271static unsigned int wm8993_read(struct snd_soc_codec *codec,
272 unsigned int reg)
273{
274 u16 *reg_cache = codec->reg_cache;
275
276 BUG_ON(reg > WM8993_MAX_REGISTER);
277
278 if (wm8993_volatile(reg))
279 return wm8993_read_hw(codec, reg);
280 else
281 return reg_cache[reg];
282}
283
284static int wm8993_write(struct snd_soc_codec *codec, unsigned int reg,
285 unsigned int value)
286{
287 u16 *reg_cache = codec->reg_cache;
288 u8 data[3];
289 int ret;
290
291 BUG_ON(reg > WM8993_MAX_REGISTER);
292
293 /* data is
294 * D15..D9 WM8993 register offset
295 * D8...D0 register data
296 */
297 data[0] = reg;
298 data[1] = value >> 8;
299 data[2] = value & 0x00ff;
300
301 if (!wm8993_volatile(reg))
302 reg_cache[reg] = value;
303
304 ret = codec->hw_write(codec->control_data, data, 3);
305
306 if (ret == 3)
307 return 0;
308 if (ret < 0)
309 return ret;
310 return -EIO;
311}
312
313struct _fll_div {
314 u16 fll_fratio;
315 u16 fll_outdiv;
316 u16 fll_clk_ref_div;
317 u16 n;
318 u16 k;
319};
320
321/* The size in bits of the FLL divide multiplied by 10
322 * to allow rounding later */
323#define FIXED_FLL_SIZE ((1 << 16) * 10)
324
325static struct {
326 unsigned int min;
327 unsigned int max;
328 u16 fll_fratio;
329 int ratio;
330} fll_fratios[] = {
331 { 0, 64000, 4, 16 },
332 { 64000, 128000, 3, 8 },
333 { 128000, 256000, 2, 4 },
334 { 256000, 1000000, 1, 2 },
335 { 1000000, 13500000, 0, 1 },
336};
337
338static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
339 unsigned int Fout)
340{
341 u64 Kpart;
342 unsigned int K, Ndiv, Nmod, target;
343 unsigned int div;
344 int i;
345
346 /* Fref must be <=13.5MHz */
347 div = 1;
Mark Brown0c11f652009-07-17 22:13:01 +0100[diff] [blame^]348 fll_div->fll_clk_ref_div = 0;
Mark Brown942c4352009-06-05 16:32:59 +0100[diff] [blame]349 while ((Fref / div) > 13500000) {
350 div *= 2;
Mark Brown0c11f652009-07-17 22:13:01 +0100[diff] [blame^]351 fll_div->fll_clk_ref_div++;
Mark Brown942c4352009-06-05 16:32:59 +0100[diff] [blame]352
353 if (div > 8) {
354 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
355 Fref);
356 return -EINVAL;
357 }
358 }
359
360 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
361
362 /* Apply the division for our remaining calculations */
363 Fref /= div;
364
365 /* Fvco should be 90-100MHz; don't check the upper bound */
366 div = 0;
367 target = Fout * 2;
368 while (target < 90000000) {
369 div++;
370 target *= 2;
371 if (div > 7) {
372 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
373 Fout);
374 return -EINVAL;
375 }
376 }
377 fll_div->fll_outdiv = div;
378
379 pr_debug("Fvco=%dHz\n", target);
380
381 /* Find an appropraite FLL_FRATIO and factor it out of the target */
382 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
383 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
384 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
385 target /= fll_fratios[i].ratio;
386 break;
387 }
388 }
389 if (i == ARRAY_SIZE(fll_fratios)) {
390 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
391 return -EINVAL;
392 }
393
394 /* Now, calculate N.K */
395 Ndiv = target / Fref;
396
397 fll_div->n = Ndiv;
398 Nmod = target % Fref;
399 pr_debug("Nmod=%d\n", Nmod);
400
401 /* Calculate fractional part - scale up so we can round. */
402 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
403
404 do_div(Kpart, Fref);
405
406 K = Kpart & 0xFFFFFFFF;
407
408 if ((K % 10) >= 5)
409 K += 5;
410
411 /* Move down to proper range now rounding is done */
412 fll_div->k = K / 10;
413
414 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
415 fll_div->n, fll_div->k,
416 fll_div->fll_fratio, fll_div->fll_outdiv,
417 fll_div->fll_clk_ref_div);
418
419 return 0;
420}
421
422static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id,
423 unsigned int Fref, unsigned int Fout)
424{
425 struct snd_soc_codec *codec = dai->codec;
426 struct wm8993_priv *wm8993 = codec->private_data;
427 u16 reg1, reg4, reg5;
428 struct _fll_div fll_div;
429 int ret;
430
431 /* Any change? */
432 if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
433 return 0;
434
435 /* Disable the FLL */
436 if (Fout == 0) {
437 dev_dbg(codec->dev, "FLL disabled\n");
438 wm8993->fll_fref = 0;
439 wm8993->fll_fout = 0;
440
441 reg1 = wm8993_read(codec, WM8993_FLL_CONTROL_1);
442 reg1 &= ~WM8993_FLL_ENA;
443 wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1);
444
445 return 0;
446 }
447
448 ret = fll_factors(&fll_div, Fref, Fout);
449 if (ret != 0)
450 return ret;
451
452 reg5 = wm8993_read(codec, WM8993_FLL_CONTROL_5);
453 reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
454
455 switch (fll_id) {
456 case WM8993_FLL_MCLK:
457 break;
458
459 case WM8993_FLL_LRCLK:
460 reg5 |= 1;
461 break;
462
463 case WM8993_FLL_BCLK:
464 reg5 |= 2;
465 break;
466
467 default:
468 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
469 return -EINVAL;
470 }
471
472 /* Any FLL configuration change requires that the FLL be
473 * disabled first. */
474 reg1 = wm8993_read(codec, WM8993_FLL_CONTROL_1);
475 reg1 &= ~WM8993_FLL_ENA;
476 wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1);
477
478 /* Apply the configuration */
479 if (fll_div.k)
480 reg1 |= WM8993_FLL_FRAC_MASK;
481 else
482 reg1 &= ~WM8993_FLL_FRAC_MASK;
483 wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1);
484
485 wm8993_write(codec, WM8993_FLL_CONTROL_2,
486 (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
487 (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
488 wm8993_write(codec, WM8993_FLL_CONTROL_3, fll_div.k);
489
490 reg4 = wm8993_read(codec, WM8993_FLL_CONTROL_4);
491 reg4 &= ~WM8993_FLL_N_MASK;
492 reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
493 wm8993_write(codec, WM8993_FLL_CONTROL_4, reg4);
494
495 reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
496 reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
497 wm8993_write(codec, WM8993_FLL_CONTROL_5, reg5);
498
499 /* Enable the FLL */
500 wm8993_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
501
502 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
503
504 wm8993->fll_fref = Fref;
505 wm8993->fll_fout = Fout;
506
507 return 0;
508}
509
510static int configure_clock(struct snd_soc_codec *codec)
511{
512 struct wm8993_priv *wm8993 = codec->private_data;
513 unsigned int reg;
514
515 /* This should be done on init() for bypass paths */
516 switch (wm8993->sysclk_source) {
517 case WM8993_SYSCLK_MCLK:
518 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
519
520 reg = wm8993_read(codec, WM8993_CLOCKING_2);
521 reg &= ~WM8993_SYSCLK_SRC;
522 if (wm8993->mclk_rate > 13500000) {
523 reg |= WM8993_MCLK_DIV;
524 wm8993->sysclk_rate = wm8993->mclk_rate / 2;
525 } else {
526 reg &= ~WM8993_MCLK_DIV;
527 wm8993->sysclk_rate = wm8993->mclk_rate;
528 }
529 reg &= ~WM8993_MCLK_DIV;
530 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
531 wm8993_write(codec, WM8993_CLOCKING_2, reg);
532 break;
533
534 case WM8993_SYSCLK_FLL:
535 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
536 wm8993->fll_fout);
537
538 reg = wm8993_read(codec, WM8993_CLOCKING_2);
539 reg |= WM8993_SYSCLK_SRC;
540 if (wm8993->fll_fout > 13500000) {
541 reg |= WM8993_MCLK_DIV;
542 wm8993->sysclk_rate = wm8993->fll_fout / 2;
543 } else {
544 reg &= ~WM8993_MCLK_DIV;
545 wm8993->sysclk_rate = wm8993->fll_fout;
546 }
547 wm8993_write(codec, WM8993_CLOCKING_2, reg);
548 break;
549
550 default:
551 dev_err(codec->dev, "System clock not configured\n");
552 return -EINVAL;
553 }
554
555 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
556
557 return 0;
558}
559
560static void wait_for_dc_servo(struct snd_soc_codec *codec, int mask)
561{
562 unsigned int reg;
563 int count = 0;
564
565 dev_dbg(codec->dev, "Waiting for DC servo...\n");
566 do {
567 count++;
568 msleep(1);
569 reg = wm8993_read(codec, WM8993_DC_SERVO_READBACK_0);
570 dev_dbg(codec->dev, "DC servo status: %x\n", reg);
571 } while ((reg & WM8993_DCS_CAL_COMPLETE_MASK)
572 != WM8993_DCS_CAL_COMPLETE_MASK && count < 1000);
573
574 if ((reg & WM8993_DCS_CAL_COMPLETE_MASK)
575 != WM8993_DCS_CAL_COMPLETE_MASK)
576 dev_err(codec->dev, "Timed out waiting for DC Servo\n");
577}
578
579static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1650, 150, 0);
580static const DECLARE_TLV_DB_SCALE(inmix_sw_tlv, 0, 3000, 0);
581static const DECLARE_TLV_DB_SCALE(inmix_tlv, -1500, 300, 1);
582static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
583static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
584static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
585static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
586static const unsigned int drc_max_tlv[] = {
587 TLV_DB_RANGE_HEAD(4),
588 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
589 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
590};
591static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
592static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
593static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
594static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
595static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
596static const DECLARE_TLV_DB_SCALE(earpiece_tlv, -600, 600, 0);
597static const DECLARE_TLV_DB_SCALE(outmix_tlv, -2100, 300, 0);
598static const DECLARE_TLV_DB_SCALE(spkmix_tlv, -300, 300, 0);
599static const DECLARE_TLV_DB_SCALE(spkmixout_tlv, -1800, 600, 1);
600static const DECLARE_TLV_DB_SCALE(outpga_tlv, -5700, 100, 0);
601static const unsigned int spkboost_tlv[] = {
602 TLV_DB_RANGE_HEAD(7),
603 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
604 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
605};
606static const DECLARE_TLV_DB_SCALE(line_tlv, -600, 600, 0);
607
608static const char *speaker_ref_text[] = {
609 "SPKVDD/2",
610 "VMID",
611};
612
613static const struct soc_enum speaker_ref =
614 SOC_ENUM_SINGLE(WM8993_SPEAKER_MIXER, 8, 2, speaker_ref_text);
615
616static const char *speaker_mode_text[] = {
617 "Class D",
618 "Class AB",
619};
620
621static const struct soc_enum speaker_mode =
622 SOC_ENUM_SINGLE(WM8993_SPKMIXR_ATTENUATION, 8, 2, speaker_mode_text);
623
624static const char *dac_deemph_text[] = {
625 "None",
626 "32kHz",
627 "44.1kHz",
628 "48kHz",
629};
630
631static const struct soc_enum dac_deemph =
632 SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text);
633
634static const char *adc_hpf_text[] = {
635 "Hi-Fi",
636 "Voice 1",
637 "Voice 2",
638 "Voice 3",
639};
640
641static const struct soc_enum adc_hpf =
642 SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text);
643
644static const char *drc_path_text[] = {
645 "ADC",
646 "DAC"
647};
648
649static const struct soc_enum drc_path =
650 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text);
651
652static const char *drc_r0_text[] = {
653 "1",
654 "1/2",
655 "1/4",
656 "1/8",
657 "1/16",
658 "0",
659};
660
661static const struct soc_enum drc_r0 =
662 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text);
663
664static const char *drc_r1_text[] = {
665 "1",
666 "1/2",
667 "1/4",
668 "1/8",
669 "0",
670};
671
672static const struct soc_enum drc_r1 =
673 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text);
674
675static const char *drc_attack_text[] = {
676 "Reserved",
677 "181us",
678 "363us",
679 "726us",
680 "1.45ms",
681 "2.9ms",
682 "5.8ms",
683 "11.6ms",
684 "23.2ms",
685 "46.4ms",
686 "92.8ms",
687 "185.6ms",
688};
689
690static const struct soc_enum drc_attack =
691 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text);
692
693static const char *drc_decay_text[] = {
694 "186ms",
695 "372ms",
696 "743ms",
697 "1.49s",
698 "2.97ms",
699 "5.94ms",
700 "11.89ms",
701 "23.78ms",
702 "47.56ms",
703};
704
705static const struct soc_enum drc_decay =
706 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text);
707
708static const char *drc_ff_text[] = {
709 "5 samples",
710 "9 samples",
711};
712
713static const struct soc_enum drc_ff =
714 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text);
715
716static const char *drc_qr_rate_text[] = {
717 "0.725ms",
718 "1.45ms",
719 "5.8ms",
720};
721
722static const struct soc_enum drc_qr_rate =
723 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text);
724
725static const char *drc_smooth_text[] = {
726 "Low",
727 "Medium",
728 "High",
729};
730
731static const struct soc_enum drc_smooth =
732 SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text);
733
734
735/*
736 * Update the DC servo calibration on gain changes
737 */
738static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol,
739 struct snd_ctl_elem_value *ucontrol)
740{
741 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
742 int ret;
743
744 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
745
746 /* Only need to do this if the outputs are active */
747 if (wm8993_read(codec, WM8993_POWER_MANAGEMENT_1)
748 & (WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA))
749 snd_soc_update_bits(codec,
750 WM8993_DC_SERVO_0,
751 WM8993_DCS_TRIG_SINGLE_0 |
752 WM8993_DCS_TRIG_SINGLE_1,
753 WM8993_DCS_TRIG_SINGLE_0 |
754 WM8993_DCS_TRIG_SINGLE_1);
755
756 return ret;
757}
758
759static const struct snd_kcontrol_new wm8993_snd_controls[] = {
760SOC_SINGLE_TLV("IN1L Volume", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
761 inpga_tlv),
762SOC_SINGLE("IN1L Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
763SOC_SINGLE("IN1L ZC Switch", WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 7, 1, 0),
764
765SOC_SINGLE_TLV("IN1R Volume", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 0, 31, 0,
766 inpga_tlv),
767SOC_SINGLE("IN1R Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 7, 1, 1),
768SOC_SINGLE("IN1R ZC Switch", WM8993_RIGHT_LINE_INPUT_1_2_VOLUME, 7, 1, 0),
769
770
771SOC_SINGLE_TLV("IN2L Volume", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
772 inpga_tlv),
773SOC_SINGLE("IN2L Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
774SOC_SINGLE("IN2L ZC Switch", WM8993_LEFT_LINE_INPUT_3_4_VOLUME, 7, 1, 0),
775
776SOC_SINGLE_TLV("IN2R Volume", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 0, 31, 0,
777 inpga_tlv),
778SOC_SINGLE("IN2R Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 7, 1, 1),
779SOC_SINGLE("IN2R ZC Switch", WM8993_RIGHT_LINE_INPUT_3_4_VOLUME, 7, 1, 0),
780
781SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8993_INPUT_MIXER3, 7, 1, 0,
782 inmix_sw_tlv),
783SOC_SINGLE_TLV("MIXINL IN1L Volume", WM8993_INPUT_MIXER3, 4, 1, 0,
784 inmix_sw_tlv),
785SOC_SINGLE_TLV("MIXINL Output Record Volume", WM8993_INPUT_MIXER3, 0, 7, 0,
786 inmix_tlv),
787SOC_SINGLE_TLV("MIXINL IN1LP Volume", WM8993_INPUT_MIXER5, 6, 7, 0, inmix_tlv),
788SOC_SINGLE_TLV("MIXINL Direct Voice Volume", WM8993_INPUT_MIXER5, 0, 6, 0,
789 inmix_tlv),
790
791SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8993_INPUT_MIXER4, 7, 1, 0,
792 inmix_sw_tlv),
793SOC_SINGLE_TLV("MIXINR IN1R Volume", WM8993_INPUT_MIXER4, 4, 1, 0,
794 inmix_sw_tlv),
795SOC_SINGLE_TLV("MIXINR Output Record Volume", WM8993_INPUT_MIXER4, 0, 7, 0,
796 inmix_tlv),
797SOC_SINGLE_TLV("MIXINR IN1RP Volume", WM8993_INPUT_MIXER6, 6, 7, 0, inmix_tlv),
798SOC_SINGLE_TLV("MIXINR Direct Voice Volume", WM8993_INPUT_MIXER6, 0, 6, 0,
799 inmix_tlv),
800
801SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
802 5, 9, 12, 0, sidetone_tlv),
803
804SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
805SOC_ENUM("DRC Path", drc_path),
806SOC_SINGLE_TLV("DRC Compressor Threashold Volume", WM8993_DRC_CONTROL_2,
807 2, 60, 1, drc_comp_threash),
808SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
809 11, 30, 1, drc_comp_amp),
810SOC_ENUM("DRC R0", drc_r0),
811SOC_ENUM("DRC R1", drc_r1),
812SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
813 drc_min_tlv),
814SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
815 drc_max_tlv),
816SOC_ENUM("DRC Attack Rate", drc_attack),
817SOC_ENUM("DRC Decay Rate", drc_decay),
818SOC_ENUM("DRC FF Delay", drc_ff),
819SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
820SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
821SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
822 drc_qr_tlv),
823SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
824SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
825SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
826SOC_ENUM("DRC Smoothing Hysteresis Threashold", drc_smooth),
827SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
828 drc_startup_tlv),
829
830SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
831
832SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
833 WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
834SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
835SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
836
837SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
838 WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
839SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
840 dac_boost_tlv),
841SOC_ENUM("DAC Deemphasis", dac_deemph),
842
843SOC_SINGLE_TLV("Left Output Mixer IN2RN Volume", WM8993_OUTPUT_MIXER5, 6, 7, 1,
844 outmix_tlv),
845SOC_SINGLE_TLV("Left Output Mixer IN2LN Volume", WM8993_OUTPUT_MIXER3, 6, 7, 1,
846 outmix_tlv),
847SOC_SINGLE_TLV("Left Output Mixer IN2LP Volume", WM8993_OUTPUT_MIXER3, 9, 7, 1,
848 outmix_tlv),
849SOC_SINGLE_TLV("Left Output Mixer IN1L Volume", WM8993_OUTPUT_MIXER3, 0, 7, 1,
850 outmix_tlv),
851SOC_SINGLE_TLV("Left Output Mixer IN1R Volume", WM8993_OUTPUT_MIXER3, 3, 7, 1,
852 outmix_tlv),
853SOC_SINGLE_TLV("Left Output Mixer Right Input Volume",
854 WM8993_OUTPUT_MIXER5, 3, 7, 1, outmix_tlv),
855SOC_SINGLE_TLV("Left Output Mixer Left Input Volume",
856 WM8993_OUTPUT_MIXER5, 0, 7, 1, outmix_tlv),
857SOC_SINGLE_TLV("Left Output Mixer DAC Volume", WM8993_OUTPUT_MIXER5, 9, 7, 1,
858 outmix_tlv),
859
860SOC_SINGLE_TLV("Right Output Mixer IN2LN Volume",
861 WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
862SOC_SINGLE_TLV("Right Output Mixer IN2RN Volume",
863 WM8993_OUTPUT_MIXER4, 6, 7, 1, outmix_tlv),
864SOC_SINGLE_TLV("Right Output Mixer IN1L Volume",
865 WM8993_OUTPUT_MIXER4, 3, 7, 1, outmix_tlv),
866SOC_SINGLE_TLV("Right Output Mixer IN1R Volume",
867 WM8993_OUTPUT_MIXER4, 0, 7, 1, outmix_tlv),
868SOC_SINGLE_TLV("Right Output Mixer IN2RP Volume",
869 WM8993_OUTPUT_MIXER4, 9, 7, 1, outmix_tlv),
870SOC_SINGLE_TLV("Right Output Mixer Left Input Volume",
871 WM8993_OUTPUT_MIXER6, 3, 7, 1, outmix_tlv),
872SOC_SINGLE_TLV("Right Output Mixer Right Input Volume",
873 WM8993_OUTPUT_MIXER6, 6, 7, 1, outmix_tlv),
874SOC_SINGLE_TLV("Right Output Mixer DAC Volume",
875 WM8993_OUTPUT_MIXER6, 9, 7, 1, outmix_tlv),
876
877SOC_DOUBLE_R_TLV("Output Volume", WM8993_LEFT_OPGA_VOLUME,
878 WM8993_RIGHT_OPGA_VOLUME, 0, 63, 0, outpga_tlv),
879SOC_DOUBLE_R("Output Switch", WM8993_LEFT_OPGA_VOLUME,
880 WM8993_RIGHT_OPGA_VOLUME, 6, 1, 0),
881SOC_DOUBLE_R("Output ZC Switch", WM8993_LEFT_OPGA_VOLUME,
882 WM8993_RIGHT_OPGA_VOLUME, 7, 1, 0),
883
884SOC_SINGLE("Earpiece Switch", WM8993_HPOUT2_VOLUME, 5, 1, 1),
885SOC_SINGLE_TLV("Earpiece Volume", WM8993_HPOUT2_VOLUME, 4, 1, 1, earpiece_tlv),
886
887SOC_SINGLE_TLV("SPKL Input Volume", WM8993_SPKMIXL_ATTENUATION,
888 5, 1, 1, spkmix_tlv),
889SOC_SINGLE_TLV("SPKL IN1LP Volume", WM8993_SPKMIXL_ATTENUATION,
890 4, 1, 1, spkmix_tlv),
891SOC_SINGLE_TLV("SPKL Output Volume", WM8993_SPKMIXL_ATTENUATION,
892 3, 1, 1, spkmix_tlv),
893SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
894 2, 1, 1, spkmix_tlv),
895
896SOC_SINGLE_TLV("SPKR Input Volume", WM8993_SPKMIXR_ATTENUATION,
897 5, 1, 1, spkmix_tlv),
898SOC_SINGLE_TLV("SPKR IN1RP Volume", WM8993_SPKMIXR_ATTENUATION,
899 4, 1, 1, spkmix_tlv),
900SOC_SINGLE_TLV("SPKR Output Volume", WM8993_SPKMIXR_ATTENUATION,
901 3, 1, 1, spkmix_tlv),
902SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
903 2, 1, 1, spkmix_tlv),
904
905SOC_DOUBLE_R_TLV("Speaker Mixer Volume",
906 WM8993_SPKMIXL_ATTENUATION, WM8993_SPKMIXR_ATTENUATION,
907 0, 3, 1, spkmixout_tlv),
908SOC_DOUBLE_R_TLV("Speaker Volume",
909 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
910 0, 63, 0, outpga_tlv),
911SOC_DOUBLE_R("Speaker Switch",
912 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
913 6, 1, 0),
914SOC_DOUBLE_R("Speaker ZC Switch",
915 WM8993_SPEAKER_VOLUME_LEFT, WM8993_SPEAKER_VOLUME_RIGHT,
916 7, 1, 0),
917SOC_DOUBLE_TLV("Speaker Boost Volume", WM8993_SPKOUT_BOOST, 0, 3, 7, 0,
918 spkboost_tlv),
919SOC_ENUM("Speaker Reference", speaker_ref),
920SOC_ENUM("Speaker Mode", speaker_mode),
921
922{
923 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Headphone Volume",
924 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
925 SNDRV_CTL_ELEM_ACCESS_READWRITE,
926 .tlv.p = outpga_tlv,
927 .info = snd_soc_info_volsw_2r,
928 .get = snd_soc_get_volsw_2r, .put = wm8993_put_dc_servo,
929 .private_value = (unsigned long)&(struct soc_mixer_control) {
930 .reg = WM8993_LEFT_OUTPUT_VOLUME,
931 .rreg = WM8993_RIGHT_OUTPUT_VOLUME,
932 .shift = 0, .max = 63
933 },
934},
935SOC_DOUBLE_R("Headphone Switch", WM8993_LEFT_OUTPUT_VOLUME,
936 WM8993_RIGHT_OUTPUT_VOLUME, 6, 1, 0),
937SOC_DOUBLE_R("Headphone ZC Switch", WM8993_LEFT_OUTPUT_VOLUME,
938 WM8993_RIGHT_OUTPUT_VOLUME, 7, 1, 0),
939
940SOC_SINGLE("LINEOUT1N Switch", WM8993_LINE_OUTPUTS_VOLUME, 6, 1, 1),
941SOC_SINGLE("LINEOUT1P Switch", WM8993_LINE_OUTPUTS_VOLUME, 5, 1, 1),
942SOC_SINGLE_TLV("LINEOUT1 Volume", WM8993_LINE_OUTPUTS_VOLUME, 4, 1, 1,
943 line_tlv),
944
945SOC_SINGLE("LINEOUT2N Switch", WM8993_LINE_OUTPUTS_VOLUME, 2, 1, 1),
946SOC_SINGLE("LINEOUT2P Switch", WM8993_LINE_OUTPUTS_VOLUME, 1, 1, 1),
947SOC_SINGLE_TLV("LINEOUT2 Volume", WM8993_LINE_OUTPUTS_VOLUME, 0, 1, 1,
948 line_tlv),
949};
950
951static const struct snd_kcontrol_new wm8993_eq_controls[] = {
952SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
953SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
954SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
955SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
956SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
957};
958
959static int wm8993_earpiece_event(struct snd_soc_dapm_widget *w,
960 struct snd_kcontrol *control, int event)
961{
962 struct snd_soc_codec *codec = w->codec;
963 u16 reg = wm8993_read(codec, WM8993_ANTIPOP1) & ~WM8993_HPOUT2_IN_ENA;
964
965 switch (event) {
966 case SND_SOC_DAPM_PRE_PMU:
967 reg |= WM8993_HPOUT2_IN_ENA;
968 wm8993_write(codec, WM8993_ANTIPOP1, reg);
969 udelay(50);
970 break;
971
972 case SND_SOC_DAPM_POST_PMD:
973 wm8993_write(codec, WM8993_ANTIPOP1, reg);
974 break;
975
976 default:
977 BUG();
978 break;
979 }
980
981 return 0;
982}
983
984static int clk_sys_event(struct snd_soc_dapm_widget *w,
985 struct snd_kcontrol *kcontrol, int event)
986{
987 struct snd_soc_codec *codec = w->codec;
988
989 switch (event) {
990 case SND_SOC_DAPM_PRE_PMU:
991 return configure_clock(codec);
992
993 case SND_SOC_DAPM_POST_PMD:
994 break;
995 }
996
997 return 0;
998}
999
1000/*
1001 * When used with DAC outputs only the WM8993 charge pump supports
1002 * operation in class W mode, providing very low power consumption
1003 * when used with digital sources. Enable and disable this mode
1004 * automatically depending on the mixer configuration.
1005 *
1006 * Currently the only supported paths are the direct DAC->headphone
1007 * paths (which provide minimum power consumption anyway).
1008 */
1009static int wm8993_class_w_put(struct snd_kcontrol *kcontrol,
1010 struct snd_ctl_elem_value *ucontrol)
1011{
1012 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
1013 struct snd_soc_codec *codec = widget->codec;
1014 struct wm8993_priv *wm8993 = codec->private_data;
1015 int ret;
1016
1017 /* Turn it off if we're using the main output mixer */
1018 if (ucontrol->value.integer.value[0] == 0) {
1019 if (wm8993->class_w_users == 0) {
1020 dev_dbg(codec->dev, "Disabling Class W\n");
1021 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
1022 WM8993_CP_DYN_FREQ |
1023 WM8993_CP_DYN_V,
1024 0);
1025 }
1026 wm8993->class_w_users++;
1027 }
1028
1029 /* Implement the change */
1030 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1031
1032 /* Enable it if we're using the direct DAC path */
1033 if (ucontrol->value.integer.value[0] == 1) {
1034 if (wm8993->class_w_users == 1) {
1035 dev_dbg(codec->dev, "Enabling Class W\n");
1036 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
1037 WM8993_CP_DYN_FREQ |
1038 WM8993_CP_DYN_V,
1039 WM8993_CP_DYN_FREQ |
1040 WM8993_CP_DYN_V);
1041 }
1042 wm8993->class_w_users--;
1043 }
1044
1045 dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
1046 wm8993->class_w_users);
1047
1048 return ret;
1049}
1050
1051#define SOC_DAPM_ENUM_W(xname, xenum) \
1052{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1053 .info = snd_soc_info_enum_double, \
1054 .get = snd_soc_dapm_get_enum_double, \
1055 .put = wm8993_class_w_put, \
1056 .private_value = (unsigned long)&xenum }
1057
1058static int hp_event(struct snd_soc_dapm_widget *w,
1059 struct snd_kcontrol *kcontrol, int event)
1060{
1061 struct snd_soc_codec *codec = w->codec;
1062 unsigned int reg = wm8993_read(codec, WM8993_ANALOGUE_HP_0);
1063
1064 switch (event) {
1065 case SND_SOC_DAPM_POST_PMU:
1066 snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
1067 WM8993_CP_ENA, WM8993_CP_ENA);
1068
1069 msleep(5);
1070
1071 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1072 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
1073 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA);
1074
1075 reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY;
1076 wm8993_write(codec, WM8993_ANALOGUE_HP_0, reg);
1077
1078 /* Start the DC servo */
1079 snd_soc_update_bits(codec, WM8993_DC_SERVO_0,
1080 WM8993_DCS_ENA_CHAN_0 |
1081 WM8993_DCS_ENA_CHAN_1 |
1082 WM8993_DCS_TRIG_STARTUP_1 |
1083 WM8993_DCS_TRIG_STARTUP_0,
1084 WM8993_DCS_ENA_CHAN_0 |
1085 WM8993_DCS_ENA_CHAN_1 |
1086 WM8993_DCS_TRIG_STARTUP_1 |
1087 WM8993_DCS_TRIG_STARTUP_0);
1088 wait_for_dc_servo(codec, WM8993_DCS_TRIG_STARTUP_0 |
1089 WM8993_DCS_TRIG_STARTUP_1);
1090 snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
1091 WM8993_DCS_TIMER_PERIOD_01_MASK, 0xa);
1092
1093 reg |= WM8993_HPOUT1R_OUTP | WM8993_HPOUT1R_RMV_SHORT |
1094 WM8993_HPOUT1L_OUTP | WM8993_HPOUT1L_RMV_SHORT;
1095 wm8993_write(codec, WM8993_ANALOGUE_HP_0, reg);
1096 break;
1097
1098 case SND_SOC_DAPM_PRE_PMD:
1099 reg &= ~(WM8993_HPOUT1L_RMV_SHORT |
1100 WM8993_HPOUT1L_DLY |
1101 WM8993_HPOUT1L_OUTP |
1102 WM8993_HPOUT1R_RMV_SHORT |
1103 WM8993_HPOUT1R_DLY |
1104 WM8993_HPOUT1R_OUTP);
1105
1106 snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
1107 WM8993_DCS_TIMER_PERIOD_01_MASK, 0);
1108 snd_soc_update_bits(codec, WM8993_DC_SERVO_0,
1109 WM8993_DCS_ENA_CHAN_0 |
1110 WM8993_DCS_ENA_CHAN_1, 0);
1111
1112 wm8993_write(codec, WM8993_ANALOGUE_HP_0, reg);
1113 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1114 WM8993_HPOUT1L_ENA | WM8993_HPOUT1R_ENA,
1115 0);
1116
1117 snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
1118 WM8993_CP_ENA, 0);
1119 break;
1120 }
1121
1122 return 0;
1123}
1124
1125static const struct snd_kcontrol_new in1l_pga[] = {
1126SOC_DAPM_SINGLE("IN1LP Switch", WM8993_INPUT_MIXER2, 5, 1, 0),
1127SOC_DAPM_SINGLE("IN1LN Switch", WM8993_INPUT_MIXER2, 4, 1, 0),
1128};
1129
1130static const struct snd_kcontrol_new in1r_pga[] = {
1131SOC_DAPM_SINGLE("IN1RP Switch", WM8993_INPUT_MIXER2, 1, 1, 0),
1132SOC_DAPM_SINGLE("IN1RN Switch", WM8993_INPUT_MIXER2, 0, 1, 0),
1133};
1134
1135static const struct snd_kcontrol_new in2l_pga[] = {
1136SOC_DAPM_SINGLE("IN2LP Switch", WM8993_INPUT_MIXER2, 7, 1, 0),
1137SOC_DAPM_SINGLE("IN2LN Switch", WM8993_INPUT_MIXER2, 6, 1, 0),
1138};
1139
1140static const struct snd_kcontrol_new in2r_pga[] = {
1141SOC_DAPM_SINGLE("IN2RP Switch", WM8993_INPUT_MIXER2, 3, 1, 0),
1142SOC_DAPM_SINGLE("IN2RN Switch", WM8993_INPUT_MIXER2, 2, 1, 0),
1143};
1144
1145static const struct snd_kcontrol_new mixinl[] = {
1146SOC_DAPM_SINGLE("IN2L Switch", WM8993_INPUT_MIXER3, 8, 1, 0),
1147SOC_DAPM_SINGLE("IN1L Switch", WM8993_INPUT_MIXER3, 5, 1, 0),
1148};
1149
1150static const struct snd_kcontrol_new mixinr[] = {
1151SOC_DAPM_SINGLE("IN2R Switch", WM8993_INPUT_MIXER4, 8, 1, 0),
1152SOC_DAPM_SINGLE("IN1R Switch", WM8993_INPUT_MIXER4, 5, 1, 0),
1153};
1154
1155static const struct snd_kcontrol_new left_output_mixer[] = {
1156SOC_DAPM_SINGLE("Right Input Switch", WM8993_OUTPUT_MIXER1, 7, 1, 0),
1157SOC_DAPM_SINGLE("Left Input Switch", WM8993_OUTPUT_MIXER1, 6, 1, 0),
1158SOC_DAPM_SINGLE("IN2RN Switch", WM8993_OUTPUT_MIXER1, 5, 1, 0),
1159SOC_DAPM_SINGLE("IN2LN Switch", WM8993_OUTPUT_MIXER1, 4, 1, 0),
1160SOC_DAPM_SINGLE("IN2LP Switch", WM8993_OUTPUT_MIXER1, 1, 1, 0),
1161SOC_DAPM_SINGLE("IN1R Switch", WM8993_OUTPUT_MIXER1, 3, 1, 0),
1162SOC_DAPM_SINGLE("IN1L Switch", WM8993_OUTPUT_MIXER1, 2, 1, 0),
1163SOC_DAPM_SINGLE("DAC Switch", WM8993_OUTPUT_MIXER1, 0, 1, 0),
1164};
1165
1166static const struct snd_kcontrol_new right_output_mixer[] = {
1167SOC_DAPM_SINGLE("Left Input Switch", WM8993_OUTPUT_MIXER2, 7, 1, 0),
1168SOC_DAPM_SINGLE("Right Input Switch", WM8993_OUTPUT_MIXER2, 6, 1, 0),
1169SOC_DAPM_SINGLE("IN2LN Switch", WM8993_OUTPUT_MIXER2, 5, 1, 0),
1170SOC_DAPM_SINGLE("IN2RN Switch", WM8993_OUTPUT_MIXER2, 4, 1, 0),
1171SOC_DAPM_SINGLE("IN1L Switch", WM8993_OUTPUT_MIXER2, 3, 1, 0),
1172SOC_DAPM_SINGLE("IN1R Switch", WM8993_OUTPUT_MIXER2, 2, 1, 0),
1173SOC_DAPM_SINGLE("IN2RP Switch", WM8993_OUTPUT_MIXER2, 1, 1, 0),
1174SOC_DAPM_SINGLE("DAC Switch", WM8993_OUTPUT_MIXER2, 0, 1, 0),
1175};
1176
1177static const struct snd_kcontrol_new earpiece_mixer[] = {
1178SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_HPOUT2_MIXER, 5, 1, 0),
1179SOC_DAPM_SINGLE("Left Output Switch", WM8993_HPOUT2_MIXER, 4, 1, 0),
1180SOC_DAPM_SINGLE("Right Output Switch", WM8993_HPOUT2_MIXER, 3, 1, 0),
1181};
1182
1183static const struct snd_kcontrol_new left_speaker_mixer[] = {
1184SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
1185SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
1186SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
1187SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
1188};
1189
1190static const struct snd_kcontrol_new right_speaker_mixer[] = {
1191SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
1192SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
1193SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
1194SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
1195};
1196
1197static const struct snd_kcontrol_new left_speaker_boost[] = {
1198SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 5, 1, 0),
1199SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 4, 1, 0),
1200SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 3, 1, 0),
1201};
1202
1203static const struct snd_kcontrol_new right_speaker_boost[] = {
1204SOC_DAPM_SINGLE("Direct Voice Switch", WM8993_SPKOUT_MIXERS, 2, 1, 0),
1205SOC_DAPM_SINGLE("SPKL Switch", WM8993_SPKOUT_MIXERS, 1, 1, 0),
1206SOC_DAPM_SINGLE("SPKR Switch", WM8993_SPKOUT_MIXERS, 0, 1, 0),
1207};
1208
1209static const char *hp_mux_text[] = {
1210 "Mixer",
1211 "DAC",
1212};
1213
1214static const struct soc_enum hpl_enum =
1215 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
1216
1217static const struct snd_kcontrol_new hpl_mux =
1218 SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum);
1219
1220static const struct soc_enum hpr_enum =
1221 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
1222
1223static const struct snd_kcontrol_new hpr_mux =
1224 SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum);
1225
1226static const struct snd_kcontrol_new line1_mix[] = {
1227SOC_DAPM_SINGLE("IN1R Switch", WM8993_LINE_MIXER1, 2, 1, 0),
1228SOC_DAPM_SINGLE("IN1L Switch", WM8993_LINE_MIXER1, 1, 1, 0),
1229SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
1230};
1231
1232static const struct snd_kcontrol_new line1n_mix[] = {
1233SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 6, 1, 0),
1234SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER1, 5, 1, 0),
1235};
1236
1237static const struct snd_kcontrol_new line1p_mix[] = {
1238SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER1, 0, 1, 0),
1239};
1240
1241static const struct snd_kcontrol_new line2_mix[] = {
1242SOC_DAPM_SINGLE("IN2R Switch", WM8993_LINE_MIXER2, 2, 1, 0),
1243SOC_DAPM_SINGLE("IN2L Switch", WM8993_LINE_MIXER2, 1, 1, 0),
1244SOC_DAPM_SINGLE("Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
1245};
1246
1247static const struct snd_kcontrol_new line2n_mix[] = {
1248SOC_DAPM_SINGLE("Left Output Switch", WM8993_LINE_MIXER2, 6, 1, 0),
1249SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 5, 1, 0),
1250};
1251
1252static const struct snd_kcontrol_new line2p_mix[] = {
1253SOC_DAPM_SINGLE("Right Output Switch", WM8993_LINE_MIXER2, 0, 1, 0),
1254};
1255
1256static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
1257SND_SOC_DAPM_INPUT("IN1LN"),
1258SND_SOC_DAPM_INPUT("IN1LP"),
1259SND_SOC_DAPM_INPUT("IN2LN"),
1260SND_SOC_DAPM_INPUT("IN2LP/VXRN"),
1261SND_SOC_DAPM_INPUT("IN1RN"),
1262SND_SOC_DAPM_INPUT("IN1RP"),
1263SND_SOC_DAPM_INPUT("IN2RN"),
1264SND_SOC_DAPM_INPUT("IN2RP/VXRP"),
1265
1266SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
1267 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1268SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
1269SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
1270
1271SND_SOC_DAPM_MICBIAS("MICBIAS2", WM8993_POWER_MANAGEMENT_1, 5, 0),
1272SND_SOC_DAPM_MICBIAS("MICBIAS1", WM8993_POWER_MANAGEMENT_1, 4, 0),
1273
1274SND_SOC_DAPM_MIXER("IN1L PGA", WM8993_POWER_MANAGEMENT_2, 6, 0,
1275 in1l_pga, ARRAY_SIZE(in1l_pga)),
1276SND_SOC_DAPM_MIXER("IN1R PGA", WM8993_POWER_MANAGEMENT_2, 4, 0,
1277 in1r_pga, ARRAY_SIZE(in1r_pga)),
1278
1279SND_SOC_DAPM_MIXER("IN2L PGA", WM8993_POWER_MANAGEMENT_2, 7, 0,
1280 in2l_pga, ARRAY_SIZE(in2l_pga)),
1281SND_SOC_DAPM_MIXER("IN2R PGA", WM8993_POWER_MANAGEMENT_2, 5, 0,
1282 in2r_pga, ARRAY_SIZE(in2r_pga)),
1283
1284/* Dummy widgets to represent differential paths */
1285SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1286
1287SND_SOC_DAPM_MIXER("MIXINL", WM8993_POWER_MANAGEMENT_2, 9, 0,
1288 mixinl, ARRAY_SIZE(mixinl)),
1289SND_SOC_DAPM_MIXER("MIXINR", WM8993_POWER_MANAGEMENT_2, 8, 0,
1290 mixinr, ARRAY_SIZE(mixinr)),
1291
1292SND_SOC_DAPM_ADC("ADCL", "Capture", WM8993_POWER_MANAGEMENT_2, 1, 0),
1293SND_SOC_DAPM_ADC("ADCR", "Capture", WM8993_POWER_MANAGEMENT_2, 0, 0),
1294
1295SND_SOC_DAPM_DAC("DACL", "Playback", WM8993_POWER_MANAGEMENT_3, 1, 0),
1296SND_SOC_DAPM_DAC("DACR", "Playback", WM8993_POWER_MANAGEMENT_3, 0, 0),
1297
1298SND_SOC_DAPM_MIXER("Left Output Mixer", WM8993_POWER_MANAGEMENT_3, 5, 0,
1299 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
1300SND_SOC_DAPM_MIXER("Right Output Mixer", WM8993_POWER_MANAGEMENT_3, 4, 0,
1301 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
1302
1303SND_SOC_DAPM_PGA("Left Output PGA", WM8993_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
1304SND_SOC_DAPM_PGA("Right Output PGA", WM8993_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
1305
1306SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1307 earpiece_mixer, ARRAY_SIZE(earpiece_mixer)),
1308SND_SOC_DAPM_PGA_E("Earpiece Driver", WM8993_POWER_MANAGEMENT_1, 11, 0,
1309 NULL, 0, wm8993_earpiece_event,
1310 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1311
1312SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
1313 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1314SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
1315 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1316
1317SND_SOC_DAPM_MIXER("SPKL Boost", SND_SOC_NOPM, 0, 0,
1318 left_speaker_boost, ARRAY_SIZE(left_speaker_boost)),
1319SND_SOC_DAPM_MIXER("SPKR Boost", SND_SOC_NOPM, 0, 0,
1320 right_speaker_boost, ARRAY_SIZE(right_speaker_boost)),
1321
1322SND_SOC_DAPM_PGA("SPKL Driver", WM8993_POWER_MANAGEMENT_1, 12, 0,
1323 NULL, 0),
1324SND_SOC_DAPM_PGA("SPKR Driver", WM8993_POWER_MANAGEMENT_1, 13, 0,
1325 NULL, 0),
1326
1327SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1328SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1329SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0,
1330 NULL, 0,
1331 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1332
1333SND_SOC_DAPM_MIXER("LINEOUT1 Mixer", SND_SOC_NOPM, 0, 0,
1334 line1_mix, ARRAY_SIZE(line1_mix)),
1335SND_SOC_DAPM_MIXER("LINEOUT2 Mixer", SND_SOC_NOPM, 0, 0,
1336 line2_mix, ARRAY_SIZE(line2_mix)),
1337
1338SND_SOC_DAPM_MIXER("LINEOUT1N Mixer", SND_SOC_NOPM, 0, 0,
1339 line1n_mix, ARRAY_SIZE(line1n_mix)),
1340SND_SOC_DAPM_MIXER("LINEOUT1P Mixer", SND_SOC_NOPM, 0, 0,
1341 line1p_mix, ARRAY_SIZE(line1p_mix)),
1342SND_SOC_DAPM_MIXER("LINEOUT2N Mixer", SND_SOC_NOPM, 0, 0,
1343 line2n_mix, ARRAY_SIZE(line2n_mix)),
1344SND_SOC_DAPM_MIXER("LINEOUT2P Mixer", SND_SOC_NOPM, 0, 0,
1345 line2p_mix, ARRAY_SIZE(line2p_mix)),
1346
1347SND_SOC_DAPM_PGA("LINEOUT1N Driver", WM8993_POWER_MANAGEMENT_3, 13, 0,
1348 NULL, 0),
1349SND_SOC_DAPM_PGA("LINEOUT1P Driver", WM8993_POWER_MANAGEMENT_3, 12, 0,
1350 NULL, 0),
1351SND_SOC_DAPM_PGA("LINEOUT2N Driver", WM8993_POWER_MANAGEMENT_3, 11, 0,
1352 NULL, 0),
1353SND_SOC_DAPM_PGA("LINEOUT2P Driver", WM8993_POWER_MANAGEMENT_3, 10, 0,
1354 NULL, 0),
1355
1356SND_SOC_DAPM_OUTPUT("SPKOUTLP"),
1357SND_SOC_DAPM_OUTPUT("SPKOUTLN"),
1358SND_SOC_DAPM_OUTPUT("SPKOUTRP"),
1359SND_SOC_DAPM_OUTPUT("SPKOUTRN"),
1360SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1361SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1362SND_SOC_DAPM_OUTPUT("HPOUT2P"),
1363SND_SOC_DAPM_OUTPUT("HPOUT2N"),
1364SND_SOC_DAPM_OUTPUT("LINEOUT1P"),
1365SND_SOC_DAPM_OUTPUT("LINEOUT1N"),
1366SND_SOC_DAPM_OUTPUT("LINEOUT2P"),
1367SND_SOC_DAPM_OUTPUT("LINEOUT2N"),
1368};
1369
1370static const struct snd_soc_dapm_route routes[] = {
1371 { "IN1L PGA", "IN1LP Switch", "IN1LP" },
1372 { "IN1L PGA", "IN1LN Switch", "IN1LN" },
1373
1374 { "IN1R PGA", "IN1RP Switch", "IN1RP" },
1375 { "IN1R PGA", "IN1RN Switch", "IN1RN" },
1376
1377 { "IN2L PGA", "IN2LP Switch", "IN2LP/VXRN" },
1378 { "IN2L PGA", "IN2LN Switch", "IN2LN" },
1379
1380 { "IN2R PGA", "IN2RP Switch", "IN2RP/VXRP" },
1381 { "IN2R PGA", "IN2RN Switch", "IN2RN" },
1382
1383 { "Direct Voice", NULL, "IN2LP/VXRN" },
1384 { "Direct Voice", NULL, "IN2RP/VXRP" },
1385
1386 { "MIXINL", "IN1L Switch", "IN1L PGA" },
1387 { "MIXINL", "IN2L Switch", "IN2L PGA" },
1388 { "MIXINL", NULL, "Direct Voice" },
1389 { "MIXINL", NULL, "IN1LP" },
1390 { "MIXINL", NULL, "Left Output Mixer" },
1391
1392 { "MIXINR", "IN1R Switch", "IN1R PGA" },
1393 { "MIXINR", "IN2R Switch", "IN2R PGA" },
1394 { "MIXINR", NULL, "Direct Voice" },
1395 { "MIXINR", NULL, "IN1RP" },
1396 { "MIXINR", NULL, "Right Output Mixer" },
1397
1398 { "ADCL", NULL, "MIXINL" },
1399 { "ADCL", NULL, "CLK_SYS" },
1400 { "ADCL", NULL, "CLK_DSP" },
1401 { "ADCR", NULL, "MIXINR" },
1402 { "ADCR", NULL, "CLK_SYS" },
1403 { "ADCR", NULL, "CLK_DSP" },
1404
1405 { "DACL", NULL, "CLK_SYS" },
1406 { "DACL", NULL, "CLK_DSP" },
1407 { "DACR", NULL, "CLK_SYS" },
1408 { "DACR", NULL, "CLK_DSP" },
1409
1410 { "Left Output Mixer", "Left Input Switch", "MIXINL" },
1411 { "Left Output Mixer", "Right Input Switch", "MIXINR" },
1412 { "Left Output Mixer", "IN2RN Switch", "IN2RN" },
1413 { "Left Output Mixer", "IN2LN Switch", "IN2LN" },
1414 { "Left Output Mixer", "IN2LP Switch", "IN2LP/VXRN" },
1415 { "Left Output Mixer", "IN1L Switch", "IN1L PGA" },
1416 { "Left Output Mixer", "IN1R Switch", "IN1R PGA" },
1417 { "Left Output Mixer", "DAC Switch", "DACL" },
1418
1419 { "Right Output Mixer", "Left Input Switch", "MIXINL" },
1420 { "Right Output Mixer", "Right Input Switch", "MIXINR" },
1421 { "Right Output Mixer", "IN2LN Switch", "IN2LN" },
1422 { "Right Output Mixer", "IN2RN Switch", "IN2RN" },
1423 { "Right Output Mixer", "IN2RP Switch", "IN2RP/VXRP" },
1424 { "Right Output Mixer", "IN1L Switch", "IN1L PGA" },
1425 { "Right Output Mixer", "IN1R Switch", "IN1R PGA" },
1426 { "Right Output Mixer", "DAC Switch", "DACR" },
1427
1428 { "Left Output PGA", NULL, "Left Output Mixer" },
1429 { "Left Output PGA", NULL, "CLK_SYS" },
1430 { "Left Output PGA", NULL, "TOCLK" },
1431
1432 { "Right Output PGA", NULL, "Right Output Mixer" },
1433 { "Right Output PGA", NULL, "CLK_SYS" },
1434 { "Right Output PGA", NULL, "TOCLK" },
1435
1436 { "Earpiece Mixer", "Direct Voice Switch", "Direct Voice" },
1437 { "Earpiece Mixer", "Left Output Switch", "Left Output PGA" },
1438 { "Earpiece Mixer", "Right Output Switch", "Right Output PGA" },
1439
1440 { "Earpiece Driver", NULL, "Earpiece Mixer" },
1441 { "HPOUT2N", NULL, "Earpiece Driver" },
1442 { "HPOUT2P", NULL, "Earpiece Driver" },
1443
1444 { "SPKL", "Input Switch", "MIXINL" },
1445 { "SPKL", "IN1LP Switch", "IN1LP" },
1446 { "SPKL", "Output Switch", "Left Output Mixer" },
1447 { "SPKL", "DAC Switch", "DACL" },
1448 { "SPKL", NULL, "CLK_SYS" },
1449 { "SPKL", NULL, "TOCLK" },
1450
1451 { "SPKR", "Input Switch", "MIXINR" },
1452 { "SPKR", "IN1RP Switch", "IN1RP" },
1453 { "SPKR", "Output Switch", "Right Output Mixer" },
1454 { "SPKR", "DAC Switch", "DACR" },
1455 { "SPKR", NULL, "CLK_SYS" },
1456 { "SPKR", NULL, "TOCLK" },
1457
1458 { "SPKL Boost", "Direct Voice Switch", "Direct Voice" },
1459 { "SPKL Boost", "SPKL Switch", "SPKL" },
1460 { "SPKL Boost", "SPKR Switch", "SPKR" },
1461
1462 { "SPKR Boost", "Direct Voice Switch", "Direct Voice" },
1463 { "SPKR Boost", "SPKR Switch", "SPKR" },
1464 { "SPKR Boost", "SPKL Switch", "SPKL" },
1465
1466 { "SPKL Driver", NULL, "SPKL Boost" },
1467 { "SPKL Driver", NULL, "CLK_SYS" },
1468
1469 { "SPKR Driver", NULL, "SPKR Boost" },
1470 { "SPKR Driver", NULL, "CLK_SYS" },
1471
1472 { "SPKOUTLP", NULL, "SPKL Driver" },
1473 { "SPKOUTLN", NULL, "SPKL Driver" },
1474 { "SPKOUTRP", NULL, "SPKR Driver" },
1475 { "SPKOUTRN", NULL, "SPKR Driver" },
1476
1477 { "Left Headphone Mux", "DAC", "DACL" },
1478 { "Left Headphone Mux", "Mixer", "Left Output Mixer" },
1479 { "Right Headphone Mux", "DAC", "DACR" },
1480 { "Right Headphone Mux", "Mixer", "Right Output Mixer" },
1481
1482 { "Headphone PGA", NULL, "Left Headphone Mux" },
1483 { "Headphone PGA", NULL, "Right Headphone Mux" },
1484 { "Headphone PGA", NULL, "CLK_SYS" },
1485 { "Headphone PGA", NULL, "TOCLK" },
1486
1487 { "HPOUT1L", NULL, "Headphone PGA" },
1488 { "HPOUT1R", NULL, "Headphone PGA" },
1489
1490 { "LINEOUT1N", NULL, "LINEOUT1N Driver" },
1491 { "LINEOUT1P", NULL, "LINEOUT1P Driver" },
1492 { "LINEOUT2N", NULL, "LINEOUT2N Driver" },
1493 { "LINEOUT2P", NULL, "LINEOUT2P Driver" },
1494};
1495
1496static const struct snd_soc_dapm_route lineout1_diff_routes[] = {
1497 { "LINEOUT1 Mixer", "IN1L Switch", "IN1L PGA" },
1498 { "LINEOUT1 Mixer", "IN1R Switch", "IN1R PGA" },
1499 { "LINEOUT1 Mixer", "Output Switch", "Left Output Mixer" },
1500
1501 { "LINEOUT1N Driver", NULL, "LINEOUT1 Mixer" },
1502 { "LINEOUT1P Driver", NULL, "LINEOUT1 Mixer" },
1503};
1504
1505static const struct snd_soc_dapm_route lineout1_se_routes[] = {
1506 { "LINEOUT1N Mixer", "Left Output Switch", "Left Output Mixer" },
1507 { "LINEOUT1N Mixer", "Right Output Switch", "Left Output Mixer" },
1508
1509 { "LINEOUT1P Mixer", "Left Output Switch", "Left Output Mixer" },
1510
1511 { "LINEOUT1N Driver", NULL, "LINEOUT1N Mixer" },
1512 { "LINEOUT1P Driver", NULL, "LINEOUT1P Mixer" },
1513};
1514
1515static const struct snd_soc_dapm_route lineout2_diff_routes[] = {
1516 { "LINEOUT2 Mixer", "IN2L Switch", "IN2L PGA" },
1517 { "LINEOUT2 Mixer", "IN2R Switch", "IN2R PGA" },
1518 { "LINEOUT2 Mixer", "Output Switch", "Right Output Mixer" },
1519
1520 { "LINEOUT2N Driver", NULL, "LINEOUT2 Mixer" },
1521 { "LINEOUT2P Driver", NULL, "LINEOUT2 Mixer" },
1522};
1523
1524static const struct snd_soc_dapm_route lineout2_se_routes[] = {
1525 { "LINEOUT2N Mixer", "Left Output Switch", "Left Output Mixer" },
1526 { "LINEOUT2N Mixer", "Right Output Switch", "Left Output Mixer" },
1527
1528 { "LINEOUT2P Mixer", "Right Output Switch", "Right Output Mixer" },
1529
1530 { "LINEOUT2N Driver", NULL, "LINEOUT2N Mixer" },
1531 { "LINEOUT2P Driver", NULL, "LINEOUT2P Mixer" },
1532};
1533
1534static int wm8993_set_bias_level(struct snd_soc_codec *codec,
1535 enum snd_soc_bias_level level)
1536{
1537 struct wm8993_priv *wm8993 = codec->private_data;
1538
1539 switch (level) {
1540 case SND_SOC_BIAS_ON:
1541 case SND_SOC_BIAS_PREPARE:
1542 /* VMID=2*40k */
1543 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1544 WM8993_VMID_SEL_MASK, 0x2);
1545 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
1546 WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
1547 break;
1548
1549 case SND_SOC_BIAS_STANDBY:
1550 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1551 /* Bring up VMID with fast soft start */
1552 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1553 WM8993_STARTUP_BIAS_ENA |
1554 WM8993_VMID_BUF_ENA |
1555 WM8993_VMID_RAMP_MASK |
1556 WM8993_BIAS_SRC,
1557 WM8993_STARTUP_BIAS_ENA |
1558 WM8993_VMID_BUF_ENA |
1559 WM8993_VMID_RAMP_MASK |
1560 WM8993_BIAS_SRC);
1561
1562 /* If either line output is single ended we
1563 * need the VMID buffer */
1564 if (!wm8993->pdata.lineout1_diff ||
1565 !wm8993->pdata.lineout2_diff)
1566 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1567 WM8993_LINEOUT_VMID_BUF_ENA,
1568 WM8993_LINEOUT_VMID_BUF_ENA);
1569
1570 /* VMID=2*40k */
1571 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1572 WM8993_VMID_SEL_MASK |
1573 WM8993_BIAS_ENA,
1574 WM8993_BIAS_ENA | 0x2);
1575 msleep(32);
1576
1577 /* Switch to normal bias */
1578 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1579 WM8993_BIAS_SRC |
1580 WM8993_STARTUP_BIAS_ENA, 0);
1581 }
1582
1583 /* VMID=2*240k */
1584 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1585 WM8993_VMID_SEL_MASK, 0x4);
1586
1587 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
1588 WM8993_TSHUT_ENA, 0);
1589 break;
1590
1591 case SND_SOC_BIAS_OFF:
1592 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1593 WM8993_LINEOUT_VMID_BUF_ENA, 0);
1594
1595 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1596 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
1597 0);
1598 break;
1599 }
1600
1601 codec->bias_level = level;
1602
1603 return 0;
1604}
1605
1606static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
1607 int clk_id, unsigned int freq, int dir)
1608{
1609 struct snd_soc_codec *codec = codec_dai->codec;
1610 struct wm8993_priv *wm8993 = codec->private_data;
1611
1612 switch (clk_id) {
1613 case WM8993_SYSCLK_MCLK:
1614 wm8993->mclk_rate = freq;
1615 case WM8993_SYSCLK_FLL:
1616 wm8993->sysclk_source = clk_id;
1617 break;
1618
1619 default:
1620 return -EINVAL;
1621 }
1622
1623 return 0;
1624}
1625
1626static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
1627 unsigned int fmt)
1628{
1629 struct snd_soc_codec *codec = dai->codec;
1630 struct wm8993_priv *wm8993 = codec->private_data;
1631 unsigned int aif1 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_1);
1632 unsigned int aif4 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_4);
1633
1634 aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1635 WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1636 aif4 &= ~WM8993_LRCLK_DIR;
1637
1638 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1639 case SND_SOC_DAIFMT_CBS_CFS:
1640 wm8993->master = 0;
1641 break;
1642 case SND_SOC_DAIFMT_CBS_CFM:
1643 aif4 |= WM8993_LRCLK_DIR;
1644 wm8993->master = 1;
1645 break;
1646 case SND_SOC_DAIFMT_CBM_CFS:
1647 aif1 |= WM8993_BCLK_DIR;
1648 wm8993->master = 1;
1649 break;
1650 case SND_SOC_DAIFMT_CBM_CFM:
1651 aif1 |= WM8993_BCLK_DIR;
1652 aif4 |= WM8993_LRCLK_DIR;
1653 wm8993->master = 1;
1654 break;
1655 default:
1656 return -EINVAL;
1657 }
1658
1659 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1660 case SND_SOC_DAIFMT_DSP_B:
1661 aif1 |= WM8993_AIF_LRCLK_INV;
1662 case SND_SOC_DAIFMT_DSP_A:
1663 aif1 |= 0x18;
1664 break;
1665 case SND_SOC_DAIFMT_I2S:
1666 aif1 |= 0x10;
1667 break;
1668 case SND_SOC_DAIFMT_RIGHT_J:
1669 break;
1670 case SND_SOC_DAIFMT_LEFT_J:
1671 aif1 |= 0x8;
1672 break;
1673 default:
1674 return -EINVAL;
1675 }
1676
1677 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1678 case SND_SOC_DAIFMT_DSP_A:
1679 case SND_SOC_DAIFMT_DSP_B:
1680 /* frame inversion not valid for DSP modes */
1681 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1682 case SND_SOC_DAIFMT_NB_NF:
1683 break;
1684 case SND_SOC_DAIFMT_IB_NF:
1685 aif1 |= WM8993_AIF_BCLK_INV;
1686 break;
1687 default:
1688 return -EINVAL;
1689 }
1690 break;
1691
1692 case SND_SOC_DAIFMT_I2S:
1693 case SND_SOC_DAIFMT_RIGHT_J:
1694 case SND_SOC_DAIFMT_LEFT_J:
1695 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1696 case SND_SOC_DAIFMT_NB_NF:
1697 break;
1698 case SND_SOC_DAIFMT_IB_IF:
1699 aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1700 break;
1701 case SND_SOC_DAIFMT_IB_NF:
1702 aif1 |= WM8993_AIF_BCLK_INV;
1703 break;
1704 case SND_SOC_DAIFMT_NB_IF:
1705 aif1 |= WM8993_AIF_LRCLK_INV;
1706 break;
1707 default:
1708 return -EINVAL;
1709 }
1710 break;
1711 default:
1712 return -EINVAL;
1713 }
1714
1715 wm8993_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1716 wm8993_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1717
1718 return 0;
1719}
1720
1721static int wm8993_hw_params(struct snd_pcm_substream *substream,
1722 struct snd_pcm_hw_params *params,
1723 struct snd_soc_dai *dai)
1724{
1725 struct snd_soc_codec *codec = dai->codec;
1726 struct wm8993_priv *wm8993 = codec->private_data;
1727 int ret, i, best, best_val, cur_val;
1728 unsigned int clocking1, clocking3, aif1, aif4;
1729
1730 clocking1 = wm8993_read(codec, WM8993_CLOCKING_1);
1731 clocking1 &= ~WM8993_BCLK_DIV_MASK;
1732
1733 clocking3 = wm8993_read(codec, WM8993_CLOCKING_3);
1734 clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1735
1736 aif1 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_1);
1737 aif1 &= ~WM8993_AIF_WL_MASK;
1738
1739 aif4 = wm8993_read(codec, WM8993_AUDIO_INTERFACE_4);
1740 aif4 &= ~WM8993_LRCLK_RATE_MASK;
1741
1742 /* What BCLK do we need? */
1743 wm8993->fs = params_rate(params);
1744 wm8993->bclk = 2 * wm8993->fs;
1745 switch (params_format(params)) {
1746 case SNDRV_PCM_FORMAT_S16_LE:
1747 wm8993->bclk *= 16;
1748 break;
1749 case SNDRV_PCM_FORMAT_S20_3LE:
1750 wm8993->bclk *= 20;
1751 aif1 |= 0x8;
1752 break;
1753 case SNDRV_PCM_FORMAT_S24_LE:
1754 wm8993->bclk *= 24;
1755 aif1 |= 0x10;
1756 break;
1757 case SNDRV_PCM_FORMAT_S32_LE:
1758 wm8993->bclk *= 32;
1759 aif1 |= 0x18;
1760 break;
1761 default:
1762 return -EINVAL;
1763 }
1764
1765 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1766
1767 ret = configure_clock(codec);
1768 if (ret != 0)
1769 return ret;
1770
1771 /* Select nearest CLK_SYS_RATE */
1772 best = 0;
1773 best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1774 - wm8993->fs);
1775 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1776 cur_val = abs((wm8993->sysclk_rate /
1777 clk_sys_rates[i].ratio) - wm8993->fs);;
1778 if (cur_val < best_val) {
1779 best = i;
1780 best_val = cur_val;
1781 }
1782 }
1783 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1784 clk_sys_rates[best].ratio);
1785 clocking3 |= (clk_sys_rates[best].clk_sys_rate
1786 << WM8993_CLK_SYS_RATE_SHIFT);
1787
1788 /* SAMPLE_RATE */
1789 best = 0;
1790 best_val = abs(wm8993->fs - sample_rates[0].rate);
1791 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1792 /* Closest match */
1793 cur_val = abs(wm8993->fs - sample_rates[i].rate);
1794 if (cur_val < best_val) {
1795 best = i;
1796 best_val = cur_val;
1797 }
1798 }
1799 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1800 sample_rates[best].rate);
Mark Browne465d542009-07-15 10:01:30 +0100[diff] [blame]1801 clocking3 |= (sample_rates[best].sample_rate
1802 << WM8993_SAMPLE_RATE_SHIFT);
Mark Brown942c4352009-06-05 16:32:59 +0100[diff] [blame]1803
1804 /* BCLK_DIV */
1805 best = 0;
1806 best_val = INT_MAX;
1807 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1808 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1809 - wm8993->bclk;
1810 if (cur_val < 0) /* Table is sorted */
1811 break;
1812 if (cur_val < best_val) {
1813 best = i;
1814 best_val = cur_val;
1815 }
1816 }
1817 wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1818 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1819 bclk_divs[best].div, wm8993->bclk);
1820 clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1821
1822 /* LRCLK is a simple fraction of BCLK */
1823 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1824 aif4 |= wm8993->bclk / wm8993->fs;
1825
1826 wm8993_write(codec, WM8993_CLOCKING_1, clocking1);
1827 wm8993_write(codec, WM8993_CLOCKING_3, clocking3);
1828 wm8993_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1829 wm8993_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1830
1831 /* ReTune Mobile? */
1832 if (wm8993->pdata.num_retune_configs) {
1833 u16 eq1 = wm8993_read(codec, WM8993_EQ1);
1834 struct wm8993_retune_mobile_setting *s;
1835
1836 best = 0;
1837 best_val = abs(wm8993->pdata.retune_configs[0].rate
1838 - wm8993->fs);
1839 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1840 cur_val = abs(wm8993->pdata.retune_configs[i].rate
1841 - wm8993->fs);
1842 if (cur_val < best_val) {
1843 best_val = cur_val;
1844 best = i;
1845 }
1846 }
1847 s = &wm8993->pdata.retune_configs[best];
1848
1849 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1850 s->name, s->rate);
1851
1852 /* Disable EQ while we reconfigure */
1853 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0);
1854
1855 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1856 wm8993_write(codec, WM8993_EQ1 + i, s->config[i]);
1857
1858 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1859 }
1860
1861 return 0;
1862}
1863
1864static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1865{
1866 struct snd_soc_codec *codec = codec_dai->codec;
1867 unsigned int reg;
1868
1869 reg = wm8993_read(codec, WM8993_DAC_CTRL);
1870
1871 if (mute)
1872 reg |= WM8993_DAC_MUTE;
1873 else
1874 reg &= ~WM8993_DAC_MUTE;
1875
1876 wm8993_write(codec, WM8993_DAC_CTRL, reg);
1877
1878 return 0;
1879}
1880
1881static struct snd_soc_dai_ops wm8993_ops = {
1882 .set_sysclk = wm8993_set_sysclk,
1883 .set_fmt = wm8993_set_dai_fmt,
1884 .hw_params = wm8993_hw_params,
1885 .digital_mute = wm8993_digital_mute,
1886 .set_pll = wm8993_set_fll,
1887};
1888
1889#define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1890
1891#define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1892 SNDRV_PCM_FMTBIT_S20_3LE |\
1893 SNDRV_PCM_FMTBIT_S24_LE |\
1894 SNDRV_PCM_FMTBIT_S32_LE)
1895
1896struct snd_soc_dai wm8993_dai = {
1897 .name = "WM8993",
1898 .playback = {
1899 .stream_name = "Playback",
1900 .channels_min = 1,
1901 .channels_max = 2,
1902 .rates = WM8993_RATES,
1903 .formats = WM8993_FORMATS,
1904 },
1905 .capture = {
1906 .stream_name = "Capture",
1907 .channels_min = 1,
1908 .channels_max = 2,
1909 .rates = WM8993_RATES,
1910 .formats = WM8993_FORMATS,
1911 },
1912 .ops = &wm8993_ops,
1913 .symmetric_rates = 1,
1914};
1915EXPORT_SYMBOL_GPL(wm8993_dai);
1916
1917static struct snd_soc_codec *wm8993_codec;
1918
1919static int wm8993_probe(struct platform_device *pdev)
1920{
1921 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1922 struct snd_soc_codec *codec;
1923 struct wm8993_priv *wm8993;
1924 int ret = 0;
1925
1926 if (!wm8993_codec) {
1927 dev_err(&pdev->dev, "I2C device not yet probed\n");
1928 goto err;
1929 }
1930
1931 socdev->card->codec = wm8993_codec;
1932 codec = wm8993_codec;
1933 wm8993 = codec->private_data;
1934
1935 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1936 if (ret < 0) {
1937 dev_err(codec->dev, "failed to create pcms\n");
1938 goto err;
1939 }
1940
1941 snd_soc_add_controls(codec, wm8993_snd_controls,
1942 ARRAY_SIZE(wm8993_snd_controls));
1943 if (wm8993->pdata.num_retune_configs != 0) {
1944 dev_dbg(codec->dev, "Using ReTune Mobile\n");
1945 } else {
1946 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n");
1947 snd_soc_add_controls(codec, wm8993_eq_controls,
1948 ARRAY_SIZE(wm8993_eq_controls));
1949 }
1950
1951 snd_soc_dapm_new_controls(codec, wm8993_dapm_widgets,
1952 ARRAY_SIZE(wm8993_dapm_widgets));
1953
1954 snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes));
1955
1956 if (wm8993->pdata.lineout1_diff)
1957 snd_soc_dapm_add_routes(codec,
1958 lineout1_diff_routes,
1959 ARRAY_SIZE(lineout1_diff_routes));
1960 else
1961 snd_soc_dapm_add_routes(codec,
1962 lineout1_se_routes,
1963 ARRAY_SIZE(lineout1_se_routes));
1964
1965 if (wm8993->pdata.lineout2_diff)
1966 snd_soc_dapm_add_routes(codec,
1967 lineout2_diff_routes,
1968 ARRAY_SIZE(lineout2_diff_routes));
1969 else
1970 snd_soc_dapm_add_routes(codec,
1971 lineout2_se_routes,
1972 ARRAY_SIZE(lineout2_se_routes));
1973
1974 snd_soc_dapm_new_widgets(codec);
1975
1976 ret = snd_soc_init_card(socdev);
1977 if (ret < 0) {
1978 dev_err(codec->dev, "failed to register card\n");
1979 goto card_err;
1980 }
1981
1982 return ret;
1983
1984card_err:
1985 snd_soc_free_pcms(socdev);
1986 snd_soc_dapm_free(socdev);
1987err:
1988 return ret;
1989}
1990
1991static int wm8993_remove(struct platform_device *pdev)
1992{
1993 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1994
1995 snd_soc_free_pcms(socdev);
1996 snd_soc_dapm_free(socdev);
1997
1998 return 0;
1999}
2000
2001struct snd_soc_codec_device soc_codec_dev_wm8993 = {
2002 .probe = wm8993_probe,
2003 .remove = wm8993_remove,
2004};
2005EXPORT_SYMBOL_GPL(soc_codec_dev_wm8993);
2006
2007static int wm8993_i2c_probe(struct i2c_client *i2c,
2008 const struct i2c_device_id *id)
2009{
2010 struct wm8993_priv *wm8993;
2011 struct snd_soc_codec *codec;
2012 unsigned int val;
2013 int ret;
2014
2015 if (wm8993_codec) {
2016 dev_err(&i2c->dev, "A WM8993 is already registered\n");
2017 return -EINVAL;
2018 }
2019
2020 wm8993 = kzalloc(sizeof(struct wm8993_priv), GFP_KERNEL);
2021 if (wm8993 == NULL)
2022 return -ENOMEM;
2023
2024 codec = &wm8993->codec;
2025 if (i2c->dev.platform_data)
2026 memcpy(&wm8993->pdata, i2c->dev.platform_data,
2027 sizeof(wm8993->pdata));
2028
2029 mutex_init(&codec->mutex);
2030 INIT_LIST_HEAD(&codec->dapm_widgets);
2031 INIT_LIST_HEAD(&codec->dapm_paths);
2032
2033 codec->name = "WM8993";
2034 codec->read = wm8993_read;
2035 codec->write = wm8993_write;
2036 codec->hw_write = (hw_write_t)i2c_master_send;
2037 codec->reg_cache = wm8993->reg_cache;
2038 codec->reg_cache_size = ARRAY_SIZE(wm8993->reg_cache);
2039 codec->bias_level = SND_SOC_BIAS_OFF;
2040 codec->set_bias_level = wm8993_set_bias_level;
2041 codec->dai = &wm8993_dai;
2042 codec->num_dai = 1;
2043 codec->private_data = wm8993;
2044
2045 memcpy(wm8993->reg_cache, wm8993_reg_defaults,
2046 sizeof(wm8993->reg_cache));
2047
2048 i2c_set_clientdata(i2c, wm8993);
2049 codec->control_data = i2c;
2050 wm8993_codec = codec;
2051
2052 codec->dev = &i2c->dev;
2053
2054 val = wm8993_read_hw(codec, WM8993_SOFTWARE_RESET);
2055 if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) {
2056 dev_err(codec->dev, "Invalid ID register value %x\n", val);
2057 ret = -EINVAL;
2058 goto err;
2059 }
2060
2061 ret = wm8993_write(codec, WM8993_SOFTWARE_RESET, 0xffff);
2062 if (ret != 0)
2063 goto err;
2064
2065 /* By default we're using the output mixers */
2066 wm8993->class_w_users = 2;
2067
2068 /* Latch volume update bits and default ZC on */
2069 snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_1_2_VOLUME,
2070 WM8993_IN1_VU, WM8993_IN1_VU);
2071 snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_1_2_VOLUME,
2072 WM8993_IN1_VU, WM8993_IN1_VU);
2073 snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_3_4_VOLUME,
2074 WM8993_IN2_VU, WM8993_IN2_VU);
2075 snd_soc_update_bits(codec, WM8993_RIGHT_LINE_INPUT_3_4_VOLUME,
2076 WM8993_IN2_VU, WM8993_IN2_VU);
2077
2078 snd_soc_update_bits(codec, WM8993_SPEAKER_VOLUME_RIGHT,
2079 WM8993_SPKOUT_VU, WM8993_SPKOUT_VU);
2080
2081 snd_soc_update_bits(codec, WM8993_LEFT_OUTPUT_VOLUME,
2082 WM8993_HPOUT1L_ZC, WM8993_HPOUT1L_ZC);
2083 snd_soc_update_bits(codec, WM8993_RIGHT_OUTPUT_VOLUME,
2084 WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC,
2085 WM8993_HPOUT1_VU | WM8993_HPOUT1R_ZC);
2086
2087 snd_soc_update_bits(codec, WM8993_LEFT_OPGA_VOLUME,
2088 WM8993_MIXOUTL_ZC, WM8993_MIXOUTL_ZC);
2089 snd_soc_update_bits(codec, WM8993_RIGHT_OPGA_VOLUME,
2090 WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU,
2091 WM8993_MIXOUTR_ZC | WM8993_MIXOUT_VU);
2092
2093 snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
2094 WM8993_DAC_VU, WM8993_DAC_VU);
2095 snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
2096 WM8993_ADC_VU, WM8993_ADC_VU);
2097
2098 /* Manualy manage the HPOUT sequencing for independent stereo
2099 * control. */
2100 snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
2101 WM8993_HPOUT1_AUTO_PU, 0);
2102
2103 /* Use automatic clock configuration */
2104 snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
2105
2106 if (!wm8993->pdata.lineout1_diff)
2107 snd_soc_update_bits(codec, WM8993_LINE_MIXER1,
2108 WM8993_LINEOUT1_MODE,
2109 WM8993_LINEOUT1_MODE);
2110 if (!wm8993->pdata.lineout2_diff)
2111 snd_soc_update_bits(codec, WM8993_LINE_MIXER2,
2112 WM8993_LINEOUT2_MODE,
2113 WM8993_LINEOUT2_MODE);
2114
2115 if (wm8993->pdata.lineout1fb)
2116 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
2117 WM8993_LINEOUT1_FB, WM8993_LINEOUT1_FB);
2118
2119 if (wm8993->pdata.lineout2fb)
2120 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
2121 WM8993_LINEOUT2_FB, WM8993_LINEOUT2_FB);
2122
2123 /* Apply the microphone bias/detection configuration - the
2124 * platform data is directly applicable to the register. */
2125 snd_soc_update_bits(codec, WM8993_MICBIAS,
2126 WM8993_JD_SCTHR_MASK | WM8993_JD_THR_MASK |
2127 WM8993_MICB1_LVL | WM8993_MICB2_LVL,
2128 wm8993->pdata.jd_scthr << WM8993_JD_SCTHR_SHIFT |
2129 wm8993->pdata.jd_thr << WM8993_JD_THR_SHIFT |
2130 wm8993->pdata.micbias1_lvl |
2131 wm8993->pdata.micbias1_lvl << 1);
2132
2133 ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2134 if (ret != 0)
2135 goto err;
2136
2137 wm8993_dai.dev = codec->dev;
2138
2139 ret = snd_soc_register_dai(&wm8993_dai);
2140 if (ret != 0)
2141 goto err_bias;
2142
2143 ret = snd_soc_register_codec(codec);
2144
2145 return 0;
2146
2147err_bias:
2148 wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
2149err:
2150 wm8993_codec = NULL;
2151 kfree(wm8993);
2152 return ret;
2153}
2154
2155static int wm8993_i2c_remove(struct i2c_client *client)
2156{
2157 struct wm8993_priv *wm8993 = i2c_get_clientdata(client);
2158
2159 snd_soc_unregister_codec(&wm8993->codec);
2160 snd_soc_unregister_dai(&wm8993_dai);
2161
2162 wm8993_set_bias_level(&wm8993->codec, SND_SOC_BIAS_OFF);
2163 kfree(wm8993);
2164
2165 return 0;
2166}
2167
2168static const struct i2c_device_id wm8993_i2c_id[] = {
2169 { "wm8993", 0 },
2170 { }
2171};
2172MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
2173
2174static struct i2c_driver wm8993_i2c_driver = {
2175 .driver = {
2176 .name = "WM8993",
2177 .owner = THIS_MODULE,
2178 },
2179 .probe = wm8993_i2c_probe,
2180 .remove = wm8993_i2c_remove,
2181 .id_table = wm8993_i2c_id,
2182};
2183
2184
2185static int __init wm8993_modinit(void)
2186{
2187 int ret;
2188
2189 ret = i2c_add_driver(&wm8993_i2c_driver);
2190 if (ret != 0)
2191 pr_err("WM8993: Unable to register I2C driver: %d\n", ret);
2192
2193 return ret;
2194}
2195module_init(wm8993_modinit);
2196
2197static void __exit wm8993_exit(void)
2198{
2199 i2c_del_driver(&wm8993_i2c_driver);
2200}
2201module_exit(wm8993_exit);
2202
2203
2204MODULE_DESCRIPTION("ASoC WM8993 driver");
2205MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2206MODULE_LICENSE("GPL");