Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2003 - 2006 NetXen, Inc. |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version 2 |
| 8 | * of the License, or (at your option) any later version. |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 9 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 10 | * This program is distributed in the hope that it will be useful, but |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 14 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, |
| 18 | * MA 02111-1307, USA. |
| 19 | * |
| 20 | * The full GNU General Public License is included in this distribution |
| 21 | * in the file called LICENSE. |
| 22 | * |
| 23 | * Contact Information: |
| 24 | * info@netxen.com |
| 25 | * NetXen, |
| 26 | * 3965 Freedom Circle, Fourth floor, |
| 27 | * Santa Clara, CA 95054 |
| 28 | */ |
| 29 | |
| 30 | #ifndef __NIC_PHAN_REG_H_ |
| 31 | #define __NIC_PHAN_REG_H_ |
| 32 | |
| 33 | /* |
| 34 | * CRB Registers or queue message done only at initialization time. |
| 35 | */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 36 | #define NIC_CRB_BASE NETXEN_CAM_RAM(0x200) |
| 37 | #define NETXEN_NIC_REG(X) (NIC_CRB_BASE+(X)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 38 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 39 | #define CRB_PHAN_CNTRL_LO_OFFSET NETXEN_NIC_REG(0x00) |
| 40 | #define CRB_PHAN_CNTRL_HI_OFFSET NETXEN_NIC_REG(0x04) |
| 41 | #define CRB_CMD_PRODUCER_OFFSET NETXEN_NIC_REG(0x08) |
| 42 | #define CRB_CMD_CONSUMER_OFFSET NETXEN_NIC_REG(0x0c) |
| 43 | #define CRB_PAUSE_ADDR_LO NETXEN_NIC_REG(0x10) /* C0 EPG BUG */ |
| 44 | #define CRB_PAUSE_ADDR_HI NETXEN_NIC_REG(0x14) |
| 45 | #define CRB_HOST_CMD_ADDR_HI NETXEN_NIC_REG(0x18) /* host add:cmd ring */ |
| 46 | #define CRB_HOST_CMD_ADDR_LO NETXEN_NIC_REG(0x1c) |
| 47 | #define CRB_CMD_INTR_LOOP NETXEN_NIC_REG(0x20) /* 4 regs for perf */ |
| 48 | #define CRB_CMD_DMA_LOOP NETXEN_NIC_REG(0x24) |
| 49 | #define CRB_RCV_INTR_LOOP NETXEN_NIC_REG(0x28) |
| 50 | #define CRB_RCV_DMA_LOOP NETXEN_NIC_REG(0x2c) |
| 51 | #define CRB_ENABLE_TX_INTR NETXEN_NIC_REG(0x30) /* phantom init status */ |
| 52 | #define CRB_MMAP_ADDR_3 NETXEN_NIC_REG(0x34) |
| 53 | #define CRB_CMDPEG_CMDRING NETXEN_NIC_REG(0x38) |
| 54 | #define CRB_HOST_DUMMY_BUF_ADDR_HI NETXEN_NIC_REG(0x3c) |
| 55 | #define CRB_HOST_DUMMY_BUF_ADDR_LO NETXEN_NIC_REG(0x40) |
| 56 | #define CRB_MMAP_ADDR_0 NETXEN_NIC_REG(0x44) |
| 57 | #define CRB_MMAP_ADDR_1 NETXEN_NIC_REG(0x48) |
| 58 | #define CRB_MMAP_ADDR_2 NETXEN_NIC_REG(0x4c) |
| 59 | #define CRB_CMDPEG_STATE NETXEN_NIC_REG(0x50) |
| 60 | #define CRB_MMAP_SIZE_0 NETXEN_NIC_REG(0x54) |
| 61 | #define CRB_MMAP_SIZE_1 NETXEN_NIC_REG(0x58) |
| 62 | #define CRB_MMAP_SIZE_2 NETXEN_NIC_REG(0x5c) |
| 63 | #define CRB_MMAP_SIZE_3 NETXEN_NIC_REG(0x60) |
| 64 | #define CRB_GLOBAL_INT_COAL NETXEN_NIC_REG(0x64) /* interrupt coalescing */ |
| 65 | #define CRB_INT_COAL_MODE NETXEN_NIC_REG(0x68) |
| 66 | #define CRB_MAX_RCV_BUFS NETXEN_NIC_REG(0x6c) |
| 67 | #define CRB_TX_INT_THRESHOLD NETXEN_NIC_REG(0x70) |
| 68 | #define CRB_RX_PKT_TIMER NETXEN_NIC_REG(0x74) |
| 69 | #define CRB_TX_PKT_TIMER NETXEN_NIC_REG(0x78) |
| 70 | #define CRB_RX_PKT_CNT NETXEN_NIC_REG(0x7c) |
| 71 | #define CRB_RX_TMR_CNT NETXEN_NIC_REG(0x80) |
| 72 | #define CRB_RX_LRO_TIMER NETXEN_NIC_REG(0x84) |
| 73 | #define CRB_RX_LRO_MID_TIMER NETXEN_NIC_REG(0x88) |
| 74 | #define CRB_DMA_MAX_RCV_BUFS NETXEN_NIC_REG(0x8c) |
| 75 | #define CRB_MAX_DMA_ENTRIES NETXEN_NIC_REG(0x90) |
| 76 | #define CRB_XG_STATE NETXEN_NIC_REG(0x94) /* XG Link status */ |
| 77 | #define CRB_AGENT_GO NETXEN_NIC_REG(0x98) /* NIC pkt gen agent */ |
| 78 | #define CRB_AGENT_TX_SIZE NETXEN_NIC_REG(0x9c) |
| 79 | #define CRB_AGENT_TX_TYPE NETXEN_NIC_REG(0xa0) |
| 80 | #define CRB_AGENT_TX_ADDR NETXEN_NIC_REG(0xa4) |
| 81 | #define CRB_AGENT_TX_MSS NETXEN_NIC_REG(0xa8) |
| 82 | #define CRB_TX_STATE NETXEN_NIC_REG(0xac) /* Debug -performance */ |
| 83 | #define CRB_TX_COUNT NETXEN_NIC_REG(0xb0) |
| 84 | #define CRB_RX_STATE NETXEN_NIC_REG(0xb4) |
| 85 | #define CRB_RX_PERF_DEBUG_1 NETXEN_NIC_REG(0xb8) |
| 86 | #define CRB_RX_LRO_CONTROL NETXEN_NIC_REG(0xbc) /* LRO On/OFF */ |
| 87 | #define CRB_RX_LRO_START_NUM NETXEN_NIC_REG(0xc0) |
| 88 | #define CRB_MPORT_MODE NETXEN_NIC_REG(0xc4) /* Multiport Mode */ |
| 89 | #define CRB_CMD_RING_SIZE NETXEN_NIC_REG(0xc8) |
| 90 | #define CRB_INT_VECTOR NETXEN_NIC_REG(0xd4) |
| 91 | #define CRB_CTX_RESET NETXEN_NIC_REG(0xd8) |
| 92 | #define CRB_HOST_STS_PROD NETXEN_NIC_REG(0xdc) |
| 93 | #define CRB_HOST_STS_CONS NETXEN_NIC_REG(0xe0) |
| 94 | #define CRB_PEG_CMD_PROD NETXEN_NIC_REG(0xe4) |
| 95 | #define CRB_PEG_CMD_CONS NETXEN_NIC_REG(0xe8) |
| 96 | #define CRB_HOST_BUFFER_PROD NETXEN_NIC_REG(0xec) |
| 97 | #define CRB_HOST_BUFFER_CONS NETXEN_NIC_REG(0xf0) |
| 98 | #define CRB_JUMBO_BUFFER_PROD NETXEN_NIC_REG(0xf4) |
| 99 | #define CRB_JUMBO_BUFFER_CONS NETXEN_NIC_REG(0xf8) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 100 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 101 | #define CRB_CMD_PRODUCER_OFFSET_1 NETXEN_NIC_REG(0x1ac) |
| 102 | #define CRB_CMD_CONSUMER_OFFSET_1 NETXEN_NIC_REG(0x1b0) |
| 103 | #define CRB_TEMP_STATE NETXEN_NIC_REG(0x1b4) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 104 | |
Linsys Contractor Mithlesh Thukral | 0c25cfe | 2007-02-28 05:14:07 -0800 | [diff] [blame^] | 105 | /* used for ethtool tests */ |
| 106 | #define CRB_SCRATCHPAD_TEST NETXEN_NIC_REG(0x280) |
| 107 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 108 | /* |
| 109 | * CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address |
| 110 | * which can be read by the Phantom host to get producer/consumer indexes from |
| 111 | * Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following |
| 112 | * registers will be used for the addresses of the ring's shared memory |
| 113 | * on the Phantom. |
| 114 | */ |
| 115 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 116 | #define nx_get_temp_val(x) ((x) >> 16) |
| 117 | #define nx_get_temp_state(x) ((x) & 0xffff) |
| 118 | #define nx_encode_temp(val, state) (((val) << 16) | (state)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 119 | |
| 120 | /* CRB registers per Rcv Descriptor ring */ |
| 121 | struct netxen_rcv_desc_crb { |
| 122 | u32 crb_rcv_producer_offset __attribute__ ((aligned(512))); |
| 123 | u32 crb_rcv_consumer_offset; |
| 124 | u32 crb_globalrcv_ring; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 125 | u32 crb_rcv_ring_size; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 126 | }; |
| 127 | |
| 128 | /* |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 129 | * CRB registers used by the receive peg logic. |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 130 | */ |
| 131 | |
| 132 | struct netxen_recv_crb { |
| 133 | struct netxen_rcv_desc_crb rcv_desc_crb[NUM_RCV_DESC_RINGS]; |
| 134 | u32 crb_rcvstatus_ring; |
| 135 | u32 crb_rcv_status_producer; |
| 136 | u32 crb_rcv_status_consumer; |
| 137 | u32 crb_rcvpeg_state; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 138 | u32 crb_status_ring_size; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 139 | }; |
| 140 | |
| 141 | #if defined(DEFINE_GLOBAL_RECV_CRB) |
| 142 | struct netxen_recv_crb recv_crb_registers[] = { |
| 143 | /* |
| 144 | * Instance 0. |
| 145 | */ |
| 146 | { |
| 147 | /* rcv_desc_crb: */ |
| 148 | { |
| 149 | { |
| 150 | /* crb_rcv_producer_offset: */ |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 151 | NETXEN_NIC_REG(0x100), |
| 152 | /* crb_rcv_consumer_offset: */ |
| 153 | NETXEN_NIC_REG(0x104), |
| 154 | /* crb_gloablrcv_ring: */ |
| 155 | NETXEN_NIC_REG(0x108), |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 156 | /* crb_rcv_ring_size */ |
| 157 | NETXEN_NIC_REG(0x10c), |
| 158 | |
| 159 | }, |
| 160 | /* Jumbo frames */ |
| 161 | { |
| 162 | /* crb_rcv_producer_offset: */ |
| 163 | NETXEN_NIC_REG(0x110), |
| 164 | /* crb_rcv_consumer_offset: */ |
| 165 | NETXEN_NIC_REG(0x114), |
| 166 | /* crb_gloablrcv_ring: */ |
| 167 | NETXEN_NIC_REG(0x118), |
| 168 | /* crb_rcv_ring_size */ |
| 169 | NETXEN_NIC_REG(0x11c), |
| 170 | }, |
| 171 | /* LRO */ |
| 172 | { |
| 173 | /* crb_rcv_producer_offset: */ |
| 174 | NETXEN_NIC_REG(0x120), |
| 175 | /* crb_rcv_consumer_offset: */ |
| 176 | NETXEN_NIC_REG(0x124), |
| 177 | /* crb_gloablrcv_ring: */ |
| 178 | NETXEN_NIC_REG(0x128), |
| 179 | /* crb_rcv_ring_size */ |
| 180 | NETXEN_NIC_REG(0x12c), |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 181 | } |
| 182 | }, |
| 183 | /* crb_rcvstatus_ring: */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 184 | NETXEN_NIC_REG(0x130), |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 185 | /* crb_rcv_status_producer: */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 186 | NETXEN_NIC_REG(0x134), |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 187 | /* crb_rcv_status_consumer: */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 188 | NETXEN_NIC_REG(0x138), |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 189 | /* crb_rcvpeg_state: */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 190 | NETXEN_NIC_REG(0x13c), |
| 191 | /* crb_status_ring_size */ |
| 192 | NETXEN_NIC_REG(0x140), |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 193 | |
| 194 | }, |
| 195 | /* |
| 196 | * Instance 1, |
| 197 | */ |
| 198 | { |
| 199 | /* rcv_desc_crb: */ |
| 200 | { |
| 201 | { |
| 202 | /* crb_rcv_producer_offset: */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 203 | NETXEN_NIC_REG(0x144), |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 204 | /* crb_rcv_consumer_offset: */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 205 | NETXEN_NIC_REG(0x148), |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 206 | /* crb_globalrcv_ring: */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 207 | NETXEN_NIC_REG(0x14c), |
| 208 | /* crb_rcv_ring_size */ |
| 209 | NETXEN_NIC_REG(0x150), |
| 210 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 211 | }, |
| 212 | /* Jumbo frames */ |
| 213 | { |
| 214 | /* crb_rcv_producer_offset: */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 215 | NETXEN_NIC_REG(0x154), |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 216 | /* crb_rcv_consumer_offset: */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 217 | NETXEN_NIC_REG(0x158), |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 218 | /* crb_globalrcv_ring: */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 219 | NETXEN_NIC_REG(0x15c), |
| 220 | /* crb_rcv_ring_size */ |
| 221 | NETXEN_NIC_REG(0x160), |
| 222 | }, |
| 223 | /* LRO */ |
| 224 | { |
| 225 | /* crb_rcv_producer_offset: */ |
| 226 | NETXEN_NIC_REG(0x164), |
| 227 | /* crb_rcv_consumer_offset: */ |
| 228 | NETXEN_NIC_REG(0x168), |
| 229 | /* crb_globalrcv_ring: */ |
| 230 | NETXEN_NIC_REG(0x16c), |
| 231 | /* crb_rcv_ring_size */ |
| 232 | NETXEN_NIC_REG(0x170), |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 233 | } |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 234 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 235 | }, |
| 236 | /* crb_rcvstatus_ring: */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 237 | NETXEN_NIC_REG(0x174), |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 238 | /* crb_rcv_status_producer: */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 239 | NETXEN_NIC_REG(0x178), |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 240 | /* crb_rcv_status_consumer: */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 241 | NETXEN_NIC_REG(0x17c), |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 242 | /* crb_rcvpeg_state: */ |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 243 | NETXEN_NIC_REG(0x180), |
| 244 | /* crb_status_ring_size */ |
| 245 | NETXEN_NIC_REG(0x184), |
| 246 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 247 | }, |
| 248 | }; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 249 | |
| 250 | u64 ctx_addr_sig_regs[][3] = { |
| 251 | {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)}, |
| 252 | {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)}, |
| 253 | {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)}, |
| 254 | {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)} |
| 255 | }; |
| 256 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 257 | #else |
| 258 | extern struct netxen_recv_crb recv_crb_registers[]; |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 259 | extern u64 ctx_addr_sig_regs[][3]; |
| 260 | #define CRB_CTX_ADDR_REG_LO (ctx_addr_sig_regs[0][0]) |
| 261 | #define CRB_CTX_ADDR_REG_HI (ctx_addr_sig_regs[0][2]) |
| 262 | #define CRB_CTX_SIGNATURE_REG (ctx_addr_sig_regs[0][1]) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 263 | #endif /* DEFINE_GLOBAL_RECEIVE_CRB */ |
| 264 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 265 | /* |
| 266 | * Temperature control. |
| 267 | */ |
| 268 | enum { |
| 269 | NX_TEMP_NORMAL = 0x1, /* Normal operating range */ |
| 270 | NX_TEMP_WARN, /* Sound alert, temperature getting high */ |
| 271 | NX_TEMP_PANIC /* Fatal error, hardware has shut down. */ |
| 272 | }; |
| 273 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 274 | #endif /* __NIC_PHAN_REG_H_ */ |