arch/arm64/boot/dts/qcom/sdm845.dtsi

/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include "skeleton64.dtsi"
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/clock/qcom,camcc-sdm845.h>
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
#include <dt-bindings/clock/qcom,videocc-sdm845.h>
#include <dt-bindings/clock/qcom,cpucc-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,tcs-mbox.h>
#include <dt-bindings/spmi/spmi.h>

/ {
	model = "Qualcomm Technologies, Inc. SDM845";
	compatible = "qcom,sdm845";
	qcom,msm-id = <321 0x0>;
	interrupt-parent = <&intc>;

	aliases {
		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
		ufshc2 = &ufshc_card; /* Removable UFS slot */
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			efficiency = <1024>;
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
				      compatible = "arm,arch-cache";
				      cache-size = <0x200000>;
				      cache-level = <3>;
				};
			};
			L1_I_0: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
			L1_D_0: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			efficiency = <1024>;
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_100>;
			L2_100: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
			L1_I_100: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
			L1_D_100: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x200>;
			enable-method = "psci";
			efficiency = <1024>;
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_200>;
			L2_200: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
			L1_I_200: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
			L1_D_200: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x300>;
			enable-method = "psci";
			efficiency = <1024>;
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_300>;
			L2_300: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
			L1_I_300: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
			L1_D_300: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x400>;
			enable-method = "psci";
			efficiency = <1740>;
			cache-size = <0x20000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_400>;
			L2_400: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
			L1_I_400: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x12000>;
			};
			L1_D_400: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x12000>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x500>;
			enable-method = "psci";
			efficiency = <1740>;
			cache-size = <0x20000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_500>;
			L2_500: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
			L1_I_500: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x12000>;
			};
			L1_D_500: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x12000>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x600>;
			enable-method = "psci";
			efficiency = <1740>;
			cache-size = <0x20000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_600>;
			L2_600: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
			L1_I_600: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x12000>;
			};
			L1_D_600: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x12000>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x700>;
			enable-method = "psci";
			efficiency = <1740>;
			cache-size = <0x20000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_700>;
			L2_700: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
			L1_I_700: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x12000>;
			};
			L1_D_700: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x12000>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};

				core3 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	soc: soc { };

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		removed_regions: removed_regions@85800000 {
			no-map;
			reg = <0 0x85800000 0 0x3700000>;
		};

		pil_camera_mem: camera_region@8ab00000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x8ab00000 0 0x500000>;
		};

		pil_modem_mem: modem_region@8b000000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x8b000000 0 0x7300000>;
		};

		pil_video_mem: pil_video_region@92300000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x92300000 0 0x500000>;
		};

		pil_cdsp_mem: cdsp_regions@92800000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x92800000 0 0x800000>;
		};

		pil_adsp_mem: pil_adsp_region@93000000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x93000000 0 0x1a00000>;
		};

		pil_mba_mem: pil_mba_region@0x94a00000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x94a00000 0 0x200000>;
		};

		pil_slpi_mem: pil_slpi_region@94c00000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x94c00000 0 0x1400000>;
		};

		pil_ipa_fw_mem: pil_ipa_fw_region@96000000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x96000000 0 0x10000>;
		};

		pil_ipa_gsi_mem: pil_ipa_gsi_region@96010000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x96010000 0 0x5000>;
		};

		pil_gpu_mem: pil_gpu_region@96015000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x96015000 0 0x1000>;
		};

		pil_spss_mem: spss_region@96100000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0 0x96100000 0 0x100000>;
		};

		adsp_mem: adsp_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0xc00000>;
		};

		qseecom_mem: qseecom_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x1400000>;
		};

		sp_mem: sp_region {  /* SPSS-HLOS ION shared mem */
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x800000>;
		};

		secure_display_memory: secure_display_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x5c00000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x2000000>;
			linux,cma-default;
		};
	};
};

#include "msm-gdsc-sdm845.dtsi"
#include "sdm845-sde.dtsi"
#include "sdm845-sde-display.dtsi"
#include "sdm845-qupv3.dtsi"

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@17a00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x17a00000 0x10000>,     /* GICD */
		      <0x17a60000 0x100000>;    /* GICR * 8 */
		interrupts = <1 9 4>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 1 0xf08>,
			     <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 0 0xf08>;
		clock-frequency = <19200000>;
	};

	timer@0x17C90000{
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17C90000 0x1000>;
		clock-frequency = <19200000>;

		frame@0x17CA0000 {
			frame-number = <0>;
			interrupts = <0 7 0x4>,
				     <0 6 0x4>;
			reg = <0x17CA0000 0x1000>,
			      <0x17CB0000 0x1000>;
		};

		frame@17cc0000 {
			frame-number = <1>;
			interrupts = <0 8 0x4>;
			reg = <0x17cc0000 0x1000>;
			status = "disabled";
		};

		frame@17cd0000 {
			frame-number = <2>;
			interrupts = <0 9 0x4>;
			reg = <0x17cd0000 0x1000>;
			status = "disabled";
		};

		frame@17ce0000 {
			frame-number = <3>;
			interrupts = <0 10 0x4>;
			reg = <0x17ce0000 0x1000>;
			status = "disabled";
		};

		frame@17cf0000 {
			frame-number = <4>;
			interrupts = <0 11 0x4>;
			reg = <0x17cf0000 0x1000>;
			status = "disabled";
		};

		frame@17d00000 {
			frame-number = <5>;
			interrupts = <0 12 0x4>;
			reg = <0x17d00000 0x1000>;
			status = "disabled";
		};

		frame@17d10000 {
			frame-number = <6>;
			interrupts = <0 13 0x4>;
			reg = <0x17d10000 0x1000>;
			status = "disabled";
		};
	};

	restart@10ac000 {
		compatible = "qcom,pshold";
		reg = <0xC264000 0x4>,
		      <0x1fd3000 0x4>;
		reg-names = "pshold-base", "tcsr-boot-misc-detect";
	};

	spmi_bus: qcom,spmi@c440000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0xc440000 0x1100>,
		      <0xc600000 0x2000000>,
		      <0xe600000 0x100000>,
		      <0xe700000 0xa0000>,
		      <0xc40a000 0x26000>;
		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
		interrupt-names = "periph_irq";
		interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>;
		qcom,ee = <0>;
		qcom,channel = <0>;
		#address-cells = <2>;
		#size-cells = <0>;
		interrupt-controller;
		#interrupt-cells = <4>;
		cell-index = <0>;
	};

	spmi_debug_bus: qcom,spmi-debug@6b22000 {
		compatible = "qcom,spmi-pmic-arb-debug";
		reg = <0x6b22000 0x60>, <0x7820A8 4>;
		reg-names = "core", "fuse";
		qcom,fuse-disable-bit = <12>;
		#address-cells = <2>;
		#size-cells = <0>;

		qcom,pm8998-debug@0 {
			compatible = "qcom,spmi-pmic";
			reg = <0x0 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
		};

		qcom,pm8998-debug@1 {
			compatible = "qcom,spmi-pmic";
			reg = <0x1 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
		};

		qcom,pmi8998-debug@2 {
			compatible = "qcom,spmi-pmic";
			reg = <0x2 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
		};

		qcom,pmi8998-debug@3 {
			compatible = "qcom,spmi-pmic";
			reg = <0x3 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
		};

		qcom,pm8005-debug@4 {
			compatible = "qcom,spmi-pmic";
			reg = <0x4 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
		};

		qcom,pm8005-debug@5 {
			compatible = "qcom,spmi-pmic";
			reg = <0x5 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
		};
	};

	msm_cpufreq: qcom,msm-cpufreq {
		compatible = "qcom,msm-cpufreq";
		clock-names = "cpu0_clk", "cpu4_clk";
		clocks = <&clock_cpucc CPU0_PWRCL_CLK>,
			 <&clock_cpucc CPU4_PERFCL_CLK>;

		qcom,governor-per-policy;

		qcom,cpufreq-table-0 =
			<  300000 >,
			<  422400 >,
			<  499200 >,
			<  576000 >,
			<  652800 >,
			<  748800 >,
			<  825600 >,
			<  902400 >,
			<  979200 >,
			< 1056000 >,
			< 1132800 >,
			< 1209600 >,
			< 1286400 >,
			< 1363200 >,
			< 1440000 >,
			< 1516800 >,
			< 1593600 >;

		qcom,cpufreq-table-4 =
			<  300000 >,
			<  422400 >,
			<  499200 >,
			<  576000 >,
			<  652800 >,
			<  729600 >,
			<  806400 >,
			<  883200 >,
			<  960000 >,
			< 1036800 >,
			< 1113600 >,
			< 1190400 >,
			< 1267200 >,
			< 1344000 >,
			< 1420800 >,
			< 1497600 >,
			< 1574400 >,
			< 1651200 >,
			< 1728000 >,
			< 1804800 >,
			< 1881600 >,
			< 1958400 >;
	};

	cpubw: qcom,cpubw {
		compatible = "qcom,devbw";
		governor = "performance";
		qcom,src-dst-ports = <1 512>;
		qcom,active-only;
		qcom,bw-tbl =
			<  762 /*  200 MHz */ >,
			< 1144 /*  300 MHz */ >,
			< 1720 /*  451 MHz */ >,
			< 2086 /*  547 MHz */ >,
			< 2597 /*  681 MHz */ >,
			< 2929 /*  768 MHz */ >,
			< 3879 /* 1017 MHz */ >,
			< 4943 /* 1296 MHz */ >,
			< 5931 /* 1555 MHz */ >,
			< 6881 /* 1804 MHz */ >;
	};

	bwmon: qcom,cpu-bwmon {
		compatible = "qcom,bimc-bwmon4";
		reg = <0x1436400 0x300>, <0x1436300 0x200>;
		reg-names = "base", "global_base";
		interrupts = <0 581 4>;
		qcom,mport = <0>;
		qcom,hw-timer-hz = <19200000>;
		qcom,target-dev = <&cpubw>;
	};

	memlat_cpu0: qcom,memlat-cpu0 {
		compatible = "qcom,devbw";
		governor = "powersave";
		qcom,src-dst-ports = <1 512>;
		qcom,active-only;
		qcom,bw-tbl =
			<  762 /*  200 MHz */ >,
			< 1144 /*  300 MHz */ >,
			< 1720 /*  451 MHz */ >,
			< 2086 /*  547 MHz */ >,
			< 2597 /*  681 MHz */ >,
			< 2929 /*  768 MHz */ >,
			< 3879 /* 1017 MHz */ >,
			< 4943 /* 1296 MHz */ >,
			< 5931 /* 1555 MHz */ >,
			< 6881 /* 1804 MHz */ >;
	};

	memlat_cpu4: qcom,memlat-cpu4 {
		compatible = "qcom,devbw";
		governor = "powersave";
		qcom,src-dst-ports = <1 512>;
		qcom,active-only;
		status = "ok";
		qcom,bw-tbl =
			<  762 /*  200 MHz */ >,
			< 1144 /*  300 MHz */ >,
			< 1720 /*  451 MHz */ >,
			< 2086 /*  547 MHz */ >,
			< 2597 /*  681 MHz */ >,
			< 2929 /*  768 MHz */ >,
			< 3879 /* 1017 MHz */ >,
			< 4943 /* 1296 MHz */ >,
			< 5931 /* 1555 MHz */ >,
			< 6881 /* 1804 MHz */ >;
	};

	snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive {
		compatible = "qcom,devbw";
		governor = "powersave";
		qcom,src-dst-ports = <139 627>;
		qcom,active-only;
		status = "ok";
		qcom,bw-tbl =
			< 1 >;
	};

	devfreq_memlat_0: qcom,cpu0-memlat-mon {
		compatible = "qcom,arm-memlat-mon";
		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
		qcom,target-dev = <&memlat_cpu0>;
		qcom,cachemiss-ev = <0x2A>;
		qcom,core-dev-table =
			<  300000  762 >,
			<  748800 1720 >,
			<  979200 2929 >,
			< 1209600 3879 >,
			< 1516800 4943 >,
			< 1593600 5931 >;
	};

	devfreq_memlat_4: qcom,cpu4-memlat-mon {
		compatible = "qcom,arm-memlat-mon";
		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
		qcom,target-dev = <&memlat_cpu4>;
		qcom,cachemiss-ev = <0x2A>;
		qcom,core-dev-table =
			<  300000  762 >,
			< 1036800 2929 >,
			< 1190400 3879 >,
			< 1574400 4943 >,
			< 1804800 5931 >,
			< 1958400 6881 >;
	};

	l3_cpu0: qcom,l3-cpu0 {
		compatible = "devfreq-simple-dev";
		clock-names = "devfreq_clk";
		clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>;
		governor = "performance";
		freq-tbl-khz =
			< 300000 >,
			< 422400 >,
			< 499200 >,
			< 576000 >,
			< 652800 >,
			< 729600 >,
			< 806400 >,
			< 883200 >,
			< 960000 >;
	};

	l3_cpu4: qcom,l3-cpu4 {
		compatible = "devfreq-simple-dev";
		clock-names = "devfreq_clk";
		clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>;
		governor = "performance";
		freq-tbl-khz =
			< 300000 >,
			< 422400 >,
			< 499200 >,
			< 576000 >,
			< 652800 >,
			< 729600 >,
			< 806400 >,
			< 883200 >,
			< 960000 >;
	};

	devfreq_l3lat_0: qcom,cpu0-l3lat-mon {
		compatible = "qcom,arm-memlat-mon";
		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
		qcom,target-dev = <&l3_cpu0>;
		qcom,cachemiss-ev = <0x17>;
		qcom,core-dev-table =
			<  300000 300000 >,
			<  748800 576000 >,
			<  979200 652800 >,
			< 1209600 806400 >,
			< 1516800 883200 >,
			< 1593600 960000 >;
	};

	devfreq_l3lat_4: qcom,cpu4-l3lat-mon {
		compatible = "qcom,arm-memlat-mon";
		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
		qcom,target-dev = <&l3_cpu4>;
		qcom,cachemiss-ev = <0x17>;
		qcom,core-dev-table =
			<  300000 300000 >,
			< 1036800 652800 >,
			< 1190400 806400 >,
			< 1574400 883200 >,
			< 1651200 960000 >;
	};

	cpu_pmu: cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		qcom,irq-is-percpu;
		interrupts = <1 5 4>;
	};

	clock_gcc: qcom,gcc@100000 {
		compatible = "qcom,gcc-sdm845", "syscon";
		reg = <0x100000 0x1f0000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&pm8998_s9_level>;
		vdd_cx_ao-supply = <&pm8998_s9_level_ao>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_videocc: qcom,videocc@ab00000 {
		compatible = "qcom,video_cc-sdm845", "syscon";
		reg = <0xab00000 0x10000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&pm8998_s9_level>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_camcc: qcom,camcc@ad00000 {
		compatible = "qcom,cam_cc-sdm845", "syscon";
		reg = <0xad00000 0x10000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&pm8998_s9_level>;
		vdd_mx-supply = <&pm8998_s6_level>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_dispcc: qcom,dispcc@af00000 {
		compatible = "qcom,dispcc-sdm845", "syscon";
		reg = <0xaf00000 0x10000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&pm8998_s9_level>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_gpucc: qcom,gpucc@5090000 {
		compatible = "qcom,gpucc-sdm845", "syscon";
		reg = <0x5090000 0x9000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&pm8998_s9_level>;
		qcom,gpu_cc_gmu_clk_src-opp-handle = <&gmu>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_gfx: qcom,gfxcc@5090000 {
		compatible = "qcom,gfxcc-sdm845";
		reg = <0x5090000 0x9000>;
		reg-names = "cc_base";
		vdd_gfx-supply = <&pm8005_s1_level>;
		vdd_mx-supply = <&pm8998_s6_level>;
		qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_cpucc: qcom,cpucc@0x17d41000 {
		compatible = "qcom,clk-cpu-osm";
		reg = <0x17d41000 0x1400>,
			<0x17d43000 0x1400>,
			<0x17d45800 0x1400>,
			<0x178d0000 0x1000>,
			<0x178c0000 0x1000>,
			<0x178b0000 0x1000>,
			<0x17d42400 0x0c00>,
			<0x17d44400 0x0c00>,
			<0x17d46c00 0x0c00>;
		reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base",
			"l3_pll", "pwrcl_pll", "perfcl_pll",
			"l3_sequencer", "pwrcl_sequencer",
			"perfcl_sequencer";

		vdd-l3-supply = <&apc0_l3_vreg>;
		vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
		vdd-perfcl-supply = <&apc1_perfcl_vreg>;

		qcom,l3-speedbin0-v0 =
			<   300000000 0x000c000f 0x00002020 0x1 1 >,
			<   422400000 0x50140116 0x00002020 0x1 2 >,
			<   499200000 0x5014021a 0x00002020 0x1 3 >,
			<   576000000 0x5014031e 0x00002020 0x1 4 >,
			<   652800000 0x401c0422 0x00002020 0x1 5 >,
			<   729600000 0x401c0526 0x00002020 0x1 6 >,
			<   806400000 0x401c062a 0x00002222 0x1 7 >;

		qcom,pwrcl-speedbin0-v0 =
			<   300000000 0x000c000f 0x00002020 0x1 1 >,
			<   422400000 0x50140116 0x00002020 0x1 2 >,
			<   499200000 0x5014021a 0x00002020 0x1 3 >,
			<   576000000 0x5014031e 0x00002020 0x1 4 >,
			<   652800000 0x401c0422 0x00002020 0x1 5 >,
			<   748800000 0x401c0527 0x00002020 0x1 6 >,
			<   825600000 0x401c062b 0x00002222 0x1 7 >,
			<   902400000 0x4024072f 0x00002626 0x1 8 >,
			<   979200000 0x40240833 0x00002929 0x1 9 >,
			<  1056000000 0x402c0937 0x00002c2c 0x1 10 >,
			<  1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
			<  1209600000 0x402c0b3f 0x00003333 0x1 12 >;

		qcom,perfcl-speedbin0-v0 =
			<   300000000 0x000c000f 0x00002020 0x1 1 >,
			<   422400000 0x50140116 0x00002020 0x1 2 >,
			<   499200000 0x5014021a 0x00002020 0x1 3 >,
			<   576000000 0x5014031e 0x00002020 0x1 4 >,
			<   652800000 0x401c0422 0x00002020 0x1 5 >,
			<   729600000 0x401c0526 0x00002020 0x1 6 >,
			<   806400000 0x401c062a 0x00002222 0x1 7 >,
			<   883200000 0x4024072e 0x00002525 0x1 8 >,
			<   960000000 0x40240832 0x00002828 0x1 9 >,
			<  1036800000 0x40240936 0x00002b2b 0x1 10 >,
			<  1113600000 0x402c0a3a 0x00002e2e 0x1 11 >,
			<  1190400000 0x402c0b3e 0x00003232 0x1 12 >;

		qcom,l3-min-cpr-vc-bin0 = <7>;
		qcom,pwrcl-min-cpr-vc-bin0 = <6>;
		qcom,perfcl-min-cpr-vc-bin0 = <7>;

		qcom,up-timer =
			<1000 1000 1000>;
		qcom,down-timer =
			<100000 100000 100000>;
		qcom,pc-override-index =
			<0 0 0>;
		qcom,set-ret-inactive;
		qcom,enable-llm-freq-vote;
		qcom,llm-freq-up-timer =
			<1000 1000 1000>;
		qcom,llm-freq-down-timer =
			<327675 327675 327675>;
		qcom,enable-llm-volt-vote;
		qcom,llm-volt-up-timer =
			<1000 1000 1000>;
		qcom,llm-volt-down-timer =
			<327675 327675 327675>;
		qcom,cc-reads = <10>;
		qcom,cc-delay = <5>;
		qcom,cc-factor = <100>;
		qcom,osm-clk-rate = <100000000>;
		qcom,xo-clk-rate = <19200000>;

		qcom,l-val-base =
			<0x178d0004 0x178c0004 0x178b0004>;
		qcom,apcs-pll-user-ctl =
			<0x178d000c 0x178c000c 0x178b000c>;
		qcom,apcs-pll-min-freq =
			<0x17d41094 0x17d43094 0x17d45894>;
		qcom,apm-mode-ctl =
			<0x0 0x0 0x17d20010>;
		qcom,apm-status-ctrl =
			<0x0 0x0 0x17d20000>;
		qcom,perfcl-isense-addr = <0x17871480>;
		qcom,l3-mem-acc-addr = <0x17990170 0x17990170 0x17990170>;
		qcom,pwrcl-mem-acc-addr = <0x17990160 0x17990164 0x17990164>;
		qcom,perfcl-mem-acc-addr = <0x17990168 0x1799016c 0x1799016c>;
		qcom,cfg-gfmux-addr =<0x178d0084 0x178c0084 0x178b0084>;
		qcom,apcs-cbc-addr = <0x178d008c 0x178c008c 0x178b008c>;
		qcom,apcs-ramp-ctl-addr = <0x17840904 0x17840904 0x17830904>;

		qcom,perfcl-apcs-apm-threshold-voltage = <800000>;
		qcom,perfcl-apcs-mem-acc-threshold-voltage = <852000>;
		qcom,boost-fsm-en;
		qcom,safe-fsm-en;
		qcom,ps-fsm-en;
		qcom,droop-fsm-en;

		clock-names = "xo_ao";
		clocks = <&clock_rpmh RPMH_CXO_CLK_A>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_rpmh: qcom,rpmhclk {
		compatible = "qcom,rpmh-clk-sdm845";
		#clock-cells = <1>;
		mboxes = <&apps_rsc 0>;
		mbox-names = "apps";
	};

	clock_debug: qcom,cc-debug@100000 {
		compatible = "qcom,debugcc-sdm845";
		qcom,cc-count = <5>;
		qcom,gcc = <&clock_gcc>;
		qcom,videocc = <&clock_videocc>;
		qcom,camcc = <&clock_camcc>;
		qcom,dispcc = <&clock_dispcc>;
		qcom,gpucc = <&clock_gpucc>;
		clock-names = "xo_clk_src";
		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		#clock-cells = <1>;
	};

	ufsphy_mem: ufsphy_mem@1d87000 {
		reg = <0x1d87000 0xda8>; /* PHY regs */
		reg-names = "phy_mem";
		#phy-cells = <0>;

		lanes-per-direction = <2>;

		clock-names = "ref_clk_src",
			"ref_clk",
			"ref_aux_clk";
		clocks = <&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
			<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;

		status = "disabled";
	};

	ufshc_mem: ufshc_mem@1d84000 {
		compatible = "qcom,ufshc";
		reg = <0x1d84000 0x2500>;
		interrupts = <0 265 0>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";

		lanes-per-direction = <2>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */

		clock-names =
			"core_clk",
			"bus_aggr_clk",
			"iface_clk",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk",
			"rx_lane1_sync_clk";
		/* TODO: add HW CTL clocks when available */
		clocks =
			<&clock_gcc GCC_UFS_PHY_AXI_CLK>,
			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,
			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
			<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,
			<&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
		freq-table-hz =
			<50000000 200000000>,
			<0 0>,
			<0 0>,
			<37500000 150000000>,
			<75000000 300000000>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>;

		qcom,msm-bus,name = "ufshc_mem";
		qcom,msm-bus,num-cases = <22>;
		qcom,msm-bus,num-paths = <2>;
		qcom,msm-bus,vectors-KBps =
		/*
		 * During HS G3 UFS runs at nominal voltage corner, vote
		 * higher bandwidth to push other buses in the data path
		 * to run at nominal to achieve max throughput.
		 * 4GBps pushes BIMC to run at nominal.
		 * 200MBps pushes CNOC to run at nominal.
		 * Vote for half of this bandwidth for HS G3 1-lane.
		 * For max bandwidth, vote high enough to push the buses
		 * to run in turbo voltage corner.
		 */
		<123 512 0 0>, <1 757 0 0>,          /* No vote */
		<123 512 922 0>, <1 757 1000 0>,     /* PWM G1 */
		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G2 */
		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G3 */
		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G4 */
		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G1 L2 */
		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G2 L2 */
		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G3 L2 */
		<123 512 14752 0>, <1 757 1000 0>,   /* PWM G4 L2 */
		<123 512 127796 0>, <1 757 1000 0>,  /* HS G1 RA */
		<123 512 255591 0>, <1 757 1000 0>,  /* HS G2 RA */
		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RA */
		<123 512 255591 0>, <1 757 1000 0>,  /* HS G1 RA L2 */
		<123 512 511181 0>, <1 757 1000 0>,  /* HS G2 RA L2 */
		<123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */
		<123 512 149422 0>, <1 757 1000 0>,  /* HS G1 RB */
		<123 512 298189 0>, <1 757 1000 0>,  /* HS G2 RB */
		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RB */
		<123 512 298189 0>, <1 757 1000 0>,  /* HS G1 RB L2 */
		<123 512 596378 0>, <1 757 1000 0>,  /* HS G2 RB L2 */
		<123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RB L2 */
		<123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",
		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",
		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",
		"MAX";

		/* PM QoS */
		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
		qcom,pm-qos-cpu-group-latency-us = <70 70>;
		qcom,pm-qos-default-cpu = <0>;

		pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
		pinctrl-0 = <&ufs_dev_reset_assert>;
		pinctrl-1 = <&ufs_dev_reset_deassert>;

		resets = <&clock_gcc GCC_UFS_PHY_BCR>;
		reset-names = "core_reset";

		status = "disabled";
	};

	ufsphy_card: ufsphy_card@1da7000 {
		reg = <0x1da7000 0xda8>; /* PHY regs */
		reg-names = "phy_mem";
		#phy-cells = <0>;

		lanes-per-direction = <1>;

		clock-names = "ref_clk_src",
			"ref_clk",
			"ref_aux_clk";
		clocks = <&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_UFS_CARD_CLKREF_CLK>,
			<&clock_gcc GCC_UFS_CARD_PHY_AUX_CLK>;

		status = "disabled";
	};

	ufshc_card: ufshc_card@1da4000 {
		compatible = "qcom,ufshc";
		reg = <0x1da4000 0x2500>;
		interrupts = <0 125 0>;
		phys = <&ufsphy_card>;
		phy-names = "ufsphy";

		lanes-per-direction = <1>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */

		clock-names =
			"core_clk",
			"bus_aggr_clk",
			"iface_clk",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk";
		/* TODO: add HW CTL clocks when available */
		clocks =
			<&clock_gcc GCC_UFS_CARD_AXI_CLK>,
			<&clock_gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
			<&clock_gcc GCC_UFS_CARD_AHB_CLK>,
			<&clock_gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
			<&clock_gcc GCC_UFS_CARD_ICE_CORE_CLK>,
			<&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
			<&clock_gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>;
		freq-table-hz =
			<50000000 200000000>,
			<0 0>,
			<0 0>,
			<37500000 150000000>,
			<75000000 300000000>,
			<0 0>,
			<0 0>,
			<0 0>;

		qcom,msm-bus,name = "ufshc_card";
		qcom,msm-bus,num-cases = <9>;
		qcom,msm-bus,num-paths = <2>;
		qcom,msm-bus,vectors-KBps =
		<122 512 0 0>, <1 756 0 0>,          /* No vote */
		<122 512 922 0>, <1 756 1000 0>,     /* PWM G1 */
		<122 512 127796 0>, <1 756 1000 0>,  /* HS G1 RA */
		<122 512 255591 0>, <1 756 1000 0>,  /* HS G2 RA */
		<122 512 2097152 0>, <1 756 102400 0>,  /* HS G3 RA */
		<122 512 149422 0>, <1 756 1000 0>,  /* HS G1 RB */
		<122 512 298189 0>, <1 756 1000 0>,  /* HS G2 RB */
		<122 512 2097152 0>, <1 756 102400 0>,  /* HS G3 RB */
		<122 512 7643136 0>, <1 756 307200 0>; /* Max. bandwidth */
		qcom,bus-vector-names = "MIN",
		"PWM_G1_L1",
		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
		"MAX";

		/* PM QoS */
		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
		qcom,pm-qos-cpu-group-latency-us = <70 70>;
		qcom,pm-qos-default-cpu = <0>;

		/*
		 * Note: this instance doesn't have control over UFS device
		 * reset
		 */

		resets = <&clock_gcc GCC_UFS_CARD_BCR>;
		reset-names = "core_reset";

		status = "disabled";
	};

	pil_modem: qcom,mss@4080000 {
		compatible = "qcom,pil-q6v55-mss";
		reg = <0x4080000 0x100>,
		      <0x1f63000 0x008>,
		      <0x1f65000 0x008>,
		      <0x1f64000 0x008>,
		      <0x4180000 0x020>,
		      <0xc2b0000 0x004>;
		reg-names = "qdsp6_base", "halt_q6", "halt_modem",
			    "halt_nc", "rmb_base", "restart_reg";

		clocks = <&clock_rpmh RPMH_CXO_CLK>,
			 <&clock_gcc GCC_MSS_CFG_AHB_CLK>,
			 <&clock_gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
			 <&clock_gcc GCC_BOOT_ROM_AHB_CLK>,
			 <&clock_gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
			 <&clock_gcc GCC_MSS_SNOC_AXI_CLK>,
			 <&clock_gcc GCC_MSS_AXIS2_CLK>,
			 <&clock_gcc GCC_MSS_MFAB_AXIS_CLK>,
			 <&clock_gcc GCC_PRNG_AHB_CLK>;
		clock-names = "xo", "iface_clk", "bus_clk",
			      "mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
			      "axis2_clk","mnoc_axi_clk", "prng_clk";
		qcom,proxy-clock-names = "xo", "axis2_clk", "prng_clk";
		qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
					  "gpll0_mss_clk", "snoc_axi_clk",
					  "mnoc_axi_clk";

		interrupts = <0 266 1>;
		vdd_cx-supply = <&pm8998_s9_level>;
		vdd_cx-voltage = <RPMH_REGULATOR_LEVEL_TURBO>;
		vdd_mx-supply = <&pm8998_s6_level>;
		vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO>;
		qcom,firmware-name = "modem";
		qcom,pil-self-auth;
		qcom,sysmon-id = <0>;
		qcom,ssctl-instance-id = <0x12>;
		qcom,override-acc;
		qcom,qdsp6v65-1-0;
		status = "ok";
		memory-region = <&pil_modem_mem>;
		qcom,mem-protect-id = <0xF>;

		/* GPIO inputs from mss */
		qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
		qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
		qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
		qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
		qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>;

		/* GPIO output to mss */
		qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
	};

	qcom,lpass@17300000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x17300000 0x00100>;
		interrupts = <0 162 1>;

		vdd_cx-supply = <&pm8998_s9_level>;
		qcom,proxy-reg-names = "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";

		qcom,pas-id = <1>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <423>;
		qcom,sysmon-id = <1>;
		status = "ok";
		qcom,ssctl-instance-id = <0x14>;
		qcom,firmware-name = "adsp";
		memory-region = <&pil_adsp_mem>;

		/* GPIO inputs from lpass */
		qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
		qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
		qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
		qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;

		/* GPIO output to lpass */
		qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
	};

	qcom,ssc@5c00000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x5c00000 0x4000>;
		interrupts = <0 377 1>;

		vdd_cx-supply = <&pm8998_l27_level>;
		vdd_px-supply = <&pm8998_lvs2>;
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		qcom,proxy-reg-names = "vdd_cx", "vdd_px";
		qcom,keep-proxy-regs-on;

		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";

		qcom,pas-id = <12>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <424>;
		qcom,sysmon-id = <3>;
		qcom,ssctl-instance-id = <0x16>;
		qcom,firmware-name = "slpi";
		status = "ok";
		memory-region = <&pil_slpi_mem>;

		/* GPIO inputs from ssc */
		qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_3_in 0 0>;
		qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_3_in 2 0>;
		qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_3_in 1 0>;
		qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_3_in 3 0>;

		/* GPIO output to ssc */
		qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_3_out 0 0>;
	};

	slim_aud: slim@171c0000 {
		cell-index = <1>;
		compatible = "qcom,slim-ngd";
		reg = <0x171c0000 0x2c000>,
			<0x17184000 0x2a000>;
		reg-names = "slimbus_physical", "slimbus_bam_physical";
		interrupts = <0 163 0>, <0 164 0>;
		interrupt-names = "slimbus_irq", "slimbus_bam_irq";
		qcom,apps-ch-pipes = <0x780000>;
		qcom,ea-pc = <0x270>;
	};

	eud: qcom,msm-eud@88e0000 {
		compatible = "qcom,msm-eud";
		interrupt-names = "eud_irq";
		interrupts = <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x88e0000 0x2000>;
		reg-names = "eud_base";
		status = "ok";
	};

	qcom,spss@1880000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x188101c 0x4>,
		      <0x1881024 0x4>,
		      <0x1881028 0x4>,
		      <0x188103c 0x4>,
		      <0x1882014 0x4>;
		reg-names = "sp2soc_irq_status", "sp2soc_irq_clr",
			    "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2";
		interrupts = <0 352 1>;

		vdd_cx-supply = <&pm8998_s9_level>;
		qcom,proxy-reg-names = "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		vdd_mx-supply = <&pm8998_s6_level>;
		vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";
		qcom,pil-generic-irq-handler;
		status = "ok";

		qcom,pas-id = <14>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,firmware-name = "spss";
		memory-region = <&pil_spss_mem>;
		qcom,spss-scsr-bits = <24 25>;
	};

	wdog: qcom,wdt@17980000{
		compatible = "qcom,msm-watchdog";
		reg = <0x17980000 0x1000>;
		reg-names = "wdt-base";
		interrupts = <0 0 0>, <0 1 0>;
		qcom,bark-time = <11000>;
		qcom,pet-time = <10000>;
		qcom,ipi-ping;
		qcom,wakeup-enable;
	};

	qcom,turing@8300000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x8300000 0x100000>;
		interrupts = <0 578 1>;

		vdd_cx-supply = <&pm8998_s9_level>;
		qcom,proxy-reg-names = "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";

		qcom,pas-id = <18>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <601>;
		qcom,sysmon-id = <7>;
		qcom,ssctl-instance-id = <0x17>;
		qcom,firmware-name = "cdsp";
		memory-region = <&pil_cdsp_mem>;

		/* GPIO inputs from turing */
		qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_5_in 0 0>;
		qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_5_in 2 0>;
		qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_5_in 1 0>;
		qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_5_in 3 0>;

		/* GPIO output to turing*/
		qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_5_out 0 0>;
		status = "ok";
	};

	qcom,msm-rtb {
		compatible = "qcom,msm-rtb";
		qcom,rtb-size = <0x100000>;
	};

	qcom,msm-cdsp-loader {
		compatible = "qcom,cdsp-loader";
		qcom,proc-img-to-load = "cdsp";
	};

	qcom,msm_fastrpc {
		compatible = "qcom,msm-fastrpc-compute";

		qcom,msm_fastrpc_compute_cb1 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1401>,
				 <&apps_smmu 0x1421>;
		};
		qcom,msm_fastrpc_compute_cb2 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1402>,
				 <&apps_smmu 0x1422>;
		};
		qcom,msm_fastrpc_compute_cb3 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1403>,
				 <&apps_smmu 0x1423>;
		};
		qcom,msm_fastrpc_compute_cb4 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1404>,
				 <&apps_smmu 0x1424>;
		};
		qcom,msm_fastrpc_compute_cb5 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1405>,
				 <&apps_smmu 0x1425>;
		};
		qcom,msm_fastrpc_compute_cb6 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1406>,
				 <&apps_smmu 0x1426>;
		};
		qcom,msm_fastrpc_compute_cb7 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1407>,
				 <&apps_smmu 0x1427>;
		};
		qcom,msm_fastrpc_compute_cb8 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1408>,
				 <&apps_smmu 0x1428>;
		};
	};

	qcom,msm-imem@146bf000 {
		compatible = "qcom,msm-imem";
		reg = <0x146bf000 0x1000>;
		ranges = <0x0 0x146bf000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10 {
			compatible = "qcom,msm-imem-mem_dump_table";
			reg = <0x10 8>;
		};

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 4>;
		};

		pil@94c {
			compatible = "qcom,msm-imem-pil";
			reg = <0x94c 200>;
		};
	};

	qcom,venus@aae0000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0xaae0000 0x4000>;

		vdd-supply = <&venus_gdsc>;
		qcom,proxy-reg-names = "vdd";

		clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
			 <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>,
			 <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
		clock-names = "core_clk", "iface_clk", "bus_clk";
		qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk";

		qcom,pas-id = <9>;
		qcom,msm-bus,name = "pil-venus";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<63 512 0 0>,
			<63 512 0 304000>;
		qcom,proxy-timeout-ms = <100>;
		qcom,firmware-name = "venus";
		memory-region = <&pil_video_mem>;
		status = "ok";
	};

	cpuss_dump {
		compatible = "qcom,cpuss-dump";
		qcom,l1_i_cache0 {
			qcom,dump-node = <&L1_I_0>;
			qcom,dump-id = <0x60>;
		};
		qcom,l1_i_cache1 {
			qcom,dump-node = <&L1_I_100>;
			qcom,dump-id = <0x61>;
		};
		qcom,l1_i_cache2 {
			qcom,dump-node = <&L1_I_200>;
			qcom,dump-id = <0x62>;
		};
		qcom,l1_i_cache3 {
			qcom,dump-node = <&L1_I_300>;
			qcom,dump-id = <0x63>;
		};
		qcom,l1_i_cache100 {
			qcom,dump-node = <&L1_I_400>;
			qcom,dump-id = <0x64>;
		};
		qcom,l1_i_cache101 {
			qcom,dump-node = <&L1_I_500>;
			qcom,dump-id = <0x65>;
		};
		qcom,l1_i_cache102 {
			qcom,dump-node = <&L1_I_600>;
			qcom,dump-id = <0x66>;
		};
		qcom,l1_i_cache103 {
			qcom,dump-node = <&L1_I_700>;
			qcom,dump-id = <0x67>;
		};
		qcom,l1_d_cache0 {
			qcom,dump-node = <&L1_D_0>;
			qcom,dump-id = <0x80>;
		};
		qcom,l1_d_cache1 {
			qcom,dump-node = <&L1_D_100>;
			qcom,dump-id = <0x81>;
		};
		qcom,l1_d_cache2 {
			qcom,dump-node = <&L1_D_200>;
			qcom,dump-id = <0x82>;
		};
		qcom,l1_d_cache3 {
			qcom,dump-node = <&L1_D_300>;
			qcom,dump-id = <0x83>;
		};
		qcom,l1_d_cache100 {
			qcom,dump-node = <&L1_D_400>;
			qcom,dump-id = <0x84>;
		};
		qcom,l1_d_cache101 {
			qcom,dump-node = <&L1_D_500>;
			qcom,dump-id = <0x85>;
		};
		qcom,l1_d_cache102 {
			qcom,dump-node = <&L1_D_600>;
			qcom,dump-id = <0x86>;
		};
		qcom,l1_d_cache103 {
			qcom,dump-node = <&L1_D_700>;
			qcom,dump-id = <0x87>;
		};
		qcom,llcc1_d_cache {
			qcom,dump-node = <&LLCC_1>;
			qcom,dump-id = <0x121>;
		};
		qcom,llcc2_d_cache {
			qcom,dump-node = <&LLCC_2>;
			qcom,dump-id = <0x122>;
		};
		qcom,llcc3_d_cache {
			qcom,dump-node = <&LLCC_3>;
			qcom,dump-id = <0x123>;
		};
		qcom,llcc4_d_cache {
			qcom,dump-node = <&LLCC_4>;
			qcom,dump-id = <0x124>;
		};
	};

	kryo3xx-erp {
		compatible = "arm,arm64-kryo3xx-cpu-erp";
		interrupts = <1 6 4>,
			     <1 7 4>,
			     <0 34 4>,
			     <0 35 4>;

		interrupt-names = "l1-l2-faultirq",
				  "l1-l2-errirq",
				  "l3-scu-errirq",
				  "l3-scu-faultirq";
	};

	qcom,llcc@1100000 {
		compatible = "qcom,llcc-core", "syscon", "simple-mfd";
		reg = <0x1100000 0x250000>;
		reg-names = "llcc_base";
		qcom,llcc-banks-off = <0x0 0x80000 0x100000 0x180000>;
		qcom,llcc-broadcast-off = <0x200000>;

		llcc: qcom,sdm845-llcc {
			compatible = "qcom,sdm845-llcc";
			#cache-cells = <1>;
			max-slices = <32>;
			qcom,dump-size = <0x3c0000>;
		};

		qcom,llcc-erp {
			compatible = "qcom,llcc-erp";
			interrupt-names = "ecc_irq";
			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
		};

		qcom,llcc-amon {
			compatible = "qcom,llcc-amon";
		};

		LLCC_1: llcc_1_dcache {
			qcom,dump-size = <0xd8000>;
		};

		LLCC_2: llcc_2_dcache {
			qcom,dump-size = <0xd8000>;
		};

		LLCC_3: llcc_3_dcache {
			qcom,dump-size = <0xd8000>;
		};

		LLCC_4: llcc_4_dcache {
			qcom,dump-size = <0xd8000>;
		};
	};

	qcom,ipc-spinlock@1f40000 {
		compatible = "qcom,ipc-spinlock-sfpb";
		reg = <0x1f40000 0x8000>;
		qcom,num-locks = <8>;
	};

	qcom,smem@86000000 {
		compatible = "qcom,smem";
		reg = <0x86000000 0x200000>,
			<0x17911008 0x4>,
			<0x778000 0x7000>,
			<0x1fd4000 0x8>;
		reg-names = "smem", "irq-reg-base", "aux-mem1",
			"smem_targ_info_reg";
		qcom,mpu-enabled;
	};

	qcom,glink-mailbox-xprt-spss@1885008 {
		compatible = "qcom,glink-mailbox-xprt";
		reg = <0x1885008 0x8>,
			<0x1885010 0x4>,
			<0x188501c 0x4>,
			<0x1886008 0x4>;
		reg-names = "mbox-loc-addr", "mbox-loc-size", "irq-reg-base",
				"irq-rx-reset";
		qcom,irq-mask = <0x1>;
		interrupts = <0 348 4>;
		label = "spss";
		qcom,tx-ring-size = <0x400>;
		qcom,rx-ring-size = <0x400>;
	};

	qmp_aop: mailbox@1799000c {
		compatible = "qcom,qmp-mbox";
		label = "aop";
		reg = <0xc300000 0x100000>,
			<0x1799000c 0x4>;
		reg-names = "msgram", "irq-reg-base";
		qcom,irq-mask = <0x1>;
		interrupts = <0 389 1>;
		mbox-desc-offset = <0x0>;
		#mbox-cells = <1>;
	};

	apps_rsc: mailbox@179e0000 {
		compatible = "qcom,tcs-drv";
		label = "apps_rsc";
		reg = <0x179e0000 0x100>, <0x179e0d00 0x3000>;
		interrupts = <0 5 0>;
		#mbox-cells = <1>;
		qcom,drv-id = <2>;
		qcom,tcs-config = <ACTIVE_TCS  2>,
				<SLEEP_TCS     3>,
				<WAKE_TCS      3>,
				<CONTROL_TCS   1>;
	};

	disp_rsc: mailbox@af20000 {
		compatible = "qcom,tcs-drv";
		label = "display_rsc";
		reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>;
		interrupts = <0 129 0>;
		#mbox-cells = <1>;
		qcom,drv-id = <0>;
		qcom,tcs-config = <SLEEP_TCS 1>,
				<WAKE_TCS    1>,
				<ACTIVE_TCS  0>,
				<CONTROL_TCS 1>;
	};

	system_pm {
		compatible = "qcom,system-pm";
		mboxes = <&apps_rsc 0>;
	};

	qcom,glink-smem-native-xprt-modem@86000000 {
		compatible = "qcom,glink-smem-native-xprt";
		reg = <0x86000000 0x200000>,
			<0x1799000c 0x4>;
		reg-names = "smem", "irq-reg-base";
		qcom,irq-mask = <0x1000>;
		interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
		label = "mpss";
	};

	qcom,glink-smem-native-xprt-adsp@86000000 {
		compatible = "qcom,glink-smem-native-xprt";
		reg = <0x86000000 0x200000>,
			<0x1799000c 0x4>;
		reg-names = "smem", "irq-reg-base";
		qcom,irq-mask = <0x100>;
		interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
		label = "lpass";
	};

	qcom,glink-smem-native-xprt-dsps@86000000 {
		compatible = "qcom,glink-smem-native-xprt";
		reg = <0x86000000 0x200000>,
			<0x1799000c 0x4>;
		reg-names = "smem", "irq-reg-base";
		qcom,irq-mask = <0x1000000>;
		interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
		label = "dsps";
	};

	qcom,glink-smem-native-xprt-cdsp@86000000 {
		compatible = "qcom,glink-smem-native-xprt";
		reg = <0x86000000 0x200000>,
			<0x1799000c 0x4>;
		reg-names = "smem", "irq-reg-base";
		qcom,irq-mask = <0x10>;
		interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
		label = "cdsp";
	};

	glink_mpss: qcom,glink-ssr-modem {
		compatible = "qcom,glink_ssr";
		label = "modem";
		qcom,edge = "mpss";
		qcom,notify-edges = <&glink_lpass>, <&glink_dsps>,
				    <&glink_cdsp>, <&glink_spss>;
		qcom,xprt = "smem";
	};

	glink_lpass: qcom,glink-ssr-adsp {
		compatible = "qcom,glink_ssr";
		label = "adsp";
		qcom,edge = "lpass";
		qcom,notify-edges = <&glink_mpss>, <&glink_dsps>, <&glink_cdsp>;
		qcom,xprt = "smem";
	};

	glink_dsps: qcom,glink-ssr-dsps {
		compatible = "qcom,glink_ssr";
		label = "slpi";
		qcom,edge = "dsps";
		qcom,notify-edges = <&glink_mpss>, <&glink_lpass>,
				    <&glink_cdsp>;
		qcom,xprt = "smem";
	};

	glink_cdsp: qcom,glink-ssr-cdsp {
		compatible = "qcom,glink_ssr";
		label = "cdsp";
		qcom,edge = "cdsp";
		qcom,notify-edges = <&glink_mpss>, <&glink_lpass>,
				    <&glink_dsps>;
		qcom,xprt = "smem";
	};

	glink_spss: qcom,glink-ssr-spss {
		compatible = "qcom,glink_ssr";
		label = "spss";
		qcom,edge = "spss";
		qcom,notify-edges = <&glink_mpss>;
		qcom,xprt = "mailbox";
	};

	qcom,ipc_router {
		compatible = "qcom,ipc_router";
		qcom,node-id = <1>;
	};

	qcom,ipc_router_modem_xprt {
		compatible = "qcom,ipc_router_glink_xprt";
		qcom,ch-name = "IPCRTR";
		qcom,xprt-remote = "mpss";
		qcom,glink-xprt = "smem";
		qcom,xprt-linkid = <1>;
		qcom,xprt-version = <1>;
		qcom,fragmented-data;
	};

	qcom,ipc_router_q6_xprt {
		compatible = "qcom,ipc_router_glink_xprt";
		qcom,ch-name = "IPCRTR";
		qcom,xprt-remote = "lpass";
		qcom,glink-xprt = "smem";
		qcom,xprt-linkid = <1>;
		qcom,xprt-version = <1>;
		qcom,fragmented-data;
	};

	qcom,ipc_router_dsps_xprt {
		compatible = "qcom,ipc_router_glink_xprt";
		qcom,ch-name = "IPCRTR";
		qcom,xprt-remote = "dsps";
		qcom,glink-xprt = "smem";
		qcom,xprt-linkid = <1>;
		qcom,xprt-version = <1>;
		qcom,fragmented-data;
	};

	qcom,ipc_router_cdsp_xprt {
		compatible = "qcom,ipc_router_glink_xprt";
		qcom,ch-name = "IPCRTR";
		qcom,xprt-remote = "cdsp";
		qcom,glink-xprt = "smem";
		qcom,xprt-linkid = <1>;
		qcom,xprt-version = <1>;
		qcom,fragmented-data;
	};

	qcom,spcom {
		compatible = "qcom,spcom";

		/* predefined channels, remote side is server */
		qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
		status = "ok";
	};

	qcom,glink_pkt {
		compatible = "qcom,glinkpkt";

		qcom,glinkpkt-at-mdm0 {
			qcom,glinkpkt-transport = "smem";
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DS";
			qcom,glinkpkt-dev-name = "at_mdm0";
		};

		qcom,glinkpkt-loopback_cntl {
			qcom,glinkpkt-transport = "lloop";
			qcom,glinkpkt-edge = "local";
			qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
			qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
		};

		qcom,glinkpkt-loopback_data {
			qcom,glinkpkt-transport = "lloop";
			qcom,glinkpkt-edge = "local";
			qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
			qcom,glinkpkt-dev-name = "glink_pkt_loopback";
		};

		qcom,glinkpkt-apr-apps2 {
			qcom,glinkpkt-transport = "smem";
			qcom,glinkpkt-edge = "adsp";
			qcom,glinkpkt-ch-name = "apr_apps2";
			qcom,glinkpkt-dev-name = "apr_apps2";
		};

		qcom,glinkpkt-data40-cntl {
			qcom,glinkpkt-transport = "smem";
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA40_CNTL";
			qcom,glinkpkt-dev-name = "smdcntl8";
		};

		qcom,glinkpkt-data1 {
			qcom,glinkpkt-transport = "smem";
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA1";
			qcom,glinkpkt-dev-name = "smd7";
		};

		qcom,glinkpkt-data4 {
			qcom,glinkpkt-transport = "smem";
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA4";
			qcom,glinkpkt-dev-name = "smd8";
		};

		qcom,glinkpkt-data11 {
			qcom,glinkpkt-transport = "smem";
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA11";
			qcom,glinkpkt-dev-name = "smd11";
		};
	};

	qcom,sps {
		compatible = "qcom,msm_sps_4k";
		qcom,pipe-attr-ee;
	};

	qcom,msm_gsi {
		compatible = "qcom,msm_gsi";
	};

	qcom,rmtfs_sharedmem@0 {
		compatible = "qcom,sharedmem-uio";
		reg = <0x0 0x200000>;
		reg-names = "rmtfs";
		qcom,client-id = <0x00000001>;
	};

	qcom,rmnet-ipa {
		compatible = "qcom,rmnet-ipa3";
		qcom,rmnet-ipa-ssr;
		qcom,ipa-loaduC;
		qcom,ipa-advertise-sg-support;
	};

	ipa_hw: qcom,ipa@01e00000 {
		compatible = "qcom,ipa";
		reg = <0x1e00000 0x34000>,
		      <0x1e04000 0x2c000>;
		reg-names = "ipa-base", "gsi-base";
		interrupts =
			<0 311 0>,
			<0 432 0>;
		interrupt-names = "ipa-irq", "gsi-irq";
		qcom,ipa-hw-ver = <13>; /* IPA core version = IPAv3.5.1 */
		qcom,ipa-hw-mode = <1>;
		qcom,ee = <0>;
		qcom,use-ipa-tethering-bridge;
		qcom,modem-cfg-emb-pipe-flt;
		qcom,ipa-wdi2;
		qcom,use-64-bit-dma-mask;
		qcom,bandwidth-vote-for-ipa;
		qcom,msm-bus,name = "ipa";
		qcom,msm-bus,num-cases = <4>;
		qcom,msm-bus,num-paths = <4>;
		qcom,msm-bus,vectors-KBps =
		/* No vote */
			<90 512 0 0>,
			<90 585 0 0>,
			<1 676 0 0>,
			<143 777 0 0>,
		/* SVS */
			<90 512 80000 640000>,
			<90 585 80000 640000>,
			<1 676 80000 80000>,
			<143 777 0 150000000>,
		/* NOMINAL */
			<90 512 206000 960000>,
			<90 585 206000 960000>,
			<1 676 206000 160000>,
			<143 777 0 300000000>,
		/* TURBO */
			<90 512 206000 3600000>,
			<90 585 206000 3600000>,
			<1 676 206000 300000>,
			<143 777 0 355333333>;
		qcom,bus-vector-names = "MIN", "SVS", "NOMINAL", "TURBO";

		/* IPA RAM mmap */
		qcom,ipa-ram-mmap = <
			0x280	/* ofst_start; */
			0x0	/* nat_ofst; */
			0x0	/* nat_size; */
			0x288	/* v4_flt_hash_ofst; */
			0x78	/* v4_flt_hash_size; */
			0x4000	/* v4_flt_hash_size_ddr; */
			0x308	/* v4_flt_nhash_ofst; */
			0x78	/* v4_flt_nhash_size; */
			0x4000	/* v4_flt_nhash_size_ddr; */
			0x388	/* v6_flt_hash_ofst; */
			0x78	/* v6_flt_hash_size; */
			0x4000	/* v6_flt_hash_size_ddr; */
			0x408	/* v6_flt_nhash_ofst; */
			0x78	/* v6_flt_nhash_size; */
			0x4000	/* v6_flt_nhash_size_ddr; */
			0xf	/* v4_rt_num_index; */
			0x0	/* v4_modem_rt_index_lo; */
			0x7	/* v4_modem_rt_index_hi; */
			0x8	/* v4_apps_rt_index_lo; */
			0xe	/* v4_apps_rt_index_hi; */
			0x488	/* v4_rt_hash_ofst; */
			0x78	/* v4_rt_hash_size; */
			0x4000	/* v4_rt_hash_size_ddr; */
			0x508	/* v4_rt_nhash_ofst; */
			0x78	/* v4_rt_nhash_size; */
			0x4000	/* v4_rt_nhash_size_ddr; */
			0xf	/* v6_rt_num_index; */
			0x0	/* v6_modem_rt_index_lo; */
			0x7	/* v6_modem_rt_index_hi; */
			0x8	/* v6_apps_rt_index_lo; */
			0xe	/* v6_apps_rt_index_hi; */
			0x588	/* v6_rt_hash_ofst; */
			0x78	/* v6_rt_hash_size; */
			0x4000	/* v6_rt_hash_size_ddr; */
			0x608	/* v6_rt_nhash_ofst; */
			0x78	/* v6_rt_nhash_size; */
			0x4000	/* v6_rt_nhash_size_ddr; */
			0x688	/* modem_hdr_ofst; */
			0x140	/* modem_hdr_size; */
			0x7c8	/* apps_hdr_ofst; */
			0x0	/* apps_hdr_size; */
			0x800	/* apps_hdr_size_ddr; */
			0x7d0	/* modem_hdr_proc_ctx_ofst; */
			0x200	/* modem_hdr_proc_ctx_size; */
			0x9d0	/* apps_hdr_proc_ctx_ofst; */
			0x200	/* apps_hdr_proc_ctx_size; */
			0x0	/* apps_hdr_proc_ctx_size_ddr; */
			0x0	/* modem_comp_decomp_ofst; diff */
			0x0	/* modem_comp_decomp_size; diff */
			0xbd8	/* modem_ofst; */
			0x1424	/* modem_size; */
			0x1ffc	/* apps_v4_flt_hash_ofst; */
			0x0	/* apps_v4_flt_hash_size; */
			0x1ffc	/* apps_v4_flt_nhash_ofst; */
			0x0	/* apps_v4_flt_nhash_size; */
			0x1ffc	/* apps_v6_flt_hash_ofst; */
			0x0	/* apps_v6_flt_hash_size; */
			0x1ffc	/* apps_v6_flt_nhash_ofst; */
			0x0	/* apps_v6_flt_nhash_size; */
			0x80	/* uc_info_ofst; */
			0x200	/* uc_info_size; */
			0x2000	/* end_ofst; */
			0x1ffc	/* apps_v4_rt_hash_ofst; */
			0x0	/* apps_v4_rt_hash_size; */
			0x1ffc	/* apps_v4_rt_nhash_ofst; */
			0x0	/* apps_v4_rt_nhash_size; */
			0x1ffc	/* apps_v6_rt_hash_ofst; */
			0x0	/* apps_v6_rt_hash_size; */
			0x1ffc	/* apps_v6_rt_nhash_ofst; */
			0x0	/* apps_v6_rt_nhash_size; */
		>;

		/* smp2p gpio information */
		qcom,smp2pgpio_map_ipa_1_out {
			compatible = "qcom,smp2pgpio-map-ipa-1-out";
			gpios = <&smp2pgpio_ipa_1_out 0 0>;
		};

		qcom,smp2pgpio_map_ipa_1_in {
			compatible = "qcom,smp2pgpio-map-ipa-1-in";
			gpios = <&smp2pgpio_ipa_1_in 0 0>;
		};
	};

	qcom,ipa_fws {
		compatible = "qcom,pil-tz-generic";
		qcom,pas-id = <0xf>;
		qcom,firmware-name = "ipa_fws";
	};

	qcom,chd_sliver {
		compatible = "qcom,core-hang-detect";
		label = "silver";
		qcom,threshold-arr = <0x17e00058 0x17e10058
		0x17e20058 0x17e30058>;
		qcom,config-arr = <0x17e00060 0x17e10060
		0x17e20060 0x17e30060>;
	};

	qcom,chd_gold {
		compatible = "qcom,core-hang-detect";
		label = "gold";
		qcom,threshold-arr = <0x17e40058 0x17e50058
		0x17e60058 0x17e70058>;
		qcom,config-arr = <0x17e40060 0x17e50060
		0x17e60060 0x17e70060>;
	};

	qcom,ghd {
		compatible = "qcom,gladiator-hang-detect-v2";
		qcom,threshold-arr = <0x1799041c 0x17990420>;
		qcom,config-reg = <0x17990434>;
	};

	qcom,msm-gladiator-v3@17900000 {
		compatible = "qcom,msm-gladiator-v3";
		reg = <0x17900000 0xd080>;
		reg-names = "gladiator_base";
		interrupts = <0 17 0>;
	};

	cmd_db: qcom,cmd-db@861e0000 {
		compatible = "qcom,cmd-db";
		reg = <0x861e0000 0x4000>;
	};

	dcc: dcc_v2@10a2000 {
		compatible = "qcom,dcc_v2";
		reg = <0x10a2000 0x1000>,
		      <0x10ae000 0x2000>;
		reg-names = "dcc-base", "dcc-ram-base";
	};

	qcom,msm-core@780000 {
		compatible = "qcom,apss-core-ea";
		reg = <0x780000 0x1000>;
	};

	qcom,icnss@18800000 {
		compatible = "qcom,icnss";
		reg = <0x18800000 0x800000>,
		      <0xa0000000 0x10000000>,
		      <0xb0000000 0x10000>;
		reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa";
		iommus = <&apps_smmu 0x0040>,
			 <&apps_smmu 0x0041>;
		interrupts = <0 414 0 /* CE0 */ >,
			     <0 415 0 /* CE1 */ >,
			     <0 416 0 /* CE2 */ >,
			     <0 417 0 /* CE3 */ >,
			     <0 418 0 /* CE4 */ >,
			     <0 419 0 /* CE5 */ >,
			     <0 420 0 /* CE6 */ >,
			     <0 421 0 /* CE7 */ >,
			     <0 422 0 /* CE8 */ >,
			     <0 423 0 /* CE9 */ >,
			     <0 424 0 /* CE10 */ >,
			     <0 425 0 /* CE11 */ >;
		qcom,wlan-msa-memory = <0x100000>;
	};
};

&pcie_0_gdsc {
	status = "ok";
};

&pcie_1_gdsc {
	status = "ok";
};

&ufs_card_gdsc {
	status = "ok";
};

&ufs_phy_gdsc {
	status = "ok";
};

&usb30_prim_gdsc {
	status = "ok";
};

&usb30_sec_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
	status = "ok";
};

&bps_gdsc {
	status = "ok";
};

&ife_0_gdsc {
	status = "ok";
};

&ife_1_gdsc {
	status = "ok";
};

&ipe_0_gdsc {
	status = "ok";
};

&ipe_1_gdsc {
	status = "ok";
};

&titan_top_gdsc {
	status = "ok";
};

&mdss_core_gdsc {
	status = "ok";
};

&gpu_cx_gdsc {
	status = "ok";
};

&gpu_gx_gdsc {
	clock-names = "core_root_clk";
	clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK_SRC>;
	qcom,force-enable-root-clk;
	parent-supply = <&pm8005_s1_level>;
	status = "ok";
};

&vcodec0_gdsc {
	status = "ok";
};

&vcodec1_gdsc {
	status = "ok";
};

&venus_gdsc {
	status = "ok";
};

#include "pm8998.dtsi"
#include "pmi8998.dtsi"
#include "pm8005.dtsi"
#include "sdm845-regulator.dtsi"
#include "sdm845-coresight.dtsi"
#include "msm-arm-smmu-sdm845.dtsi"
#include "sdm845-ion.dtsi"
#include "sdm845-smp2p.dtsi"
#include "sdm845-camera.dtsi"
#include "sdm845-bus.dtsi"
#include "sdm845-vidc.dtsi"
#include "sdm845-pm.dtsi"
#include "sdm845-pinctrl.dtsi"
#include "sdm845-audio.dtsi"
#include "sdm845-gpu.dtsi"
#include "sdm845-usb.dtsi"