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gerrit-public.fairphone.software / kernel / msm-4.9 / 0d1a567c6eadd31450fb0a1d2688039f57669a78 / . / drivers / clk / imx / clk-imx6sl.c
blob: f3d9dc2d2405c1630f6b4e688143b81b66f3ea0a [file] [log] [blame]
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]1/*
Anson Huang848db4a2014-01-07 12:46:04 -0500[diff] [blame]2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/clk.h>
11#include <linux/clkdev.h>
12#include <linux/err.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <dt-bindings/clock/imx6sl-clock.h>
17
18#include "clk.h"
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]19
Anson Huangf2ea36e2018-11-30 07:23:47 +0000[diff] [blame]20#define CCDR 0x4
21#define BM_CCM_CCDR_MMDC_CH0_MASK (1 << 17)
Anson Huang6e6cdf62014-02-11 16:25:48 +0800[diff] [blame]22#define CCSR 0xc
23#define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
24#define CACRR 0x10
25#define CDHIPR 0x48
26#define BM_CDHIPR_ARM_PODF_BUSY (1 << 16)
27#define ARM_WAIT_DIV_396M 2
28#define ARM_WAIT_DIV_792M 4
29#define ARM_WAIT_DIV_996M 6
30
31#define PLL_ARM 0x0
32#define BM_PLL_ARM_DIV_SELECT (0x7f << 0)
33#define BM_PLL_ARM_POWERDOWN (1 << 12)
34#define BM_PLL_ARM_ENABLE (1 << 13)
35#define BM_PLL_ARM_LOCK (1 << 31)
36#define PLL_ARM_DIV_792M 66
37
Liu Yingb21c22e2014-01-15 14:19:34 +0800[diff] [blame]38static const char *step_sels[] = { "osc", "pll2_pfd2", };
39static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
40static const char *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", };
41static const char *ocram_sels[] = { "periph", "ocram_alt_sels", };
42static const char *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
43static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
44static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
45static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", };
46static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
Fabio Estevambad66c32014-08-19 15:21:11 -0300[diff] [blame]47static const char *csi_sels[] = { "osc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
48static const char *lcdif_axi_sels[] = { "pll2_bus", "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", };
Liu Yingb21c22e2014-01-15 14:19:34 +0800[diff] [blame]49static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
50static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
51static const char *perclk_sels[] = { "ipg", "osc", };
Fancy Fange37c1ad2014-09-04 16:33:12 +0800[diff] [blame]52static const char *pxp_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd3", };
53static const char *epdc_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd2", };
Liu Yingb21c22e2014-01-15 14:19:34 +0800[diff] [blame]54static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
55static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
56static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
57static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
58static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
59static const char *ecspi_sels[] = { "pll3_60m", "osc", };
60static const char *uart_sels[] = { "pll3_80m", "osc", };
Shawn Guoe90f4192014-09-01 14:29:53 +0800[diff] [blame]61static const char *lvds_sels[] = {
62 "pll1_sys", "pll2_bus", "pll2_pfd0", "pll2_pfd1", "pll2_pfd2", "dummy", "pll4_audio", "pll5_video",
63 "dummy", "enet_ref", "dummy", "dummy", "pll3_usb_otg", "pll7_usb_host", "pll3_pfd0", "pll3_pfd1",
64 "pll3_pfd2", "pll3_pfd3", "osc", "dummy", "dummy", "dummy", "dummy", "dummy",
65 "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
66};
67static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
68static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
69static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
70static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
71static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
72static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
73static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
74static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]75
76static struct clk_div_table clk_enet_ref_table[] = {
77 { .val = 0, .div = 20, },
78 { .val = 1, .div = 10, },
79 { .val = 2, .div = 5, },
80 { .val = 3, .div = 4, },
81 { }
82};
83
84static struct clk_div_table post_div_table[] = {
85 { .val = 2, .div = 1, },
86 { .val = 1, .div = 2, },
87 { .val = 0, .div = 4, },
88 { }
89};
90
91static struct clk_div_table video_div_table[] = {
92 { .val = 0, .div = 1, },
93 { .val = 1, .div = 2, },
94 { .val = 2, .div = 1, },
95 { .val = 3, .div = 4, },
96 { }
97};
98
Shengjiu Wangdbaf3812014-09-09 17:13:25 +0800[diff] [blame]99static unsigned int share_count_ssi1;
100static unsigned int share_count_ssi2;
101static unsigned int share_count_ssi3;
Shengjiu Wang84a87252015-10-10 18:15:06 +0800[diff] [blame]102static unsigned int share_count_spdif;
Shengjiu Wangdbaf3812014-09-09 17:13:25 +0800[diff] [blame]103
Shawn Guo4e5d0d62013-11-16 22:33:16 +0800[diff] [blame]104static struct clk *clks[IMX6SL_CLK_END];
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]105static struct clk_onecell_data clk_data;
Anson Huang6e6cdf62014-02-11 16:25:48 +0800[diff] [blame]106static void __iomem *ccm_base;
107static void __iomem *anatop_base;
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]108
Anson Huang17626b72014-01-22 15:14:47 +0800[diff] [blame]109static const u32 clks_init_on[] __initconst = {
110 IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT,
111};
112
Anson Huang751f7e92014-01-09 16:03:16 +0800[diff] [blame]113/*
114 * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
115 * during WAIT mode entry process could cause cache memory
116 * corruption.
117 *
118 * Software workaround:
119 * To prevent this issue from occurring, software should ensure that the
120 * ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
121 * entering WAIT mode.
122 *
123 * This function will set the ARM clk to max value within the 12:5 limit.
Anson Huang6e6cdf62014-02-11 16:25:48 +0800[diff] [blame]124 * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz),
125 * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since
126 * the clk APIs can NOT be called in idle thread(may cause kernel schedule
127 * as there is sleep function in PLL wait function), so here we just slow
128 * down ARM to below freq according to previous freq:
129 *
130 * run mode wait mode
131 * 396MHz -> 132MHz;
132 * 792MHz -> 158.4MHz;
133 * 996MHz -> 142.3MHz;
Anson Huang751f7e92014-01-09 16:03:16 +0800[diff] [blame]134 */
Anson Huang6e6cdf62014-02-11 16:25:48 +0800[diff] [blame]135static int imx6sl_get_arm_divider_for_wait(void)
136{
137 if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) {
138 return ARM_WAIT_DIV_396M;
139 } else {
140 if ((readl_relaxed(anatop_base + PLL_ARM) &
141 BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M)
142 return ARM_WAIT_DIV_792M;
143 else
144 return ARM_WAIT_DIV_996M;
145 }
146}
147
148static void imx6sl_enable_pll_arm(bool enable)
149{
150 static u32 saved_pll_arm;
151 u32 val;
152
153 if (enable) {
154 saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM);
155 val |= BM_PLL_ARM_ENABLE;
156 val &= ~BM_PLL_ARM_POWERDOWN;
157 writel_relaxed(val, anatop_base + PLL_ARM);
158 while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK))
159 ;
160 } else {
161 writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM);
162 }
163}
164
Anson Huang751f7e92014-01-09 16:03:16 +0800[diff] [blame]165void imx6sl_set_wait_clk(bool enter)
166{
Anson Huang6e6cdf62014-02-11 16:25:48 +0800[diff] [blame]167 static unsigned long saved_arm_div;
168 int arm_div_for_wait = imx6sl_get_arm_divider_for_wait();
169
170 /*
171 * According to hardware design, arm podf change need
172 * PLL1 clock enabled.
173 */
174 if (arm_div_for_wait == ARM_WAIT_DIV_396M)
175 imx6sl_enable_pll_arm(true);
Anson Huang751f7e92014-01-09 16:03:16 +0800[diff] [blame]176
177 if (enter) {
Anson Huang6e6cdf62014-02-11 16:25:48 +0800[diff] [blame]178 saved_arm_div = readl_relaxed(ccm_base + CACRR);
179 writel_relaxed(arm_div_for_wait, ccm_base + CACRR);
Anson Huang751f7e92014-01-09 16:03:16 +0800[diff] [blame]180 } else {
Anson Huang6e6cdf62014-02-11 16:25:48 +0800[diff] [blame]181 writel_relaxed(saved_arm_div, ccm_base + CACRR);
Anson Huang751f7e92014-01-09 16:03:16 +0800[diff] [blame]182 }
Anson Huang6e6cdf62014-02-11 16:25:48 +0800[diff] [blame]183 while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY)
184 ;
185
186 if (arm_div_for_wait == ARM_WAIT_DIV_396M)
187 imx6sl_enable_pll_arm(false);
Anson Huang751f7e92014-01-09 16:03:16 +0800[diff] [blame]188}
189
Lucas Stach0822f932015-09-21 18:54:03 +0200[diff] [blame]190static struct clk ** const uart_clks[] __initconst = {
191 &clks[IMX6SL_CLK_UART],
192 &clks[IMX6SL_CLK_UART_SERIAL],
193 NULL
194};
195
Shawn Guo53bb71d2013-05-21 09:58:51 +0800[diff] [blame]196static void __init imx6sl_clocks_init(struct device_node *ccm_node)
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]197{
198 struct device_node *np;
199 void __iomem *base;
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]200 int i;
Anson Huang848db4a2014-01-07 12:46:04 -0500[diff] [blame]201 int ret;
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]202
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]203 clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
204 clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
205 clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
Shawn Guoe90f4192014-09-01 14:29:53 +0800[diff] [blame]206 /* Clock source from external clock via CLK1 PAD */
207 clks[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]208
209 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
210 base = of_iomap(np, 0);
211 WARN_ON(!base);
Anson Huang6e6cdf62014-02-11 16:25:48 +0800[diff] [blame]212 anatop_base = base;
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]213
Shawn Guoe90f4192014-09-01 14:29:53 +0800[diff] [blame]214 clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
215 clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
216 clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
217 clks[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
218 clks[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
219 clks[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
220 clks[IMX6SL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
221
222 /* type name parent_name base div_mask */
Dong Aishengf83d3162016-06-08 22:33:36 +0800[diff] [blame]223 clks[IMX6SL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
224 clks[IMX6SL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
225 clks[IMX6SL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
226 clks[IMX6SL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
227 clks[IMX6SL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);
228 clks[IMX6SL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3);
229 clks[IMX6SL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3);
Shawn Guoe90f4192014-09-01 14:29:53 +0800[diff] [blame]230
231 clks[IMX6SL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
232 clks[IMX6SL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
233 clks[IMX6SL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
234 clks[IMX6SL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
235 clks[IMX6SL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
236 clks[IMX6SL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
237 clks[IMX6SL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
238
239 /* Do not bypass PLLs initially */
240 clk_set_parent(clks[IMX6SL_PLL1_BYPASS], clks[IMX6SL_CLK_PLL1]);
241 clk_set_parent(clks[IMX6SL_PLL2_BYPASS], clks[IMX6SL_CLK_PLL2]);
242 clk_set_parent(clks[IMX6SL_PLL3_BYPASS], clks[IMX6SL_CLK_PLL3]);
243 clk_set_parent(clks[IMX6SL_PLL4_BYPASS], clks[IMX6SL_CLK_PLL4]);
244 clk_set_parent(clks[IMX6SL_PLL5_BYPASS], clks[IMX6SL_CLK_PLL5]);
245 clk_set_parent(clks[IMX6SL_PLL6_BYPASS], clks[IMX6SL_CLK_PLL6]);
246 clk_set_parent(clks[IMX6SL_PLL7_BYPASS], clks[IMX6SL_CLK_PLL7]);
247
248 clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
249 clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
250 clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
251 clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
252 clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
253 clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
Shawn Guo69d9a3f2014-09-12 10:40:28 +0800[diff] [blame]254 clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
Shawn Guoe90f4192014-09-01 14:29:53 +0800[diff] [blame]255
256 clks[IMX6SL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
257 clks[IMX6SL_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
258 clks[IMX6SL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]259
260 /*
261 * usbphy1 and usbphy2 are implemented as dummy gates using reserve
262 * bit 20. They are used by phy driver to keep the refcount of
263 * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be
264 * turned on during boot, and software will not need to control it
265 * anymore after that.
266 */
267 clks[IMX6SL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
268 clks[IMX6SL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
269 clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
270 clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
271
272 /* dev name parent_name flags reg shift width div: flags, div_table lock */
273 clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
Nicolin Chen238fb182013-12-13 23:44:07 +0800[diff] [blame]274 clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]275 clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
276 clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
277 clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
278
279 /* name parent_name reg idx */
280 clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus", base + 0x100, 0);
281 clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", base + 0x100, 1);
282 clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", base + 0x100, 2);
283 clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0, 0);
284 clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0, 1);
285 clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0, 2);
286 clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0, 3);
287
288 /* name parent_name mult div */
289 clks[IMX6SL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2", 1, 2);
290 clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
291 clks[IMX6SL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
292 clks[IMX6SL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
293
Shawn Guo53bb71d2013-05-21 09:58:51 +0800[diff] [blame]294 np = ccm_node;
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]295 base = of_iomap(np, 0);
296 WARN_ON(!base);
Anson Huang6e6cdf62014-02-11 16:25:48 +0800[diff] [blame]297 ccm_base = base;
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]298
299 /* name reg shift width parent_names num_parents */
300 clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
301 clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
302 clks[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels));
303 clks[IMX6SL_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels));
304 clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
305 clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
306 clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
307 clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
Fabio Estevambad66c32014-08-19 15:21:11 -0300[diff] [blame]308 clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
309 clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, lcdif_axi_sels, ARRAY_SIZE(lcdif_axi_sels));
Liu Yingdfd87142013-07-04 17:57:17 +0800[diff] [blame]310 clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
311 clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
312 clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
313 clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
314 clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
315 clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
316 clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
317 clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup);
Fancy Fange37c1ad2014-09-04 16:33:12 +0800[diff] [blame]318 clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels));
319 clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels));
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]320 clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels));
321 clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels));
322 clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels));
323 clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels));
324 clks[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
325 clks[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
326 clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
327 clks[IMX6SL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
328 clks[IMX6SL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
329
330 /* name reg shift width busy: reg, shift parent_names num_parents */
331 clks[IMX6SL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
332 clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
333
334 /* name parent_name reg shift width */
335 clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3);
336 clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3);
337 clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3);
338 clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
339 clks[IMX6SL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
340 clks[IMX6SL_CLK_LCDIF_AXI_PODF] = imx_clk_divider("lcdif_axi_podf", "lcdif_axi_sel", base + 0x3c, 16, 3);
341 clks[IMX6SL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
342 clks[IMX6SL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
343 clks[IMX6SL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
344 clks[IMX6SL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
345 clks[IMX6SL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
346 clks[IMX6SL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
347 clks[IMX6SL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
348 clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
349 clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
350 clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
Liu Yingdfd87142013-07-04 17:57:17 +0800[diff] [blame]351 clks[IMX6SL_CLK_PERCLK] = imx_clk_fixup_divider("perclk", "perclk_sel", base + 0x1c, 0, 6, imx_cscmr1_fixup);
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]352 clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3);
353 clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3);
354 clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3);
355 clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3);
356 clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3);
357 clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3);
Liu Yingdfd87142013-07-04 17:57:17 +0800[diff] [blame]358 clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_fixup_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3, imx_cscmr1_fixup);
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]359 clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3);
360 clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3);
361 clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3);
362 clks[IMX6SL_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3);
363 clks[IMX6SL_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3);
364 clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x28, 9, 3);
365 clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3);
366 clks[IMX6SL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6);
367 clks[IMX6SL_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_sel", base + 0x24, 0, 6);
368
369 /* name parent_name reg shift width busy: reg, shift */
370 clks[IMX6SL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
371 clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
372 clks[IMX6SL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
373
374 /* name parent_name reg shift */
375 clks[IMX6SL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
376 clks[IMX6SL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
377 clks[IMX6SL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
378 clks[IMX6SL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
Fugang Duan4ca2ad52014-05-19 15:46:41 +0800[diff] [blame]379 clks[IMX6SL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]380 clks[IMX6SL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12);
381 clks[IMX6SL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14);
382 clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16);
383 clks[IMX6SL_CLK_GPT] = imx_clk_gate2("gpt", "perclk", base + 0x6c, 20);
384 clks[IMX6SL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22);
385 clks[IMX6SL_CLK_GPU2D_OVG] = imx_clk_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26);
386 clks[IMX6SL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
387 clks[IMX6SL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
388 clks[IMX6SL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
389 clks[IMX6SL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
390 clks[IMX6SL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x74, 0);
391 clks[IMX6SL_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "pxp_axi_podf", base + 0x74, 2);
392 clks[IMX6SL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_axi", "epdc_axi_podf", base + 0x74, 4);
393 clks[IMX6SL_CLK_LCDIF_AXI] = imx_clk_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6);
394 clks[IMX6SL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8);
395 clks[IMX6SL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10);
396 clks[IMX6SL_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28);
397 clks[IMX6SL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16);
398 clks[IMX6SL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18);
399 clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
400 clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
401 clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
Nicolin Chen8962a5d2013-12-13 23:44:08 +0800[diff] [blame]402 clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
Shengjiu Wang84a87252015-10-10 18:15:06 +0800[diff] [blame]403 clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif0_podf", base + 0x7c, 14, &share_count_spdif);
404 clks[IMX6SL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
Shengjiu Wangdbaf3812014-09-09 17:13:25 +0800[diff] [blame]405 clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
406 clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
407 clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
408 clks[IMX6SL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
409 clks[IMX6SL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
410 clks[IMX6SL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]411 clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24);
412 clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26);
413 clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
414 clks[IMX6SL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
415 clks[IMX6SL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
416 clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
417 clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
418
Anson Huangf2ea36e2018-11-30 07:23:47 +0000[diff] [blame]419 /* Ensure the MMDC CH0 handshake is bypassed */
420 writel_relaxed(readl_relaxed(base + CCDR) |
421 BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
422
Alexander Shiyan229be9c2014-06-10 19:40:26 +0400[diff] [blame]423 imx_check_clocks(clks, ARRAY_SIZE(clks));
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]424
425 clk_data.clks = clks;
426 clk_data.clk_num = ARRAY_SIZE(clks);
427 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
428
Anson Huang848db4a2014-01-07 12:46:04 -0500[diff] [blame]429 /* Ensure the AHB clk is at 132MHz. */
430 ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
431 if (ret)
432 pr_warn("%s: failed to set AHB clock rate %d!\n",
433 __func__, ret);
434
Anson Huang17626b72014-01-22 15:14:47 +0800[diff] [blame]435 /*
436 * Make sure those always on clocks are enabled to maintain the correct
437 * usecount and enabling/disabling of parent PLLs.
438 */
439 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
440 clk_prepare_enable(clks[clks_init_on[i]]);
441
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]442 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
443 clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
444 clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
445 }
446
Nicolin Chen4390e622013-12-13 23:37:52 +0800[diff] [blame]447 /* Audio-related clocks configuration */
448 clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
449
Fabio Estevam0783a562014-08-19 15:21:12 -0300[diff] [blame]450 /* set PLL5 video as lcdif pix parent clock */
451 clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
452 clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
453
454 clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL],
455 clks[IMX6SL_CLK_PLL2_PFD2]);
Lucas Stach0822f932015-09-21 18:54:03 +0200[diff] [blame]456
457 imx_register_uart_clocks(uart_clks);
Shawn Guo45fe6812013-05-03 11:06:46 +0800[diff] [blame]458}
Shawn Guo53bb71d2013-05-21 09:58:51 +0800[diff] [blame]459CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);