Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 1 | /* |
| 2 | * TI DaVinci GPIO Support |
| 3 | * |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 4 | * Copyright (c) 2006-2007 David Brownell |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | */ |
Russell King | 2f8163b | 2011-07-26 10:53:52 +0100 | [diff] [blame] | 12 | #include <linux/gpio.h> |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 13 | #include <linux/errno.h> |
| 14 | #include <linux/kernel.h> |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 15 | #include <linux/clk.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/io.h> |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 18 | #include <linux/irq.h> |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 19 | #include <linux/irqdomain.h> |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame^] | 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/of_device.h> |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/platform_data/gpio-davinci.h> |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 25 | |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 26 | struct davinci_gpio_regs { |
| 27 | u32 dir; |
| 28 | u32 out_data; |
| 29 | u32 set_data; |
| 30 | u32 clr_data; |
| 31 | u32 in_data; |
| 32 | u32 set_rising; |
| 33 | u32 clr_rising; |
| 34 | u32 set_falling; |
| 35 | u32 clr_falling; |
| 36 | u32 intstat; |
| 37 | }; |
| 38 | |
Philip Avinash | 131a10a | 2013-08-18 10:48:57 +0530 | [diff] [blame] | 39 | #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ |
| 40 | |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 41 | #define chip2controller(chip) \ |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 42 | container_of(chip, struct davinci_gpio_controller, chip) |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 43 | |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 44 | static void __iomem *gpio_base; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 45 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 46 | static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 47 | { |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 48 | void __iomem *ptr; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 49 | |
| 50 | if (gpio < 32 * 1) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 51 | ptr = gpio_base + 0x10; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 52 | else if (gpio < 32 * 2) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 53 | ptr = gpio_base + 0x38; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 54 | else if (gpio < 32 * 3) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 55 | ptr = gpio_base + 0x60; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 56 | else if (gpio < 32 * 4) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 57 | ptr = gpio_base + 0x88; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 58 | else if (gpio < 32 * 5) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 59 | ptr = gpio_base + 0xb0; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 60 | else |
| 61 | ptr = NULL; |
| 62 | return ptr; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 63 | } |
| 64 | |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 65 | static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) |
Kevin Hilman | 21ce873 | 2010-02-25 16:49:56 -0800 | [diff] [blame] | 66 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 67 | struct davinci_gpio_regs __iomem *g; |
Kevin Hilman | 21ce873 | 2010-02-25 16:49:56 -0800 | [diff] [blame] | 68 | |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 69 | g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); |
Kevin Hilman | 21ce873 | 2010-02-25 16:49:56 -0800 | [diff] [blame] | 70 | |
| 71 | return g; |
| 72 | } |
| 73 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 74 | static int davinci_gpio_irq_setup(struct platform_device *pdev); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 75 | |
| 76 | /*--------------------------------------------------------------------------*/ |
| 77 | |
Cyril Chemparathy | 5b3a05c | 2010-05-01 18:38:27 -0400 | [diff] [blame] | 78 | /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 79 | static inline int __davinci_direction(struct gpio_chip *chip, |
| 80 | unsigned offset, bool out, int value) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 81 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 82 | struct davinci_gpio_controller *d = chip2controller(chip); |
| 83 | struct davinci_gpio_regs __iomem *g = d->regs; |
Cyril Chemparathy | b27b6d0 | 2010-05-01 18:37:55 -0400 | [diff] [blame] | 84 | unsigned long flags; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 85 | u32 temp; |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 86 | u32 mask = 1 << offset; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 87 | |
Cyril Chemparathy | b27b6d0 | 2010-05-01 18:37:55 -0400 | [diff] [blame] | 88 | spin_lock_irqsave(&d->lock, flags); |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 89 | temp = readl_relaxed(&g->dir); |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 90 | if (out) { |
| 91 | temp &= ~mask; |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 92 | writel_relaxed(mask, value ? &g->set_data : &g->clr_data); |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 93 | } else { |
| 94 | temp |= mask; |
| 95 | } |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 96 | writel_relaxed(temp, &g->dir); |
Cyril Chemparathy | b27b6d0 | 2010-05-01 18:37:55 -0400 | [diff] [blame] | 97 | spin_unlock_irqrestore(&d->lock, flags); |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 98 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 99 | return 0; |
| 100 | } |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 101 | |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 102 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
| 103 | { |
| 104 | return __davinci_direction(chip, offset, false, 0); |
| 105 | } |
| 106 | |
| 107 | static int |
| 108 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) |
| 109 | { |
| 110 | return __davinci_direction(chip, offset, true, value); |
| 111 | } |
| 112 | |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 113 | /* |
| 114 | * Read the pin's value (works even if it's set up as output); |
| 115 | * returns zero/nonzero. |
| 116 | * |
| 117 | * Note that changes are synched to the GPIO clock, so reading values back |
| 118 | * right after you've set them may give old values. |
| 119 | */ |
| 120 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 121 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 122 | struct davinci_gpio_controller *d = chip2controller(chip); |
| 123 | struct davinci_gpio_regs __iomem *g = d->regs; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 124 | |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 125 | return (1 << offset) & readl_relaxed(&g->in_data); |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 126 | } |
| 127 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 128 | /* |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 129 | * Assuming the pin is muxed as a gpio output, set its output value. |
| 130 | */ |
| 131 | static void |
| 132 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 133 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 134 | struct davinci_gpio_controller *d = chip2controller(chip); |
| 135 | struct davinci_gpio_regs __iomem *g = d->regs; |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 136 | |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 137 | writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data); |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 138 | } |
| 139 | |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame^] | 140 | static struct davinci_gpio_platform_data * |
| 141 | davinci_gpio_get_pdata(struct platform_device *pdev) |
| 142 | { |
| 143 | struct device_node *dn = pdev->dev.of_node; |
| 144 | struct davinci_gpio_platform_data *pdata; |
| 145 | int ret; |
| 146 | u32 val; |
| 147 | |
| 148 | if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) |
| 149 | return pdev->dev.platform_data; |
| 150 | |
| 151 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
| 152 | if (!pdata) |
| 153 | return NULL; |
| 154 | |
| 155 | ret = of_property_read_u32(dn, "ti,ngpio", &val); |
| 156 | if (ret) |
| 157 | goto of_err; |
| 158 | |
| 159 | pdata->ngpio = val; |
| 160 | |
| 161 | ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); |
| 162 | if (ret) |
| 163 | goto of_err; |
| 164 | |
| 165 | pdata->gpio_unbanked = val; |
| 166 | |
| 167 | return pdata; |
| 168 | |
| 169 | of_err: |
| 170 | dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); |
| 171 | return NULL; |
| 172 | } |
| 173 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 174 | static int davinci_gpio_probe(struct platform_device *pdev) |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 175 | { |
| 176 | int i, base; |
Mark A. Greer | a994955 | 2009-04-15 12:40:35 -0700 | [diff] [blame] | 177 | unsigned ngpio; |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 178 | struct davinci_gpio_controller *chips; |
| 179 | struct davinci_gpio_platform_data *pdata; |
| 180 | struct davinci_gpio_regs __iomem *regs; |
| 181 | struct device *dev = &pdev->dev; |
| 182 | struct resource *res; |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 183 | |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame^] | 184 | pdata = davinci_gpio_get_pdata(pdev); |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 185 | if (!pdata) { |
| 186 | dev_err(dev, "No platform data found\n"); |
| 187 | return -EINVAL; |
| 188 | } |
Cyril Chemparathy | 686b634 | 2010-05-01 18:37:54 -0400 | [diff] [blame] | 189 | |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame^] | 190 | dev->platform_data = pdata; |
| 191 | |
Mark A. Greer | a994955 | 2009-04-15 12:40:35 -0700 | [diff] [blame] | 192 | /* |
| 193 | * The gpio banks conceptually expose a segmented bitmap, |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 194 | * and "ngpio" is one more than the largest zero-based |
| 195 | * bit index that's valid. |
| 196 | */ |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 197 | ngpio = pdata->ngpio; |
Mark A. Greer | a994955 | 2009-04-15 12:40:35 -0700 | [diff] [blame] | 198 | if (ngpio == 0) { |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 199 | dev_err(dev, "How many GPIOs?\n"); |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 200 | return -EINVAL; |
| 201 | } |
| 202 | |
Grygorii Strashko | c21d500 | 2013-11-21 17:34:35 +0200 | [diff] [blame] | 203 | if (WARN_ON(ARCH_NR_GPIOS < ngpio)) |
| 204 | ngpio = ARCH_NR_GPIOS; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 205 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 206 | chips = devm_kzalloc(dev, |
| 207 | ngpio * sizeof(struct davinci_gpio_controller), |
| 208 | GFP_KERNEL); |
| 209 | if (!chips) { |
| 210 | dev_err(dev, "Memory allocation failed\n"); |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 211 | return -ENOMEM; |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 215 | if (!res) { |
| 216 | dev_err(dev, "Invalid memory resource\n"); |
| 217 | return -EBUSY; |
| 218 | } |
| 219 | |
| 220 | gpio_base = devm_ioremap_resource(dev, res); |
| 221 | if (IS_ERR(gpio_base)) |
| 222 | return PTR_ERR(gpio_base); |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 223 | |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 224 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 225 | chips[i].chip.label = "DaVinci"; |
| 226 | |
| 227 | chips[i].chip.direction_input = davinci_direction_in; |
| 228 | chips[i].chip.get = davinci_gpio_get; |
| 229 | chips[i].chip.direction_output = davinci_direction_out; |
| 230 | chips[i].chip.set = davinci_gpio_set; |
| 231 | |
| 232 | chips[i].chip.base = base; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 233 | chips[i].chip.ngpio = ngpio - base; |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 234 | if (chips[i].chip.ngpio > 32) |
| 235 | chips[i].chip.ngpio = 32; |
| 236 | |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame^] | 237 | #ifdef CONFIG_OF_GPIO |
| 238 | chips[i].chip.of_node = dev->of_node; |
| 239 | #endif |
Cyril Chemparathy | b27b6d0 | 2010-05-01 18:37:55 -0400 | [diff] [blame] | 240 | spin_lock_init(&chips[i].lock); |
| 241 | |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 242 | regs = gpio2regs(base); |
| 243 | chips[i].regs = regs; |
| 244 | chips[i].set_data = ®s->set_data; |
| 245 | chips[i].clr_data = ®s->clr_data; |
| 246 | chips[i].in_data = ®s->in_data; |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 247 | |
| 248 | gpiochip_add(&chips[i].chip); |
| 249 | } |
| 250 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 251 | platform_set_drvdata(pdev, chips); |
| 252 | davinci_gpio_irq_setup(pdev); |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 253 | return 0; |
| 254 | } |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 255 | |
| 256 | /*--------------------------------------------------------------------------*/ |
| 257 | /* |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 258 | * We expect irqs will normally be set up as input pins, but they can also be |
| 259 | * used as output pins ... which is convenient for testing. |
| 260 | * |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 261 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 262 | * to their GPIOBNK0 irq, with a bit less overhead. |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 263 | * |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 264 | * All those INTC hookups (direct, plus several IRQ banks) can also |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 265 | * serve as EDMA event triggers. |
| 266 | */ |
| 267 | |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 268 | static void gpio_irq_disable(struct irq_data *d) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 269 | { |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 270 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 271 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 272 | |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 273 | writel_relaxed(mask, &g->clr_falling); |
| 274 | writel_relaxed(mask, &g->clr_rising); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 275 | } |
| 276 | |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 277 | static void gpio_irq_enable(struct irq_data *d) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 278 | { |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 279 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 280 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
Thomas Gleixner | 5093aec | 2011-03-24 12:47:04 +0100 | [diff] [blame] | 281 | unsigned status = irqd_get_trigger_type(d); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 282 | |
David Brownell | df4aab4 | 2009-05-04 13:14:27 -0700 | [diff] [blame] | 283 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
| 284 | if (!status) |
| 285 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
| 286 | |
| 287 | if (status & IRQ_TYPE_EDGE_FALLING) |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 288 | writel_relaxed(mask, &g->set_falling); |
David Brownell | df4aab4 | 2009-05-04 13:14:27 -0700 | [diff] [blame] | 289 | if (status & IRQ_TYPE_EDGE_RISING) |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 290 | writel_relaxed(mask, &g->set_rising); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 291 | } |
| 292 | |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 293 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 294 | { |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 295 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
| 296 | return -EINVAL; |
| 297 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 298 | return 0; |
| 299 | } |
| 300 | |
| 301 | static struct irq_chip gpio_irqchip = { |
| 302 | .name = "GPIO", |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 303 | .irq_enable = gpio_irq_enable, |
| 304 | .irq_disable = gpio_irq_disable, |
| 305 | .irq_set_type = gpio_irq_type, |
Thomas Gleixner | 5093aec | 2011-03-24 12:47:04 +0100 | [diff] [blame] | 306 | .flags = IRQCHIP_SET_TYPE_MASKED, |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 307 | }; |
| 308 | |
| 309 | static void |
| 310 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
| 311 | { |
Thomas Gleixner | 7416401 | 2011-06-06 11:51:43 +0200 | [diff] [blame] | 312 | struct davinci_gpio_regs __iomem *g; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 313 | u32 mask = 0xffff; |
Ido Yariv | f299bb9 | 2011-07-12 00:03:11 +0300 | [diff] [blame] | 314 | struct davinci_gpio_controller *d; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 315 | |
Ido Yariv | f299bb9 | 2011-07-12 00:03:11 +0300 | [diff] [blame] | 316 | d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc); |
| 317 | g = (struct davinci_gpio_regs __iomem *)d->regs; |
Thomas Gleixner | 7416401 | 2011-06-06 11:51:43 +0200 | [diff] [blame] | 318 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 319 | /* we only care about one bank */ |
| 320 | if (irq & 1) |
| 321 | mask <<= 16; |
| 322 | |
| 323 | /* temporarily mask (level sensitive) parent IRQ */ |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 324 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
| 325 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 326 | while (1) { |
| 327 | u32 status; |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 328 | int bit; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 329 | |
| 330 | /* ack any irqs */ |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 331 | status = readl_relaxed(&g->intstat) & mask; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 332 | if (!status) |
| 333 | break; |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 334 | writel_relaxed(status, &g->intstat); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 335 | |
| 336 | /* now demux them to the right lowlevel handler */ |
Ido Yariv | f299bb9 | 2011-07-12 00:03:11 +0300 | [diff] [blame] | 337 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 338 | while (status) { |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 339 | bit = __ffs(status); |
| 340 | status &= ~BIT(bit); |
| 341 | generic_handle_irq( |
| 342 | irq_find_mapping(d->irq_domain, |
| 343 | d->chip.base + bit)); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 344 | } |
| 345 | } |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 346 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 347 | /* now it may re-trigger */ |
| 348 | } |
| 349 | |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 350 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
| 351 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 352 | struct davinci_gpio_controller *d = chip2controller(chip); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 353 | |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 354 | return irq_create_mapping(d->irq_domain, d->chip.base + offset); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 355 | } |
| 356 | |
| 357 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) |
| 358 | { |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 359 | struct davinci_gpio_controller *d = chip2controller(chip); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 360 | |
Philip Avinash | 131a10a | 2013-08-18 10:48:57 +0530 | [diff] [blame] | 361 | /* |
| 362 | * NOTE: we assume for now that only irqs in the first gpio_chip |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 363 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). |
| 364 | */ |
Lad, Prabhakar | 34af1ab | 2013-11-08 12:15:55 +0530 | [diff] [blame] | 365 | if (offset < d->gpio_unbanked) |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 366 | return d->gpio_irq + offset; |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 367 | else |
| 368 | return -ENODEV; |
| 369 | } |
| 370 | |
Sekhar Nori | ab2dde9 | 2012-03-11 18:16:11 +0530 | [diff] [blame] | 371 | static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 372 | { |
Sekhar Nori | ab2dde9 | 2012-03-11 18:16:11 +0530 | [diff] [blame] | 373 | struct davinci_gpio_controller *d; |
| 374 | struct davinci_gpio_regs __iomem *g; |
Sekhar Nori | ab2dde9 | 2012-03-11 18:16:11 +0530 | [diff] [blame] | 375 | u32 mask; |
| 376 | |
| 377 | d = (struct davinci_gpio_controller *)data->handler_data; |
| 378 | g = (struct davinci_gpio_regs __iomem *)d->regs; |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 379 | mask = __gpio_mask(data->irq - d->gpio_irq); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 380 | |
| 381 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
| 382 | return -EINVAL; |
| 383 | |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 384 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 385 | ? &g->set_falling : &g->clr_falling); |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 386 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 387 | ? &g->set_rising : &g->clr_rising); |
| 388 | |
| 389 | return 0; |
| 390 | } |
| 391 | |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 392 | static int |
| 393 | davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, |
| 394 | irq_hw_number_t hw) |
| 395 | { |
| 396 | struct davinci_gpio_regs __iomem *g = gpio2regs(hw); |
| 397 | |
| 398 | irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, |
| 399 | "davinci_gpio"); |
| 400 | irq_set_irq_type(irq, IRQ_TYPE_NONE); |
| 401 | irq_set_chip_data(irq, (__force void *)g); |
| 402 | irq_set_handler_data(irq, (void *)__gpio_mask(hw)); |
| 403 | set_irq_flags(irq, IRQF_VALID); |
| 404 | |
| 405 | return 0; |
| 406 | } |
| 407 | |
| 408 | static const struct irq_domain_ops davinci_gpio_irq_ops = { |
| 409 | .map = davinci_gpio_irq_map, |
| 410 | .xlate = irq_domain_xlate_onetwocell, |
| 411 | }; |
| 412 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 413 | /* |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 414 | * NOTE: for suspend/resume, probably best to make a platform_device with |
| 415 | * suspend_late/resume_resume calls hooking into results of the set_wake() |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 416 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
| 417 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 418 | * (dm6446) can be set appropriately for GPIOV33 pins. |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 419 | */ |
| 420 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 421 | static int davinci_gpio_irq_setup(struct platform_device *pdev) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 422 | { |
| 423 | unsigned gpio, irq, bank; |
| 424 | struct clk *clk; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 425 | u32 binten = 0; |
Mark A. Greer | a994955 | 2009-04-15 12:40:35 -0700 | [diff] [blame] | 426 | unsigned ngpio, bank_irq; |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 427 | struct device *dev = &pdev->dev; |
| 428 | struct resource *res; |
| 429 | struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); |
| 430 | struct davinci_gpio_platform_data *pdata = dev->platform_data; |
| 431 | struct davinci_gpio_regs __iomem *g; |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 432 | struct irq_domain *irq_domain; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 433 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 434 | ngpio = pdata->ngpio; |
| 435 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 436 | if (!res) { |
| 437 | dev_err(dev, "Invalid IRQ resource\n"); |
| 438 | return -EBUSY; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 439 | } |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 440 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 441 | bank_irq = res->start; |
| 442 | |
| 443 | if (!bank_irq) { |
| 444 | dev_err(dev, "Invalid IRQ resource\n"); |
| 445 | return -ENODEV; |
| 446 | } |
| 447 | |
| 448 | clk = devm_clk_get(dev, "gpio"); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 449 | if (IS_ERR(clk)) { |
| 450 | printk(KERN_ERR "Error %ld getting gpio clock?\n", |
| 451 | PTR_ERR(clk)); |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 452 | return PTR_ERR(clk); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 453 | } |
Murali Karicheri | ce6b658 | 2012-08-30 14:03:57 -0400 | [diff] [blame] | 454 | clk_prepare_enable(clk); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 455 | |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 456 | irq = irq_alloc_descs(-1, 0, ngpio, 0); |
| 457 | if (irq < 0) { |
| 458 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); |
| 459 | return irq; |
| 460 | } |
| 461 | |
| 462 | irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0, |
| 463 | &davinci_gpio_irq_ops, |
| 464 | chips); |
| 465 | if (!irq_domain) { |
| 466 | dev_err(dev, "Couldn't register an IRQ domain\n"); |
| 467 | return -ENODEV; |
| 468 | } |
| 469 | |
Philip Avinash | 131a10a | 2013-08-18 10:48:57 +0530 | [diff] [blame] | 470 | /* |
| 471 | * Arrange gpio_to_irq() support, handling either direct IRQs or |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 472 | * banked IRQs. Having GPIOs in the first GPIO bank use direct |
| 473 | * IRQs, while the others use banked IRQs, would need some setup |
| 474 | * tweaks to recognize hardware which can do that. |
| 475 | */ |
| 476 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { |
| 477 | chips[bank].chip.to_irq = gpio_to_irq_banked; |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 478 | if (!pdata->gpio_unbanked) |
| 479 | chips[bank].irq_domain = irq_domain; |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 480 | } |
| 481 | |
| 482 | /* |
| 483 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO |
| 484 | * controller only handling trigger modes. We currently assume no |
| 485 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. |
| 486 | */ |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 487 | if (pdata->gpio_unbanked) { |
Sekhar Nori | 81b279d | 2012-03-11 18:16:12 +0530 | [diff] [blame] | 488 | static struct irq_chip_type gpio_unbanked; |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 489 | |
| 490 | /* pass "bank 0" GPIO IRQs to AINTC */ |
| 491 | chips[0].chip.to_irq = gpio_to_irq_unbanked; |
Lad, Prabhakar | 34af1ab | 2013-11-08 12:15:55 +0530 | [diff] [blame] | 492 | chips[0].gpio_irq = bank_irq; |
| 493 | chips[0].gpio_unbanked = pdata->gpio_unbanked; |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 494 | binten = BIT(0); |
| 495 | |
| 496 | /* AINTC handles mask/unmask; GPIO handles triggering */ |
| 497 | irq = bank_irq; |
Sekhar Nori | 81b279d | 2012-03-11 18:16:12 +0530 | [diff] [blame] | 498 | gpio_unbanked = *container_of(irq_get_chip(irq), |
| 499 | struct irq_chip_type, chip); |
| 500 | gpio_unbanked.chip.name = "GPIO-AINTC"; |
| 501 | gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked; |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 502 | |
| 503 | /* default trigger: both edges */ |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 504 | g = gpio2regs(0); |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 505 | writel_relaxed(~0, &g->set_falling); |
| 506 | writel_relaxed(~0, &g->set_rising); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 507 | |
| 508 | /* set the direct IRQs up to use that irqchip */ |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 509 | for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { |
Sekhar Nori | 81b279d | 2012-03-11 18:16:12 +0530 | [diff] [blame] | 510 | irq_set_chip(irq, &gpio_unbanked.chip); |
Sekhar Nori | ab2dde9 | 2012-03-11 18:16:11 +0530 | [diff] [blame] | 511 | irq_set_handler_data(irq, &chips[gpio / 32]); |
Thomas Gleixner | 5093aec | 2011-03-24 12:47:04 +0100 | [diff] [blame] | 512 | irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 513 | } |
| 514 | |
| 515 | goto done; |
| 516 | } |
| 517 | |
| 518 | /* |
| 519 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we |
| 520 | * then chain through our own handler. |
| 521 | */ |
Lad, Prabhakar | 9211ff3 | 2013-11-21 23:45:27 +0530 | [diff] [blame] | 522 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) { |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 523 | /* disabled by default, enabled only as needed */ |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 524 | g = gpio2regs(gpio); |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 525 | writel_relaxed(~0, &g->clr_falling); |
| 526 | writel_relaxed(~0, &g->clr_rising); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 527 | |
| 528 | /* set up all irqs in this bank */ |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 529 | irq_set_chained_handler(bank_irq, gpio_irq_handler); |
Ido Yariv | f299bb9 | 2011-07-12 00:03:11 +0300 | [diff] [blame] | 530 | |
| 531 | /* |
| 532 | * Each chip handles 32 gpios, and each irq bank consists of 16 |
| 533 | * gpio irqs. Pass the irq bank's corresponding controller to |
| 534 | * the chained irq handler. |
| 535 | */ |
| 536 | irq_set_handler_data(bank_irq, &chips[gpio / 32]); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 537 | |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 538 | binten |= BIT(bank); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 539 | } |
| 540 | |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 541 | done: |
Philip Avinash | 131a10a | 2013-08-18 10:48:57 +0530 | [diff] [blame] | 542 | /* |
| 543 | * BINTEN -- per-bank interrupt enable. genirq would also let these |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 544 | * bits be set/cleared dynamically. |
| 545 | */ |
Lad, Prabhakar | 388291c | 2013-12-11 23:22:07 +0530 | [diff] [blame] | 546 | writel_relaxed(binten, gpio_base + BINTEN); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 547 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 548 | return 0; |
| 549 | } |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 550 | |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame^] | 551 | #if IS_ENABLED(CONFIG_OF) |
| 552 | static const struct of_device_id davinci_gpio_ids[] = { |
| 553 | { .compatible = "ti,dm6441-gpio", }, |
| 554 | { /* sentinel */ }, |
| 555 | }; |
| 556 | MODULE_DEVICE_TABLE(of, davinci_gpio_ids); |
| 557 | #endif |
| 558 | |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 559 | static struct platform_driver davinci_gpio_driver = { |
| 560 | .probe = davinci_gpio_probe, |
| 561 | .driver = { |
KV Sujith | c770844 | 2013-11-21 23:45:29 +0530 | [diff] [blame^] | 562 | .name = "davinci_gpio", |
| 563 | .owner = THIS_MODULE, |
| 564 | .of_match_table = of_match_ptr(davinci_gpio_ids), |
KV Sujith | 118150f | 2013-08-18 10:48:58 +0530 | [diff] [blame] | 565 | }, |
| 566 | }; |
| 567 | |
| 568 | /** |
| 569 | * GPIO driver registration needs to be done before machine_init functions |
| 570 | * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. |
| 571 | */ |
| 572 | static int __init davinci_gpio_drv_reg(void) |
| 573 | { |
| 574 | return platform_driver_register(&davinci_gpio_driver); |
| 575 | } |
| 576 | postcore_initcall(davinci_gpio_drv_reg); |