Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 0ecdf00ba6e50eaa452356d0d4e79657dab702a4 / . / drivers / scsi / pm8001 / pm80xx_hwi.c
blob: 37ddc5dda7bbf729d7870789609df06c422059d2 [file] [log] [blame]
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1/*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46#define SMP_DIRECT 1
47#define SMP_INDIRECT 2
48/**
49 * read_main_config_table - read the configure table and save it.
50 * @pm8001_ha: our hba card information
51 */
52static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
53{
54 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
55
56 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
57 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
58 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
59 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
60 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
61 pm8001_mr32(address, MAIN_FW_REVISION);
62 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
63 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
64 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
65 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
66 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
67 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
68 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
69 pm8001_mr32(address, MAIN_GST_OFFSET);
70 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
71 pm8001_mr32(address, MAIN_IBQ_OFFSET);
72 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
73 pm8001_mr32(address, MAIN_OBQ_OFFSET);
74
75 /* read Error Dump Offset and Length */
76 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
77 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
78 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
79 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
80 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
81 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
82 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
83 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
84
85 /* read GPIO LED settings from the configuration table */
86 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
87 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
88
89 /* read analog Setting offset from the configuration table */
90 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
91 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
92
93 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
94 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
95 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
96 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
97}
98
99/**
100 * read_general_status_table - read the general status table and save it.
101 * @pm8001_ha: our hba card information
102 */
103static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
104{
105 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
106 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
107 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
108 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
109 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
110 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
111 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
112 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
113 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
114 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
115 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
116 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
117 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
118 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
119 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
120 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
121 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
122 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
123 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
124 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
125 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
126 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
127 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
128 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
129 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
130 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
131 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
132 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
133 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
134}
135/**
136 * read_phy_attr_table - read the phy attribute table and save it.
137 * @pm8001_ha: our hba card information
138 */
139static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
140{
141 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
142 pm8001_ha->phy_attr_table.phystart1_16[0] =
143 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
144 pm8001_ha->phy_attr_table.phystart1_16[1] =
145 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
146 pm8001_ha->phy_attr_table.phystart1_16[2] =
147 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
148 pm8001_ha->phy_attr_table.phystart1_16[3] =
149 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
150 pm8001_ha->phy_attr_table.phystart1_16[4] =
151 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
152 pm8001_ha->phy_attr_table.phystart1_16[5] =
153 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
154 pm8001_ha->phy_attr_table.phystart1_16[6] =
155 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
156 pm8001_ha->phy_attr_table.phystart1_16[7] =
157 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
158 pm8001_ha->phy_attr_table.phystart1_16[8] =
159 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
160 pm8001_ha->phy_attr_table.phystart1_16[9] =
161 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
162 pm8001_ha->phy_attr_table.phystart1_16[10] =
163 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
164 pm8001_ha->phy_attr_table.phystart1_16[11] =
165 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
166 pm8001_ha->phy_attr_table.phystart1_16[12] =
167 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
168 pm8001_ha->phy_attr_table.phystart1_16[13] =
169 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
170 pm8001_ha->phy_attr_table.phystart1_16[14] =
171 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
172 pm8001_ha->phy_attr_table.phystart1_16[15] =
173 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
174
175 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
176 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
177 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
178 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
179 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
180 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
181 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
182 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
183 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
184 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
185 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
186 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
187 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
188 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
189 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
190 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
191 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
192 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
193 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
194 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
195 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
196 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
197 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
198 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
199 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
200 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
201 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
202 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
203 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
204 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
205 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
206 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
207
208}
209
210/**
211 * read_inbnd_queue_table - read the inbound queue table and save it.
212 * @pm8001_ha: our hba card information
213 */
214static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
215{
216 int i;
217 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
218 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
219 u32 offset = i * 0x20;
220 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
221 get_pci_bar_index(pm8001_mr32(address,
222 (offset + IB_PIPCI_BAR)));
223 pm8001_ha->inbnd_q_tbl[i].pi_offset =
224 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
225 }
226}
227
228/**
229 * read_outbnd_queue_table - read the outbound queue table and save it.
230 * @pm8001_ha: our hba card information
231 */
232static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
233{
234 int i;
235 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
236 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
237 u32 offset = i * 0x24;
238 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
239 get_pci_bar_index(pm8001_mr32(address,
240 (offset + OB_CIPCI_BAR)));
241 pm8001_ha->outbnd_q_tbl[i].ci_offset =
242 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
243 }
244}
245
246/**
247 * init_default_table_values - init the default table.
248 * @pm8001_ha: our hba card information
249 */
250static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
251{
252 int i;
253 u32 offsetib, offsetob;
254 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
255 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
256
257 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
258 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
259 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
260 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
261 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
262 PM8001_EVENT_LOG_SIZE;
263 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
264 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
265 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
266 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
267 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
268 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
269 PM8001_EVENT_LOG_SIZE;
270 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
271 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
272
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]273 /* Disable end to end CRC checking */
274 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
275
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]276 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
277 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
Hans Verkuil9504a922013-07-26 18:43:45 +0200[diff] [blame]278 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]279 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
280 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
281 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
282 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
283 pm8001_ha->inbnd_q_tbl[i].base_virt =
284 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
285 pm8001_ha->inbnd_q_tbl[i].total_length =
286 pm8001_ha->memoryMap.region[IB + i].total_len;
287 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
288 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
289 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
290 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
291 pm8001_ha->inbnd_q_tbl[i].ci_virt =
292 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
293 offsetib = i * 0x20;
294 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
295 get_pci_bar_index(pm8001_mr32(addressib,
296 (offsetib + 0x14)));
297 pm8001_ha->inbnd_q_tbl[i].pi_offset =
298 pm8001_mr32(addressib, (offsetib + 0x18));
299 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
300 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
301 }
302 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
303 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
Hans Verkuil9504a922013-07-26 18:43:45 +0200[diff] [blame]304 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]305 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
306 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
307 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
308 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
309 pm8001_ha->outbnd_q_tbl[i].base_virt =
310 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
311 pm8001_ha->outbnd_q_tbl[i].total_length =
312 pm8001_ha->memoryMap.region[OB + i].total_len;
313 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
314 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
315 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
316 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
317 /* interrupt vector based on oq */
318 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
319 pm8001_ha->outbnd_q_tbl[i].pi_virt =
320 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
321 offsetob = i * 0x24;
322 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
323 get_pci_bar_index(pm8001_mr32(addressob,
324 offsetob + 0x14));
325 pm8001_ha->outbnd_q_tbl[i].ci_offset =
326 pm8001_mr32(addressob, (offsetob + 0x18));
327 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
328 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
329 }
330}
331
332/**
333 * update_main_config_table - update the main default table to the HBA.
334 * @pm8001_ha: our hba card information
335 */
336static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
337{
338 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
339 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
340 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
341 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
342 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
343 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
344 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
345 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
346 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
347 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
348 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
349 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
350 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
351 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
352 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
353 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
354 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
355 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
356 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
357 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
358 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]359 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
360 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]361
362 /* SPCv specific */
363 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
364 /* Set GPIOLED to 0x2 for LED indicator */
365 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
366 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
367 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
368
369 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
370 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
371 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
372 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
373}
374
375/**
376 * update_inbnd_queue_table - update the inbound queue table to the HBA.
377 * @pm8001_ha: our hba card information
378 */
379static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
380 int number)
381{
382 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
383 u16 offset = number * 0x20;
384 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
385 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
386 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
387 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
388 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
389 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
390 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
391 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
392 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
393 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
394}
395
396/**
397 * update_outbnd_queue_table - update the outbound queue table to the HBA.
398 * @pm8001_ha: our hba card information
399 */
400static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
401 int number)
402{
403 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
404 u16 offset = number * 0x24;
405 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
406 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
407 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
408 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
409 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
410 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
411 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
412 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
413 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
414 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
415 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
416 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
417}
418
419/**
420 * mpi_init_check - check firmware initialization status.
421 * @pm8001_ha: our hba card information
422 */
423static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
424{
425 u32 max_wait_count;
426 u32 value;
427 u32 gst_len_mpistate;
428
429 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
430 table is updated */
431 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
432 /* wait until Inbound DoorBell Clear Register toggled */
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]433 if (IS_SPCV_12G(pm8001_ha->pdev)) {
434 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
435 } else {
436 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
437 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]438 do {
439 udelay(1);
440 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
441 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
442 } while ((value != 0) && (--max_wait_count));
443
444 if (!max_wait_count)
445 return -1;
446 /* check the MPI-State for initialization upto 100ms*/
447 max_wait_count = 100 * 1000;/* 100 msec */
448 do {
449 udelay(1);
450 gst_len_mpistate =
451 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
452 GST_GSTLEN_MPIS_OFFSET);
453 } while ((GST_MPI_STATE_INIT !=
454 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
455 if (!max_wait_count)
456 return -1;
457
458 /* check MPI Initialization error */
459 gst_len_mpistate = gst_len_mpistate >> 16;
460 if (0x0000 != gst_len_mpistate)
461 return -1;
462
463 return 0;
464}
465
466/**
467 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
468 * @pm8001_ha: our hba card information
469 */
470static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
471{
472 u32 value;
473 u32 max_wait_count;
474 u32 max_wait_time;
475 int ret = 0;
476
477 /* reset / PCIe ready */
478 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
479 do {
480 udelay(1);
481 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
482 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
483
484 /* check ila status */
485 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
486 do {
487 udelay(1);
488 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
489 } while (((value & SCRATCH_PAD_ILA_READY) !=
490 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
491 if (!max_wait_count)
492 ret = -1;
493 else {
494 PM8001_MSG_DBG(pm8001_ha,
495 pm8001_printk(" ila ready status in %d millisec\n",
496 (max_wait_time - max_wait_count)));
497 }
498
499 /* check RAAE status */
500 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
501 do {
502 udelay(1);
503 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
504 } while (((value & SCRATCH_PAD_RAAE_READY) !=
505 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
506 if (!max_wait_count)
507 ret = -1;
508 else {
509 PM8001_MSG_DBG(pm8001_ha,
510 pm8001_printk(" raae ready status in %d millisec\n",
511 (max_wait_time - max_wait_count)));
512 }
513
514 /* check iop0 status */
515 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
516 do {
517 udelay(1);
518 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
519 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
520 (--max_wait_count));
521 if (!max_wait_count)
522 ret = -1;
523 else {
524 PM8001_MSG_DBG(pm8001_ha,
525 pm8001_printk(" iop0 ready status in %d millisec\n",
526 (max_wait_time - max_wait_count)));
527 }
528
529 /* check iop1 status only for 16 port controllers */
530 if ((pm8001_ha->chip_id != chip_8008) &&
531 (pm8001_ha->chip_id != chip_8009)) {
532 /* 200 milli sec */
533 max_wait_time = max_wait_count = 200 * 1000;
534 do {
535 udelay(1);
536 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
537 } while (((value & SCRATCH_PAD_IOP1_READY) !=
538 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
539 if (!max_wait_count)
540 ret = -1;
541 else {
542 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
543 "iop1 ready status in %d millisec\n",
544 (max_wait_time - max_wait_count)));
545 }
546 }
547
548 return ret;
549}
550
551static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
552{
553 void __iomem *base_addr;
554 u32 value;
555 u32 offset;
556 u32 pcibar;
557 u32 pcilogic;
558
559 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
560 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
561
562 PM8001_INIT_DBG(pm8001_ha,
563 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
564 offset, value));
565 pcilogic = (value & 0xFC000000) >> 26;
566 pcibar = get_pci_bar_index(pcilogic);
567 PM8001_INIT_DBG(pm8001_ha,
568 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
569 pm8001_ha->main_cfg_tbl_addr = base_addr =
570 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
571 pm8001_ha->general_stat_tbl_addr =
572 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
573 0xFFFFFF);
574 pm8001_ha->inbnd_q_tbl_addr =
575 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
576 0xFFFFFF);
577 pm8001_ha->outbnd_q_tbl_addr =
578 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
579 0xFFFFFF);
580 pm8001_ha->ivt_tbl_addr =
581 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
582 0xFFFFFF);
583 pm8001_ha->pspa_q_tbl_addr =
584 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
585 0xFFFFFF);
586
587 PM8001_INIT_DBG(pm8001_ha,
588 pm8001_printk("GST OFFSET 0x%x\n",
589 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
590 PM8001_INIT_DBG(pm8001_ha,
591 pm8001_printk("INBND OFFSET 0x%x\n",
592 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
593 PM8001_INIT_DBG(pm8001_ha,
594 pm8001_printk("OBND OFFSET 0x%x\n",
595 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
596 PM8001_INIT_DBG(pm8001_ha,
597 pm8001_printk("IVT OFFSET 0x%x\n",
598 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
599 PM8001_INIT_DBG(pm8001_ha,
600 pm8001_printk("PSPA OFFSET 0x%x\n",
601 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
602 PM8001_INIT_DBG(pm8001_ha,
603 pm8001_printk("addr - main cfg %p general status %p\n",
604 pm8001_ha->main_cfg_tbl_addr,
605 pm8001_ha->general_stat_tbl_addr));
606 PM8001_INIT_DBG(pm8001_ha,
607 pm8001_printk("addr - inbnd %p obnd %p\n",
608 pm8001_ha->inbnd_q_tbl_addr,
609 pm8001_ha->outbnd_q_tbl_addr));
610 PM8001_INIT_DBG(pm8001_ha,
611 pm8001_printk("addr - pspa %p ivt %p\n",
612 pm8001_ha->pspa_q_tbl_addr,
613 pm8001_ha->ivt_tbl_addr));
614}
615
616/**
617 * pm80xx_set_thermal_config - support the thermal configuration
618 * @pm8001_ha: our hba card information.
619 */
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]620int
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]621pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
622{
623 struct set_ctrl_cfg_req payload;
624 struct inbound_queue_table *circularQ;
625 int rc;
626 u32 tag;
627 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
628
629 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
630 rc = pm8001_tag_alloc(pm8001_ha, &tag);
631 if (rc)
632 return -1;
633
634 circularQ = &pm8001_ha->inbnd_q_tbl[0];
635 payload.tag = cpu_to_le32(tag);
636 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
637 (THERMAL_ENABLE << 8) | THERMAL_OP_CODE;
638 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
639
640 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
641 return rc;
642
643}
644
645/**
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]646* pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
647* Timer configuration page
648* @pm8001_ha: our hba card information.
649*/
650static int
651pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
652{
653 struct set_ctrl_cfg_req payload;
654 struct inbound_queue_table *circularQ;
655 SASProtocolTimerConfig_t SASConfigPage;
656 int rc;
657 u32 tag;
658 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
659
660 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
661 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
662
663 rc = pm8001_tag_alloc(pm8001_ha, &tag);
664
665 if (rc)
666 return -1;
667
668 circularQ = &pm8001_ha->inbnd_q_tbl[0];
669 payload.tag = cpu_to_le32(tag);
670
671 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE;
672 SASConfigPage.MST_MSI = 3 << 15;
673 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO;
674 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) |
675 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
676 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME;
677
678 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
679 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
680
681
682 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) |
683 SAS_OPNRJT_RTRY_INTVL;
684 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16)
685 | SAS_COPNRJT_RTRY_TMO;
686 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16)
687 | SAS_COPNRJT_RTRY_THR;
688 SASConfigPage.MAX_AIP = SAS_MAX_AIP;
689
690 PM8001_INIT_DBG(pm8001_ha,
691 pm8001_printk("SASConfigPage.pageCode "
692 "0x%08x\n", SASConfigPage.pageCode));
693 PM8001_INIT_DBG(pm8001_ha,
694 pm8001_printk("SASConfigPage.MST_MSI "
695 " 0x%08x\n", SASConfigPage.MST_MSI));
696 PM8001_INIT_DBG(pm8001_ha,
697 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
698 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
699 PM8001_INIT_DBG(pm8001_ha,
700 pm8001_printk("SASConfigPage.STP_FRM_TMO "
701 " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
702 PM8001_INIT_DBG(pm8001_ha,
703 pm8001_printk("SASConfigPage.STP_IDLE_TMO "
704 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
705 PM8001_INIT_DBG(pm8001_ha,
706 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
707 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
708 PM8001_INIT_DBG(pm8001_ha,
709 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
710 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
711 PM8001_INIT_DBG(pm8001_ha,
712 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
713 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
714 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
715 " 0x%08x\n", SASConfigPage.MAX_AIP));
716
717 memcpy(&payload.cfg_pg, &SASConfigPage,
718 sizeof(SASProtocolTimerConfig_t));
719
720 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
721
722 return rc;
723}
724
725/**
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]726 * pm80xx_get_encrypt_info - Check for encryption
727 * @pm8001_ha: our hba card information.
728 */
729static int
730pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
731{
732 u32 scratch3_value;
733 int ret;
734
735 /* Read encryption status from SCRATCH PAD 3 */
736 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
737
738 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
739 SCRATCH_PAD3_ENC_READY) {
740 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
741 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
742 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
743 SCRATCH_PAD3_SMF_ENABLED)
744 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
745 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
746 SCRATCH_PAD3_SMA_ENABLED)
747 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
748 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
749 SCRATCH_PAD3_SMB_ENABLED)
750 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
751 pm8001_ha->encrypt_info.status = 0;
752 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
753 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
754 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
755 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
756 pm8001_ha->encrypt_info.sec_mode,
757 pm8001_ha->encrypt_info.status));
758 ret = 0;
759 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
760 SCRATCH_PAD3_ENC_DISABLED) {
761 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
762 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
763 scratch3_value));
764 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
765 pm8001_ha->encrypt_info.cipher_mode = 0;
766 pm8001_ha->encrypt_info.sec_mode = 0;
767 return 0;
768 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
769 SCRATCH_PAD3_ENC_DIS_ERR) {
770 pm8001_ha->encrypt_info.status =
771 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
772 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
773 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
774 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
775 SCRATCH_PAD3_SMF_ENABLED)
776 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
777 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
778 SCRATCH_PAD3_SMA_ENABLED)
779 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
780 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
781 SCRATCH_PAD3_SMB_ENABLED)
782 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
783 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
784 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
785 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
786 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
787 pm8001_ha->encrypt_info.sec_mode,
788 pm8001_ha->encrypt_info.status));
789 ret = -1;
790 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
791 SCRATCH_PAD3_ENC_ENA_ERR) {
792
793 pm8001_ha->encrypt_info.status =
794 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
795 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
796 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
797 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
798 SCRATCH_PAD3_SMF_ENABLED)
799 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
800 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
801 SCRATCH_PAD3_SMA_ENABLED)
802 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
803 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
804 SCRATCH_PAD3_SMB_ENABLED)
805 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
806
807 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
808 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
809 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
810 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
811 pm8001_ha->encrypt_info.sec_mode,
812 pm8001_ha->encrypt_info.status));
813 ret = -1;
814 }
815 return ret;
816}
817
818/**
819 * pm80xx_encrypt_update - update flash with encryption informtion
820 * @pm8001_ha: our hba card information.
821 */
822static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
823{
824 struct kek_mgmt_req payload;
825 struct inbound_queue_table *circularQ;
826 int rc;
827 u32 tag;
828 u32 opc = OPC_INB_KEK_MANAGEMENT;
829
830 memset(&payload, 0, sizeof(struct kek_mgmt_req));
831 rc = pm8001_tag_alloc(pm8001_ha, &tag);
832 if (rc)
833 return -1;
834
835 circularQ = &pm8001_ha->inbnd_q_tbl[0];
836 payload.tag = cpu_to_le32(tag);
837 /* Currently only one key is used. New KEK index is 1.
838 * Current KEK index is 1. Store KEK to NVRAM is 1.
839 */
840 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
841 KEK_MGMT_SUBOP_KEYCARDUPDATE);
842
843 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
844
845 return rc;
846}
847
848/**
849 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
850 * @pm8001_ha: our hba card information
851 */
852static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
853{
854 int ret;
855 u8 i = 0;
856
857 /* check the firmware status */
858 if (-1 == check_fw_ready(pm8001_ha)) {
859 PM8001_FAIL_DBG(pm8001_ha,
860 pm8001_printk("Firmware is not ready!\n"));
861 return -EBUSY;
862 }
863
864 /* Initialize pci space address eg: mpi offset */
865 init_pci_device_addresses(pm8001_ha);
866 init_default_table_values(pm8001_ha);
867 read_main_config_table(pm8001_ha);
868 read_general_status_table(pm8001_ha);
869 read_inbnd_queue_table(pm8001_ha);
870 read_outbnd_queue_table(pm8001_ha);
871 read_phy_attr_table(pm8001_ha);
872
873 /* update main config table ,inbound table and outbound table */
874 update_main_config_table(pm8001_ha);
875 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
876 update_inbnd_queue_table(pm8001_ha, i);
877 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
878 update_outbnd_queue_table(pm8001_ha, i);
879
880 /* notify firmware update finished and check initialization status */
881 if (0 == mpi_init_check(pm8001_ha)) {
882 PM8001_INIT_DBG(pm8001_ha,
883 pm8001_printk("MPI initialize successful!\n"));
884 } else
885 return -EBUSY;
886
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]887 /* send SAS protocol timer configuration page to FW */
888 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]889
890 /* Check for encryption */
891 if (pm8001_ha->chip->encrypt) {
892 PM8001_INIT_DBG(pm8001_ha,
893 pm8001_printk("Checking for encryption\n"));
894 ret = pm80xx_get_encrypt_info(pm8001_ha);
895 if (ret == -1) {
896 PM8001_INIT_DBG(pm8001_ha,
897 pm8001_printk("Encryption error !!\n"));
898 if (pm8001_ha->encrypt_info.status == 0x81) {
899 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
900 "Encryption enabled with error."
901 "Saving encryption key to flash\n"));
902 pm80xx_encrypt_update(pm8001_ha);
903 }
904 }
905 }
906 return 0;
907}
908
909static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
910{
911 u32 max_wait_count;
912 u32 value;
913 u32 gst_len_mpistate;
914 init_pci_device_addresses(pm8001_ha);
915 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
916 table is stop */
917 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
918
919 /* wait until Inbound DoorBell Clear Register toggled */
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]920 if (IS_SPCV_12G(pm8001_ha->pdev)) {
921 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
922 } else {
923 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
924 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]925 do {
926 udelay(1);
927 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
928 value &= SPCv_MSGU_CFG_TABLE_RESET;
929 } while ((value != 0) && (--max_wait_count));
930
931 if (!max_wait_count) {
932 PM8001_FAIL_DBG(pm8001_ha,
933 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
934 return -1;
935 }
936
937 /* check the MPI-State for termination in progress */
938 /* wait until Inbound DoorBell Clear Register toggled */
939 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
940 do {
941 udelay(1);
942 gst_len_mpistate =
943 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
944 GST_GSTLEN_MPIS_OFFSET);
945 if (GST_MPI_STATE_UNINIT ==
946 (gst_len_mpistate & GST_MPI_STATE_MASK))
947 break;
948 } while (--max_wait_count);
949 if (!max_wait_count) {
950 PM8001_FAIL_DBG(pm8001_ha,
951 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
952 gst_len_mpistate & GST_MPI_STATE_MASK));
953 return -1;
954 }
955
956 return 0;
957}
958
959/**
960 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
961 * the FW register status to the originated status.
962 * @pm8001_ha: our hba card information
963 */
964
965static int
966pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
967{
968 u32 regval;
969 u32 bootloader_state;
970
971 /* Check if MPI is in ready state to reset */
972 if (mpi_uninit_check(pm8001_ha) != 0) {
973 PM8001_FAIL_DBG(pm8001_ha,
974 pm8001_printk("MPI state is not ready\n"));
975 return -1;
976 }
977
978 /* checked for reset register normal state; 0x0 */
979 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
980 PM8001_INIT_DBG(pm8001_ha,
981 pm8001_printk("reset register before write : 0x%x\n", regval));
982
983 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
984 mdelay(500);
985
986 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
987 PM8001_INIT_DBG(pm8001_ha,
988 pm8001_printk("reset register after write 0x%x\n", regval));
989
990 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
991 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
992 PM8001_MSG_DBG(pm8001_ha,
993 pm8001_printk(" soft reset successful [regval: 0x%x]\n",
994 regval));
995 } else {
996 PM8001_MSG_DBG(pm8001_ha,
997 pm8001_printk(" soft reset failed [regval: 0x%x]\n",
998 regval));
999
1000 /* check bootloader is successfully executed or in HDA mode */
1001 bootloader_state =
1002 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1003 SCRATCH_PAD1_BOOTSTATE_MASK;
1004
1005 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1006 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1007 "Bootloader state - HDA mode SEEPROM\n"));
1008 } else if (bootloader_state ==
1009 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1010 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1011 "Bootloader state - HDA mode Bootstrap Pin\n"));
1012 } else if (bootloader_state ==
1013 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1014 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1015 "Bootloader state - HDA mode soft reset\n"));
1016 } else if (bootloader_state ==
1017 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1018 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1019 "Bootloader state-HDA mode critical error\n"));
1020 }
1021 return -EBUSY;
1022 }
1023
1024 /* check the firmware status after reset */
1025 if (-1 == check_fw_ready(pm8001_ha)) {
1026 PM8001_FAIL_DBG(pm8001_ha,
1027 pm8001_printk("Firmware is not ready!\n"));
1028 return -EBUSY;
1029 }
1030 PM8001_INIT_DBG(pm8001_ha,
1031 pm8001_printk("SPCv soft reset Complete\n"));
1032 return 0;
1033}
1034
1035static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1036{
1037 u32 i;
1038
1039 PM8001_INIT_DBG(pm8001_ha,
1040 pm8001_printk("chip reset start\n"));
1041
1042 /* do SPCv chip reset. */
1043 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1044 PM8001_INIT_DBG(pm8001_ha,
1045 pm8001_printk("SPC soft reset Complete\n"));
1046
1047 /* Check this ..whether delay is required or no */
1048 /* delay 10 usec */
1049 udelay(10);
1050
1051 /* wait for 20 msec until the firmware gets reloaded */
1052 i = 20;
1053 do {
1054 mdelay(1);
1055 } while ((--i) != 0);
1056
1057 PM8001_INIT_DBG(pm8001_ha,
1058 pm8001_printk("chip reset finished\n"));
1059}
1060
1061/**
1062 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1063 * @pm8001_ha: our hba card information
1064 */
1065static void
1066pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1067{
1068 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1069 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1070}
1071
1072/**
1073 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1074 * @pm8001_ha: our hba card information
1075 */
1076static void
1077pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1078{
1079 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1080}
1081
1082/**
1083 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1084 * @pm8001_ha: our hba card information
1085 */
1086static void
1087pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1088{
1089#ifdef PM8001_USE_MSIX
1090 u32 mask;
1091 mask = (u32)(1 << vec);
1092
1093 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1094 return;
1095#endif
1096 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1097
1098}
1099
1100/**
1101 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1102 * @pm8001_ha: our hba card information
1103 */
1104static void
1105pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1106{
1107#ifdef PM8001_USE_MSIX
1108 u32 mask;
1109 if (vec == 0xFF)
1110 mask = 0xFFFFFFFF;
1111 else
1112 mask = (u32)(1 << vec);
1113 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1114 return;
1115#endif
1116 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1117}
1118
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1119static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1120 struct pm8001_device *pm8001_ha_dev)
1121{
1122 int res;
1123 u32 ccb_tag;
1124 struct pm8001_ccb_info *ccb;
1125 struct sas_task *task = NULL;
1126 struct task_abort_req task_abort;
1127 struct inbound_queue_table *circularQ;
1128 u32 opc = OPC_INB_SATA_ABORT;
1129 int ret;
1130
1131 if (!pm8001_ha_dev) {
1132 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1133 return;
1134 }
1135
1136 task = sas_alloc_slow_task(GFP_ATOMIC);
1137
1138 if (!task) {
1139 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1140 "allocate task\n"));
1141 return;
1142 }
1143
1144 task->task_done = pm8001_task_done;
1145
1146 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1147 if (res)
1148 return;
1149
1150 ccb = &pm8001_ha->ccb_info[ccb_tag];
1151 ccb->device = pm8001_ha_dev;
1152 ccb->ccb_tag = ccb_tag;
1153 ccb->task = task;
1154
1155 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1156
1157 memset(&task_abort, 0, sizeof(task_abort));
1158 task_abort.abort_all = cpu_to_le32(1);
1159 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1160 task_abort.tag = cpu_to_le32(ccb_tag);
1161
1162 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1163
1164}
1165
1166static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1167 struct pm8001_device *pm8001_ha_dev)
1168{
1169 struct sata_start_req sata_cmd;
1170 int res;
1171 u32 ccb_tag;
1172 struct pm8001_ccb_info *ccb;
1173 struct sas_task *task = NULL;
1174 struct host_to_dev_fis fis;
1175 struct domain_device *dev;
1176 struct inbound_queue_table *circularQ;
1177 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1178
1179 task = sas_alloc_slow_task(GFP_ATOMIC);
1180
1181 if (!task) {
1182 PM8001_FAIL_DBG(pm8001_ha,
1183 pm8001_printk("cannot allocate task !!!\n"));
1184 return;
1185 }
1186 task->task_done = pm8001_task_done;
1187
1188 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1189 if (res) {
1190 PM8001_FAIL_DBG(pm8001_ha,
1191 pm8001_printk("cannot allocate tag !!!\n"));
1192 return;
1193 }
1194
1195 /* allocate domain device by ourselves as libsas
1196 * is not going to provide any
1197 */
1198 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1199 if (!dev) {
1200 PM8001_FAIL_DBG(pm8001_ha,
1201 pm8001_printk("Domain device cannot be allocated\n"));
1202 sas_free_task(task);
1203 return;
1204 } else {
1205 task->dev = dev;
1206 task->dev->lldd_dev = pm8001_ha_dev;
1207 }
1208
1209 ccb = &pm8001_ha->ccb_info[ccb_tag];
1210 ccb->device = pm8001_ha_dev;
1211 ccb->ccb_tag = ccb_tag;
1212 ccb->task = task;
1213 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1214 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1215
1216 memset(&sata_cmd, 0, sizeof(sata_cmd));
1217 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1218
1219 /* construct read log FIS */
1220 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1221 fis.fis_type = 0x27;
1222 fis.flags = 0x80;
1223 fis.command = ATA_CMD_READ_LOG_EXT;
1224 fis.lbal = 0x10;
1225 fis.sector_count = 0x1;
1226
1227 sata_cmd.tag = cpu_to_le32(ccb_tag);
1228 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1229 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1230 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1231
1232 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1233
1234}
1235
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1236/**
1237 * mpi_ssp_completion- process the event that FW response to the SSP request.
1238 * @pm8001_ha: our hba card information
1239 * @piomb: the message contents of this outbound message.
1240 *
1241 * When FW has completed a ssp request for example a IO request, after it has
1242 * filled the SG data with the data, it will trigger this event represent
1243 * that he has finished the job,please check the coresponding buffer.
1244 * So we will tell the caller who maybe waiting the result to tell upper layer
1245 * that the task has been finished.
1246 */
1247static void
1248mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1249{
1250 struct sas_task *t;
1251 struct pm8001_ccb_info *ccb;
1252 unsigned long flags;
1253 u32 status;
1254 u32 param;
1255 u32 tag;
1256 struct ssp_completion_resp *psspPayload;
1257 struct task_status_struct *ts;
1258 struct ssp_response_iu *iu;
1259 struct pm8001_device *pm8001_dev;
1260 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1261 status = le32_to_cpu(psspPayload->status);
1262 tag = le32_to_cpu(psspPayload->tag);
1263 ccb = &pm8001_ha->ccb_info[tag];
1264 if ((status == IO_ABORTED) && ccb->open_retry) {
1265 /* Being completed by another */
1266 ccb->open_retry = 0;
1267 return;
1268 }
1269 pm8001_dev = ccb->device;
1270 param = le32_to_cpu(psspPayload->param);
1271 t = ccb->task;
1272
1273 if (status && status != IO_UNDERFLOW)
1274 PM8001_FAIL_DBG(pm8001_ha,
1275 pm8001_printk("sas IO status 0x%x\n", status));
1276 if (unlikely(!t || !t->lldd_task || !t->dev))
1277 return;
1278 ts = &t->task_status;
1279 switch (status) {
1280 case IO_SUCCESS:
1281 PM8001_IO_DBG(pm8001_ha,
1282 pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1283 param));
1284 if (param == 0) {
1285 ts->resp = SAS_TASK_COMPLETE;
1286 ts->stat = SAM_STAT_GOOD;
1287 } else {
1288 ts->resp = SAS_TASK_COMPLETE;
1289 ts->stat = SAS_PROTO_RESPONSE;
1290 ts->residual = param;
1291 iu = &psspPayload->ssp_resp_iu;
1292 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1293 }
1294 if (pm8001_dev)
1295 pm8001_dev->running_req--;
1296 break;
1297 case IO_ABORTED:
1298 PM8001_IO_DBG(pm8001_ha,
1299 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1300 ts->resp = SAS_TASK_COMPLETE;
1301 ts->stat = SAS_ABORTED_TASK;
1302 break;
1303 case IO_UNDERFLOW:
1304 /* SSP Completion with error */
1305 PM8001_IO_DBG(pm8001_ha,
1306 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1307 param));
1308 ts->resp = SAS_TASK_COMPLETE;
1309 ts->stat = SAS_DATA_UNDERRUN;
1310 ts->residual = param;
1311 if (pm8001_dev)
1312 pm8001_dev->running_req--;
1313 break;
1314 case IO_NO_DEVICE:
1315 PM8001_IO_DBG(pm8001_ha,
1316 pm8001_printk("IO_NO_DEVICE\n"));
1317 ts->resp = SAS_TASK_UNDELIVERED;
1318 ts->stat = SAS_PHY_DOWN;
1319 break;
1320 case IO_XFER_ERROR_BREAK:
1321 PM8001_IO_DBG(pm8001_ha,
1322 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1323 ts->resp = SAS_TASK_COMPLETE;
1324 ts->stat = SAS_OPEN_REJECT;
1325 /* Force the midlayer to retry */
1326 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1327 break;
1328 case IO_XFER_ERROR_PHY_NOT_READY:
1329 PM8001_IO_DBG(pm8001_ha,
1330 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1331 ts->resp = SAS_TASK_COMPLETE;
1332 ts->stat = SAS_OPEN_REJECT;
1333 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1334 break;
1335 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1336 PM8001_IO_DBG(pm8001_ha,
1337 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1338 ts->resp = SAS_TASK_COMPLETE;
1339 ts->stat = SAS_OPEN_REJECT;
1340 ts->open_rej_reason = SAS_OREJ_EPROTO;
1341 break;
1342 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1343 PM8001_IO_DBG(pm8001_ha,
1344 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1345 ts->resp = SAS_TASK_COMPLETE;
1346 ts->stat = SAS_OPEN_REJECT;
1347 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1348 break;
1349 case IO_OPEN_CNX_ERROR_BREAK:
1350 PM8001_IO_DBG(pm8001_ha,
1351 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1352 ts->resp = SAS_TASK_COMPLETE;
1353 ts->stat = SAS_OPEN_REJECT;
1354 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1355 break;
1356 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1357 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1358 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1359 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1360 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1361 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1362 PM8001_IO_DBG(pm8001_ha,
1363 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1364 ts->resp = SAS_TASK_COMPLETE;
1365 ts->stat = SAS_OPEN_REJECT;
1366 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1367 if (!t->uldd_task)
1368 pm8001_handle_event(pm8001_ha,
1369 pm8001_dev,
1370 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1371 break;
1372 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1373 PM8001_IO_DBG(pm8001_ha,
1374 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1375 ts->resp = SAS_TASK_COMPLETE;
1376 ts->stat = SAS_OPEN_REJECT;
1377 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1378 break;
1379 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1380 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1381 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1382 ts->resp = SAS_TASK_COMPLETE;
1383 ts->stat = SAS_OPEN_REJECT;
1384 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1385 break;
1386 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1387 PM8001_IO_DBG(pm8001_ha,
1388 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1389 ts->resp = SAS_TASK_UNDELIVERED;
1390 ts->stat = SAS_OPEN_REJECT;
1391 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1392 break;
1393 case IO_XFER_ERROR_NAK_RECEIVED:
1394 PM8001_IO_DBG(pm8001_ha,
1395 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1396 ts->resp = SAS_TASK_COMPLETE;
1397 ts->stat = SAS_OPEN_REJECT;
1398 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1399 break;
1400 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1401 PM8001_IO_DBG(pm8001_ha,
1402 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1403 ts->resp = SAS_TASK_COMPLETE;
1404 ts->stat = SAS_NAK_R_ERR;
1405 break;
1406 case IO_XFER_ERROR_DMA:
1407 PM8001_IO_DBG(pm8001_ha,
1408 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1409 ts->resp = SAS_TASK_COMPLETE;
1410 ts->stat = SAS_OPEN_REJECT;
1411 break;
1412 case IO_XFER_OPEN_RETRY_TIMEOUT:
1413 PM8001_IO_DBG(pm8001_ha,
1414 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1415 ts->resp = SAS_TASK_COMPLETE;
1416 ts->stat = SAS_OPEN_REJECT;
1417 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1418 break;
1419 case IO_XFER_ERROR_OFFSET_MISMATCH:
1420 PM8001_IO_DBG(pm8001_ha,
1421 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1422 ts->resp = SAS_TASK_COMPLETE;
1423 ts->stat = SAS_OPEN_REJECT;
1424 break;
1425 case IO_PORT_IN_RESET:
1426 PM8001_IO_DBG(pm8001_ha,
1427 pm8001_printk("IO_PORT_IN_RESET\n"));
1428 ts->resp = SAS_TASK_COMPLETE;
1429 ts->stat = SAS_OPEN_REJECT;
1430 break;
1431 case IO_DS_NON_OPERATIONAL:
1432 PM8001_IO_DBG(pm8001_ha,
1433 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1434 ts->resp = SAS_TASK_COMPLETE;
1435 ts->stat = SAS_OPEN_REJECT;
1436 if (!t->uldd_task)
1437 pm8001_handle_event(pm8001_ha,
1438 pm8001_dev,
1439 IO_DS_NON_OPERATIONAL);
1440 break;
1441 case IO_DS_IN_RECOVERY:
1442 PM8001_IO_DBG(pm8001_ha,
1443 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1444 ts->resp = SAS_TASK_COMPLETE;
1445 ts->stat = SAS_OPEN_REJECT;
1446 break;
1447 case IO_TM_TAG_NOT_FOUND:
1448 PM8001_IO_DBG(pm8001_ha,
1449 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1450 ts->resp = SAS_TASK_COMPLETE;
1451 ts->stat = SAS_OPEN_REJECT;
1452 break;
1453 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1454 PM8001_IO_DBG(pm8001_ha,
1455 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1456 ts->resp = SAS_TASK_COMPLETE;
1457 ts->stat = SAS_OPEN_REJECT;
1458 break;
1459 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1460 PM8001_IO_DBG(pm8001_ha,
1461 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1462 ts->resp = SAS_TASK_COMPLETE;
1463 ts->stat = SAS_OPEN_REJECT;
1464 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1465 break;
1466 default:
1467 PM8001_IO_DBG(pm8001_ha,
1468 pm8001_printk("Unknown status 0x%x\n", status));
1469 /* not allowed case. Therefore, return failed status */
1470 ts->resp = SAS_TASK_COMPLETE;
1471 ts->stat = SAS_OPEN_REJECT;
1472 break;
1473 }
1474 PM8001_IO_DBG(pm8001_ha,
1475 pm8001_printk("scsi_status = 0x%x\n ",
1476 psspPayload->ssp_resp_iu.status));
1477 spin_lock_irqsave(&t->task_state_lock, flags);
1478 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1479 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1480 t->task_state_flags |= SAS_TASK_STATE_DONE;
1481 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1482 spin_unlock_irqrestore(&t->task_state_lock, flags);
1483 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1484 "task 0x%p done with io_status 0x%x resp 0x%x "
1485 "stat 0x%x but aborted by upper layer!\n",
1486 t, status, ts->resp, ts->stat));
1487 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1488 } else {
1489 spin_unlock_irqrestore(&t->task_state_lock, flags);
1490 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1491 mb();/* in order to force CPU ordering */
1492 t->task_done(t);
1493 }
1494}
1495
1496/*See the comments for mpi_ssp_completion */
1497static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1498{
1499 struct sas_task *t;
1500 unsigned long flags;
1501 struct task_status_struct *ts;
1502 struct pm8001_ccb_info *ccb;
1503 struct pm8001_device *pm8001_dev;
1504 struct ssp_event_resp *psspPayload =
1505 (struct ssp_event_resp *)(piomb + 4);
1506 u32 event = le32_to_cpu(psspPayload->event);
1507 u32 tag = le32_to_cpu(psspPayload->tag);
1508 u32 port_id = le32_to_cpu(psspPayload->port_id);
1509
1510 ccb = &pm8001_ha->ccb_info[tag];
1511 t = ccb->task;
1512 pm8001_dev = ccb->device;
1513 if (event)
1514 PM8001_FAIL_DBG(pm8001_ha,
1515 pm8001_printk("sas IO status 0x%x\n", event));
1516 if (unlikely(!t || !t->lldd_task || !t->dev))
1517 return;
1518 ts = &t->task_status;
1519 PM8001_IO_DBG(pm8001_ha,
1520 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1521 port_id, tag, event));
1522 switch (event) {
1523 case IO_OVERFLOW:
1524 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1525 ts->resp = SAS_TASK_COMPLETE;
1526 ts->stat = SAS_DATA_OVERRUN;
1527 ts->residual = 0;
1528 if (pm8001_dev)
1529 pm8001_dev->running_req--;
1530 break;
1531 case IO_XFER_ERROR_BREAK:
1532 PM8001_IO_DBG(pm8001_ha,
1533 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1534 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1535 return;
1536 case IO_XFER_ERROR_PHY_NOT_READY:
1537 PM8001_IO_DBG(pm8001_ha,
1538 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1539 ts->resp = SAS_TASK_COMPLETE;
1540 ts->stat = SAS_OPEN_REJECT;
1541 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1542 break;
1543 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1544 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1545 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1546 ts->resp = SAS_TASK_COMPLETE;
1547 ts->stat = SAS_OPEN_REJECT;
1548 ts->open_rej_reason = SAS_OREJ_EPROTO;
1549 break;
1550 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1551 PM8001_IO_DBG(pm8001_ha,
1552 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1553 ts->resp = SAS_TASK_COMPLETE;
1554 ts->stat = SAS_OPEN_REJECT;
1555 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1556 break;
1557 case IO_OPEN_CNX_ERROR_BREAK:
1558 PM8001_IO_DBG(pm8001_ha,
1559 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1560 ts->resp = SAS_TASK_COMPLETE;
1561 ts->stat = SAS_OPEN_REJECT;
1562 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1563 break;
1564 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1565 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1566 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1567 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1568 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1569 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1570 PM8001_IO_DBG(pm8001_ha,
1571 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1572 ts->resp = SAS_TASK_COMPLETE;
1573 ts->stat = SAS_OPEN_REJECT;
1574 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1575 if (!t->uldd_task)
1576 pm8001_handle_event(pm8001_ha,
1577 pm8001_dev,
1578 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1579 break;
1580 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1581 PM8001_IO_DBG(pm8001_ha,
1582 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1583 ts->resp = SAS_TASK_COMPLETE;
1584 ts->stat = SAS_OPEN_REJECT;
1585 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1586 break;
1587 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1588 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1589 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1590 ts->resp = SAS_TASK_COMPLETE;
1591 ts->stat = SAS_OPEN_REJECT;
1592 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1593 break;
1594 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1595 PM8001_IO_DBG(pm8001_ha,
1596 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1597 ts->resp = SAS_TASK_COMPLETE;
1598 ts->stat = SAS_OPEN_REJECT;
1599 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1600 break;
1601 case IO_XFER_ERROR_NAK_RECEIVED:
1602 PM8001_IO_DBG(pm8001_ha,
1603 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1604 ts->resp = SAS_TASK_COMPLETE;
1605 ts->stat = SAS_OPEN_REJECT;
1606 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1607 break;
1608 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1609 PM8001_IO_DBG(pm8001_ha,
1610 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1611 ts->resp = SAS_TASK_COMPLETE;
1612 ts->stat = SAS_NAK_R_ERR;
1613 break;
1614 case IO_XFER_OPEN_RETRY_TIMEOUT:
1615 PM8001_IO_DBG(pm8001_ha,
1616 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1617 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1618 return;
1619 case IO_XFER_ERROR_UNEXPECTED_PHASE:
1620 PM8001_IO_DBG(pm8001_ha,
1621 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1622 ts->resp = SAS_TASK_COMPLETE;
1623 ts->stat = SAS_DATA_OVERRUN;
1624 break;
1625 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1626 PM8001_IO_DBG(pm8001_ha,
1627 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1628 ts->resp = SAS_TASK_COMPLETE;
1629 ts->stat = SAS_DATA_OVERRUN;
1630 break;
1631 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1632 PM8001_IO_DBG(pm8001_ha,
1633 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1634 ts->resp = SAS_TASK_COMPLETE;
1635 ts->stat = SAS_DATA_OVERRUN;
1636 break;
1637 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1638 PM8001_IO_DBG(pm8001_ha,
1639 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1640 ts->resp = SAS_TASK_COMPLETE;
1641 ts->stat = SAS_DATA_OVERRUN;
1642 break;
1643 case IO_XFER_ERROR_OFFSET_MISMATCH:
1644 PM8001_IO_DBG(pm8001_ha,
1645 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1646 ts->resp = SAS_TASK_COMPLETE;
1647 ts->stat = SAS_DATA_OVERRUN;
1648 break;
1649 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1650 PM8001_IO_DBG(pm8001_ha,
1651 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1652 ts->resp = SAS_TASK_COMPLETE;
1653 ts->stat = SAS_DATA_OVERRUN;
1654 break;
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1655 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
1656 PM8001_IO_DBG(pm8001_ha,
1657 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
1658 /* TBC: used default set values */
1659 ts->resp = SAS_TASK_COMPLETE;
1660 ts->stat = SAS_DATA_OVERRUN;
1661 break;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1662 case IO_XFER_CMD_FRAME_ISSUED:
1663 PM8001_IO_DBG(pm8001_ha,
1664 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1665 return;
1666 default:
1667 PM8001_IO_DBG(pm8001_ha,
1668 pm8001_printk("Unknown status 0x%x\n", event));
1669 /* not allowed case. Therefore, return failed status */
1670 ts->resp = SAS_TASK_COMPLETE;
1671 ts->stat = SAS_DATA_OVERRUN;
1672 break;
1673 }
1674 spin_lock_irqsave(&t->task_state_lock, flags);
1675 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1676 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1677 t->task_state_flags |= SAS_TASK_STATE_DONE;
1678 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1679 spin_unlock_irqrestore(&t->task_state_lock, flags);
1680 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1681 "task 0x%p done with event 0x%x resp 0x%x "
1682 "stat 0x%x but aborted by upper layer!\n",
1683 t, event, ts->resp, ts->stat));
1684 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1685 } else {
1686 spin_unlock_irqrestore(&t->task_state_lock, flags);
1687 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1688 mb();/* in order to force CPU ordering */
1689 t->task_done(t);
1690 }
1691}
1692
1693/*See the comments for mpi_ssp_completion */
1694static void
1695mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1696{
1697 struct sas_task *t;
1698 struct pm8001_ccb_info *ccb;
1699 u32 param;
1700 u32 status;
1701 u32 tag;
1702 struct sata_completion_resp *psataPayload;
1703 struct task_status_struct *ts;
1704 struct ata_task_resp *resp ;
1705 u32 *sata_resp;
1706 struct pm8001_device *pm8001_dev;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1707 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1708
1709 psataPayload = (struct sata_completion_resp *)(piomb + 4);
1710 status = le32_to_cpu(psataPayload->status);
1711 tag = le32_to_cpu(psataPayload->tag);
1712
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1713 if (!tag) {
1714 PM8001_FAIL_DBG(pm8001_ha,
1715 pm8001_printk("tag null\n"));
1716 return;
1717 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1718 ccb = &pm8001_ha->ccb_info[tag];
1719 param = le32_to_cpu(psataPayload->param);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1720 if (ccb) {
1721 t = ccb->task;
1722 pm8001_dev = ccb->device;
1723 } else {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1724 PM8001_FAIL_DBG(pm8001_ha,
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1725 pm8001_printk("ccb null\n"));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1726 return;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1727 }
1728
1729 if (t) {
1730 if (t->dev && (t->dev->lldd_dev))
1731 pm8001_dev = t->dev->lldd_dev;
1732 } else {
1733 PM8001_FAIL_DBG(pm8001_ha,
1734 pm8001_printk("task null\n"));
1735 return;
1736 }
1737
1738 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
1739 && unlikely(!t || !t->lldd_task || !t->dev)) {
1740 PM8001_FAIL_DBG(pm8001_ha,
1741 pm8001_printk("task or dev null\n"));
1742 return;
1743 }
1744
1745 ts = &t->task_status;
1746 if (!ts) {
1747 PM8001_FAIL_DBG(pm8001_ha,
1748 pm8001_printk("ts null\n"));
1749 return;
1750 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1751
1752 switch (status) {
1753 case IO_SUCCESS:
1754 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
1755 if (param == 0) {
1756 ts->resp = SAS_TASK_COMPLETE;
1757 ts->stat = SAM_STAT_GOOD;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1758 /* check if response is for SEND READ LOG */
1759 if (pm8001_dev &&
1760 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
1761 /* set new bit for abort_all */
1762 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
1763 /* clear bit for read log */
1764 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
1765 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
1766 /* Free the tag */
1767 pm8001_tag_free(pm8001_ha, tag);
1768 sas_free_task(t);
1769 return;
1770 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1771 } else {
1772 u8 len;
1773 ts->resp = SAS_TASK_COMPLETE;
1774 ts->stat = SAS_PROTO_RESPONSE;
1775 ts->residual = param;
1776 PM8001_IO_DBG(pm8001_ha,
1777 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
1778 param));
1779 sata_resp = &psataPayload->sata_resp[0];
1780 resp = (struct ata_task_resp *)ts->buf;
1781 if (t->ata_task.dma_xfer == 0 &&
1782 t->data_dir == PCI_DMA_FROMDEVICE) {
1783 len = sizeof(struct pio_setup_fis);
1784 PM8001_IO_DBG(pm8001_ha,
1785 pm8001_printk("PIO read len = %d\n", len));
1786 } else if (t->ata_task.use_ncq) {
1787 len = sizeof(struct set_dev_bits_fis);
1788 PM8001_IO_DBG(pm8001_ha,
1789 pm8001_printk("FPDMA len = %d\n", len));
1790 } else {
1791 len = sizeof(struct dev_to_host_fis);
1792 PM8001_IO_DBG(pm8001_ha,
1793 pm8001_printk("other len = %d\n", len));
1794 }
1795 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
1796 resp->frame_len = len;
1797 memcpy(&resp->ending_fis[0], sata_resp, len);
1798 ts->buf_valid_size = sizeof(*resp);
1799 } else
1800 PM8001_IO_DBG(pm8001_ha,
1801 pm8001_printk("response to large\n"));
1802 }
1803 if (pm8001_dev)
1804 pm8001_dev->running_req--;
1805 break;
1806 case IO_ABORTED:
1807 PM8001_IO_DBG(pm8001_ha,
1808 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1809 ts->resp = SAS_TASK_COMPLETE;
1810 ts->stat = SAS_ABORTED_TASK;
1811 if (pm8001_dev)
1812 pm8001_dev->running_req--;
1813 break;
1814 /* following cases are to do cases */
1815 case IO_UNDERFLOW:
1816 /* SATA Completion with error */
1817 PM8001_IO_DBG(pm8001_ha,
1818 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
1819 ts->resp = SAS_TASK_COMPLETE;
1820 ts->stat = SAS_DATA_UNDERRUN;
1821 ts->residual = param;
1822 if (pm8001_dev)
1823 pm8001_dev->running_req--;
1824 break;
1825 case IO_NO_DEVICE:
1826 PM8001_IO_DBG(pm8001_ha,
1827 pm8001_printk("IO_NO_DEVICE\n"));
1828 ts->resp = SAS_TASK_UNDELIVERED;
1829 ts->stat = SAS_PHY_DOWN;
1830 break;
1831 case IO_XFER_ERROR_BREAK:
1832 PM8001_IO_DBG(pm8001_ha,
1833 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1834 ts->resp = SAS_TASK_COMPLETE;
1835 ts->stat = SAS_INTERRUPTED;
1836 break;
1837 case IO_XFER_ERROR_PHY_NOT_READY:
1838 PM8001_IO_DBG(pm8001_ha,
1839 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1840 ts->resp = SAS_TASK_COMPLETE;
1841 ts->stat = SAS_OPEN_REJECT;
1842 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1843 break;
1844 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1845 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1846 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1847 ts->resp = SAS_TASK_COMPLETE;
1848 ts->stat = SAS_OPEN_REJECT;
1849 ts->open_rej_reason = SAS_OREJ_EPROTO;
1850 break;
1851 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1852 PM8001_IO_DBG(pm8001_ha,
1853 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1854 ts->resp = SAS_TASK_COMPLETE;
1855 ts->stat = SAS_OPEN_REJECT;
1856 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1857 break;
1858 case IO_OPEN_CNX_ERROR_BREAK:
1859 PM8001_IO_DBG(pm8001_ha,
1860 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1861 ts->resp = SAS_TASK_COMPLETE;
1862 ts->stat = SAS_OPEN_REJECT;
1863 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
1864 break;
1865 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1866 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1867 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1868 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1869 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1870 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1871 PM8001_IO_DBG(pm8001_ha,
1872 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1873 ts->resp = SAS_TASK_COMPLETE;
1874 ts->stat = SAS_DEV_NO_RESPONSE;
1875 if (!t->uldd_task) {
1876 pm8001_handle_event(pm8001_ha,
1877 pm8001_dev,
1878 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1879 ts->resp = SAS_TASK_UNDELIVERED;
1880 ts->stat = SAS_QUEUE_FULL;
1881 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1882 mb();/*in order to force CPU ordering*/
1883 spin_unlock_irq(&pm8001_ha->lock);
1884 t->task_done(t);
1885 spin_lock_irq(&pm8001_ha->lock);
1886 return;
1887 }
1888 break;
1889 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1890 PM8001_IO_DBG(pm8001_ha,
1891 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1892 ts->resp = SAS_TASK_UNDELIVERED;
1893 ts->stat = SAS_OPEN_REJECT;
1894 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1895 if (!t->uldd_task) {
1896 pm8001_handle_event(pm8001_ha,
1897 pm8001_dev,
1898 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1899 ts->resp = SAS_TASK_UNDELIVERED;
1900 ts->stat = SAS_QUEUE_FULL;
1901 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1902 mb();/*ditto*/
1903 spin_unlock_irq(&pm8001_ha->lock);
1904 t->task_done(t);
1905 spin_lock_irq(&pm8001_ha->lock);
1906 return;
1907 }
1908 break;
1909 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1910 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1911 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1912 ts->resp = SAS_TASK_COMPLETE;
1913 ts->stat = SAS_OPEN_REJECT;
1914 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1915 break;
1916 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1917 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1918 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
1919 ts->resp = SAS_TASK_COMPLETE;
1920 ts->stat = SAS_DEV_NO_RESPONSE;
1921 if (!t->uldd_task) {
1922 pm8001_handle_event(pm8001_ha,
1923 pm8001_dev,
1924 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
1925 ts->resp = SAS_TASK_UNDELIVERED;
1926 ts->stat = SAS_QUEUE_FULL;
1927 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1928 mb();/* ditto*/
1929 spin_unlock_irq(&pm8001_ha->lock);
1930 t->task_done(t);
1931 spin_lock_irq(&pm8001_ha->lock);
1932 return;
1933 }
1934 break;
1935 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1936 PM8001_IO_DBG(pm8001_ha,
1937 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1938 ts->resp = SAS_TASK_COMPLETE;
1939 ts->stat = SAS_OPEN_REJECT;
1940 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1941 break;
1942 case IO_XFER_ERROR_NAK_RECEIVED:
1943 PM8001_IO_DBG(pm8001_ha,
1944 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1945 ts->resp = SAS_TASK_COMPLETE;
1946 ts->stat = SAS_NAK_R_ERR;
1947 break;
1948 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1949 PM8001_IO_DBG(pm8001_ha,
1950 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1951 ts->resp = SAS_TASK_COMPLETE;
1952 ts->stat = SAS_NAK_R_ERR;
1953 break;
1954 case IO_XFER_ERROR_DMA:
1955 PM8001_IO_DBG(pm8001_ha,
1956 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1957 ts->resp = SAS_TASK_COMPLETE;
1958 ts->stat = SAS_ABORTED_TASK;
1959 break;
1960 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
1961 PM8001_IO_DBG(pm8001_ha,
1962 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
1963 ts->resp = SAS_TASK_UNDELIVERED;
1964 ts->stat = SAS_DEV_NO_RESPONSE;
1965 break;
1966 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
1967 PM8001_IO_DBG(pm8001_ha,
1968 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
1969 ts->resp = SAS_TASK_COMPLETE;
1970 ts->stat = SAS_DATA_UNDERRUN;
1971 break;
1972 case IO_XFER_OPEN_RETRY_TIMEOUT:
1973 PM8001_IO_DBG(pm8001_ha,
1974 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1975 ts->resp = SAS_TASK_COMPLETE;
1976 ts->stat = SAS_OPEN_TO;
1977 break;
1978 case IO_PORT_IN_RESET:
1979 PM8001_IO_DBG(pm8001_ha,
1980 pm8001_printk("IO_PORT_IN_RESET\n"));
1981 ts->resp = SAS_TASK_COMPLETE;
1982 ts->stat = SAS_DEV_NO_RESPONSE;
1983 break;
1984 case IO_DS_NON_OPERATIONAL:
1985 PM8001_IO_DBG(pm8001_ha,
1986 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1987 ts->resp = SAS_TASK_COMPLETE;
1988 ts->stat = SAS_DEV_NO_RESPONSE;
1989 if (!t->uldd_task) {
1990 pm8001_handle_event(pm8001_ha, pm8001_dev,
1991 IO_DS_NON_OPERATIONAL);
1992 ts->resp = SAS_TASK_UNDELIVERED;
1993 ts->stat = SAS_QUEUE_FULL;
1994 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1995 mb();/*ditto*/
1996 spin_unlock_irq(&pm8001_ha->lock);
1997 t->task_done(t);
1998 spin_lock_irq(&pm8001_ha->lock);
1999 return;
2000 }
2001 break;
2002 case IO_DS_IN_RECOVERY:
2003 PM8001_IO_DBG(pm8001_ha,
2004 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2005 ts->resp = SAS_TASK_COMPLETE;
2006 ts->stat = SAS_DEV_NO_RESPONSE;
2007 break;
2008 case IO_DS_IN_ERROR:
2009 PM8001_IO_DBG(pm8001_ha,
2010 pm8001_printk("IO_DS_IN_ERROR\n"));
2011 ts->resp = SAS_TASK_COMPLETE;
2012 ts->stat = SAS_DEV_NO_RESPONSE;
2013 if (!t->uldd_task) {
2014 pm8001_handle_event(pm8001_ha, pm8001_dev,
2015 IO_DS_IN_ERROR);
2016 ts->resp = SAS_TASK_UNDELIVERED;
2017 ts->stat = SAS_QUEUE_FULL;
2018 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2019 mb();/*ditto*/
2020 spin_unlock_irq(&pm8001_ha->lock);
2021 t->task_done(t);
2022 spin_lock_irq(&pm8001_ha->lock);
2023 return;
2024 }
2025 break;
2026 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2027 PM8001_IO_DBG(pm8001_ha,
2028 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2029 ts->resp = SAS_TASK_COMPLETE;
2030 ts->stat = SAS_OPEN_REJECT;
2031 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2032 default:
2033 PM8001_IO_DBG(pm8001_ha,
2034 pm8001_printk("Unknown status 0x%x\n", status));
2035 /* not allowed case. Therefore, return failed status */
2036 ts->resp = SAS_TASK_COMPLETE;
2037 ts->stat = SAS_DEV_NO_RESPONSE;
2038 break;
2039 }
2040 spin_lock_irqsave(&t->task_state_lock, flags);
2041 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2042 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2043 t->task_state_flags |= SAS_TASK_STATE_DONE;
2044 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2045 spin_unlock_irqrestore(&t->task_state_lock, flags);
2046 PM8001_FAIL_DBG(pm8001_ha,
2047 pm8001_printk("task 0x%p done with io_status 0x%x"
2048 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2049 t, status, ts->resp, ts->stat));
2050 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2051 } else if (t->uldd_task) {
2052 spin_unlock_irqrestore(&t->task_state_lock, flags);
2053 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2054 mb();/* ditto */
2055 spin_unlock_irq(&pm8001_ha->lock);
2056 t->task_done(t);
2057 spin_lock_irq(&pm8001_ha->lock);
2058 } else if (!t->uldd_task) {
2059 spin_unlock_irqrestore(&t->task_state_lock, flags);
2060 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2061 mb();/*ditto*/
2062 spin_unlock_irq(&pm8001_ha->lock);
2063 t->task_done(t);
2064 spin_lock_irq(&pm8001_ha->lock);
2065 }
2066}
2067
2068/*See the comments for mpi_ssp_completion */
2069static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2070{
2071 struct sas_task *t;
2072 struct task_status_struct *ts;
2073 struct pm8001_ccb_info *ccb;
2074 struct pm8001_device *pm8001_dev;
2075 struct sata_event_resp *psataPayload =
2076 (struct sata_event_resp *)(piomb + 4);
2077 u32 event = le32_to_cpu(psataPayload->event);
2078 u32 tag = le32_to_cpu(psataPayload->tag);
2079 u32 port_id = le32_to_cpu(psataPayload->port_id);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2080 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2081 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2082
2083 ccb = &pm8001_ha->ccb_info[tag];
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2084
2085 if (ccb) {
2086 t = ccb->task;
2087 pm8001_dev = ccb->device;
2088 } else {
2089 PM8001_FAIL_DBG(pm8001_ha,
2090 pm8001_printk("No CCB !!!. returning\n"));
2091 return;
2092 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2093 if (event)
2094 PM8001_FAIL_DBG(pm8001_ha,
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2095 pm8001_printk("SATA EVENT 0x%x\n", event));
2096
2097 /* Check if this is NCQ error */
2098 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2099 /* find device using device id */
2100 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2101 /* send read log extension */
2102 if (pm8001_dev)
2103 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2104 return;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2105 }
2106
2107 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2108 PM8001_FAIL_DBG(pm8001_ha,
2109 pm8001_printk("task or dev null\n"));
2110 return;
2111 }
2112
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2113 ts = &t->task_status;
2114 PM8001_IO_DBG(pm8001_ha,
2115 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2116 port_id, tag, event));
2117 switch (event) {
2118 case IO_OVERFLOW:
2119 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2120 ts->resp = SAS_TASK_COMPLETE;
2121 ts->stat = SAS_DATA_OVERRUN;
2122 ts->residual = 0;
2123 if (pm8001_dev)
2124 pm8001_dev->running_req--;
2125 break;
2126 case IO_XFER_ERROR_BREAK:
2127 PM8001_IO_DBG(pm8001_ha,
2128 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2129 ts->resp = SAS_TASK_COMPLETE;
2130 ts->stat = SAS_INTERRUPTED;
2131 break;
2132 case IO_XFER_ERROR_PHY_NOT_READY:
2133 PM8001_IO_DBG(pm8001_ha,
2134 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2135 ts->resp = SAS_TASK_COMPLETE;
2136 ts->stat = SAS_OPEN_REJECT;
2137 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2138 break;
2139 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2140 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2141 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2142 ts->resp = SAS_TASK_COMPLETE;
2143 ts->stat = SAS_OPEN_REJECT;
2144 ts->open_rej_reason = SAS_OREJ_EPROTO;
2145 break;
2146 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2147 PM8001_IO_DBG(pm8001_ha,
2148 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2149 ts->resp = SAS_TASK_COMPLETE;
2150 ts->stat = SAS_OPEN_REJECT;
2151 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2152 break;
2153 case IO_OPEN_CNX_ERROR_BREAK:
2154 PM8001_IO_DBG(pm8001_ha,
2155 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2156 ts->resp = SAS_TASK_COMPLETE;
2157 ts->stat = SAS_OPEN_REJECT;
2158 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2159 break;
2160 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2161 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2162 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2163 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2164 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2165 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2166 PM8001_FAIL_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2167 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2168 ts->resp = SAS_TASK_UNDELIVERED;
2169 ts->stat = SAS_DEV_NO_RESPONSE;
2170 if (!t->uldd_task) {
2171 pm8001_handle_event(pm8001_ha,
2172 pm8001_dev,
2173 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2174 ts->resp = SAS_TASK_COMPLETE;
2175 ts->stat = SAS_QUEUE_FULL;
2176 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2177 mb();/*ditto*/
2178 spin_unlock_irq(&pm8001_ha->lock);
2179 t->task_done(t);
2180 spin_lock_irq(&pm8001_ha->lock);
2181 return;
2182 }
2183 break;
2184 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2185 PM8001_IO_DBG(pm8001_ha,
2186 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2187 ts->resp = SAS_TASK_UNDELIVERED;
2188 ts->stat = SAS_OPEN_REJECT;
2189 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2190 break;
2191 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2192 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2193 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2194 ts->resp = SAS_TASK_COMPLETE;
2195 ts->stat = SAS_OPEN_REJECT;
2196 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2197 break;
2198 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2199 PM8001_IO_DBG(pm8001_ha,
2200 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2201 ts->resp = SAS_TASK_COMPLETE;
2202 ts->stat = SAS_OPEN_REJECT;
2203 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2204 break;
2205 case IO_XFER_ERROR_NAK_RECEIVED:
2206 PM8001_IO_DBG(pm8001_ha,
2207 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2208 ts->resp = SAS_TASK_COMPLETE;
2209 ts->stat = SAS_NAK_R_ERR;
2210 break;
2211 case IO_XFER_ERROR_PEER_ABORTED:
2212 PM8001_IO_DBG(pm8001_ha,
2213 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2214 ts->resp = SAS_TASK_COMPLETE;
2215 ts->stat = SAS_NAK_R_ERR;
2216 break;
2217 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2218 PM8001_IO_DBG(pm8001_ha,
2219 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2220 ts->resp = SAS_TASK_COMPLETE;
2221 ts->stat = SAS_DATA_UNDERRUN;
2222 break;
2223 case IO_XFER_OPEN_RETRY_TIMEOUT:
2224 PM8001_IO_DBG(pm8001_ha,
2225 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2226 ts->resp = SAS_TASK_COMPLETE;
2227 ts->stat = SAS_OPEN_TO;
2228 break;
2229 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2230 PM8001_IO_DBG(pm8001_ha,
2231 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2232 ts->resp = SAS_TASK_COMPLETE;
2233 ts->stat = SAS_OPEN_TO;
2234 break;
2235 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2236 PM8001_IO_DBG(pm8001_ha,
2237 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2238 ts->resp = SAS_TASK_COMPLETE;
2239 ts->stat = SAS_OPEN_TO;
2240 break;
2241 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2242 PM8001_IO_DBG(pm8001_ha,
2243 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2244 ts->resp = SAS_TASK_COMPLETE;
2245 ts->stat = SAS_OPEN_TO;
2246 break;
2247 case IO_XFER_ERROR_OFFSET_MISMATCH:
2248 PM8001_IO_DBG(pm8001_ha,
2249 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2250 ts->resp = SAS_TASK_COMPLETE;
2251 ts->stat = SAS_OPEN_TO;
2252 break;
2253 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2254 PM8001_IO_DBG(pm8001_ha,
2255 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2256 ts->resp = SAS_TASK_COMPLETE;
2257 ts->stat = SAS_OPEN_TO;
2258 break;
2259 case IO_XFER_CMD_FRAME_ISSUED:
2260 PM8001_IO_DBG(pm8001_ha,
2261 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2262 break;
2263 case IO_XFER_PIO_SETUP_ERROR:
2264 PM8001_IO_DBG(pm8001_ha,
2265 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2266 ts->resp = SAS_TASK_COMPLETE;
2267 ts->stat = SAS_OPEN_TO;
2268 break;
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2269 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2270 PM8001_FAIL_DBG(pm8001_ha,
2271 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2272 /* TBC: used default set values */
2273 ts->resp = SAS_TASK_COMPLETE;
2274 ts->stat = SAS_OPEN_TO;
2275 break;
2276 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2277 PM8001_FAIL_DBG(pm8001_ha,
2278 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2279 /* TBC: used default set values */
2280 ts->resp = SAS_TASK_COMPLETE;
2281 ts->stat = SAS_OPEN_TO;
2282 break;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2283 default:
2284 PM8001_IO_DBG(pm8001_ha,
2285 pm8001_printk("Unknown status 0x%x\n", event));
2286 /* not allowed case. Therefore, return failed status */
2287 ts->resp = SAS_TASK_COMPLETE;
2288 ts->stat = SAS_OPEN_TO;
2289 break;
2290 }
2291 spin_lock_irqsave(&t->task_state_lock, flags);
2292 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2293 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2294 t->task_state_flags |= SAS_TASK_STATE_DONE;
2295 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2296 spin_unlock_irqrestore(&t->task_state_lock, flags);
2297 PM8001_FAIL_DBG(pm8001_ha,
2298 pm8001_printk("task 0x%p done with io_status 0x%x"
2299 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2300 t, event, ts->resp, ts->stat));
2301 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2302 } else if (t->uldd_task) {
2303 spin_unlock_irqrestore(&t->task_state_lock, flags);
2304 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2305 mb();/* ditto */
2306 spin_unlock_irq(&pm8001_ha->lock);
2307 t->task_done(t);
2308 spin_lock_irq(&pm8001_ha->lock);
2309 } else if (!t->uldd_task) {
2310 spin_unlock_irqrestore(&t->task_state_lock, flags);
2311 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2312 mb();/*ditto*/
2313 spin_unlock_irq(&pm8001_ha->lock);
2314 t->task_done(t);
2315 spin_lock_irq(&pm8001_ha->lock);
2316 }
2317}
2318
2319/*See the comments for mpi_ssp_completion */
2320static void
2321mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2322{
2323 u32 param, i;
2324 struct sas_task *t;
2325 struct pm8001_ccb_info *ccb;
2326 unsigned long flags;
2327 u32 status;
2328 u32 tag;
2329 struct smp_completion_resp *psmpPayload;
2330 struct task_status_struct *ts;
2331 struct pm8001_device *pm8001_dev;
2332 char *pdma_respaddr = NULL;
2333
2334 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2335 status = le32_to_cpu(psmpPayload->status);
2336 tag = le32_to_cpu(psmpPayload->tag);
2337
2338 ccb = &pm8001_ha->ccb_info[tag];
2339 param = le32_to_cpu(psmpPayload->param);
2340 t = ccb->task;
2341 ts = &t->task_status;
2342 pm8001_dev = ccb->device;
2343 if (status)
2344 PM8001_FAIL_DBG(pm8001_ha,
2345 pm8001_printk("smp IO status 0x%x\n", status));
2346 if (unlikely(!t || !t->lldd_task || !t->dev))
2347 return;
2348
2349 switch (status) {
2350
2351 case IO_SUCCESS:
2352 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2353 ts->resp = SAS_TASK_COMPLETE;
2354 ts->stat = SAM_STAT_GOOD;
2355 if (pm8001_dev)
2356 pm8001_dev->running_req--;
2357 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2358 PM8001_IO_DBG(pm8001_ha,
2359 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2360 param));
2361 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2362 ((u64)sg_dma_address
2363 (&t->smp_task.smp_resp))));
2364 for (i = 0; i < param; i++) {
2365 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2366 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2367 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2368 i, *(pdma_respaddr+i),
2369 psmpPayload->_r_a[i]));
2370 }
2371 }
2372 break;
2373 case IO_ABORTED:
2374 PM8001_IO_DBG(pm8001_ha,
2375 pm8001_printk("IO_ABORTED IOMB\n"));
2376 ts->resp = SAS_TASK_COMPLETE;
2377 ts->stat = SAS_ABORTED_TASK;
2378 if (pm8001_dev)
2379 pm8001_dev->running_req--;
2380 break;
2381 case IO_OVERFLOW:
2382 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2383 ts->resp = SAS_TASK_COMPLETE;
2384 ts->stat = SAS_DATA_OVERRUN;
2385 ts->residual = 0;
2386 if (pm8001_dev)
2387 pm8001_dev->running_req--;
2388 break;
2389 case IO_NO_DEVICE:
2390 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2391 ts->resp = SAS_TASK_COMPLETE;
2392 ts->stat = SAS_PHY_DOWN;
2393 break;
2394 case IO_ERROR_HW_TIMEOUT:
2395 PM8001_IO_DBG(pm8001_ha,
2396 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2397 ts->resp = SAS_TASK_COMPLETE;
2398 ts->stat = SAM_STAT_BUSY;
2399 break;
2400 case IO_XFER_ERROR_BREAK:
2401 PM8001_IO_DBG(pm8001_ha,
2402 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2403 ts->resp = SAS_TASK_COMPLETE;
2404 ts->stat = SAM_STAT_BUSY;
2405 break;
2406 case IO_XFER_ERROR_PHY_NOT_READY:
2407 PM8001_IO_DBG(pm8001_ha,
2408 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2409 ts->resp = SAS_TASK_COMPLETE;
2410 ts->stat = SAM_STAT_BUSY;
2411 break;
2412 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2413 PM8001_IO_DBG(pm8001_ha,
2414 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2415 ts->resp = SAS_TASK_COMPLETE;
2416 ts->stat = SAS_OPEN_REJECT;
2417 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2418 break;
2419 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2420 PM8001_IO_DBG(pm8001_ha,
2421 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2422 ts->resp = SAS_TASK_COMPLETE;
2423 ts->stat = SAS_OPEN_REJECT;
2424 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2425 break;
2426 case IO_OPEN_CNX_ERROR_BREAK:
2427 PM8001_IO_DBG(pm8001_ha,
2428 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2429 ts->resp = SAS_TASK_COMPLETE;
2430 ts->stat = SAS_OPEN_REJECT;
2431 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2432 break;
2433 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2434 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2435 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2436 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2437 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2438 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2439 PM8001_IO_DBG(pm8001_ha,
2440 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2441 ts->resp = SAS_TASK_COMPLETE;
2442 ts->stat = SAS_OPEN_REJECT;
2443 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2444 pm8001_handle_event(pm8001_ha,
2445 pm8001_dev,
2446 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2447 break;
2448 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2449 PM8001_IO_DBG(pm8001_ha,
2450 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2451 ts->resp = SAS_TASK_COMPLETE;
2452 ts->stat = SAS_OPEN_REJECT;
2453 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2454 break;
2455 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2456 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2457 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2458 ts->resp = SAS_TASK_COMPLETE;
2459 ts->stat = SAS_OPEN_REJECT;
2460 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2461 break;
2462 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2463 PM8001_IO_DBG(pm8001_ha,
2464 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2465 ts->resp = SAS_TASK_COMPLETE;
2466 ts->stat = SAS_OPEN_REJECT;
2467 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2468 break;
2469 case IO_XFER_ERROR_RX_FRAME:
2470 PM8001_IO_DBG(pm8001_ha,
2471 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2472 ts->resp = SAS_TASK_COMPLETE;
2473 ts->stat = SAS_DEV_NO_RESPONSE;
2474 break;
2475 case IO_XFER_OPEN_RETRY_TIMEOUT:
2476 PM8001_IO_DBG(pm8001_ha,
2477 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2478 ts->resp = SAS_TASK_COMPLETE;
2479 ts->stat = SAS_OPEN_REJECT;
2480 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2481 break;
2482 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2483 PM8001_IO_DBG(pm8001_ha,
2484 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2485 ts->resp = SAS_TASK_COMPLETE;
2486 ts->stat = SAS_QUEUE_FULL;
2487 break;
2488 case IO_PORT_IN_RESET:
2489 PM8001_IO_DBG(pm8001_ha,
2490 pm8001_printk("IO_PORT_IN_RESET\n"));
2491 ts->resp = SAS_TASK_COMPLETE;
2492 ts->stat = SAS_OPEN_REJECT;
2493 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2494 break;
2495 case IO_DS_NON_OPERATIONAL:
2496 PM8001_IO_DBG(pm8001_ha,
2497 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2498 ts->resp = SAS_TASK_COMPLETE;
2499 ts->stat = SAS_DEV_NO_RESPONSE;
2500 break;
2501 case IO_DS_IN_RECOVERY:
2502 PM8001_IO_DBG(pm8001_ha,
2503 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2504 ts->resp = SAS_TASK_COMPLETE;
2505 ts->stat = SAS_OPEN_REJECT;
2506 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2507 break;
2508 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2509 PM8001_IO_DBG(pm8001_ha,
2510 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2511 ts->resp = SAS_TASK_COMPLETE;
2512 ts->stat = SAS_OPEN_REJECT;
2513 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2514 break;
2515 default:
2516 PM8001_IO_DBG(pm8001_ha,
2517 pm8001_printk("Unknown status 0x%x\n", status));
2518 ts->resp = SAS_TASK_COMPLETE;
2519 ts->stat = SAS_DEV_NO_RESPONSE;
2520 /* not allowed case. Therefore, return failed status */
2521 break;
2522 }
2523 spin_lock_irqsave(&t->task_state_lock, flags);
2524 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2525 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2526 t->task_state_flags |= SAS_TASK_STATE_DONE;
2527 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2528 spin_unlock_irqrestore(&t->task_state_lock, flags);
2529 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2530 "task 0x%p done with io_status 0x%x resp 0x%x"
2531 "stat 0x%x but aborted by upper layer!\n",
2532 t, status, ts->resp, ts->stat));
2533 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2534 } else {
2535 spin_unlock_irqrestore(&t->task_state_lock, flags);
2536 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2537 mb();/* in order to force CPU ordering */
2538 t->task_done(t);
2539 }
2540}
2541
2542/**
2543 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2544 * @pm8001_ha: our hba card information
2545 * @Qnum: the outbound queue message number.
2546 * @SEA: source of event to ack
2547 * @port_id: port id.
2548 * @phyId: phy id.
2549 * @param0: parameter 0.
2550 * @param1: parameter 1.
2551 */
2552static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2553 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2554{
2555 struct hw_event_ack_req payload;
2556 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2557
2558 struct inbound_queue_table *circularQ;
2559
2560 memset((u8 *)&payload, 0, sizeof(payload));
2561 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2562 payload.tag = cpu_to_le32(1);
2563 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2564 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2565 payload.param0 = cpu_to_le32(param0);
2566 payload.param1 = cpu_to_le32(param1);
2567 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2568}
2569
2570static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2571 u32 phyId, u32 phy_op);
2572
2573/**
2574 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2575 * @pm8001_ha: our hba card information
2576 * @piomb: IO message buffer
2577 */
2578static void
2579hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2580{
2581 struct hw_event_resp *pPayload =
2582 (struct hw_event_resp *)(piomb + 4);
2583 u32 lr_status_evt_portid =
2584 le32_to_cpu(pPayload->lr_status_evt_portid);
2585 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2586
2587 u8 link_rate =
2588 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2589 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2590 u8 phy_id =
2591 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2592 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2593
2594 struct pm8001_port *port = &pm8001_ha->port[port_id];
2595 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2596 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2597 unsigned long flags;
2598 u8 deviceType = pPayload->sas_identify.dev_type;
2599 port->port_state = portstate;
2600 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2601 "portid:%d; phyid:%d; linkrate:%d; "
2602 "portstate:%x; devicetype:%x\n",
2603 port_id, phy_id, link_rate, portstate, deviceType));
2604
2605 switch (deviceType) {
2606 case SAS_PHY_UNUSED:
2607 PM8001_MSG_DBG(pm8001_ha,
2608 pm8001_printk("device type no device.\n"));
2609 break;
2610 case SAS_END_DEVICE:
2611 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2612 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2613 PHY_NOTIFY_ENABLE_SPINUP);
2614 port->port_attached = 1;
2615 pm8001_get_lrate_mode(phy, link_rate);
2616 break;
2617 case SAS_EDGE_EXPANDER_DEVICE:
2618 PM8001_MSG_DBG(pm8001_ha,
2619 pm8001_printk("expander device.\n"));
2620 port->port_attached = 1;
2621 pm8001_get_lrate_mode(phy, link_rate);
2622 break;
2623 case SAS_FANOUT_EXPANDER_DEVICE:
2624 PM8001_MSG_DBG(pm8001_ha,
2625 pm8001_printk("fanout expander device.\n"));
2626 port->port_attached = 1;
2627 pm8001_get_lrate_mode(phy, link_rate);
2628 break;
2629 default:
2630 PM8001_MSG_DBG(pm8001_ha,
2631 pm8001_printk("unknown device type(%x)\n", deviceType));
2632 break;
2633 }
2634 phy->phy_type |= PORT_TYPE_SAS;
2635 phy->identify.device_type = deviceType;
2636 phy->phy_attached = 1;
2637 if (phy->identify.device_type == SAS_END_DEVICE)
2638 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2639 else if (phy->identify.device_type != SAS_PHY_UNUSED)
2640 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2641 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2642 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2643 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2644 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2645 sizeof(struct sas_identify_frame)-4);
2646 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2647 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2648 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2649 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2650 mdelay(200);/*delay a moment to wait disk to spinup*/
2651 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2652}
2653
2654/**
2655 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2656 * @pm8001_ha: our hba card information
2657 * @piomb: IO message buffer
2658 */
2659static void
2660hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2661{
2662 struct hw_event_resp *pPayload =
2663 (struct hw_event_resp *)(piomb + 4);
2664 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2665 u32 lr_status_evt_portid =
2666 le32_to_cpu(pPayload->lr_status_evt_portid);
2667 u8 link_rate =
2668 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2669 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2670 u8 phy_id =
2671 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2672
2673 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2674
2675 struct pm8001_port *port = &pm8001_ha->port[port_id];
2676 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2677 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2678 unsigned long flags;
2679 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2680 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
2681 port_id, phy_id, link_rate, portstate));
2682
2683 port->port_state = portstate;
2684 port->port_attached = 1;
2685 pm8001_get_lrate_mode(phy, link_rate);
2686 phy->phy_type |= PORT_TYPE_SATA;
2687 phy->phy_attached = 1;
2688 phy->sas_phy.oob_mode = SATA_OOB_MODE;
2689 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2690 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2691 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2692 sizeof(struct dev_to_host_fis));
2693 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2694 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]2695 phy->identify.device_type = SAS_SATA_DEV;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2696 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2697 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2698 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2699}
2700
2701/**
2702 * hw_event_phy_down -we should notify the libsas the phy is down.
2703 * @pm8001_ha: our hba card information
2704 * @piomb: IO message buffer
2705 */
2706static void
2707hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
2708{
2709 struct hw_event_resp *pPayload =
2710 (struct hw_event_resp *)(piomb + 4);
2711
2712 u32 lr_status_evt_portid =
2713 le32_to_cpu(pPayload->lr_status_evt_portid);
2714 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2715 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2716 u8 phy_id =
2717 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2718 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2719
2720 struct pm8001_port *port = &pm8001_ha->port[port_id];
2721 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2722 port->port_state = portstate;
2723 phy->phy_type = 0;
2724 phy->identify.device_type = 0;
2725 phy->phy_attached = 0;
2726 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
2727 switch (portstate) {
2728 case PORT_VALID:
2729 break;
2730 case PORT_INVALID:
2731 PM8001_MSG_DBG(pm8001_ha,
2732 pm8001_printk(" PortInvalid portID %d\n", port_id));
2733 PM8001_MSG_DBG(pm8001_ha,
2734 pm8001_printk(" Last phy Down and port invalid\n"));
2735 port->port_attached = 0;
2736 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2737 port_id, phy_id, 0, 0);
2738 break;
2739 case PORT_IN_RESET:
2740 PM8001_MSG_DBG(pm8001_ha,
2741 pm8001_printk(" Port In Reset portID %d\n", port_id));
2742 break;
2743 case PORT_NOT_ESTABLISHED:
2744 PM8001_MSG_DBG(pm8001_ha,
2745 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
2746 port->port_attached = 0;
2747 break;
2748 case PORT_LOSTCOMM:
2749 PM8001_MSG_DBG(pm8001_ha,
2750 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
2751 PM8001_MSG_DBG(pm8001_ha,
2752 pm8001_printk(" Last phy Down and port invalid\n"));
2753 port->port_attached = 0;
2754 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2755 port_id, phy_id, 0, 0);
2756 break;
2757 default:
2758 port->port_attached = 0;
2759 PM8001_MSG_DBG(pm8001_ha,
2760 pm8001_printk(" phy Down and(default) = 0x%x\n",
2761 portstate));
2762 break;
2763
2764 }
2765}
2766
2767static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2768{
2769 struct phy_start_resp *pPayload =
2770 (struct phy_start_resp *)(piomb + 4);
2771 u32 status =
2772 le32_to_cpu(pPayload->status);
2773 u32 phy_id =
2774 le32_to_cpu(pPayload->phyid);
2775 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2776
2777 PM8001_INIT_DBG(pm8001_ha,
2778 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
2779 status, phy_id));
2780 if (status == 0) {
2781 phy->phy_state = 1;
2782 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2783 complete(phy->enable_completion);
2784 }
2785 return 0;
2786
2787}
2788
2789/**
2790 * mpi_thermal_hw_event -The hw event has come.
2791 * @pm8001_ha: our hba card information
2792 * @piomb: IO message buffer
2793 */
2794static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2795{
2796 struct thermal_hw_event *pPayload =
2797 (struct thermal_hw_event *)(piomb + 4);
2798
2799 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
2800 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
2801
2802 if (thermal_event & 0x40) {
2803 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2804 "Thermal Event: Local high temperature violated!\n"));
2805 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2806 "Thermal Event: Measured local high temperature %d\n",
2807 ((rht_lht & 0xFF00) >> 8)));
2808 }
2809 if (thermal_event & 0x10) {
2810 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2811 "Thermal Event: Remote high temperature violated!\n"));
2812 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2813 "Thermal Event: Measured remote high temperature %d\n",
2814 ((rht_lht & 0xFF000000) >> 24)));
2815 }
2816 return 0;
2817}
2818
2819/**
2820 * mpi_hw_event -The hw event has come.
2821 * @pm8001_ha: our hba card information
2822 * @piomb: IO message buffer
2823 */
2824static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2825{
2826 unsigned long flags;
2827 struct hw_event_resp *pPayload =
2828 (struct hw_event_resp *)(piomb + 4);
2829 u32 lr_status_evt_portid =
2830 le32_to_cpu(pPayload->lr_status_evt_portid);
2831 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2832 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2833 u8 phy_id =
2834 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2835 u16 eventType =
2836 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
2837 u8 status =
2838 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
2839
2840 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2841 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2842 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
2843 PM8001_MSG_DBG(pm8001_ha,
2844 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
2845 port_id, phy_id, eventType, status));
2846
2847 switch (eventType) {
2848
2849 case HW_EVENT_SAS_PHY_UP:
2850 PM8001_MSG_DBG(pm8001_ha,
2851 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
2852 hw_event_sas_phy_up(pm8001_ha, piomb);
2853 break;
2854 case HW_EVENT_SATA_PHY_UP:
2855 PM8001_MSG_DBG(pm8001_ha,
2856 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
2857 hw_event_sata_phy_up(pm8001_ha, piomb);
2858 break;
2859 case HW_EVENT_SATA_SPINUP_HOLD:
2860 PM8001_MSG_DBG(pm8001_ha,
2861 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
2862 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
2863 break;
2864 case HW_EVENT_PHY_DOWN:
2865 PM8001_MSG_DBG(pm8001_ha,
2866 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
2867 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
2868 phy->phy_attached = 0;
2869 phy->phy_state = 0;
2870 hw_event_phy_down(pm8001_ha, piomb);
2871 break;
2872 case HW_EVENT_PORT_INVALID:
2873 PM8001_MSG_DBG(pm8001_ha,
2874 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
2875 sas_phy_disconnected(sas_phy);
2876 phy->phy_attached = 0;
2877 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2878 break;
2879 /* the broadcast change primitive received, tell the LIBSAS this event
2880 to revalidate the sas domain*/
2881 case HW_EVENT_BROADCAST_CHANGE:
2882 PM8001_MSG_DBG(pm8001_ha,
2883 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
2884 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
2885 port_id, phy_id, 1, 0);
2886 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2887 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
2888 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2889 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2890 break;
2891 case HW_EVENT_PHY_ERROR:
2892 PM8001_MSG_DBG(pm8001_ha,
2893 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
2894 sas_phy_disconnected(&phy->sas_phy);
2895 phy->phy_attached = 0;
2896 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
2897 break;
2898 case HW_EVENT_BROADCAST_EXP:
2899 PM8001_MSG_DBG(pm8001_ha,
2900 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
2901 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2902 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
2903 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2904 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2905 break;
2906 case HW_EVENT_LINK_ERR_INVALID_DWORD:
2907 PM8001_MSG_DBG(pm8001_ha,
2908 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
2909 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2910 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
2911 sas_phy_disconnected(sas_phy);
2912 phy->phy_attached = 0;
2913 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2914 break;
2915 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
2916 PM8001_MSG_DBG(pm8001_ha,
2917 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
2918 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2919 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
2920 port_id, phy_id, 0, 0);
2921 sas_phy_disconnected(sas_phy);
2922 phy->phy_attached = 0;
2923 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2924 break;
2925 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
2926 PM8001_MSG_DBG(pm8001_ha,
2927 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
2928 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2929 HW_EVENT_LINK_ERR_CODE_VIOLATION,
2930 port_id, phy_id, 0, 0);
2931 sas_phy_disconnected(sas_phy);
2932 phy->phy_attached = 0;
2933 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2934 break;
2935 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
2936 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2937 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
2938 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2939 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
2940 port_id, phy_id, 0, 0);
2941 sas_phy_disconnected(sas_phy);
2942 phy->phy_attached = 0;
2943 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2944 break;
2945 case HW_EVENT_MALFUNCTION:
2946 PM8001_MSG_DBG(pm8001_ha,
2947 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
2948 break;
2949 case HW_EVENT_BROADCAST_SES:
2950 PM8001_MSG_DBG(pm8001_ha,
2951 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
2952 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2953 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
2954 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2955 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2956 break;
2957 case HW_EVENT_INBOUND_CRC_ERROR:
2958 PM8001_MSG_DBG(pm8001_ha,
2959 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
2960 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2961 HW_EVENT_INBOUND_CRC_ERROR,
2962 port_id, phy_id, 0, 0);
2963 break;
2964 case HW_EVENT_HARD_RESET_RECEIVED:
2965 PM8001_MSG_DBG(pm8001_ha,
2966 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
2967 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
2968 break;
2969 case HW_EVENT_ID_FRAME_TIMEOUT:
2970 PM8001_MSG_DBG(pm8001_ha,
2971 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
2972 sas_phy_disconnected(sas_phy);
2973 phy->phy_attached = 0;
2974 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2975 break;
2976 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
2977 PM8001_MSG_DBG(pm8001_ha,
2978 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
2979 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2980 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
2981 port_id, phy_id, 0, 0);
2982 sas_phy_disconnected(sas_phy);
2983 phy->phy_attached = 0;
2984 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2985 break;
2986 case HW_EVENT_PORT_RESET_TIMER_TMO:
2987 PM8001_MSG_DBG(pm8001_ha,
2988 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
2989 sas_phy_disconnected(sas_phy);
2990 phy->phy_attached = 0;
2991 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2992 break;
2993 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
2994 PM8001_MSG_DBG(pm8001_ha,
2995 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2996 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2997 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
2998 port_id, phy_id, 0, 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2999 sas_phy_disconnected(sas_phy);
3000 phy->phy_attached = 0;
3001 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3002 break;
3003 case HW_EVENT_PORT_RECOVER:
3004 PM8001_MSG_DBG(pm8001_ha,
3005 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3006 break;
3007 case HW_EVENT_PORT_RESET_COMPLETE:
3008 PM8001_MSG_DBG(pm8001_ha,
3009 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3010 break;
3011 case EVENT_BROADCAST_ASYNCH_EVENT:
3012 PM8001_MSG_DBG(pm8001_ha,
3013 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3014 break;
3015 default:
3016 PM8001_MSG_DBG(pm8001_ha,
3017 pm8001_printk("Unknown event type 0x%x\n", eventType));
3018 break;
3019 }
3020 return 0;
3021}
3022
3023/**
3024 * mpi_phy_stop_resp - SPCv specific
3025 * @pm8001_ha: our hba card information
3026 * @piomb: IO message buffer
3027 */
3028static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3029{
3030 struct phy_stop_resp *pPayload =
3031 (struct phy_stop_resp *)(piomb + 4);
3032 u32 status =
3033 le32_to_cpu(pPayload->status);
3034 u32 phyid =
3035 le32_to_cpu(pPayload->phyid);
3036 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3037 PM8001_MSG_DBG(pm8001_ha,
3038 pm8001_printk("phy:0x%x status:0x%x\n",
3039 phyid, status));
3040 if (status == 0)
3041 phy->phy_state = 0;
3042 return 0;
3043}
3044
3045/**
3046 * mpi_set_controller_config_resp - SPCv specific
3047 * @pm8001_ha: our hba card information
3048 * @piomb: IO message buffer
3049 */
3050static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3051 void *piomb)
3052{
3053 struct set_ctrl_cfg_resp *pPayload =
3054 (struct set_ctrl_cfg_resp *)(piomb + 4);
3055 u32 status = le32_to_cpu(pPayload->status);
3056 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3057
3058 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3059 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3060 status, err_qlfr_pgcd));
3061
3062 return 0;
3063}
3064
3065/**
3066 * mpi_get_controller_config_resp - SPCv specific
3067 * @pm8001_ha: our hba card information
3068 * @piomb: IO message buffer
3069 */
3070static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3071 void *piomb)
3072{
3073 PM8001_MSG_DBG(pm8001_ha,
3074 pm8001_printk(" pm80xx_addition_functionality\n"));
3075
3076 return 0;
3077}
3078
3079/**
3080 * mpi_get_phy_profile_resp - SPCv specific
3081 * @pm8001_ha: our hba card information
3082 * @piomb: IO message buffer
3083 */
3084static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3085 void *piomb)
3086{
3087 PM8001_MSG_DBG(pm8001_ha,
3088 pm8001_printk(" pm80xx_addition_functionality\n"));
3089
3090 return 0;
3091}
3092
3093/**
3094 * mpi_flash_op_ext_resp - SPCv specific
3095 * @pm8001_ha: our hba card information
3096 * @piomb: IO message buffer
3097 */
3098static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3099{
3100 PM8001_MSG_DBG(pm8001_ha,
3101 pm8001_printk(" pm80xx_addition_functionality\n"));
3102
3103 return 0;
3104}
3105
3106/**
3107 * mpi_set_phy_profile_resp - SPCv specific
3108 * @pm8001_ha: our hba card information
3109 * @piomb: IO message buffer
3110 */
3111static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3112 void *piomb)
3113{
3114 PM8001_MSG_DBG(pm8001_ha,
3115 pm8001_printk(" pm80xx_addition_functionality\n"));
3116
3117 return 0;
3118}
3119
3120/**
3121 * mpi_kek_management_resp - SPCv specific
3122 * @pm8001_ha: our hba card information
3123 * @piomb: IO message buffer
3124 */
3125static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3126 void *piomb)
3127{
3128 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3129
3130 u32 status = le32_to_cpu(pPayload->status);
3131 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3132 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3133
3134 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3135 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3136 status, kidx_new_curr_ksop, err_qlfr));
3137
3138 return 0;
3139}
3140
3141/**
3142 * mpi_dek_management_resp - SPCv specific
3143 * @pm8001_ha: our hba card information
3144 * @piomb: IO message buffer
3145 */
3146static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3147 void *piomb)
3148{
3149 PM8001_MSG_DBG(pm8001_ha,
3150 pm8001_printk(" pm80xx_addition_functionality\n"));
3151
3152 return 0;
3153}
3154
3155/**
3156 * ssp_coalesced_comp_resp - SPCv specific
3157 * @pm8001_ha: our hba card information
3158 * @piomb: IO message buffer
3159 */
3160static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3161 void *piomb)
3162{
3163 PM8001_MSG_DBG(pm8001_ha,
3164 pm8001_printk(" pm80xx_addition_functionality\n"));
3165
3166 return 0;
3167}
3168
3169/**
3170 * process_one_iomb - process one outbound Queue memory block
3171 * @pm8001_ha: our hba card information
3172 * @piomb: IO message buffer
3173 */
3174static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3175{
3176 __le32 pHeader = *(__le32 *)piomb;
3177 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3178
3179 switch (opc) {
3180 case OPC_OUB_ECHO:
3181 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3182 break;
3183 case OPC_OUB_HW_EVENT:
3184 PM8001_MSG_DBG(pm8001_ha,
3185 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3186 mpi_hw_event(pm8001_ha, piomb);
3187 break;
3188 case OPC_OUB_THERM_HW_EVENT:
3189 PM8001_MSG_DBG(pm8001_ha,
3190 pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3191 mpi_thermal_hw_event(pm8001_ha, piomb);
3192 break;
3193 case OPC_OUB_SSP_COMP:
3194 PM8001_MSG_DBG(pm8001_ha,
3195 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3196 mpi_ssp_completion(pm8001_ha, piomb);
3197 break;
3198 case OPC_OUB_SMP_COMP:
3199 PM8001_MSG_DBG(pm8001_ha,
3200 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3201 mpi_smp_completion(pm8001_ha, piomb);
3202 break;
3203 case OPC_OUB_LOCAL_PHY_CNTRL:
3204 PM8001_MSG_DBG(pm8001_ha,
3205 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3206 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3207 break;
3208 case OPC_OUB_DEV_REGIST:
3209 PM8001_MSG_DBG(pm8001_ha,
3210 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3211 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3212 break;
3213 case OPC_OUB_DEREG_DEV:
3214 PM8001_MSG_DBG(pm8001_ha,
Masanari Iida8b513d02013-05-21 23:13:12 +0900[diff] [blame]3215 pm8001_printk("unregister the device\n"));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3216 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3217 break;
3218 case OPC_OUB_GET_DEV_HANDLE:
3219 PM8001_MSG_DBG(pm8001_ha,
3220 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3221 break;
3222 case OPC_OUB_SATA_COMP:
3223 PM8001_MSG_DBG(pm8001_ha,
3224 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3225 mpi_sata_completion(pm8001_ha, piomb);
3226 break;
3227 case OPC_OUB_SATA_EVENT:
3228 PM8001_MSG_DBG(pm8001_ha,
3229 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3230 mpi_sata_event(pm8001_ha, piomb);
3231 break;
3232 case OPC_OUB_SSP_EVENT:
3233 PM8001_MSG_DBG(pm8001_ha,
3234 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3235 mpi_ssp_event(pm8001_ha, piomb);
3236 break;
3237 case OPC_OUB_DEV_HANDLE_ARRIV:
3238 PM8001_MSG_DBG(pm8001_ha,
3239 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3240 /*This is for target*/
3241 break;
3242 case OPC_OUB_SSP_RECV_EVENT:
3243 PM8001_MSG_DBG(pm8001_ha,
3244 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3245 /*This is for target*/
3246 break;
3247 case OPC_OUB_FW_FLASH_UPDATE:
3248 PM8001_MSG_DBG(pm8001_ha,
3249 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3250 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3251 break;
3252 case OPC_OUB_GPIO_RESPONSE:
3253 PM8001_MSG_DBG(pm8001_ha,
3254 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3255 break;
3256 case OPC_OUB_GPIO_EVENT:
3257 PM8001_MSG_DBG(pm8001_ha,
3258 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3259 break;
3260 case OPC_OUB_GENERAL_EVENT:
3261 PM8001_MSG_DBG(pm8001_ha,
3262 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3263 pm8001_mpi_general_event(pm8001_ha, piomb);
3264 break;
3265 case OPC_OUB_SSP_ABORT_RSP:
3266 PM8001_MSG_DBG(pm8001_ha,
3267 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3268 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3269 break;
3270 case OPC_OUB_SATA_ABORT_RSP:
3271 PM8001_MSG_DBG(pm8001_ha,
3272 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3273 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3274 break;
3275 case OPC_OUB_SAS_DIAG_MODE_START_END:
3276 PM8001_MSG_DBG(pm8001_ha,
3277 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3278 break;
3279 case OPC_OUB_SAS_DIAG_EXECUTE:
3280 PM8001_MSG_DBG(pm8001_ha,
3281 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3282 break;
3283 case OPC_OUB_GET_TIME_STAMP:
3284 PM8001_MSG_DBG(pm8001_ha,
3285 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3286 break;
3287 case OPC_OUB_SAS_HW_EVENT_ACK:
3288 PM8001_MSG_DBG(pm8001_ha,
3289 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3290 break;
3291 case OPC_OUB_PORT_CONTROL:
3292 PM8001_MSG_DBG(pm8001_ha,
3293 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3294 break;
3295 case OPC_OUB_SMP_ABORT_RSP:
3296 PM8001_MSG_DBG(pm8001_ha,
3297 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3298 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3299 break;
3300 case OPC_OUB_GET_NVMD_DATA:
3301 PM8001_MSG_DBG(pm8001_ha,
3302 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3303 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3304 break;
3305 case OPC_OUB_SET_NVMD_DATA:
3306 PM8001_MSG_DBG(pm8001_ha,
3307 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3308 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3309 break;
3310 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3311 PM8001_MSG_DBG(pm8001_ha,
3312 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3313 break;
3314 case OPC_OUB_SET_DEVICE_STATE:
3315 PM8001_MSG_DBG(pm8001_ha,
3316 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3317 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3318 break;
3319 case OPC_OUB_GET_DEVICE_STATE:
3320 PM8001_MSG_DBG(pm8001_ha,
3321 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3322 break;
3323 case OPC_OUB_SET_DEV_INFO:
3324 PM8001_MSG_DBG(pm8001_ha,
3325 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3326 break;
3327 /* spcv specifc commands */
3328 case OPC_OUB_PHY_START_RESP:
3329 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3330 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3331 mpi_phy_start_resp(pm8001_ha, piomb);
3332 break;
3333 case OPC_OUB_PHY_STOP_RESP:
3334 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3335 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3336 mpi_phy_stop_resp(pm8001_ha, piomb);
3337 break;
3338 case OPC_OUB_SET_CONTROLLER_CONFIG:
3339 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3340 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3341 mpi_set_controller_config_resp(pm8001_ha, piomb);
3342 break;
3343 case OPC_OUB_GET_CONTROLLER_CONFIG:
3344 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3345 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3346 mpi_get_controller_config_resp(pm8001_ha, piomb);
3347 break;
3348 case OPC_OUB_GET_PHY_PROFILE:
3349 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3350 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3351 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3352 break;
3353 case OPC_OUB_FLASH_OP_EXT:
3354 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3355 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3356 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3357 break;
3358 case OPC_OUB_SET_PHY_PROFILE:
3359 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3360 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3361 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3362 break;
3363 case OPC_OUB_KEK_MANAGEMENT_RESP:
3364 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3365 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3366 mpi_kek_management_resp(pm8001_ha, piomb);
3367 break;
3368 case OPC_OUB_DEK_MANAGEMENT_RESP:
3369 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3370 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3371 mpi_dek_management_resp(pm8001_ha, piomb);
3372 break;
3373 case OPC_OUB_SSP_COALESCED_COMP_RESP:
3374 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3375 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3376 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3377 break;
3378 default:
3379 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3380 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3381 break;
3382 }
3383}
3384
3385static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3386{
3387 struct outbound_queue_table *circularQ;
3388 void *pMsg1 = NULL;
3389 u8 uninitialized_var(bc);
3390 u32 ret = MPI_IO_STATUS_FAIL;
3391 unsigned long flags;
3392
3393 spin_lock_irqsave(&pm8001_ha->lock, flags);
3394 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3395 do {
3396 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3397 if (MPI_IO_STATUS_SUCCESS == ret) {
3398 /* process the outbound message */
3399 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3400 /* free the message from the outbound circular buffer */
3401 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3402 circularQ, bc);
3403 }
3404 if (MPI_IO_STATUS_BUSY == ret) {
3405 /* Update the producer index from SPC */
3406 circularQ->producer_index =
3407 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3408 if (le32_to_cpu(circularQ->producer_index) ==
3409 circularQ->consumer_idx)
3410 /* OQ is empty */
3411 break;
3412 }
3413 } while (1);
3414 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3415 return ret;
3416}
3417
3418/* PCI_DMA_... to our direction translation. */
3419static const u8 data_dir_flags[] = {
3420 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3421 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3422 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3423 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3424};
3425
3426static void build_smp_cmd(u32 deviceID, __le32 hTag,
3427 struct smp_req *psmp_cmd, int mode, int length)
3428{
3429 psmp_cmd->tag = hTag;
3430 psmp_cmd->device_id = cpu_to_le32(deviceID);
3431 if (mode == SMP_DIRECT) {
3432 length = length - 4; /* subtract crc */
3433 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3434 } else {
3435 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3436 }
3437}
3438
3439/**
3440 * pm8001_chip_smp_req - send a SMP task to FW
3441 * @pm8001_ha: our hba card information.
3442 * @ccb: the ccb information this request used.
3443 */
3444static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3445 struct pm8001_ccb_info *ccb)
3446{
3447 int elem, rc;
3448 struct sas_task *task = ccb->task;
3449 struct domain_device *dev = task->dev;
3450 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3451 struct scatterlist *sg_req, *sg_resp;
3452 u32 req_len, resp_len;
3453 struct smp_req smp_cmd;
3454 u32 opc;
3455 struct inbound_queue_table *circularQ;
3456 char *preq_dma_addr = NULL;
3457 __le64 tmp_addr;
3458 u32 i, length;
3459
3460 memset(&smp_cmd, 0, sizeof(smp_cmd));
3461 /*
3462 * DMA-map SMP request, response buffers
3463 */
3464 sg_req = &task->smp_task.smp_req;
3465 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3466 if (!elem)
3467 return -ENOMEM;
3468 req_len = sg_dma_len(sg_req);
3469
3470 sg_resp = &task->smp_task.smp_resp;
3471 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3472 if (!elem) {
3473 rc = -ENOMEM;
3474 goto err_out;
3475 }
3476 resp_len = sg_dma_len(sg_resp);
3477 /* must be in dwords */
3478 if ((req_len & 0x3) || (resp_len & 0x3)) {
3479 rc = -EINVAL;
3480 goto err_out_2;
3481 }
3482
3483 opc = OPC_INB_SMP_REQUEST;
3484 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3485 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3486
3487 length = sg_req->length;
3488 PM8001_IO_DBG(pm8001_ha,
3489 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3490 if (!(length - 8))
3491 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3492 else
3493 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3494
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3495
3496 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3497 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3498
3499 /* INDIRECT MODE command settings. Use DMA */
3500 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3501 PM8001_IO_DBG(pm8001_ha,
3502 pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3503 /* for SPCv indirect mode. Place the top 4 bytes of
3504 * SMP Request header here. */
3505 for (i = 0; i < 4; i++)
3506 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3507 /* exclude top 4 bytes for SMP req header */
3508 smp_cmd.long_smp_req.long_req_addr =
3509 cpu_to_le64((u64)sg_dma_address
Anand Kumar Santhanamcb993e52013-09-17 14:37:14 +0530[diff] [blame]3510 (&task->smp_task.smp_req) + 4);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3511 /* exclude 4 bytes for SMP req header and CRC */
3512 smp_cmd.long_smp_req.long_req_size =
3513 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3514 smp_cmd.long_smp_req.long_resp_addr =
3515 cpu_to_le64((u64)sg_dma_address
3516 (&task->smp_task.smp_resp));
3517 smp_cmd.long_smp_req.long_resp_size =
3518 cpu_to_le32((u32)sg_dma_len
3519 (&task->smp_task.smp_resp)-4);
3520 } else { /* DIRECT MODE */
3521 smp_cmd.long_smp_req.long_req_addr =
3522 cpu_to_le64((u64)sg_dma_address
3523 (&task->smp_task.smp_req));
3524 smp_cmd.long_smp_req.long_req_size =
3525 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3526 smp_cmd.long_smp_req.long_resp_addr =
3527 cpu_to_le64((u64)sg_dma_address
3528 (&task->smp_task.smp_resp));
3529 smp_cmd.long_smp_req.long_resp_size =
3530 cpu_to_le32
3531 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3532 }
3533 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3534 PM8001_IO_DBG(pm8001_ha,
3535 pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3536 for (i = 0; i < length; i++)
3537 if (i < 16) {
3538 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3539 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3540 "Byte[%d]:%x (DMA data:%x)\n",
3541 i, smp_cmd.smp_req16[i],
3542 *(preq_dma_addr)));
3543 } else {
3544 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3545 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3546 "Byte[%d]:%x (DMA data:%x)\n",
3547 i, smp_cmd.smp_req[i],
3548 *(preq_dma_addr)));
3549 }
3550 }
3551
3552 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3553 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3554 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0);
3555 return 0;
3556
3557err_out_2:
3558 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3559 PCI_DMA_FROMDEVICE);
3560err_out:
3561 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3562 PCI_DMA_TODEVICE);
3563 return rc;
3564}
3565
3566static int check_enc_sas_cmd(struct sas_task *task)
3567{
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]3568 u8 cmd = task->ssp_task.cmd->cmnd[0];
3569
3570 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3571 return 1;
3572 else
3573 return 0;
3574}
3575
3576static int check_enc_sat_cmd(struct sas_task *task)
3577{
3578 int ret = 0;
3579 switch (task->ata_task.fis.command) {
3580 case ATA_CMD_FPDMA_READ:
3581 case ATA_CMD_READ_EXT:
3582 case ATA_CMD_READ:
3583 case ATA_CMD_FPDMA_WRITE:
3584 case ATA_CMD_WRITE_EXT:
3585 case ATA_CMD_WRITE:
3586 case ATA_CMD_PIO_READ:
3587 case ATA_CMD_PIO_READ_EXT:
3588 case ATA_CMD_PIO_WRITE:
3589 case ATA_CMD_PIO_WRITE_EXT:
3590 ret = 1;
3591 break;
3592 default:
3593 ret = 0;
3594 break;
3595 }
3596 return ret;
3597}
3598
3599/**
3600 * pm80xx_chip_ssp_io_req - send a SSP task to FW
3601 * @pm8001_ha: our hba card information.
3602 * @ccb: the ccb information this request used.
3603 */
3604static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3605 struct pm8001_ccb_info *ccb)
3606{
3607 struct sas_task *task = ccb->task;
3608 struct domain_device *dev = task->dev;
3609 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3610 struct ssp_ini_io_start_req ssp_cmd;
3611 u32 tag = ccb->ccb_tag;
3612 int ret;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame^]3613 u64 phys_addr, start_addr, end_addr;
3614 u32 end_addr_high, end_addr_low;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3615 struct inbound_queue_table *circularQ;
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]3616 u32 q_index;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3617 u32 opc = OPC_INB_SSPINIIOSTART;
3618 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3619 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3620 /* data address domain added for spcv; set to 0 by host,
3621 * used internally by controller
3622 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
3623 */
3624 ssp_cmd.dad_dir_m_tlr =
3625 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
3626 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3627 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3628 ssp_cmd.tag = cpu_to_le32(tag);
3629 if (task->ssp_task.enable_first_burst)
3630 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3631 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3632 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]3633 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
3634 task->ssp_task.cmd->cmd_len);
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]3635 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
3636 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3637
3638 /* Check if encryption is set */
3639 if (pm8001_ha->chip->encrypt &&
3640 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
3641 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3642 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]3643 task->ssp_task.cmd->cmnd[0]));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3644 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
3645 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
3646 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
3647 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
3648
3649 /* fill in PRD (scatter/gather) table, if any */
3650 if (task->num_scatter > 1) {
3651 pm8001_chip_make_sg(task->scatter,
3652 ccb->n_elem, ccb->buf_prd);
3653 phys_addr = ccb->ccb_dma_handle +
3654 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3655 ssp_cmd.enc_addr_low =
3656 cpu_to_le32(lower_32_bits(phys_addr));
3657 ssp_cmd.enc_addr_high =
3658 cpu_to_le32(upper_32_bits(phys_addr));
3659 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3660 } else if (task->num_scatter == 1) {
3661 u64 dma_addr = sg_dma_address(task->scatter);
3662 ssp_cmd.enc_addr_low =
3663 cpu_to_le32(lower_32_bits(dma_addr));
3664 ssp_cmd.enc_addr_high =
3665 cpu_to_le32(upper_32_bits(dma_addr));
3666 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3667 ssp_cmd.enc_esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame^]3668 /* Check 4G Boundary */
3669 start_addr = cpu_to_le64(dma_addr);
3670 end_addr = (start_addr + ssp_cmd.enc_len) - 1;
3671 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3672 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3673 if (end_addr_high != ssp_cmd.enc_addr_high) {
3674 PM8001_FAIL_DBG(pm8001_ha,
3675 pm8001_printk("The sg list address "
3676 "start_addr=0x%016llx data_len=0x%x "
3677 "end_addr_high=0x%08x end_addr_low="
3678 "0x%08x has crossed 4G boundary\n",
3679 start_addr, ssp_cmd.enc_len,
3680 end_addr_high, end_addr_low));
3681 pm8001_chip_make_sg(task->scatter, 1,
3682 ccb->buf_prd);
3683 phys_addr = ccb->ccb_dma_handle +
3684 offsetof(struct pm8001_ccb_info,
3685 buf_prd[0]);
3686 ssp_cmd.enc_addr_low =
3687 cpu_to_le32(lower_32_bits(phys_addr));
3688 ssp_cmd.enc_addr_high =
3689 cpu_to_le32(upper_32_bits(phys_addr));
3690 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3691 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3692 } else if (task->num_scatter == 0) {
3693 ssp_cmd.enc_addr_low = 0;
3694 ssp_cmd.enc_addr_high = 0;
3695 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3696 ssp_cmd.enc_esgl = 0;
3697 }
3698 /* XTS mode. All other fields are 0 */
3699 ssp_cmd.key_cmode = 0x6 << 4;
3700 /* set tweak values. Should be the start lba */
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]3701 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
3702 (task->ssp_task.cmd->cmnd[3] << 16) |
3703 (task->ssp_task.cmd->cmnd[4] << 8) |
3704 (task->ssp_task.cmd->cmnd[5]));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3705 } else {
3706 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3707 "Sending Normal SAS command 0x%x inb q %x\n",
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]3708 task->ssp_task.cmd->cmnd[0], q_index));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3709 /* fill in PRD (scatter/gather) table, if any */
3710 if (task->num_scatter > 1) {
3711 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
3712 ccb->buf_prd);
3713 phys_addr = ccb->ccb_dma_handle +
3714 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3715 ssp_cmd.addr_low =
3716 cpu_to_le32(lower_32_bits(phys_addr));
3717 ssp_cmd.addr_high =
3718 cpu_to_le32(upper_32_bits(phys_addr));
3719 ssp_cmd.esgl = cpu_to_le32(1<<31);
3720 } else if (task->num_scatter == 1) {
3721 u64 dma_addr = sg_dma_address(task->scatter);
3722 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
3723 ssp_cmd.addr_high =
3724 cpu_to_le32(upper_32_bits(dma_addr));
3725 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3726 ssp_cmd.esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame^]3727 /* Check 4G Boundary */
3728 start_addr = cpu_to_le64(dma_addr);
3729 end_addr = (start_addr + ssp_cmd.len) - 1;
3730 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3731 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3732 if (end_addr_high != ssp_cmd.addr_high) {
3733 PM8001_FAIL_DBG(pm8001_ha,
3734 pm8001_printk("The sg list address "
3735 "start_addr=0x%016llx data_len=0x%x "
3736 "end_addr_high=0x%08x end_addr_low="
3737 "0x%08x has crossed 4G boundary\n",
3738 start_addr, ssp_cmd.len,
3739 end_addr_high, end_addr_low));
3740 pm8001_chip_make_sg(task->scatter, 1,
3741 ccb->buf_prd);
3742 phys_addr = ccb->ccb_dma_handle +
3743 offsetof(struct pm8001_ccb_info,
3744 buf_prd[0]);
3745 ssp_cmd.addr_low =
3746 cpu_to_le32(lower_32_bits(phys_addr));
3747 ssp_cmd.addr_high =
3748 cpu_to_le32(upper_32_bits(phys_addr));
3749 ssp_cmd.esgl = cpu_to_le32(1<<31);
3750 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3751 } else if (task->num_scatter == 0) {
3752 ssp_cmd.addr_low = 0;
3753 ssp_cmd.addr_high = 0;
3754 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3755 ssp_cmd.esgl = 0;
3756 }
3757 }
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]3758 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
3759 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
3760 &ssp_cmd, q_index);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3761 return ret;
3762}
3763
3764static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
3765 struct pm8001_ccb_info *ccb)
3766{
3767 struct sas_task *task = ccb->task;
3768 struct domain_device *dev = task->dev;
3769 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
3770 u32 tag = ccb->ccb_tag;
3771 int ret;
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]3772 u32 q_index;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3773 struct sata_start_req sata_cmd;
3774 u32 hdr_tag, ncg_tag = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame^]3775 u64 phys_addr, start_addr, end_addr;
3776 u32 end_addr_high, end_addr_low;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3777 u32 ATAP = 0x0;
3778 u32 dir;
3779 struct inbound_queue_table *circularQ;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]3780 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3781 u32 opc = OPC_INB_SATA_HOST_OPSTART;
3782 memset(&sata_cmd, 0, sizeof(sata_cmd));
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]3783 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
3784 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3785
3786 if (task->data_dir == PCI_DMA_NONE) {
3787 ATAP = 0x04; /* no data*/
3788 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
3789 } else if (likely(!task->ata_task.device_control_reg_update)) {
3790 if (task->ata_task.dma_xfer) {
3791 ATAP = 0x06; /* DMA */
3792 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
3793 } else {
3794 ATAP = 0x05; /* PIO*/
3795 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
3796 }
3797 if (task->ata_task.use_ncq &&
3798 dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
3799 ATAP = 0x07; /* FPDMA */
3800 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
3801 }
3802 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]3803 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
3804 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3805 ncg_tag = hdr_tag;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]3806 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3807 dir = data_dir_flags[task->data_dir] << 8;
3808 sata_cmd.tag = cpu_to_le32(tag);
3809 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
3810 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3811
3812 sata_cmd.sata_fis = task->ata_task.fis;
3813 if (likely(!task->ata_task.device_control_reg_update))
3814 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
3815 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
3816
3817 /* Check if encryption is set */
3818 if (pm8001_ha->chip->encrypt &&
3819 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
3820 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3821 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
3822 sata_cmd.sata_fis.command));
3823 opc = OPC_INB_SATA_DIF_ENC_IO;
3824
3825 /* set encryption bit */
3826 sata_cmd.ncqtag_atap_dir_m_dad =
3827 cpu_to_le32(((ncg_tag & 0xff)<<16)|
3828 ((ATAP & 0x3f) << 10) | 0x20 | dir);
3829 /* dad (bit 0-1) is 0 */
3830 /* fill in PRD (scatter/gather) table, if any */
3831 if (task->num_scatter > 1) {
3832 pm8001_chip_make_sg(task->scatter,
3833 ccb->n_elem, ccb->buf_prd);
3834 phys_addr = ccb->ccb_dma_handle +
3835 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3836 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
3837 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
3838 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
3839 } else if (task->num_scatter == 1) {
3840 u64 dma_addr = sg_dma_address(task->scatter);
3841 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
3842 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
3843 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3844 sata_cmd.enc_esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame^]3845 /* Check 4G Boundary */
3846 start_addr = cpu_to_le64(dma_addr);
3847 end_addr = (start_addr + sata_cmd.enc_len) - 1;
3848 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3849 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3850 if (end_addr_high != sata_cmd.enc_addr_high) {
3851 PM8001_FAIL_DBG(pm8001_ha,
3852 pm8001_printk("The sg list address "
3853 "start_addr=0x%016llx data_len=0x%x "
3854 "end_addr_high=0x%08x end_addr_low"
3855 "=0x%08x has crossed 4G boundary\n",
3856 start_addr, sata_cmd.enc_len,
3857 end_addr_high, end_addr_low));
3858 pm8001_chip_make_sg(task->scatter, 1,
3859 ccb->buf_prd);
3860 phys_addr = ccb->ccb_dma_handle +
3861 offsetof(struct pm8001_ccb_info,
3862 buf_prd[0]);
3863 sata_cmd.enc_addr_low =
3864 lower_32_bits(phys_addr);
3865 sata_cmd.enc_addr_high =
3866 upper_32_bits(phys_addr);
3867 sata_cmd.enc_esgl =
3868 cpu_to_le32(1 << 31);
3869 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3870 } else if (task->num_scatter == 0) {
3871 sata_cmd.enc_addr_low = 0;
3872 sata_cmd.enc_addr_high = 0;
3873 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3874 sata_cmd.enc_esgl = 0;
3875 }
3876 /* XTS mode. All other fields are 0 */
3877 sata_cmd.key_index_mode = 0x6 << 4;
3878 /* set tweak values. Should be the start lba */
3879 sata_cmd.twk_val0 =
3880 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
3881 (sata_cmd.sata_fis.lbah << 16) |
3882 (sata_cmd.sata_fis.lbam << 8) |
3883 (sata_cmd.sata_fis.lbal));
3884 sata_cmd.twk_val1 =
3885 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
3886 (sata_cmd.sata_fis.lbam_exp));
3887 } else {
3888 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3889 "Sending Normal SATA command 0x%x inb %x\n",
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]3890 sata_cmd.sata_fis.command, q_index));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3891 /* dad (bit 0-1) is 0 */
3892 sata_cmd.ncqtag_atap_dir_m_dad =
3893 cpu_to_le32(((ncg_tag & 0xff)<<16) |
3894 ((ATAP & 0x3f) << 10) | dir);
3895
3896 /* fill in PRD (scatter/gather) table, if any */
3897 if (task->num_scatter > 1) {
3898 pm8001_chip_make_sg(task->scatter,
3899 ccb->n_elem, ccb->buf_prd);
3900 phys_addr = ccb->ccb_dma_handle +
3901 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3902 sata_cmd.addr_low = lower_32_bits(phys_addr);
3903 sata_cmd.addr_high = upper_32_bits(phys_addr);
3904 sata_cmd.esgl = cpu_to_le32(1 << 31);
3905 } else if (task->num_scatter == 1) {
3906 u64 dma_addr = sg_dma_address(task->scatter);
3907 sata_cmd.addr_low = lower_32_bits(dma_addr);
3908 sata_cmd.addr_high = upper_32_bits(dma_addr);
3909 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3910 sata_cmd.esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame^]3911 /* Check 4G Boundary */
3912 start_addr = cpu_to_le64(dma_addr);
3913 end_addr = (start_addr + sata_cmd.len) - 1;
3914 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3915 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3916 if (end_addr_high != sata_cmd.addr_high) {
3917 PM8001_FAIL_DBG(pm8001_ha,
3918 pm8001_printk("The sg list address "
3919 "start_addr=0x%016llx data_len=0x%x"
3920 "end_addr_high=0x%08x end_addr_low="
3921 "0x%08x has crossed 4G boundary\n",
3922 start_addr, sata_cmd.len,
3923 end_addr_high, end_addr_low));
3924 pm8001_chip_make_sg(task->scatter, 1,
3925 ccb->buf_prd);
3926 phys_addr = ccb->ccb_dma_handle +
3927 offsetof(struct pm8001_ccb_info,
3928 buf_prd[0]);
3929 sata_cmd.addr_low =
3930 lower_32_bits(phys_addr);
3931 sata_cmd.addr_high =
3932 upper_32_bits(phys_addr);
3933 sata_cmd.esgl = cpu_to_le32(1 << 31);
3934 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3935 } else if (task->num_scatter == 0) {
3936 sata_cmd.addr_low = 0;
3937 sata_cmd.addr_high = 0;
3938 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3939 sata_cmd.esgl = 0;
3940 }
3941 /* scsi cdb */
3942 sata_cmd.atapi_scsi_cdb[0] =
3943 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
3944 (task->ata_task.atapi_packet[1] << 8) |
3945 (task->ata_task.atapi_packet[2] << 16) |
3946 (task->ata_task.atapi_packet[3] << 24)));
3947 sata_cmd.atapi_scsi_cdb[1] =
3948 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
3949 (task->ata_task.atapi_packet[5] << 8) |
3950 (task->ata_task.atapi_packet[6] << 16) |
3951 (task->ata_task.atapi_packet[7] << 24)));
3952 sata_cmd.atapi_scsi_cdb[2] =
3953 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
3954 (task->ata_task.atapi_packet[9] << 8) |
3955 (task->ata_task.atapi_packet[10] << 16) |
3956 (task->ata_task.atapi_packet[11] << 24)));
3957 sata_cmd.atapi_scsi_cdb[3] =
3958 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
3959 (task->ata_task.atapi_packet[13] << 8) |
3960 (task->ata_task.atapi_packet[14] << 16) |
3961 (task->ata_task.atapi_packet[15] << 24)));
3962 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]3963
3964 /* Check for read log for failed drive and return */
3965 if (sata_cmd.sata_fis.command == 0x2f) {
3966 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
3967 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
3968 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
3969 struct task_status_struct *ts;
3970
3971 pm8001_ha_dev->id &= 0xDFFFFFFF;
3972 ts = &task->task_status;
3973
3974 spin_lock_irqsave(&task->task_state_lock, flags);
3975 ts->resp = SAS_TASK_COMPLETE;
3976 ts->stat = SAM_STAT_GOOD;
3977 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3978 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3979 task->task_state_flags |= SAS_TASK_STATE_DONE;
3980 if (unlikely((task->task_state_flags &
3981 SAS_TASK_STATE_ABORTED))) {
3982 spin_unlock_irqrestore(&task->task_state_lock,
3983 flags);
3984 PM8001_FAIL_DBG(pm8001_ha,
3985 pm8001_printk("task 0x%p resp 0x%x "
3986 " stat 0x%x but aborted by upper layer "
3987 "\n", task, ts->resp, ts->stat));
3988 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
3989 return 0;
3990 } else if (task->uldd_task) {
3991 spin_unlock_irqrestore(&task->task_state_lock,
3992 flags);
3993 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
3994 mb();/* ditto */
3995 spin_unlock_irq(&pm8001_ha->lock);
3996 task->task_done(task);
3997 spin_lock_irq(&pm8001_ha->lock);
3998 return 0;
3999 } else if (!task->uldd_task) {
4000 spin_unlock_irqrestore(&task->task_state_lock,
4001 flags);
4002 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4003 mb();/*ditto*/
4004 spin_unlock_irq(&pm8001_ha->lock);
4005 task->task_done(task);
4006 spin_lock_irq(&pm8001_ha->lock);
4007 return 0;
4008 }
4009 }
4010 }
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4011 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4012 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4013 &sata_cmd, q_index);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4014 return ret;
4015}
4016
4017/**
4018 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4019 * @pm8001_ha: our hba card information.
4020 * @num: the inbound queue number
4021 * @phy_id: the phy id which we wanted to start up.
4022 */
4023static int
4024pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4025{
4026 struct phy_start_req payload;
4027 struct inbound_queue_table *circularQ;
4028 int ret;
4029 u32 tag = 0x01;
4030 u32 opcode = OPC_INB_PHYSTART;
4031 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4032 memset(&payload, 0, sizeof(payload));
4033 payload.tag = cpu_to_le32(tag);
4034
4035 PM8001_INIT_DBG(pm8001_ha,
4036 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4037 /*
4038 ** [0:7] PHY Identifier
4039 ** [8:11] link rate 1.5G, 3G, 6G
4040 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
4041 ** [14] 0b disable spin up hold; 1b enable spin up hold
4042 ** [15] ob no change in current PHY analig setup 1b enable using SPAST
4043 */
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]4044 if (!IS_SPCV_12G(pm8001_ha->pdev))
4045 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4046 LINKMODE_AUTO | LINKRATE_15 |
4047 LINKRATE_30 | LINKRATE_60 | phy_id);
4048 else
4049 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4050 LINKMODE_AUTO | LINKRATE_15 |
4051 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 |
4052 phy_id);
4053
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4054 /* SSC Disable and SAS Analog ST configuration */
4055 /**
4056 payload.ase_sh_lm_slr_phyid =
4057 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4058 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4059 phy_id);
4060 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4061 **/
4062
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]4063 payload.sas_identify.dev_type = SAS_END_DEVICE;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4064 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4065 memcpy(payload.sas_identify.sas_addr,
4066 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4067 payload.sas_identify.phy_id = phy_id;
4068 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4069 return ret;
4070}
4071
4072/**
4073 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4074 * @pm8001_ha: our hba card information.
4075 * @num: the inbound queue number
4076 * @phy_id: the phy id which we wanted to start up.
4077 */
4078static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4079 u8 phy_id)
4080{
4081 struct phy_stop_req payload;
4082 struct inbound_queue_table *circularQ;
4083 int ret;
4084 u32 tag = 0x01;
4085 u32 opcode = OPC_INB_PHYSTOP;
4086 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4087 memset(&payload, 0, sizeof(payload));
4088 payload.tag = cpu_to_le32(tag);
4089 payload.phy_id = cpu_to_le32(phy_id);
4090 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4091 return ret;
4092}
4093
4094/**
4095 * see comments on pm8001_mpi_reg_resp.
4096 */
4097static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4098 struct pm8001_device *pm8001_dev, u32 flag)
4099{
4100 struct reg_dev_req payload;
4101 u32 opc;
4102 u32 stp_sspsmp_sata = 0x4;
4103 struct inbound_queue_table *circularQ;
4104 u32 linkrate, phy_id;
4105 int rc, tag = 0xdeadbeef;
4106 struct pm8001_ccb_info *ccb;
4107 u8 retryFlag = 0x1;
4108 u16 firstBurstSize = 0;
4109 u16 ITNT = 2000;
4110 struct domain_device *dev = pm8001_dev->sas_device;
4111 struct domain_device *parent_dev = dev->parent;
4112 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4113
4114 memset(&payload, 0, sizeof(payload));
4115 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4116 if (rc)
4117 return rc;
4118 ccb = &pm8001_ha->ccb_info[tag];
4119 ccb->device = pm8001_dev;
4120 ccb->ccb_tag = tag;
4121 payload.tag = cpu_to_le32(tag);
4122
4123 if (flag == 1) {
4124 stp_sspsmp_sata = 0x02; /*direct attached sata */
4125 } else {
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]4126 if (pm8001_dev->dev_type == SAS_SATA_DEV)
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4127 stp_sspsmp_sata = 0x00; /* stp*/
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]4128 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4129 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4130 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4131 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4132 }
4133 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4134 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4135 else
4136 phy_id = pm8001_dev->attached_phy;
4137
4138 opc = OPC_INB_REG_DEV;
4139
4140 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4141 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4142
4143 payload.phyid_portid =
4144 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4145 ((phy_id & 0xFF) << 8));
4146
4147 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4148 ((linkrate & 0x0F) << 24) |
4149 ((stp_sspsmp_sata & 0x03) << 28));
4150 payload.firstburstsize_ITNexustimeout =
4151 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4152
4153 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4154 SAS_ADDR_SIZE);
4155
4156 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4157
4158 return rc;
4159}
4160
4161/**
4162 * pm80xx_chip_phy_ctl_req - support the local phy operation
4163 * @pm8001_ha: our hba card information.
4164 * @num: the inbound queue number
4165 * @phy_id: the phy id which we wanted to operate
4166 * @phy_op:
4167 */
4168static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4169 u32 phyId, u32 phy_op)
4170{
4171 struct local_phy_ctl_req payload;
4172 struct inbound_queue_table *circularQ;
4173 int ret;
4174 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4175 memset(&payload, 0, sizeof(payload));
4176 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4177 payload.tag = cpu_to_le32(1);
4178 payload.phyop_phyid =
4179 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4180 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4181 return ret;
4182}
4183
4184static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4185{
4186 u32 value;
4187#ifdef PM8001_USE_MSIX
4188 return 1;
4189#endif
4190 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4191 if (value)
4192 return 1;
4193 return 0;
4194
4195}
4196
4197/**
4198 * pm8001_chip_isr - PM8001 isr handler.
4199 * @pm8001_ha: our hba card information.
4200 * @irq: irq number.
4201 * @stat: stat.
4202 */
4203static irqreturn_t
4204pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4205{
4206 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4207 process_oq(pm8001_ha, vec);
4208 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4209 return IRQ_HANDLED;
4210}
4211
4212const struct pm8001_dispatch pm8001_80xx_dispatch = {
4213 .name = "pmc80xx",
4214 .chip_init = pm80xx_chip_init,
4215 .chip_soft_rst = pm80xx_chip_soft_rst,
4216 .chip_rst = pm80xx_hw_chip_rst,
4217 .chip_iounmap = pm8001_chip_iounmap,
4218 .isr = pm80xx_chip_isr,
4219 .is_our_interupt = pm80xx_chip_is_our_interupt,
4220 .isr_process_oq = process_oq,
4221 .interrupt_enable = pm80xx_chip_interrupt_enable,
4222 .interrupt_disable = pm80xx_chip_interrupt_disable,
4223 .make_prd = pm8001_chip_make_sg,
4224 .smp_req = pm80xx_chip_smp_req,
4225 .ssp_io_req = pm80xx_chip_ssp_io_req,
4226 .sata_req = pm80xx_chip_sata_req,
4227 .phy_start_req = pm80xx_chip_phy_start_req,
4228 .phy_stop_req = pm80xx_chip_phy_stop_req,
4229 .reg_dev_req = pm80xx_chip_reg_dev_req,
4230 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4231 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
4232 .task_abort = pm8001_chip_abort_task,
4233 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4234 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4235 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4236 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4237 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4238};