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Sarah Sharp74c68742009-04-27 19:52:22 -07001/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include "xhci.h"
24
25#define XHCI_INIT_VALUE 0x0
26
27/* Add verbose debugging later, just print everything for now */
28
29void xhci_dbg_regs(struct xhci_hcd *xhci)
30{
31 u32 temp;
32
33 xhci_dbg(xhci, "// xHCI capability registers at 0x%x:\n",
34 (unsigned int) xhci->cap_regs);
35 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
36 xhci_dbg(xhci, "// @%x = 0x%x (CAPLENGTH AND HCIVERSION)\n",
37 (unsigned int) &xhci->cap_regs->hc_capbase,
38 (unsigned int) temp);
39 xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n",
40 (unsigned int) HC_LENGTH(temp));
41#if 0
42 xhci_dbg(xhci, "// HCIVERSION: 0x%x\n",
43 (unsigned int) HC_VERSION(temp));
44#endif
45
46 xhci_dbg(xhci, "// xHCI operational registers at 0x%x:\n",
47 (unsigned int) xhci->op_regs);
48
49 temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
50 xhci_dbg(xhci, "// @%x = 0x%x RTSOFF\n",
51 (unsigned int) &xhci->cap_regs->run_regs_off,
52 (unsigned int) temp & RTSOFF_MASK);
53 xhci_dbg(xhci, "// xHCI runtime registers at 0x%x:\n",
54 (unsigned int) xhci->run_regs);
55
56 temp = xhci_readl(xhci, &xhci->cap_regs->db_off);
57 xhci_dbg(xhci, "// @%x = 0x%x DBOFF\n",
58 (unsigned int) &xhci->cap_regs->db_off, temp);
Sarah Sharp0ebbab32009-04-27 19:52:34 -070059 xhci_dbg(xhci, "// Doorbell array at 0x%x:\n",
60 (unsigned int) xhci->dba);
Sarah Sharp74c68742009-04-27 19:52:22 -070061}
62
63void xhci_print_cap_regs(struct xhci_hcd *xhci)
64{
65 u32 temp;
66
67 xhci_dbg(xhci, "xHCI capability registers at 0x%x:\n",
68 (unsigned int) xhci->cap_regs);
69
70 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
71 xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
72 (unsigned int) temp);
73 xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
74 (unsigned int) HC_LENGTH(temp));
75 xhci_dbg(xhci, "HCIVERSION: 0x%x\n",
76 (unsigned int) HC_VERSION(temp));
77
78 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
79 xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
80 (unsigned int) temp);
81 xhci_dbg(xhci, " Max device slots: %u\n",
82 (unsigned int) HCS_MAX_SLOTS(temp));
83 xhci_dbg(xhci, " Max interrupters: %u\n",
84 (unsigned int) HCS_MAX_INTRS(temp));
85 xhci_dbg(xhci, " Max ports: %u\n",
86 (unsigned int) HCS_MAX_PORTS(temp));
87
88 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
89 xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
90 (unsigned int) temp);
91 xhci_dbg(xhci, " Isoc scheduling threshold: %u\n",
92 (unsigned int) HCS_IST(temp));
93 xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n",
94 (unsigned int) HCS_ERST_MAX(temp));
95
96 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
97 xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
98 (unsigned int) temp);
99 xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n",
100 (unsigned int) HCS_U1_LATENCY(temp));
101 xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n",
102 (unsigned int) HCS_U2_LATENCY(temp));
103
104 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
105 xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
106 xhci_dbg(xhci, " HC generates %s bit addresses\n",
107 HCC_64BIT_ADDR(temp) ? "64" : "32");
108 /* FIXME */
109 xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n");
110
111 temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
112 xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
113}
114
115void xhci_print_command_reg(struct xhci_hcd *xhci)
116{
117 u32 temp;
118
119 temp = xhci_readl(xhci, &xhci->op_regs->command);
120 xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
121 xhci_dbg(xhci, " HC is %s\n",
122 (temp & CMD_RUN) ? "running" : "being stopped");
123 xhci_dbg(xhci, " HC has %sfinished hard reset\n",
124 (temp & CMD_RESET) ? "not " : "");
125 xhci_dbg(xhci, " Event Interrupts %s\n",
126 (temp & CMD_EIE) ? "enabled " : "disabled");
127 xhci_dbg(xhci, " Host System Error Interrupts %s\n",
128 (temp & CMD_EIE) ? "enabled " : "disabled");
129 xhci_dbg(xhci, " HC has %sfinished light reset\n",
130 (temp & CMD_LRESET) ? "not " : "");
131}
132
133void xhci_print_status(struct xhci_hcd *xhci)
134{
135 u32 temp;
136
137 temp = xhci_readl(xhci, &xhci->op_regs->status);
138 xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
139 xhci_dbg(xhci, " Event ring is %sempty\n",
140 (temp & STS_EINT) ? "not " : "");
141 xhci_dbg(xhci, " %sHost System Error\n",
142 (temp & STS_FATAL) ? "WARNING: " : "No ");
143 xhci_dbg(xhci, " HC is %s\n",
144 (temp & STS_HALT) ? "halted" : "running");
145}
146
147void xhci_print_op_regs(struct xhci_hcd *xhci)
148{
149 xhci_dbg(xhci, "xHCI operational registers at 0x%x:\n",
150 (unsigned int) xhci->op_regs);
151 xhci_print_command_reg(xhci);
152 xhci_print_status(xhci);
153}
154
Sarah Sharp0f2a7932009-04-27 19:57:12 -0700155void xhci_print_ports(struct xhci_hcd *xhci)
156{
157 u32 __iomem *addr;
158 int i, j;
159 int ports;
160 char *names[NUM_PORT_REGS] = {
161 "status",
162 "power",
163 "link",
164 "reserved",
165 };
166
167 ports = HCS_MAX_PORTS(xhci->hcs_params1);
168 addr = &xhci->op_regs->port_status_base;
169 for (i = 0; i < ports; i++) {
170 for (j = 0; j < NUM_PORT_REGS; ++j) {
171 xhci_dbg(xhci, "0x%x port %s reg = 0x%x\n",
172 (unsigned int) addr,
173 names[j],
174 (unsigned int) xhci_readl(xhci, addr));
175 addr++;
176 }
177 }
178}
179
Sarah Sharp74c68742009-04-27 19:52:22 -0700180void xhci_print_ir_set(struct xhci_hcd *xhci, struct intr_reg *ir_set, int set_num)
181{
182 void *addr;
183 u32 temp;
184
185 addr = &ir_set->irq_pending;
186 temp = xhci_readl(xhci, addr);
187 if (temp == XHCI_INIT_VALUE)
188 return;
189
190 xhci_dbg(xhci, " 0x%x: ir_set[%i]\n", (unsigned int) ir_set, set_num);
191
192 xhci_dbg(xhci, " 0x%x: ir_set.pending = 0x%x\n",
193 (unsigned int) addr, (unsigned int) temp);
194
195 addr = &ir_set->irq_control;
196 temp = xhci_readl(xhci, addr);
197 xhci_dbg(xhci, " 0x%x: ir_set.control = 0x%x\n",
198 (unsigned int) addr, (unsigned int) temp);
199
200 addr = &ir_set->erst_size;
201 temp = xhci_readl(xhci, addr);
202 xhci_dbg(xhci, " 0x%x: ir_set.erst_size = 0x%x\n",
203 (unsigned int) addr, (unsigned int) temp);
204
205 addr = &ir_set->rsvd;
206 temp = xhci_readl(xhci, addr);
207 if (temp != XHCI_INIT_VALUE)
208 xhci_dbg(xhci, " WARN: 0x%x: ir_set.rsvd = 0x%x\n",
209 (unsigned int) addr, (unsigned int) temp);
210
211 addr = &ir_set->erst_base[0];
212 temp = xhci_readl(xhci, addr);
213 xhci_dbg(xhci, " 0x%x: ir_set.erst_base[0] = 0x%x\n",
214 (unsigned int) addr, (unsigned int) temp);
215
216 addr = &ir_set->erst_base[1];
217 temp = xhci_readl(xhci, addr);
218 xhci_dbg(xhci, " 0x%x: ir_set.erst_base[1] = 0x%x\n",
219 (unsigned int) addr, (unsigned int) temp);
220
221 addr = &ir_set->erst_dequeue[0];
222 temp = xhci_readl(xhci, addr);
223 xhci_dbg(xhci, " 0x%x: ir_set.erst_dequeue[0] = 0x%x\n",
224 (unsigned int) addr, (unsigned int) temp);
225
226 addr = &ir_set->erst_dequeue[1];
227 temp = xhci_readl(xhci, addr);
228 xhci_dbg(xhci, " 0x%x: ir_set.erst_dequeue[1] = 0x%x\n",
229 (unsigned int) addr, (unsigned int) temp);
230}
231
232void xhci_print_run_regs(struct xhci_hcd *xhci)
233{
234 u32 temp;
235 int i;
236
237 xhci_dbg(xhci, "xHCI runtime registers at 0x%x:\n",
238 (unsigned int) xhci->run_regs);
239 temp = xhci_readl(xhci, &xhci->run_regs->microframe_index);
240 xhci_dbg(xhci, " 0x%x: Microframe index = 0x%x\n",
241 (unsigned int) &xhci->run_regs->microframe_index,
242 (unsigned int) temp);
243 for (i = 0; i < 7; ++i) {
244 temp = xhci_readl(xhci, &xhci->run_regs->rsvd[i]);
245 if (temp != XHCI_INIT_VALUE)
246 xhci_dbg(xhci, " WARN: 0x%x: Rsvd[%i] = 0x%x\n",
247 (unsigned int) &xhci->run_regs->rsvd[i],
248 i, (unsigned int) temp);
249 }
250}
251
252void xhci_print_registers(struct xhci_hcd *xhci)
253{
254 xhci_print_cap_regs(xhci);
255 xhci_print_op_regs(xhci);
Sarah Sharp0f2a7932009-04-27 19:57:12 -0700256 xhci_print_ports(xhci);
Sarah Sharp74c68742009-04-27 19:52:22 -0700257}
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700258
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700259void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb)
260{
261 int i;
262 for (i = 0; i < 4; ++i)
263 xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",
264 i*4, trb->generic.field[i]);
265}
266
267/**
268 * Debug a transfer request block (TRB).
269 */
270void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb)
271{
272 u64 address;
273 u32 type = xhci_readl(xhci, &trb->link.control) & TRB_TYPE_BITMASK;
274
275 switch (type) {
276 case TRB_TYPE(TRB_LINK):
277 xhci_dbg(xhci, "Link TRB:\n");
278 xhci_print_trb_offsets(xhci, trb);
279
280 address = trb->link.segment_ptr[0] +
281 (((u64) trb->link.segment_ptr[1]) << 32);
282 xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);
283
284 xhci_dbg(xhci, "Interrupter target = 0x%x\n",
285 GET_INTR_TARGET(trb->link.intr_target));
286 xhci_dbg(xhci, "Cycle bit = %u\n",
287 (unsigned int) (trb->link.control & TRB_CYCLE));
288 xhci_dbg(xhci, "Toggle cycle bit = %u\n",
289 (unsigned int) (trb->link.control & LINK_TOGGLE));
290 xhci_dbg(xhci, "No Snoop bit = %u\n",
291 (unsigned int) (trb->link.control & TRB_NO_SNOOP));
292 break;
293 case TRB_TYPE(TRB_TRANSFER):
294 address = trb->trans_event.buffer[0] +
295 (((u64) trb->trans_event.buffer[1]) << 32);
296 /*
297 * FIXME: look at flags to figure out if it's an address or if
298 * the data is directly in the buffer field.
299 */
300 xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);
301 break;
302 case TRB_TYPE(TRB_COMPLETION):
303 address = trb->event_cmd.cmd_trb[0] +
304 (((u64) trb->event_cmd.cmd_trb[1]) << 32);
305 xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);
306 xhci_dbg(xhci, "Completion status = %u\n",
307 (unsigned int) GET_COMP_CODE(trb->event_cmd.status));
308 xhci_dbg(xhci, "Flags = 0x%x\n", (unsigned int) trb->event_cmd.flags);
309 break;
310 default:
311 xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",
312 (unsigned int) type>>10);
313 xhci_print_trb_offsets(xhci, trb);
314 break;
315 }
316}
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700317
318/**
319 * Debug a segment with an xHCI ring.
320 *
321 * @return The Link TRB of the segment, or NULL if there is no Link TRB
322 * (which is a bug, since all segments must have a Link TRB).
323 *
324 * Prints out all TRBs in the segment, even those after the Link TRB.
325 *
326 * XXX: should we print out TRBs that the HC owns? As long as we don't
327 * write, that should be fine... We shouldn't expect that the memory pointed to
328 * by the TRB is valid at all. Do we care about ones the HC owns? Probably,
329 * for HC debugging.
330 */
331void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg)
332{
333 int i;
334 u32 addr = (u32) seg->dma;
335 union xhci_trb *trb = seg->trbs;
336
337 for (i = 0; i < TRBS_PER_SEGMENT; ++i) {
338 trb = &seg->trbs[i];
339 xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", addr,
340 (unsigned int) trb->link.segment_ptr[0],
341 (unsigned int) trb->link.segment_ptr[1],
342 (unsigned int) trb->link.intr_target,
343 (unsigned int) trb->link.control);
344 addr += sizeof(*trb);
345 }
346}
347
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700348void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring)
349{
350 xhci_dbg(xhci, "Ring deq = 0x%x (virt), 0x%x (dma)\n",
351 (unsigned int) ring->dequeue,
352 trb_virt_to_dma(ring->deq_seg, ring->dequeue));
353 xhci_dbg(xhci, "Ring deq updated %u times\n",
354 ring->deq_updates);
355 xhci_dbg(xhci, "Ring enq = 0x%x (virt), 0x%x (dma)\n",
356 (unsigned int) ring->enqueue,
357 trb_virt_to_dma(ring->enq_seg, ring->enqueue));
358 xhci_dbg(xhci, "Ring enq updated %u times\n",
359 ring->enq_updates);
360}
361
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700362/**
363 * Debugging for an xHCI ring, which is a queue broken into multiple segments.
364 *
365 * Print out each segment in the ring. Check that the DMA address in
366 * each link segment actually matches the segment's stored DMA address.
367 * Check that the link end bit is only set at the end of the ring.
368 * Check that the dequeue and enqueue pointers point to real data in this ring
369 * (not some other ring).
370 */
371void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring)
372{
373 /* FIXME: Throw an error if any segment doesn't have a Link TRB */
374 struct xhci_segment *seg;
375 struct xhci_segment *first_seg = ring->first_seg;
376 xhci_debug_segment(xhci, first_seg);
377
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700378 if (!ring->enq_updates && !ring->deq_updates) {
379 xhci_dbg(xhci, " Ring has not been updated\n");
380 return;
381 }
Sarah Sharp0ebbab32009-04-27 19:52:34 -0700382 for (seg = first_seg->next; seg != first_seg; seg = seg->next)
383 xhci_debug_segment(xhci, seg);
384}
385
386void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
387{
388 u32 addr = (u32) erst->erst_dma_addr;
389 int i;
390 struct xhci_erst_entry *entry;
391
392 for (i = 0; i < erst->num_entries; ++i) {
393 entry = &erst->entries[i];
394 xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n",
395 (unsigned int) addr,
396 (unsigned int) entry->seg_addr[0],
397 (unsigned int) entry->seg_addr[1],
398 (unsigned int) entry->seg_size,
399 (unsigned int) entry->rsvd);
400 addr += sizeof(*entry);
401 }
402}
403
404void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
405{
406 u32 val;
407
408 val = xhci_readl(xhci, &xhci->op_regs->cmd_ring[0]);
409 xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = 0x%x\n", val);
410 val = xhci_readl(xhci, &xhci->op_regs->cmd_ring[1]);
411 xhci_dbg(xhci, "// xHC command ring deq ptr high bits = 0x%x\n", val);
412}