Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/m32r/mm/cache.c |
| 3 | * |
Hirokazu Takata | 9b791d4 | 2006-01-06 00:18:44 -0800 | [diff] [blame] | 4 | * Copyright (C) 2002-2005 Hirokazu Takata, Hayato Fujiwara |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | #include <asm/pgtable.h> |
| 8 | |
| 9 | #undef MCCR |
| 10 | |
Hirokazu Takata | 9b791d4 | 2006-01-06 00:18:44 -0800 | [diff] [blame] | 11 | #if defined(CONFIG_CHIP_XNUX2) || defined(CONFIG_CHIP_M32700) \ |
| 12 | || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_OPSP) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | /* Cache Control Register */ |
| 14 | #define MCCR ((volatile unsigned long*)0xfffffffc) |
| 15 | #define MCCR_CC (1UL << 7) /* Cache mode modify bit */ |
| 16 | #define MCCR_IIV (1UL << 6) /* I-cache invalidate */ |
| 17 | #define MCCR_DIV (1UL << 5) /* D-cache invalidate */ |
| 18 | #define MCCR_DCB (1UL << 4) /* D-cache copy back */ |
| 19 | #define MCCR_ICM (1UL << 1) /* I-cache mode [0:off,1:on] */ |
| 20 | #define MCCR_DCM (1UL << 0) /* D-cache mode [0:off,1:on] */ |
| 21 | #define MCCR_ICACHE_INV (MCCR_CC|MCCR_IIV) |
| 22 | #define MCCR_DCACHE_CB (MCCR_CC|MCCR_DCB) |
| 23 | #define MCCR_DCACHE_CBINV (MCCR_CC|MCCR_DIV|MCCR_DCB) |
| 24 | #define CHECK_MCCR(mccr) (mccr = *MCCR) |
| 25 | #elif defined(CONFIG_CHIP_M32102) |
| 26 | #define MCCR ((volatile unsigned char*)0xfffffffe) |
| 27 | #define MCCR_IIV (1UL << 0) /* I-cache invalidate */ |
| 28 | #define MCCR_ICACHE_INV MCCR_IIV |
Hirokazu Takata | 9287d95 | 2006-01-06 00:18:41 -0800 | [diff] [blame] | 29 | #elif defined(CONFIG_CHIP_M32104) |
Hirokazu Takata | 9b791d4 | 2006-01-06 00:18:44 -0800 | [diff] [blame] | 30 | #define MCCR ((volatile unsigned short*)0xfffffffe) |
Hirokazu Takata | 9287d95 | 2006-01-06 00:18:41 -0800 | [diff] [blame] | 31 | #define MCCR_IIV (1UL << 8) /* I-cache invalidate */ |
| 32 | #define MCCR_DIV (1UL << 9) /* D-cache invalidate */ |
| 33 | #define MCCR_DCB (1UL << 10) /* D-cache copy back */ |
| 34 | #define MCCR_ICM (1UL << 0) /* I-cache mode [0:off,1:on] */ |
| 35 | #define MCCR_DCM (1UL << 1) /* D-cache mode [0:off,1:on] */ |
| 36 | #define MCCR_ICACHE_INV MCCR_IIV |
| 37 | #define MCCR_DCACHE_CB MCCR_DCB |
| 38 | #define MCCR_DCACHE_CBINV (MCCR_DIV|MCCR_DCB) |
Hirokazu Takata | 9b791d4 | 2006-01-06 00:18:44 -0800 | [diff] [blame] | 39 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | |
| 41 | #ifndef MCCR |
| 42 | #error Unknown cache type. |
| 43 | #endif |
| 44 | |
| 45 | |
| 46 | /* Copy back and invalidate D-cache and invalidate I-cache all */ |
| 47 | void _flush_cache_all(void) |
| 48 | { |
| 49 | #if defined(CONFIG_CHIP_M32102) |
Hirokazu Takata | 9b791d4 | 2006-01-06 00:18:44 -0800 | [diff] [blame] | 50 | unsigned char mccr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | *MCCR = MCCR_ICACHE_INV; |
Hirokazu Takata | 9b791d4 | 2006-01-06 00:18:44 -0800 | [diff] [blame] | 52 | #elif defined(CONFIG_CHIP_M32104) |
| 53 | unsigned short mccr; |
| 54 | |
| 55 | /* Copyback and invalidate D-cache */ |
| 56 | /* Invalidate I-cache */ |
| 57 | *MCCR |= (MCCR_ICACHE_INV | MCCR_DCACHE_CBINV); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | #else |
| 59 | unsigned long mccr; |
| 60 | |
| 61 | /* Copyback and invalidate D-cache */ |
| 62 | /* Invalidate I-cache */ |
| 63 | *MCCR = MCCR_ICACHE_INV | MCCR_DCACHE_CBINV; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | #endif |
Hirokazu Takata | 9b791d4 | 2006-01-06 00:18:44 -0800 | [diff] [blame] | 65 | while ((mccr = *MCCR) & MCCR_IIV); /* loop while invalidating... */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 66 | } |
| 67 | |
| 68 | /* Copy back D-cache and invalidate I-cache all */ |
| 69 | void _flush_cache_copyback_all(void) |
| 70 | { |
| 71 | #if defined(CONFIG_CHIP_M32102) |
Hirokazu Takata | 9b791d4 | 2006-01-06 00:18:44 -0800 | [diff] [blame] | 72 | unsigned char mccr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | *MCCR = MCCR_ICACHE_INV; |
Hirokazu Takata | 9b791d4 | 2006-01-06 00:18:44 -0800 | [diff] [blame] | 74 | #elif defined(CONFIG_CHIP_M32104) |
| 75 | unsigned short mccr; |
| 76 | |
| 77 | /* Copyback and invalidate D-cache */ |
| 78 | /* Invalidate I-cache */ |
| 79 | *MCCR |= (MCCR_ICACHE_INV | MCCR_DCACHE_CB); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 80 | #else |
| 81 | unsigned long mccr; |
| 82 | |
| 83 | /* Copyback D-cache */ |
| 84 | /* Invalidate I-cache */ |
| 85 | *MCCR = MCCR_ICACHE_INV | MCCR_DCACHE_CB; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | #endif |
Hirokazu Takata | 9b791d4 | 2006-01-06 00:18:44 -0800 | [diff] [blame] | 87 | while ((mccr = *MCCR) & MCCR_IIV); /* loop while invalidating... */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 88 | } |