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David Howells108b42b2006-03-31 16:00:29 +01001 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
4
5By: David Howells <dhowells@redhat.com>
David Howells90fddab2010-03-24 09:43:00 +00006 Paul E. McKenney <paulmck@linux.vnet.ibm.com>
David Howells108b42b2006-03-31 16:00:29 +01007
8Contents:
9
10 (*) Abstract memory access model.
11
12 - Device operations.
13 - Guarantees.
14
15 (*) What are memory barriers?
16
17 - Varieties of memory barrier.
18 - What may not be assumed about memory barriers?
19 - Data dependency barriers.
20 - Control dependencies.
21 - SMP barrier pairing.
22 - Examples of memory barrier sequences.
David Howells670bd952006-06-10 09:54:12 -070023 - Read memory barriers vs load speculation.
Paul E. McKenney241e6662011-02-10 16:54:50 -080024 - Transitivity
David Howells108b42b2006-03-31 16:00:29 +010025
26 (*) Explicit kernel barriers.
27
28 - Compiler barrier.
Jarek Poplawski81fc6322007-05-23 13:58:20 -070029 - CPU memory barriers.
David Howells108b42b2006-03-31 16:00:29 +010030 - MMIO write barrier.
31
32 (*) Implicit kernel memory barriers.
33
34 - Locking functions.
35 - Interrupt disabling functions.
David Howells50fa6102009-04-28 15:01:38 +010036 - Sleep and wake-up functions.
David Howells108b42b2006-03-31 16:00:29 +010037 - Miscellaneous functions.
38
39 (*) Inter-CPU locking barrier effects.
40
41 - Locks vs memory accesses.
42 - Locks vs I/O accesses.
43
44 (*) Where are memory barriers needed?
45
46 - Interprocessor interaction.
47 - Atomic operations.
48 - Accessing devices.
49 - Interrupts.
50
51 (*) Kernel I/O barrier effects.
52
53 (*) Assumed minimum execution ordering model.
54
55 (*) The effects of the cpu cache.
56
57 - Cache coherency.
58 - Cache coherency vs DMA.
59 - Cache coherency vs MMIO.
60
61 (*) The things CPUs get up to.
62
63 - And then there's the Alpha.
64
David Howells90fddab2010-03-24 09:43:00 +000065 (*) Example uses.
66
67 - Circular buffers.
68
David Howells108b42b2006-03-31 16:00:29 +010069 (*) References.
70
71
72============================
73ABSTRACT MEMORY ACCESS MODEL
74============================
75
76Consider the following abstract model of the system:
77
78 : :
79 : :
80 : :
81 +-------+ : +--------+ : +-------+
82 | | : | | : | |
83 | | : | | : | |
84 | CPU 1 |<----->| Memory |<----->| CPU 2 |
85 | | : | | : | |
86 | | : | | : | |
87 +-------+ : +--------+ : +-------+
88 ^ : ^ : ^
89 | : | : |
90 | : | : |
91 | : v : |
92 | : +--------+ : |
93 | : | | : |
94 | : | | : |
95 +---------->| Device |<----------+
96 : | | :
97 : | | :
98 : +--------+ :
99 : :
100
101Each CPU executes a program that generates memory access operations. In the
102abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
103perform the memory operations in any order it likes, provided program causality
104appears to be maintained. Similarly, the compiler may also arrange the
105instructions it emits in any order it likes, provided it doesn't affect the
106apparent operation of the program.
107
108So in the above diagram, the effects of the memory operations performed by a
109CPU are perceived by the rest of the system as the operations cross the
110interface between the CPU and rest of the system (the dotted lines).
111
112
113For example, consider the following sequence of events:
114
115 CPU 1 CPU 2
116 =============== ===============
117 { A == 1; B == 2 }
Alexey Dobriyan615cc2c2014-06-06 14:36:41 -0700118 A = 3; x = B;
119 B = 4; y = A;
David Howells108b42b2006-03-31 16:00:29 +0100120
121The set of accesses as seen by the memory system in the middle can be arranged
122in 24 different combinations:
123
Pranith Kumar8ab8b3e2014-09-02 23:34:29 -0400124 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
125 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
126 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
127 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
128 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
129 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
130 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
David Howells108b42b2006-03-31 16:00:29 +0100131 STORE B=4, ...
132 ...
133
134and can thus result in four different combinations of values:
135
Pranith Kumar8ab8b3e2014-09-02 23:34:29 -0400136 x == 2, y == 1
137 x == 2, y == 3
138 x == 4, y == 1
139 x == 4, y == 3
David Howells108b42b2006-03-31 16:00:29 +0100140
141
142Furthermore, the stores committed by a CPU to the memory system may not be
143perceived by the loads made by another CPU in the same order as the stores were
144committed.
145
146
147As a further example, consider this sequence of events:
148
149 CPU 1 CPU 2
150 =============== ===============
151 { A == 1, B == 2, C = 3, P == &A, Q == &C }
152 B = 4; Q = P;
153 P = &B D = *Q;
154
155There is an obvious data dependency here, as the value loaded into D depends on
156the address retrieved from P by CPU 2. At the end of the sequence, any of the
157following results are possible:
158
159 (Q == &A) and (D == 1)
160 (Q == &B) and (D == 2)
161 (Q == &B) and (D == 4)
162
163Note that CPU 2 will never try and load C into D because the CPU will load P
164into Q before issuing the load of *Q.
165
166
167DEVICE OPERATIONS
168-----------------
169
170Some devices present their control interfaces as collections of memory
171locations, but the order in which the control registers are accessed is very
172important. For instance, imagine an ethernet card with a set of internal
173registers that are accessed through an address port register (A) and a data
174port register (D). To read internal register 5, the following code might then
175be used:
176
177 *A = 5;
178 x = *D;
179
180but this might show up as either of the following two sequences:
181
182 STORE *A = 5, x = LOAD *D
183 x = LOAD *D, STORE *A = 5
184
185the second of which will almost certainly result in a malfunction, since it set
186the address _after_ attempting to read the register.
187
188
189GUARANTEES
190----------
191
192There are some minimal guarantees that may be expected of a CPU:
193
194 (*) On any given CPU, dependent memory accesses will be issued in order, with
195 respect to itself. This means that for:
196
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800197 ACCESS_ONCE(Q) = P; smp_read_barrier_depends(); D = ACCESS_ONCE(*Q);
David Howells108b42b2006-03-31 16:00:29 +0100198
199 the CPU will issue the following memory operations:
200
201 Q = LOAD P, D = LOAD *Q
202
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800203 and always in that order. On most systems, smp_read_barrier_depends()
204 does nothing, but it is required for DEC Alpha. The ACCESS_ONCE()
205 is required to prevent compiler mischief. Please note that you
206 should normally use something like rcu_dereference() instead of
207 open-coding smp_read_barrier_depends().
David Howells108b42b2006-03-31 16:00:29 +0100208
209 (*) Overlapping loads and stores within a particular CPU will appear to be
210 ordered within that CPU. This means that for:
211
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800212 a = ACCESS_ONCE(*X); ACCESS_ONCE(*X) = b;
David Howells108b42b2006-03-31 16:00:29 +0100213
214 the CPU will only issue the following sequence of memory operations:
215
216 a = LOAD *X, STORE *X = b
217
218 And for:
219
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800220 ACCESS_ONCE(*X) = c; d = ACCESS_ONCE(*X);
David Howells108b42b2006-03-31 16:00:29 +0100221
222 the CPU will only issue:
223
224 STORE *X = c, d = LOAD *X
225
Matt LaPlantefa00e7e2006-11-30 04:55:36 +0100226 (Loads and stores overlap if they are targeted at overlapping pieces of
David Howells108b42b2006-03-31 16:00:29 +0100227 memory).
228
229And there are a number of things that _must_ or _must_not_ be assumed:
230
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800231 (*) It _must_not_ be assumed that the compiler will do what you want with
232 memory references that are not protected by ACCESS_ONCE(). Without
233 ACCESS_ONCE(), the compiler is within its rights to do all sorts
Paul E. McKenney692118d2013-12-11 13:59:07 -0800234 of "creative" transformations, which are covered in the Compiler
235 Barrier section.
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800236
David Howells108b42b2006-03-31 16:00:29 +0100237 (*) It _must_not_ be assumed that independent loads and stores will be issued
238 in the order given. This means that for:
239
240 X = *A; Y = *B; *D = Z;
241
242 we may get any of the following sequences:
243
244 X = LOAD *A, Y = LOAD *B, STORE *D = Z
245 X = LOAD *A, STORE *D = Z, Y = LOAD *B
246 Y = LOAD *B, X = LOAD *A, STORE *D = Z
247 Y = LOAD *B, STORE *D = Z, X = LOAD *A
248 STORE *D = Z, X = LOAD *A, Y = LOAD *B
249 STORE *D = Z, Y = LOAD *B, X = LOAD *A
250
251 (*) It _must_ be assumed that overlapping memory accesses may be merged or
252 discarded. This means that for:
253
254 X = *A; Y = *(A + 4);
255
256 we may get any one of the following sequences:
257
258 X = LOAD *A; Y = LOAD *(A + 4);
259 Y = LOAD *(A + 4); X = LOAD *A;
260 {X, Y} = LOAD {*A, *(A + 4) };
261
262 And for:
263
Paul E. McKenneyf191eec2012-10-03 10:28:30 -0700264 *A = X; *(A + 4) = Y;
David Howells108b42b2006-03-31 16:00:29 +0100265
Paul E. McKenneyf191eec2012-10-03 10:28:30 -0700266 we may get any of:
David Howells108b42b2006-03-31 16:00:29 +0100267
Paul E. McKenneyf191eec2012-10-03 10:28:30 -0700268 STORE *A = X; STORE *(A + 4) = Y;
269 STORE *(A + 4) = Y; STORE *A = X;
270 STORE {*A, *(A + 4) } = {X, Y};
David Howells108b42b2006-03-31 16:00:29 +0100271
272
273=========================
274WHAT ARE MEMORY BARRIERS?
275=========================
276
277As can be seen above, independent memory operations are effectively performed
278in random order, but this can be a problem for CPU-CPU interaction and for I/O.
279What is required is some way of intervening to instruct the compiler and the
280CPU to restrict the order.
281
282Memory barriers are such interventions. They impose a perceived partial
David Howells2b948952006-06-25 05:48:49 -0700283ordering over the memory operations on either side of the barrier.
284
285Such enforcement is important because the CPUs and other devices in a system
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700286can use a variety of tricks to improve performance, including reordering,
David Howells2b948952006-06-25 05:48:49 -0700287deferral and combination of memory operations; speculative loads; speculative
288branch prediction and various types of caching. Memory barriers are used to
289override or suppress these tricks, allowing the code to sanely control the
290interaction of multiple CPUs and/or devices.
David Howells108b42b2006-03-31 16:00:29 +0100291
292
293VARIETIES OF MEMORY BARRIER
294---------------------------
295
296Memory barriers come in four basic varieties:
297
298 (1) Write (or store) memory barriers.
299
300 A write memory barrier gives a guarantee that all the STORE operations
301 specified before the barrier will appear to happen before all the STORE
302 operations specified after the barrier with respect to the other
303 components of the system.
304
305 A write barrier is a partial ordering on stores only; it is not required
306 to have any effect on loads.
307
David Howells6bc39272006-06-25 05:49:22 -0700308 A CPU can be viewed as committing a sequence of store operations to the
David Howells108b42b2006-03-31 16:00:29 +0100309 memory system as time progresses. All stores before a write barrier will
310 occur in the sequence _before_ all the stores after the write barrier.
311
312 [!] Note that write barriers should normally be paired with read or data
313 dependency barriers; see the "SMP barrier pairing" subsection.
314
315
316 (2) Data dependency barriers.
317
318 A data dependency barrier is a weaker form of read barrier. In the case
319 where two loads are performed such that the second depends on the result
320 of the first (eg: the first load retrieves the address to which the second
321 load will be directed), a data dependency barrier would be required to
322 make sure that the target of the second load is updated before the address
323 obtained by the first load is accessed.
324
325 A data dependency barrier is a partial ordering on interdependent loads
326 only; it is not required to have any effect on stores, independent loads
327 or overlapping loads.
328
329 As mentioned in (1), the other CPUs in the system can be viewed as
330 committing sequences of stores to the memory system that the CPU being
331 considered can then perceive. A data dependency barrier issued by the CPU
332 under consideration guarantees that for any load preceding it, if that
333 load touches one of a sequence of stores from another CPU, then by the
334 time the barrier completes, the effects of all the stores prior to that
335 touched by the load will be perceptible to any loads issued after the data
336 dependency barrier.
337
338 See the "Examples of memory barrier sequences" subsection for diagrams
339 showing the ordering constraints.
340
341 [!] Note that the first load really has to have a _data_ dependency and
342 not a control dependency. If the address for the second load is dependent
343 on the first load, but the dependency is through a conditional rather than
344 actually loading the address itself, then it's a _control_ dependency and
345 a full read barrier or better is required. See the "Control dependencies"
346 subsection for more information.
347
348 [!] Note that data dependency barriers should normally be paired with
349 write barriers; see the "SMP barrier pairing" subsection.
350
351
352 (3) Read (or load) memory barriers.
353
354 A read barrier is a data dependency barrier plus a guarantee that all the
355 LOAD operations specified before the barrier will appear to happen before
356 all the LOAD operations specified after the barrier with respect to the
357 other components of the system.
358
359 A read barrier is a partial ordering on loads only; it is not required to
360 have any effect on stores.
361
362 Read memory barriers imply data dependency barriers, and so can substitute
363 for them.
364
365 [!] Note that read barriers should normally be paired with write barriers;
366 see the "SMP barrier pairing" subsection.
367
368
369 (4) General memory barriers.
370
David Howells670bd952006-06-10 09:54:12 -0700371 A general memory barrier gives a guarantee that all the LOAD and STORE
372 operations specified before the barrier will appear to happen before all
373 the LOAD and STORE operations specified after the barrier with respect to
374 the other components of the system.
375
376 A general memory barrier is a partial ordering over both loads and stores.
David Howells108b42b2006-03-31 16:00:29 +0100377
378 General memory barriers imply both read and write memory barriers, and so
379 can substitute for either.
380
381
382And a couple of implicit varieties:
383
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100384 (5) ACQUIRE operations.
David Howells108b42b2006-03-31 16:00:29 +0100385
386 This acts as a one-way permeable barrier. It guarantees that all memory
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100387 operations after the ACQUIRE operation will appear to happen after the
388 ACQUIRE operation with respect to the other components of the system.
389 ACQUIRE operations include LOCK operations and smp_load_acquire()
390 operations.
David Howells108b42b2006-03-31 16:00:29 +0100391
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100392 Memory operations that occur before an ACQUIRE operation may appear to
393 happen after it completes.
David Howells108b42b2006-03-31 16:00:29 +0100394
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100395 An ACQUIRE operation should almost always be paired with a RELEASE
396 operation.
David Howells108b42b2006-03-31 16:00:29 +0100397
398
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100399 (6) RELEASE operations.
David Howells108b42b2006-03-31 16:00:29 +0100400
401 This also acts as a one-way permeable barrier. It guarantees that all
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100402 memory operations before the RELEASE operation will appear to happen
403 before the RELEASE operation with respect to the other components of the
404 system. RELEASE operations include UNLOCK operations and
405 smp_store_release() operations.
David Howells108b42b2006-03-31 16:00:29 +0100406
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100407 Memory operations that occur after a RELEASE operation may appear to
David Howells108b42b2006-03-31 16:00:29 +0100408 happen before it completes.
409
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100410 The use of ACQUIRE and RELEASE operations generally precludes the need
411 for other sorts of memory barrier (but note the exceptions mentioned in
412 the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE
413 pair is -not- guaranteed to act as a full memory barrier. However, after
414 an ACQUIRE on a given variable, all memory accesses preceding any prior
415 RELEASE on that same variable are guaranteed to be visible. In other
416 words, within a given variable's critical section, all accesses of all
417 previous critical sections for that variable are guaranteed to have
418 completed.
Paul E. McKenney17eb88e2013-12-11 13:59:09 -0800419
Peter Zijlstra2e4f5382013-11-06 14:57:36 +0100420 This means that ACQUIRE acts as a minimal "acquire" operation and
421 RELEASE acts as a minimal "release" operation.
David Howells108b42b2006-03-31 16:00:29 +0100422
423
424Memory barriers are only required where there's a possibility of interaction
425between two CPUs or between a CPU and a device. If it can be guaranteed that
426there won't be any such interaction in any particular piece of code, then
427memory barriers are unnecessary in that piece of code.
428
429
430Note that these are the _minimum_ guarantees. Different architectures may give
431more substantial guarantees, but they may _not_ be relied upon outside of arch
432specific code.
433
434
435WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
436----------------------------------------------
437
438There are certain things that the Linux kernel memory barriers do not guarantee:
439
440 (*) There is no guarantee that any of the memory accesses specified before a
441 memory barrier will be _complete_ by the completion of a memory barrier
442 instruction; the barrier can be considered to draw a line in that CPU's
443 access queue that accesses of the appropriate type may not cross.
444
445 (*) There is no guarantee that issuing a memory barrier on one CPU will have
446 any direct effect on another CPU or any other hardware in the system. The
447 indirect effect will be the order in which the second CPU sees the effects
448 of the first CPU's accesses occur, but see the next point:
449
David Howells6bc39272006-06-25 05:49:22 -0700450 (*) There is no guarantee that a CPU will see the correct order of effects
David Howells108b42b2006-03-31 16:00:29 +0100451 from a second CPU's accesses, even _if_ the second CPU uses a memory
452 barrier, unless the first CPU _also_ uses a matching memory barrier (see
453 the subsection on "SMP Barrier Pairing").
454
455 (*) There is no guarantee that some intervening piece of off-the-CPU
456 hardware[*] will not reorder the memory accesses. CPU cache coherency
457 mechanisms should propagate the indirect effects of a memory barrier
458 between CPUs, but might not do so in order.
459
460 [*] For information on bus mastering DMA and coherency please read:
461
Randy Dunlap4b5ff462008-03-10 17:16:32 -0700462 Documentation/PCI/pci.txt
Paul Bolle395cf962011-08-15 02:02:26 +0200463 Documentation/DMA-API-HOWTO.txt
David Howells108b42b2006-03-31 16:00:29 +0100464 Documentation/DMA-API.txt
465
466
467DATA DEPENDENCY BARRIERS
468------------------------
469
470The usage requirements of data dependency barriers are a little subtle, and
471it's not always obvious that they're needed. To illustrate, consider the
472following sequence of events:
473
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800474 CPU 1 CPU 2
475 =============== ===============
David Howells108b42b2006-03-31 16:00:29 +0100476 { A == 1, B == 2, C = 3, P == &A, Q == &C }
477 B = 4;
478 <write barrier>
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800479 ACCESS_ONCE(P) = &B
480 Q = ACCESS_ONCE(P);
481 D = *Q;
David Howells108b42b2006-03-31 16:00:29 +0100482
483There's a clear data dependency here, and it would seem that by the end of the
484sequence, Q must be either &A or &B, and that:
485
486 (Q == &A) implies (D == 1)
487 (Q == &B) implies (D == 4)
488
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700489But! CPU 2's perception of P may be updated _before_ its perception of B, thus
David Howells108b42b2006-03-31 16:00:29 +0100490leading to the following situation:
491
492 (Q == &B) and (D == 2) ????
493
494Whilst this may seem like a failure of coherency or causality maintenance, it
495isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
496Alpha).
497
David Howells2b948952006-06-25 05:48:49 -0700498To deal with this, a data dependency barrier or better must be inserted
499between the address load and the data load:
David Howells108b42b2006-03-31 16:00:29 +0100500
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800501 CPU 1 CPU 2
502 =============== ===============
David Howells108b42b2006-03-31 16:00:29 +0100503 { A == 1, B == 2, C = 3, P == &A, Q == &C }
504 B = 4;
505 <write barrier>
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800506 ACCESS_ONCE(P) = &B
507 Q = ACCESS_ONCE(P);
508 <data dependency barrier>
509 D = *Q;
David Howells108b42b2006-03-31 16:00:29 +0100510
511This enforces the occurrence of one of the two implications, and prevents the
512third possibility from arising.
513
514[!] Note that this extremely counterintuitive situation arises most easily on
515machines with split caches, so that, for example, one cache bank processes
516even-numbered cache lines and the other bank processes odd-numbered cache
517lines. The pointer P might be stored in an odd-numbered cache line, and the
518variable B might be stored in an even-numbered cache line. Then, if the
519even-numbered bank of the reading CPU's cache is extremely busy while the
520odd-numbered bank is idle, one can see the new value of the pointer P (&B),
David Howells6bc39272006-06-25 05:49:22 -0700521but the old value of the variable B (2).
David Howells108b42b2006-03-31 16:00:29 +0100522
523
Ingo Molnare0edc782013-11-22 11:24:53 +0100524Another example of where data dependency barriers might be required is where a
David Howells108b42b2006-03-31 16:00:29 +0100525number is read from memory and then used to calculate the index for an array
526access:
527
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800528 CPU 1 CPU 2
529 =============== ===============
David Howells108b42b2006-03-31 16:00:29 +0100530 { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
531 M[1] = 4;
532 <write barrier>
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800533 ACCESS_ONCE(P) = 1
534 Q = ACCESS_ONCE(P);
535 <data dependency barrier>
536 D = M[Q];
David Howells108b42b2006-03-31 16:00:29 +0100537
538
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800539The data dependency barrier is very important to the RCU system,
540for example. See rcu_assign_pointer() and rcu_dereference() in
541include/linux/rcupdate.h. This permits the current target of an RCU'd
542pointer to be replaced with a new modified target, without the replacement
543target appearing to be incompletely initialised.
David Howells108b42b2006-03-31 16:00:29 +0100544
545See also the subsection on "Cache Coherency" for a more thorough example.
546
547
548CONTROL DEPENDENCIES
549--------------------
550
551A control dependency requires a full read memory barrier, not simply a data
552dependency barrier to make it work correctly. Consider the following bit of
553code:
554
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800555 q = ACCESS_ONCE(a);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800556 if (q) {
557 <data dependency barrier> /* BUG: No data dependency!!! */
558 p = ACCESS_ONCE(b);
Paul E. McKenney45c8a362013-07-02 15:24:09 -0700559 }
David Howells108b42b2006-03-31 16:00:29 +0100560
561This will not have the desired effect because there is no actual data
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800562dependency, but rather a control dependency that the CPU may short-circuit
563by attempting to predict the outcome in advance, so that other CPUs see
564the load from b as having happened before the load from a. In such a
565case what's actually required is:
David Howells108b42b2006-03-31 16:00:29 +0100566
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800567 q = ACCESS_ONCE(a);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800568 if (q) {
Paul E. McKenney45c8a362013-07-02 15:24:09 -0700569 <read barrier>
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800570 p = ACCESS_ONCE(b);
Paul E. McKenney45c8a362013-07-02 15:24:09 -0700571 }
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800572
573However, stores are not speculated. This means that ordering -is- provided
574in the following example:
575
576 q = ACCESS_ONCE(a);
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700577 if (q) {
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800578 ACCESS_ONCE(b) = p;
579 }
580
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700581Please note that ACCESS_ONCE() is not optional! Without the
582ACCESS_ONCE(), might combine the load from 'a' with other loads from
583'a', and the store to 'b' with other stores to 'b', with possible highly
584counterintuitive effects on ordering.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800585
586Worse yet, if the compiler is able to prove (say) that the value of
587variable 'a' is always non-zero, it would be well within its rights
588to optimize the original example by eliminating the "if" statement
589as follows:
590
591 q = a;
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700592 b = p; /* BUG: Compiler and CPU can both reorder!!! */
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800593
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700594So don't leave out the ACCESS_ONCE().
595
596It is tempting to try to enforce ordering on identical stores on both
597branches of the "if" statement as follows:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800598
599 q = ACCESS_ONCE(a);
600 if (q) {
Paul E. McKenney9b2b3bf2014-02-12 20:19:47 -0800601 barrier();
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800602 ACCESS_ONCE(b) = p;
603 do_something();
604 } else {
Paul E. McKenney9b2b3bf2014-02-12 20:19:47 -0800605 barrier();
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800606 ACCESS_ONCE(b) = p;
607 do_something_else();
608 }
609
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700610Unfortunately, current compilers will transform this as follows at high
611optimization levels:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800612
613 q = ACCESS_ONCE(a);
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700614 barrier();
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800615 ACCESS_ONCE(b) = p; /* BUG: No ordering vs. load from a!!! */
616 if (q) {
617 /* ACCESS_ONCE(b) = p; -- moved up, BUG!!! */
618 do_something();
619 } else {
620 /* ACCESS_ONCE(b) = p; -- moved up, BUG!!! */
621 do_something_else();
622 }
623
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700624Now there is no conditional between the load from 'a' and the store to
625'b', which means that the CPU is within its rights to reorder them:
626The conditional is absolutely required, and must be present in the
627assembly code even after all compiler optimizations have been applied.
628Therefore, if you need ordering in this example, you need explicit
629memory barriers, for example, smp_store_release():
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800630
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700631 q = ACCESS_ONCE(a);
632 if (q) {
633 smp_store_release(&b, p);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800634 do_something();
635 } else {
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700636 smp_store_release(&b, p);
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800637 do_something_else();
638 }
639
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700640In contrast, without explicit memory barriers, two-legged-if control
641ordering is guaranteed only when the stores differ, for example:
642
643 q = ACCESS_ONCE(a);
644 if (q) {
645 ACCESS_ONCE(b) = p;
646 do_something();
647 } else {
648 ACCESS_ONCE(b) = r;
649 do_something_else();
650 }
651
652The initial ACCESS_ONCE() is still required to prevent the compiler from
653proving the value of 'a'.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800654
655In addition, you need to be careful what you do with the local variable 'q',
656otherwise the compiler might be able to guess the value and again remove
657the needed conditional. For example:
658
659 q = ACCESS_ONCE(a);
660 if (q % MAX) {
661 ACCESS_ONCE(b) = p;
662 do_something();
663 } else {
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700664 ACCESS_ONCE(b) = r;
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800665 do_something_else();
666 }
667
668If MAX is defined to be 1, then the compiler knows that (q % MAX) is
669equal to zero, in which case the compiler is within its rights to
670transform the above code into the following:
671
672 q = ACCESS_ONCE(a);
673 ACCESS_ONCE(b) = p;
674 do_something_else();
675
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700676Given this transformation, the CPU is not required to respect the ordering
677between the load from variable 'a' and the store to variable 'b'. It is
678tempting to add a barrier(), but this does not help. The conditional
679is gone, and the barrier won't bring it back. Therefore, if you are
680relying on this ordering, you should make sure that MAX is greater than
681one, perhaps as follows:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800682
683 q = ACCESS_ONCE(a);
684 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */
685 if (q % MAX) {
686 ACCESS_ONCE(b) = p;
687 do_something();
688 } else {
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700689 ACCESS_ONCE(b) = r;
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800690 do_something_else();
691 }
692
Paul E. McKenney2456d2a2014-08-13 15:40:02 -0700693Please note once again that the stores to 'b' differ. If they were
694identical, as noted earlier, the compiler could pull this store outside
695of the 'if' statement.
696
Paul E. McKenney8b19d1d2014-10-12 07:55:47 -0700697You must also be careful not to rely too much on boolean short-circuit
698evaluation. Consider this example:
699
700 q = ACCESS_ONCE(a);
701 if (a || 1 > 0)
702 ACCESS_ONCE(b) = 1;
703
704Because the second condition is always true, the compiler can transform
705this example as following, defeating control dependency:
706
707 q = ACCESS_ONCE(a);
708 ACCESS_ONCE(b) = 1;
709
710This example underscores the need to ensure that the compiler cannot
711out-guess your code. More generally, although ACCESS_ONCE() does force
712the compiler to actually emit code for a given load, it does not force
713the compiler to use the results.
714
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800715Finally, control dependencies do -not- provide transitivity. This is
Paul E. McKenney5646f7a2014-07-25 17:05:24 -0700716demonstrated by two related examples, with the initial values of
717x and y both being zero:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800718
719 CPU 0 CPU 1
720 ===================== =====================
721 r1 = ACCESS_ONCE(x); r2 = ACCESS_ONCE(y);
Paul E. McKenney5646f7a2014-07-25 17:05:24 -0700722 if (r1 > 0) if (r2 > 0)
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800723 ACCESS_ONCE(y) = 1; ACCESS_ONCE(x) = 1;
724
725 assert(!(r1 == 1 && r2 == 1));
726
727The above two-CPU example will never trigger the assert(). However,
728if control dependencies guaranteed transitivity (which they do not),
Paul E. McKenney5646f7a2014-07-25 17:05:24 -0700729then adding the following CPU would guarantee a related assertion:
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800730
Paul E. McKenney5646f7a2014-07-25 17:05:24 -0700731 CPU 2
732 =====================
733 ACCESS_ONCE(x) = 2;
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800734
Paul E. McKenney5646f7a2014-07-25 17:05:24 -0700735 assert(!(r1 == 2 && r2 == 1 && x == 2)); /* FAILS!!! */
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800736
Paul E. McKenney5646f7a2014-07-25 17:05:24 -0700737But because control dependencies do -not- provide transitivity, the above
738assertion can fail after the combined three-CPU example completes. If you
739need the three-CPU example to provide ordering, you will need smp_mb()
740between the loads and stores in the CPU 0 and CPU 1 code fragments,
741that is, just before or just after the "if" statements.
742
743These two examples are the LB and WWC litmus tests from this paper:
744http://www.cl.cam.ac.uk/users/pes20/ppc-supplemental/test6.pdf and this
745site: https://www.cl.cam.ac.uk/~pes20/ppcmem/index.html.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800746
747In summary:
748
749 (*) Control dependencies can order prior loads against later stores.
750 However, they do -not- guarantee any other sort of ordering:
751 Not prior loads against later loads, nor prior stores against
752 later anything. If you need these other forms of ordering,
753 use smb_rmb(), smp_wmb(), or, in the case of prior stores and
754 later loads, smp_mb().
755
Paul E. McKenney9b2b3bf2014-02-12 20:19:47 -0800756 (*) If both legs of the "if" statement begin with identical stores
757 to the same variable, a barrier() statement is required at the
758 beginning of each leg of the "if" statement.
759
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800760 (*) Control dependencies require at least one run-time conditional
Paul E. McKenney586dd562014-02-11 12:28:06 -0800761 between the prior load and the subsequent store, and this
762 conditional must involve the prior load. If the compiler
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800763 is able to optimize the conditional away, it will have also
764 optimized away the ordering. Careful use of ACCESS_ONCE() can
765 help to preserve the needed conditional.
766
767 (*) Control dependencies require that the compiler avoid reordering the
768 dependency into nonexistence. Careful use of ACCESS_ONCE() or
Paul E. McKenney692118d2013-12-11 13:59:07 -0800769 barrier() can help to preserve your control dependency. Please
770 see the Compiler Barrier section for more information.
Peter Zijlstra18c03c62013-12-11 13:59:06 -0800771
772 (*) Control dependencies do -not- provide transitivity. If you
773 need transitivity, use smp_mb().
David Howells108b42b2006-03-31 16:00:29 +0100774
775
776SMP BARRIER PAIRING
777-------------------
778
779When dealing with CPU-CPU interactions, certain types of memory barrier should
780always be paired. A lack of appropriate pairing is almost certainly an error.
781
Paul E. McKenney128ea442014-06-19 10:01:23 -0700782General barriers pair with each other, though they also pair with
783most other types of barriers, albeit without transitivity. An acquire
784barrier pairs with a release barrier, but both may also pair with other
785barriers, including of course general barriers. A write barrier pairs
786with a data dependency barrier, an acquire barrier, a release barrier,
787a read barrier, or a general barrier. Similarly a read barrier or a
788data dependency barrier pairs with a write barrier, an acquire barrier,
789a release barrier, or a general barrier:
David Howells108b42b2006-03-31 16:00:29 +0100790
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800791 CPU 1 CPU 2
792 =============== ===============
793 ACCESS_ONCE(a) = 1;
David Howells108b42b2006-03-31 16:00:29 +0100794 <write barrier>
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800795 ACCESS_ONCE(b) = 2; x = ACCESS_ONCE(b);
796 <read barrier>
797 y = ACCESS_ONCE(a);
David Howells108b42b2006-03-31 16:00:29 +0100798
799Or:
800
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800801 CPU 1 CPU 2
802 =============== ===============================
David Howells108b42b2006-03-31 16:00:29 +0100803 a = 1;
804 <write barrier>
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800805 ACCESS_ONCE(b) = &a; x = ACCESS_ONCE(b);
806 <data dependency barrier>
807 y = *x;
David Howells108b42b2006-03-31 16:00:29 +0100808
809Basically, the read barrier always has to be there, even though it can be of
810the "weaker" type.
811
David Howells670bd952006-06-10 09:54:12 -0700812[!] Note that the stores before the write barrier would normally be expected to
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700813match the loads after the read barrier or the data dependency barrier, and vice
David Howells670bd952006-06-10 09:54:12 -0700814versa:
815
Paul E. McKenney2ecf8102013-12-11 13:59:04 -0800816 CPU 1 CPU 2
817 =================== ===================
818 ACCESS_ONCE(a) = 1; }---- --->{ v = ACCESS_ONCE(c);
819 ACCESS_ONCE(b) = 2; } \ / { w = ACCESS_ONCE(d);
820 <write barrier> \ <read barrier>
821 ACCESS_ONCE(c) = 3; } / \ { x = ACCESS_ONCE(a);
822 ACCESS_ONCE(d) = 4; }---- --->{ y = ACCESS_ONCE(b);
David Howells670bd952006-06-10 09:54:12 -0700823
David Howells108b42b2006-03-31 16:00:29 +0100824
825EXAMPLES OF MEMORY BARRIER SEQUENCES
826------------------------------------
827
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700828Firstly, write barriers act as partial orderings on store operations.
David Howells108b42b2006-03-31 16:00:29 +0100829Consider the following sequence of events:
830
831 CPU 1
832 =======================
833 STORE A = 1
834 STORE B = 2
835 STORE C = 3
836 <write barrier>
837 STORE D = 4
838 STORE E = 5
839
840This sequence of events is committed to the memory coherence system in an order
841that the rest of the system might perceive as the unordered set of { STORE A,
Adrian Bunk80f72282006-06-30 18:27:16 +0200842STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
David Howells108b42b2006-03-31 16:00:29 +0100843}:
844
845 +-------+ : :
846 | | +------+
847 | |------>| C=3 | } /\
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700848 | | : +------+ }----- \ -----> Events perceptible to
849 | | : | A=1 | } \/ the rest of the system
David Howells108b42b2006-03-31 16:00:29 +0100850 | | : +------+ }
851 | CPU 1 | : | B=2 | }
852 | | +------+ }
853 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
854 | | +------+ } requires all stores prior to the
855 | | : | E=5 | } barrier to be committed before
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700856 | | : +------+ } further stores may take place
David Howells108b42b2006-03-31 16:00:29 +0100857 | |------>| D=4 | }
858 | | +------+
859 +-------+ : :
860 |
David Howells670bd952006-06-10 09:54:12 -0700861 | Sequence in which stores are committed to the
862 | memory system by CPU 1
David Howells108b42b2006-03-31 16:00:29 +0100863 V
864
865
Jarek Poplawski81fc6322007-05-23 13:58:20 -0700866Secondly, data dependency barriers act as partial orderings on data-dependent
David Howells108b42b2006-03-31 16:00:29 +0100867loads. Consider the following sequence of events:
868
869 CPU 1 CPU 2
870 ======================= =======================
David Howellsc14038c2006-04-10 22:54:24 -0700871 { B = 7; X = 9; Y = 8; C = &Y }
David Howells108b42b2006-03-31 16:00:29 +0100872 STORE A = 1
873 STORE B = 2
874 <write barrier>
875 STORE C = &B LOAD X
876 STORE D = 4 LOAD C (gets &B)
877 LOAD *C (reads B)
878
879Without intervention, CPU 2 may perceive the events on CPU 1 in some
880effectively random order, despite the write barrier issued by CPU 1:
881
882 +-------+ : : : :
883 | | +------+ +-------+ | Sequence of update
884 | |------>| B=2 |----- --->| Y->8 | | of perception on
885 | | : +------+ \ +-------+ | CPU 2
886 | CPU 1 | : | A=1 | \ --->| C->&Y | V
887 | | +------+ | +-------+
888 | | wwwwwwwwwwwwwwww | : :
889 | | +------+ | : :
890 | | : | C=&B |--- | : : +-------+
891 | | : +------+ \ | +-------+ | |
892 | |------>| D=4 | ----------->| C->&B |------>| |
893 | | +------+ | +-------+ | |
894 +-------+ : : | : : | |
895 | : : | |
896 | : : | CPU 2 |
897 | +-------+ | |
898 Apparently incorrect ---> | | B->7 |------>| |
899 perception of B (!) | +-------+ | |
900 | : : | |
901 | +-------+ | |
902 The load of X holds ---> \ | X->9 |------>| |
903 up the maintenance \ +-------+ | |
904 of coherence of B ----->| B->2 | +-------+
905 +-------+
906 : :
907
908
909In the above example, CPU 2 perceives that B is 7, despite the load of *C
Paolo Ornati670e9f32006-10-03 22:57:56 +0200910(which would be B) coming after the LOAD of C.
David Howells108b42b2006-03-31 16:00:29 +0100911
912If, however, a data dependency barrier were to be placed between the load of C
David Howellsc14038c2006-04-10 22:54:24 -0700913and the load of *C (ie: B) on CPU 2:
914
915 CPU 1 CPU 2
916 ======================= =======================
917 { B = 7; X = 9; Y = 8; C = &Y }
918 STORE A = 1
919 STORE B = 2
920 <write barrier>
921 STORE C = &B LOAD X
922 STORE D = 4 LOAD C (gets &B)
923 <data dependency barrier>
924 LOAD *C (reads B)
925
926then the following will occur:
David Howells108b42b2006-03-31 16:00:29 +0100927
928 +-------+ : : : :
929 | | +------+ +-------+
930 | |------>| B=2 |----- --->| Y->8 |
931 | | : +------+ \ +-------+
932 | CPU 1 | : | A=1 | \ --->| C->&Y |
933 | | +------+ | +-------+
934 | | wwwwwwwwwwwwwwww | : :
935 | | +------+ | : :
936 | | : | C=&B |--- | : : +-------+
937 | | : +------+ \ | +-------+ | |
938 | |------>| D=4 | ----------->| C->&B |------>| |
939 | | +------+ | +-------+ | |
940 +-------+ : : | : : | |
941 | : : | |
942 | : : | CPU 2 |
943 | +-------+ | |
David Howells670bd952006-06-10 09:54:12 -0700944 | | X->9 |------>| |
945 | +-------+ | |
946 Makes sure all effects ---> \ ddddddddddddddddd | |
947 prior to the store of C \ +-------+ | |
948 are perceptible to ----->| B->2 |------>| |
949 subsequent loads +-------+ | |
David Howells108b42b2006-03-31 16:00:29 +0100950 : : +-------+
951
952
953And thirdly, a read barrier acts as a partial order on loads. Consider the
954following sequence of events:
955
956 CPU 1 CPU 2
957 ======================= =======================
David Howells670bd952006-06-10 09:54:12 -0700958 { A = 0, B = 9 }
David Howells108b42b2006-03-31 16:00:29 +0100959 STORE A=1
David Howells108b42b2006-03-31 16:00:29 +0100960 <write barrier>
David Howells670bd952006-06-10 09:54:12 -0700961 STORE B=2
David Howells108b42b2006-03-31 16:00:29 +0100962 LOAD B
David Howells670bd952006-06-10 09:54:12 -0700963 LOAD A
David Howells108b42b2006-03-31 16:00:29 +0100964
965Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
966some effectively random order, despite the write barrier issued by CPU 1:
967
David Howells670bd952006-06-10 09:54:12 -0700968 +-------+ : : : :
969 | | +------+ +-------+
970 | |------>| A=1 |------ --->| A->0 |
971 | | +------+ \ +-------+
972 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
973 | | +------+ | +-------+
974 | |------>| B=2 |--- | : :
975 | | +------+ \ | : : +-------+
976 +-------+ : : \ | +-------+ | |
977 ---------->| B->2 |------>| |
978 | +-------+ | CPU 2 |
979 | | A->0 |------>| |
980 | +-------+ | |
981 | : : +-------+
982 \ : :
983 \ +-------+
984 ---->| A->1 |
985 +-------+
986 : :
David Howells108b42b2006-03-31 16:00:29 +0100987
988
David Howells6bc39272006-06-25 05:49:22 -0700989If, however, a read barrier were to be placed between the load of B and the
David Howells670bd952006-06-10 09:54:12 -0700990load of A on CPU 2:
David Howells108b42b2006-03-31 16:00:29 +0100991
David Howells670bd952006-06-10 09:54:12 -0700992 CPU 1 CPU 2
993 ======================= =======================
994 { A = 0, B = 9 }
995 STORE A=1
996 <write barrier>
997 STORE B=2
998 LOAD B
999 <read barrier>
1000 LOAD A
1001
1002then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
10032:
1004
1005 +-------+ : : : :
1006 | | +------+ +-------+
1007 | |------>| A=1 |------ --->| A->0 |
1008 | | +------+ \ +-------+
1009 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1010 | | +------+ | +-------+
1011 | |------>| B=2 |--- | : :
1012 | | +------+ \ | : : +-------+
1013 +-------+ : : \ | +-------+ | |
1014 ---------->| B->2 |------>| |
1015 | +-------+ | CPU 2 |
1016 | : : | |
1017 | : : | |
1018 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1019 barrier causes all effects \ +-------+ | |
1020 prior to the storage of B ---->| A->1 |------>| |
1021 to be perceptible to CPU 2 +-------+ | |
1022 : : +-------+
1023
1024
1025To illustrate this more completely, consider what could happen if the code
1026contained a load of A either side of the read barrier:
1027
1028 CPU 1 CPU 2
1029 ======================= =======================
1030 { A = 0, B = 9 }
1031 STORE A=1
1032 <write barrier>
1033 STORE B=2
1034 LOAD B
1035 LOAD A [first load of A]
1036 <read barrier>
1037 LOAD A [second load of A]
1038
1039Even though the two loads of A both occur after the load of B, they may both
1040come up with different values:
1041
1042 +-------+ : : : :
1043 | | +------+ +-------+
1044 | |------>| A=1 |------ --->| A->0 |
1045 | | +------+ \ +-------+
1046 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1047 | | +------+ | +-------+
1048 | |------>| B=2 |--- | : :
1049 | | +------+ \ | : : +-------+
1050 +-------+ : : \ | +-------+ | |
1051 ---------->| B->2 |------>| |
1052 | +-------+ | CPU 2 |
1053 | : : | |
1054 | : : | |
1055 | +-------+ | |
1056 | | A->0 |------>| 1st |
1057 | +-------+ | |
1058 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1059 barrier causes all effects \ +-------+ | |
1060 prior to the storage of B ---->| A->1 |------>| 2nd |
1061 to be perceptible to CPU 2 +-------+ | |
1062 : : +-------+
1063
1064
1065But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1066before the read barrier completes anyway:
1067
1068 +-------+ : : : :
1069 | | +------+ +-------+
1070 | |------>| A=1 |------ --->| A->0 |
1071 | | +------+ \ +-------+
1072 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1073 | | +------+ | +-------+
1074 | |------>| B=2 |--- | : :
1075 | | +------+ \ | : : +-------+
1076 +-------+ : : \ | +-------+ | |
1077 ---------->| B->2 |------>| |
1078 | +-------+ | CPU 2 |
1079 | : : | |
1080 \ : : | |
1081 \ +-------+ | |
1082 ---->| A->1 |------>| 1st |
1083 +-------+ | |
1084 rrrrrrrrrrrrrrrrr | |
1085 +-------+ | |
1086 | A->1 |------>| 2nd |
1087 +-------+ | |
1088 : : +-------+
1089
1090
1091The guarantee is that the second load will always come up with A == 1 if the
1092load of B came up with B == 2. No such guarantee exists for the first load of
1093A; that may come up with either A == 0 or A == 1.
1094
1095
1096READ MEMORY BARRIERS VS LOAD SPECULATION
1097----------------------------------------
1098
1099Many CPUs speculate with loads: that is they see that they will need to load an
1100item from memory, and they find a time where they're not using the bus for any
1101other loads, and so do the load in advance - even though they haven't actually
1102got to that point in the instruction execution flow yet. This permits the
1103actual load instruction to potentially complete immediately because the CPU
1104already has the value to hand.
1105
1106It may turn out that the CPU didn't actually need the value - perhaps because a
1107branch circumvented the load - in which case it can discard the value or just
1108cache it for later use.
1109
1110Consider:
1111
Ingo Molnare0edc782013-11-22 11:24:53 +01001112 CPU 1 CPU 2
David Howells670bd952006-06-10 09:54:12 -07001113 ======================= =======================
Ingo Molnare0edc782013-11-22 11:24:53 +01001114 LOAD B
1115 DIVIDE } Divide instructions generally
1116 DIVIDE } take a long time to perform
1117 LOAD A
David Howells670bd952006-06-10 09:54:12 -07001118
1119Which might appear as this:
1120
1121 : : +-------+
1122 +-------+ | |
1123 --->| B->2 |------>| |
1124 +-------+ | CPU 2 |
1125 : :DIVIDE | |
1126 +-------+ | |
1127 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1128 division speculates on the +-------+ ~ | |
1129 LOAD of A : : ~ | |
1130 : :DIVIDE | |
1131 : : ~ | |
1132 Once the divisions are complete --> : : ~-->| |
1133 the CPU can then perform the : : | |
1134 LOAD with immediate effect : : +-------+
1135
1136
1137Placing a read barrier or a data dependency barrier just before the second
1138load:
1139
Ingo Molnare0edc782013-11-22 11:24:53 +01001140 CPU 1 CPU 2
David Howells670bd952006-06-10 09:54:12 -07001141 ======================= =======================
Ingo Molnare0edc782013-11-22 11:24:53 +01001142 LOAD B
1143 DIVIDE
1144 DIVIDE
David Howells670bd952006-06-10 09:54:12 -07001145 <read barrier>
Ingo Molnare0edc782013-11-22 11:24:53 +01001146 LOAD A
David Howells670bd952006-06-10 09:54:12 -07001147
1148will force any value speculatively obtained to be reconsidered to an extent
1149dependent on the type of barrier used. If there was no change made to the
1150speculated memory location, then the speculated value will just be used:
1151
1152 : : +-------+
1153 +-------+ | |
1154 --->| B->2 |------>| |
1155 +-------+ | CPU 2 |
1156 : :DIVIDE | |
1157 +-------+ | |
1158 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1159 division speculates on the +-------+ ~ | |
1160 LOAD of A : : ~ | |
1161 : :DIVIDE | |
1162 : : ~ | |
1163 : : ~ | |
1164 rrrrrrrrrrrrrrrr~ | |
1165 : : ~ | |
1166 : : ~-->| |
1167 : : | |
1168 : : +-------+
1169
1170
1171but if there was an update or an invalidation from another CPU pending, then
1172the speculation will be cancelled and the value reloaded:
1173
1174 : : +-------+
1175 +-------+ | |
1176 --->| B->2 |------>| |
1177 +-------+ | CPU 2 |
1178 : :DIVIDE | |
1179 +-------+ | |
1180 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1181 division speculates on the +-------+ ~ | |
1182 LOAD of A : : ~ | |
1183 : :DIVIDE | |
1184 : : ~ | |
1185 : : ~ | |
1186 rrrrrrrrrrrrrrrrr | |
1187 +-------+ | |
1188 The speculation is discarded ---> --->| A->1 |------>| |
1189 and an updated value is +-------+ | |
1190 retrieved : : +-------+
David Howells108b42b2006-03-31 16:00:29 +01001191
1192
Paul E. McKenney241e6662011-02-10 16:54:50 -08001193TRANSITIVITY
1194------------
1195
1196Transitivity is a deeply intuitive notion about ordering that is not
1197always provided by real computer systems. The following example
1198demonstrates transitivity (also called "cumulativity"):
1199
1200 CPU 1 CPU 2 CPU 3
1201 ======================= ======================= =======================
1202 { X = 0, Y = 0 }
1203 STORE X=1 LOAD X STORE Y=1
1204 <general barrier> <general barrier>
1205 LOAD Y LOAD X
1206
1207Suppose that CPU 2's load from X returns 1 and its load from Y returns 0.
1208This indicates that CPU 2's load from X in some sense follows CPU 1's
1209store to X and that CPU 2's load from Y in some sense preceded CPU 3's
1210store to Y. The question is then "Can CPU 3's load from X return 0?"
1211
1212Because CPU 2's load from X in some sense came after CPU 1's store, it
1213is natural to expect that CPU 3's load from X must therefore return 1.
1214This expectation is an example of transitivity: if a load executing on
1215CPU A follows a load from the same variable executing on CPU B, then
1216CPU A's load must either return the same value that CPU B's load did,
1217or must return some later value.
1218
1219In the Linux kernel, use of general memory barriers guarantees
1220transitivity. Therefore, in the above example, if CPU 2's load from X
1221returns 1 and its load from Y returns 0, then CPU 3's load from X must
1222also return 1.
1223
1224However, transitivity is -not- guaranteed for read or write barriers.
1225For example, suppose that CPU 2's general barrier in the above example
1226is changed to a read barrier as shown below:
1227
1228 CPU 1 CPU 2 CPU 3
1229 ======================= ======================= =======================
1230 { X = 0, Y = 0 }
1231 STORE X=1 LOAD X STORE Y=1
1232 <read barrier> <general barrier>
1233 LOAD Y LOAD X
1234
1235This substitution destroys transitivity: in this example, it is perfectly
1236legal for CPU 2's load from X to return 1, its load from Y to return 0,
1237and CPU 3's load from X to return 0.
1238
1239The key point is that although CPU 2's read barrier orders its pair
1240of loads, it does not guarantee to order CPU 1's store. Therefore, if
1241this example runs on a system where CPUs 1 and 2 share a store buffer
1242or a level of cache, CPU 2 might have early access to CPU 1's writes.
1243General barriers are therefore required to ensure that all CPUs agree
1244on the combined order of CPU 1's and CPU 2's accesses.
1245
1246To reiterate, if your code requires transitivity, use general barriers
1247throughout.
1248
1249
David Howells108b42b2006-03-31 16:00:29 +01001250========================
1251EXPLICIT KERNEL BARRIERS
1252========================
1253
1254The Linux kernel has a variety of different barriers that act at different
1255levels:
1256
1257 (*) Compiler barrier.
1258
1259 (*) CPU memory barriers.
1260
1261 (*) MMIO write barrier.
1262
1263
1264COMPILER BARRIER
1265----------------
1266
1267The Linux kernel has an explicit compiler barrier function that prevents the
1268compiler from moving the memory accesses either side of it to the other side:
1269
1270 barrier();
1271
Peter Zijlstra18c03c62013-12-11 13:59:06 -08001272This is a general barrier -- there are no read-read or write-write variants
Paul E. McKenney692118d2013-12-11 13:59:07 -08001273of barrier(). However, ACCESS_ONCE() can be thought of as a weak form
Peter Zijlstra18c03c62013-12-11 13:59:06 -08001274for barrier() that affects only the specific accesses flagged by the
1275ACCESS_ONCE().
David Howells108b42b2006-03-31 16:00:29 +01001276
Paul E. McKenney692118d2013-12-11 13:59:07 -08001277The barrier() function has the following effects:
1278
1279 (*) Prevents the compiler from reordering accesses following the
1280 barrier() to precede any accesses preceding the barrier().
1281 One example use for this property is to ease communication between
1282 interrupt-handler code and the code that was interrupted.
1283
1284 (*) Within a loop, forces the compiler to load the variables used
1285 in that loop's conditional on each pass through that loop.
1286
1287The ACCESS_ONCE() function can prevent any number of optimizations that,
1288while perfectly safe in single-threaded code, can be fatal in concurrent
1289code. Here are some examples of these sorts of optimizations:
1290
Paul E. McKenney449f7412014-01-02 15:03:50 -08001291 (*) The compiler is within its rights to reorder loads and stores
1292 to the same variable, and in some cases, the CPU is within its
1293 rights to reorder loads to the same variable. This means that
1294 the following code:
1295
1296 a[0] = x;
1297 a[1] = x;
1298
1299 Might result in an older value of x stored in a[1] than in a[0].
1300 Prevent both the compiler and the CPU from doing this as follows:
1301
1302 a[0] = ACCESS_ONCE(x);
1303 a[1] = ACCESS_ONCE(x);
1304
1305 In short, ACCESS_ONCE() provides cache coherence for accesses from
1306 multiple CPUs to a single variable.
1307
Paul E. McKenney692118d2013-12-11 13:59:07 -08001308 (*) The compiler is within its rights to merge successive loads from
1309 the same variable. Such merging can cause the compiler to "optimize"
1310 the following code:
1311
1312 while (tmp = a)
1313 do_something_with(tmp);
1314
1315 into the following code, which, although in some sense legitimate
1316 for single-threaded code, is almost certainly not what the developer
1317 intended:
1318
1319 if (tmp = a)
1320 for (;;)
1321 do_something_with(tmp);
1322
1323 Use ACCESS_ONCE() to prevent the compiler from doing this to you:
1324
1325 while (tmp = ACCESS_ONCE(a))
1326 do_something_with(tmp);
1327
1328 (*) The compiler is within its rights to reload a variable, for example,
1329 in cases where high register pressure prevents the compiler from
1330 keeping all data of interest in registers. The compiler might
1331 therefore optimize the variable 'tmp' out of our previous example:
1332
1333 while (tmp = a)
1334 do_something_with(tmp);
1335
1336 This could result in the following code, which is perfectly safe in
1337 single-threaded code, but can be fatal in concurrent code:
1338
1339 while (a)
1340 do_something_with(a);
1341
1342 For example, the optimized version of this code could result in
1343 passing a zero to do_something_with() in the case where the variable
1344 a was modified by some other CPU between the "while" statement and
1345 the call to do_something_with().
1346
1347 Again, use ACCESS_ONCE() to prevent the compiler from doing this:
1348
1349 while (tmp = ACCESS_ONCE(a))
1350 do_something_with(tmp);
1351
1352 Note that if the compiler runs short of registers, it might save
1353 tmp onto the stack. The overhead of this saving and later restoring
1354 is why compilers reload variables. Doing so is perfectly safe for
1355 single-threaded code, so you need to tell the compiler about cases
1356 where it is not safe.
1357
1358 (*) The compiler is within its rights to omit a load entirely if it knows
1359 what the value will be. For example, if the compiler can prove that
1360 the value of variable 'a' is always zero, it can optimize this code:
1361
1362 while (tmp = a)
1363 do_something_with(tmp);
1364
1365 Into this:
1366
1367 do { } while (0);
1368
1369 This transformation is a win for single-threaded code because it gets
1370 rid of a load and a branch. The problem is that the compiler will
1371 carry out its proof assuming that the current CPU is the only one
1372 updating variable 'a'. If variable 'a' is shared, then the compiler's
1373 proof will be erroneous. Use ACCESS_ONCE() to tell the compiler
1374 that it doesn't know as much as it thinks it does:
1375
1376 while (tmp = ACCESS_ONCE(a))
1377 do_something_with(tmp);
1378
1379 But please note that the compiler is also closely watching what you
1380 do with the value after the ACCESS_ONCE(). For example, suppose you
1381 do the following and MAX is a preprocessor macro with the value 1:
1382
1383 while ((tmp = ACCESS_ONCE(a)) % MAX)
1384 do_something_with(tmp);
1385
1386 Then the compiler knows that the result of the "%" operator applied
1387 to MAX will always be zero, again allowing the compiler to optimize
1388 the code into near-nonexistence. (It will still load from the
1389 variable 'a'.)
1390
1391 (*) Similarly, the compiler is within its rights to omit a store entirely
1392 if it knows that the variable already has the value being stored.
1393 Again, the compiler assumes that the current CPU is the only one
1394 storing into the variable, which can cause the compiler to do the
1395 wrong thing for shared variables. For example, suppose you have
1396 the following:
1397
1398 a = 0;
1399 /* Code that does not store to variable a. */
1400 a = 0;
1401
1402 The compiler sees that the value of variable 'a' is already zero, so
1403 it might well omit the second store. This would come as a fatal
1404 surprise if some other CPU might have stored to variable 'a' in the
1405 meantime.
1406
1407 Use ACCESS_ONCE() to prevent the compiler from making this sort of
1408 wrong guess:
1409
1410 ACCESS_ONCE(a) = 0;
1411 /* Code that does not store to variable a. */
1412 ACCESS_ONCE(a) = 0;
1413
1414 (*) The compiler is within its rights to reorder memory accesses unless
1415 you tell it not to. For example, consider the following interaction
1416 between process-level code and an interrupt handler:
1417
1418 void process_level(void)
1419 {
1420 msg = get_message();
1421 flag = true;
1422 }
1423
1424 void interrupt_handler(void)
1425 {
1426 if (flag)
1427 process_message(msg);
1428 }
1429
Masanari Iidadf5cbb22014-03-21 10:04:30 +09001430 There is nothing to prevent the compiler from transforming
Paul E. McKenney692118d2013-12-11 13:59:07 -08001431 process_level() to the following, in fact, this might well be a
1432 win for single-threaded code:
1433
1434 void process_level(void)
1435 {
1436 flag = true;
1437 msg = get_message();
1438 }
1439
1440 If the interrupt occurs between these two statement, then
1441 interrupt_handler() might be passed a garbled msg. Use ACCESS_ONCE()
1442 to prevent this as follows:
1443
1444 void process_level(void)
1445 {
1446 ACCESS_ONCE(msg) = get_message();
1447 ACCESS_ONCE(flag) = true;
1448 }
1449
1450 void interrupt_handler(void)
1451 {
1452 if (ACCESS_ONCE(flag))
1453 process_message(ACCESS_ONCE(msg));
1454 }
1455
1456 Note that the ACCESS_ONCE() wrappers in interrupt_handler()
1457 are needed if this interrupt handler can itself be interrupted
1458 by something that also accesses 'flag' and 'msg', for example,
1459 a nested interrupt or an NMI. Otherwise, ACCESS_ONCE() is not
1460 needed in interrupt_handler() other than for documentation purposes.
1461 (Note also that nested interrupts do not typically occur in modern
1462 Linux kernels, in fact, if an interrupt handler returns with
1463 interrupts enabled, you will get a WARN_ONCE() splat.)
1464
1465 You should assume that the compiler can move ACCESS_ONCE() past
1466 code not containing ACCESS_ONCE(), barrier(), or similar primitives.
1467
1468 This effect could also be achieved using barrier(), but ACCESS_ONCE()
1469 is more selective: With ACCESS_ONCE(), the compiler need only forget
1470 the contents of the indicated memory locations, while with barrier()
1471 the compiler must discard the value of all memory locations that
1472 it has currented cached in any machine registers. Of course,
1473 the compiler must also respect the order in which the ACCESS_ONCE()s
1474 occur, though the CPU of course need not do so.
1475
1476 (*) The compiler is within its rights to invent stores to a variable,
1477 as in the following example:
1478
1479 if (a)
1480 b = a;
1481 else
1482 b = 42;
1483
1484 The compiler might save a branch by optimizing this as follows:
1485
1486 b = 42;
1487 if (a)
1488 b = a;
1489
1490 In single-threaded code, this is not only safe, but also saves
1491 a branch. Unfortunately, in concurrent code, this optimization
1492 could cause some other CPU to see a spurious value of 42 -- even
1493 if variable 'a' was never zero -- when loading variable 'b'.
1494 Use ACCESS_ONCE() to prevent this as follows:
1495
1496 if (a)
1497 ACCESS_ONCE(b) = a;
1498 else
1499 ACCESS_ONCE(b) = 42;
1500
1501 The compiler can also invent loads. These are usually less
1502 damaging, but they can result in cache-line bouncing and thus in
1503 poor performance and scalability. Use ACCESS_ONCE() to prevent
1504 invented loads.
1505
1506 (*) For aligned memory locations whose size allows them to be accessed
1507 with a single memory-reference instruction, prevents "load tearing"
1508 and "store tearing," in which a single large access is replaced by
1509 multiple smaller accesses. For example, given an architecture having
1510 16-bit store instructions with 7-bit immediate fields, the compiler
1511 might be tempted to use two 16-bit store-immediate instructions to
1512 implement the following 32-bit store:
1513
1514 p = 0x00010002;
1515
1516 Please note that GCC really does use this sort of optimization,
1517 which is not surprising given that it would likely take more
1518 than two instructions to build the constant and then store it.
1519 This optimization can therefore be a win in single-threaded code.
1520 In fact, a recent bug (since fixed) caused GCC to incorrectly use
1521 this optimization in a volatile store. In the absence of such bugs,
1522 use of ACCESS_ONCE() prevents store tearing in the following example:
1523
1524 ACCESS_ONCE(p) = 0x00010002;
1525
1526 Use of packed structures can also result in load and store tearing,
1527 as in this example:
1528
1529 struct __attribute__((__packed__)) foo {
1530 short a;
1531 int b;
1532 short c;
1533 };
1534 struct foo foo1, foo2;
1535 ...
1536
1537 foo2.a = foo1.a;
1538 foo2.b = foo1.b;
1539 foo2.c = foo1.c;
1540
1541 Because there are no ACCESS_ONCE() wrappers and no volatile markings,
1542 the compiler would be well within its rights to implement these three
1543 assignment statements as a pair of 32-bit loads followed by a pair
1544 of 32-bit stores. This would result in load tearing on 'foo1.b'
1545 and store tearing on 'foo2.b'. ACCESS_ONCE() again prevents tearing
1546 in this example:
1547
1548 foo2.a = foo1.a;
1549 ACCESS_ONCE(foo2.b) = ACCESS_ONCE(foo1.b);
1550 foo2.c = foo1.c;
1551
1552All that aside, it is never necessary to use ACCESS_ONCE() on a variable
1553that has been marked volatile. For example, because 'jiffies' is marked
1554volatile, it is never necessary to say ACCESS_ONCE(jiffies). The reason
1555for this is that ACCESS_ONCE() is implemented as a volatile cast, which
1556has no effect when its argument is already marked volatile.
1557
1558Please note that these compiler barriers have no direct effect on the CPU,
1559which may then reorder things however it wishes.
David Howells108b42b2006-03-31 16:00:29 +01001560
1561
1562CPU MEMORY BARRIERS
1563-------------------
1564
1565The Linux kernel has eight basic CPU memory barriers:
1566
1567 TYPE MANDATORY SMP CONDITIONAL
1568 =============== ======================= ===========================
1569 GENERAL mb() smp_mb()
1570 WRITE wmb() smp_wmb()
1571 READ rmb() smp_rmb()
1572 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
1573
1574
Nick Piggin73f10282008-05-14 06:35:11 +02001575All memory barriers except the data dependency barriers imply a compiler
1576barrier. Data dependencies do not impose any additional compiler ordering.
1577
1578Aside: In the case of data dependencies, the compiler would be expected to
1579issue the loads in the correct order (eg. `a[b]` would have to load the value
1580of b before loading a[b]), however there is no guarantee in the C specification
1581that the compiler may not speculate the value of b (eg. is equal to 1) and load
1582a before b (eg. tmp = a[1]; if (b != 1) tmp = a[b]; ). There is also the
1583problem of a compiler reloading b after having loaded a[b], thus having a newer
1584copy of b than a[b]. A consensus has not yet been reached about these problems,
1585however the ACCESS_ONCE macro is a good place to start looking.
David Howells108b42b2006-03-31 16:00:29 +01001586
1587SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
Jarek Poplawski81fc6322007-05-23 13:58:20 -07001588systems because it is assumed that a CPU will appear to be self-consistent,
David Howells108b42b2006-03-31 16:00:29 +01001589and will order overlapping accesses correctly with respect to itself.
1590
1591[!] Note that SMP memory barriers _must_ be used to control the ordering of
1592references to shared memory on SMP systems, though the use of locking instead
1593is sufficient.
1594
1595Mandatory barriers should not be used to control SMP effects, since mandatory
1596barriers unnecessarily impose overhead on UP systems. They may, however, be
1597used to control MMIO effects on accesses through relaxed memory I/O windows.
1598These are required even on non-SMP systems as they affect the order in which
1599memory operations appear to a device by prohibiting both the compiler and the
1600CPU from reordering them.
1601
1602
1603There are some more advanced barrier functions:
1604
1605 (*) set_mb(var, value)
David Howells108b42b2006-03-31 16:00:29 +01001606
Oleg Nesterov75b2bd52006-11-08 17:44:38 -08001607 This assigns the value to the variable and then inserts a full memory
Steven Rostedtf92213b2006-07-14 16:05:01 -04001608 barrier after it, depending on the function. It isn't guaranteed to
David Howells108b42b2006-03-31 16:00:29 +01001609 insert anything more than a compiler barrier in a UP compilation.
1610
1611
Peter Zijlstra1b156112014-03-13 19:00:35 +01001612 (*) smp_mb__before_atomic();
1613 (*) smp_mb__after_atomic();
David Howells108b42b2006-03-31 16:00:29 +01001614
Peter Zijlstra1b156112014-03-13 19:00:35 +01001615 These are for use with atomic (such as add, subtract, increment and
1616 decrement) functions that don't return a value, especially when used for
1617 reference counting. These functions do not imply memory barriers.
1618
1619 These are also used for atomic bitop functions that do not return a
1620 value (such as set_bit and clear_bit).
David Howells108b42b2006-03-31 16:00:29 +01001621
1622 As an example, consider a piece of code that marks an object as being dead
1623 and then decrements the object's reference count:
1624
1625 obj->dead = 1;
Peter Zijlstra1b156112014-03-13 19:00:35 +01001626 smp_mb__before_atomic();
David Howells108b42b2006-03-31 16:00:29 +01001627 atomic_dec(&obj->ref_count);
1628
1629 This makes sure that the death mark on the object is perceived to be set
1630 *before* the reference counter is decremented.
1631
1632 See Documentation/atomic_ops.txt for more information. See the "Atomic
1633 operations" subsection for information on where to use these.
1634
1635
David Howells108b42b2006-03-31 16:00:29 +01001636MMIO WRITE BARRIER
1637------------------
1638
1639The Linux kernel also has a special barrier for use with memory-mapped I/O
1640writes:
1641
1642 mmiowb();
1643
1644This is a variation on the mandatory write barrier that causes writes to weakly
1645ordered I/O regions to be partially ordered. Its effects may go beyond the
1646CPU->Hardware interface and actually affect the hardware at some level.
1647
1648See the subsection "Locks vs I/O accesses" for more information.
1649
1650
1651===============================
1652IMPLICIT KERNEL MEMORY BARRIERS
1653===============================
1654
1655Some of the other functions in the linux kernel imply memory barriers, amongst
David Howells670bd952006-06-10 09:54:12 -07001656which are locking and scheduling functions.
David Howells108b42b2006-03-31 16:00:29 +01001657
1658This specification is a _minimum_ guarantee; any particular architecture may
1659provide more substantial guarantees, but these may not be relied upon outside
1660of arch specific code.
1661
1662
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001663ACQUIRING FUNCTIONS
1664-------------------
David Howells108b42b2006-03-31 16:00:29 +01001665
1666The Linux kernel has a number of locking constructs:
1667
1668 (*) spin locks
1669 (*) R/W spin locks
1670 (*) mutexes
1671 (*) semaphores
1672 (*) R/W semaphores
1673 (*) RCU
1674
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001675In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
David Howells108b42b2006-03-31 16:00:29 +01001676for each construct. These operations all imply certain barriers:
1677
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001678 (1) ACQUIRE operation implication:
David Howells108b42b2006-03-31 16:00:29 +01001679
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001680 Memory operations issued after the ACQUIRE will be completed after the
1681 ACQUIRE operation has completed.
David Howells108b42b2006-03-31 16:00:29 +01001682
Paul E. McKenney8dd853d2014-02-23 08:34:24 -08001683 Memory operations issued before the ACQUIRE may be completed after
1684 the ACQUIRE operation has completed. An smp_mb__before_spinlock(),
1685 combined with a following ACQUIRE, orders prior loads against
1686 subsequent loads and stores and also orders prior stores against
1687 subsequent stores. Note that this is weaker than smp_mb()! The
1688 smp_mb__before_spinlock() primitive is free on many architectures.
David Howells108b42b2006-03-31 16:00:29 +01001689
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001690 (2) RELEASE operation implication:
David Howells108b42b2006-03-31 16:00:29 +01001691
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001692 Memory operations issued before the RELEASE will be completed before the
1693 RELEASE operation has completed.
David Howells108b42b2006-03-31 16:00:29 +01001694
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001695 Memory operations issued after the RELEASE may be completed before the
1696 RELEASE operation has completed.
David Howells108b42b2006-03-31 16:00:29 +01001697
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001698 (3) ACQUIRE vs ACQUIRE implication:
David Howells108b42b2006-03-31 16:00:29 +01001699
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001700 All ACQUIRE operations issued before another ACQUIRE operation will be
1701 completed before that ACQUIRE operation.
David Howells108b42b2006-03-31 16:00:29 +01001702
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001703 (4) ACQUIRE vs RELEASE implication:
David Howells108b42b2006-03-31 16:00:29 +01001704
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001705 All ACQUIRE operations issued before a RELEASE operation will be
1706 completed before the RELEASE operation.
David Howells108b42b2006-03-31 16:00:29 +01001707
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001708 (5) Failed conditional ACQUIRE implication:
David Howells108b42b2006-03-31 16:00:29 +01001709
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001710 Certain locking variants of the ACQUIRE operation may fail, either due to
1711 being unable to get the lock immediately, or due to receiving an unblocked
David Howells108b42b2006-03-31 16:00:29 +01001712 signal whilst asleep waiting for the lock to become available. Failed
1713 locks do not imply any sort of barrier.
1714
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001715[!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
1716one-way barriers is that the effects of instructions outside of a critical
1717section may seep into the inside of the critical section.
David Howells108b42b2006-03-31 16:00:29 +01001718
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001719An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
1720because it is possible for an access preceding the ACQUIRE to happen after the
1721ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
1722the two accesses can themselves then cross:
David Howells670bd952006-06-10 09:54:12 -07001723
1724 *A = a;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001725 ACQUIRE M
1726 RELEASE M
David Howells670bd952006-06-10 09:54:12 -07001727 *B = b;
1728
1729may occur as:
1730
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001731 ACQUIRE M, STORE *B, STORE *A, RELEASE M
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001732
Paul E. McKenney8dd853d2014-02-23 08:34:24 -08001733When the ACQUIRE and RELEASE are a lock acquisition and release,
1734respectively, this same reordering can occur if the lock's ACQUIRE and
1735RELEASE are to the same lock variable, but only from the perspective of
1736another CPU not holding that lock. In short, a ACQUIRE followed by an
1737RELEASE may -not- be assumed to be a full memory barrier.
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001738
Paul E. McKenney8dd853d2014-02-23 08:34:24 -08001739Similarly, the reverse case of a RELEASE followed by an ACQUIRE does not
1740imply a full memory barrier. If it is necessary for a RELEASE-ACQUIRE
1741pair to produce a full barrier, the ACQUIRE can be followed by an
1742smp_mb__after_unlock_lock() invocation. This will produce a full barrier
1743if either (a) the RELEASE and the ACQUIRE are executed by the same
1744CPU or task, or (b) the RELEASE and ACQUIRE act on the same variable.
1745The smp_mb__after_unlock_lock() primitive is free on many architectures.
1746Without smp_mb__after_unlock_lock(), the CPU's execution of the critical
1747sections corresponding to the RELEASE and the ACQUIRE can cross, so that:
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001748
1749 *A = a;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001750 RELEASE M
1751 ACQUIRE N
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001752 *B = b;
1753
1754could occur as:
1755
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001756 ACQUIRE N, STORE *B, STORE *A, RELEASE M
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001757
Paul E. McKenney8dd853d2014-02-23 08:34:24 -08001758It might appear that this reordering could introduce a deadlock.
1759However, this cannot happen because if such a deadlock threatened,
1760the RELEASE would simply complete, thereby avoiding the deadlock.
1761
1762 Why does this work?
1763
1764 One key point is that we are only talking about the CPU doing
1765 the reordering, not the compiler. If the compiler (or, for
1766 that matter, the developer) switched the operations, deadlock
1767 -could- occur.
1768
1769 But suppose the CPU reordered the operations. In this case,
1770 the unlock precedes the lock in the assembly code. The CPU
1771 simply elected to try executing the later lock operation first.
1772 If there is a deadlock, this lock operation will simply spin (or
1773 try to sleep, but more on that later). The CPU will eventually
1774 execute the unlock operation (which preceded the lock operation
1775 in the assembly code), which will unravel the potential deadlock,
1776 allowing the lock operation to succeed.
1777
1778 But what if the lock is a sleeplock? In that case, the code will
1779 try to enter the scheduler, where it will eventually encounter
1780 a memory barrier, which will force the earlier unlock operation
1781 to complete, again unraveling the deadlock. There might be
1782 a sleep-unlock race, but the locking primitive needs to resolve
1783 such races properly in any case.
1784
1785With smp_mb__after_unlock_lock(), the two critical sections cannot overlap.
1786For example, with the following code, the store to *A will always be
1787seen by other CPUs before the store to *B:
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001788
1789 *A = a;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001790 RELEASE M
1791 ACQUIRE N
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001792 smp_mb__after_unlock_lock();
1793 *B = b;
1794
Paul E. McKenney8dd853d2014-02-23 08:34:24 -08001795The operations will always occur in one of the following orders:
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001796
Paul E. McKenney8dd853d2014-02-23 08:34:24 -08001797 STORE *A, RELEASE, ACQUIRE, smp_mb__after_unlock_lock(), STORE *B
1798 STORE *A, ACQUIRE, RELEASE, smp_mb__after_unlock_lock(), STORE *B
1799 ACQUIRE, STORE *A, RELEASE, smp_mb__after_unlock_lock(), STORE *B
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08001800
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001801If the RELEASE and ACQUIRE were instead both operating on the same lock
Paul E. McKenney8dd853d2014-02-23 08:34:24 -08001802variable, only the first of these alternatives can occur. In addition,
1803the more strongly ordered systems may rule out some of the above orders.
1804But in any case, as noted earlier, the smp_mb__after_unlock_lock()
1805ensures that the store to *A will always be seen as happening before
1806the store to *B.
David Howells670bd952006-06-10 09:54:12 -07001807
David Howells108b42b2006-03-31 16:00:29 +01001808Locks and semaphores may not provide any guarantee of ordering on UP compiled
1809systems, and so cannot be counted on in such a situation to actually achieve
1810anything at all - especially with respect to I/O accesses - unless combined
1811with interrupt disabling operations.
1812
1813See also the section on "Inter-CPU locking barrier effects".
1814
1815
1816As an example, consider the following:
1817
1818 *A = a;
1819 *B = b;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001820 ACQUIRE
David Howells108b42b2006-03-31 16:00:29 +01001821 *C = c;
1822 *D = d;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001823 RELEASE
David Howells108b42b2006-03-31 16:00:29 +01001824 *E = e;
1825 *F = f;
1826
1827The following sequence of events is acceptable:
1828
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001829 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
David Howells108b42b2006-03-31 16:00:29 +01001830
1831 [+] Note that {*F,*A} indicates a combined access.
1832
1833But none of the following are:
1834
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001835 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
1836 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
1837 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
1838 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
David Howells108b42b2006-03-31 16:00:29 +01001839
1840
1841
1842INTERRUPT DISABLING FUNCTIONS
1843-----------------------------
1844
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01001845Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts
1846(RELEASE equivalent) will act as compiler barriers only. So if memory or I/O
David Howells108b42b2006-03-31 16:00:29 +01001847barriers are required in such a situation, they must be provided from some
1848other means.
1849
1850
David Howells50fa6102009-04-28 15:01:38 +01001851SLEEP AND WAKE-UP FUNCTIONS
1852---------------------------
1853
1854Sleeping and waking on an event flagged in global data can be viewed as an
1855interaction between two pieces of data: the task state of the task waiting for
1856the event and the global data used to indicate the event. To make sure that
1857these appear to happen in the right order, the primitives to begin the process
1858of going to sleep, and the primitives to initiate a wake up imply certain
1859barriers.
1860
1861Firstly, the sleeper normally follows something like this sequence of events:
1862
1863 for (;;) {
1864 set_current_state(TASK_UNINTERRUPTIBLE);
1865 if (event_indicated)
1866 break;
1867 schedule();
1868 }
1869
1870A general memory barrier is interpolated automatically by set_current_state()
1871after it has altered the task state:
1872
1873 CPU 1
1874 ===============================
1875 set_current_state();
1876 set_mb();
1877 STORE current->state
1878 <general barrier>
1879 LOAD event_indicated
1880
1881set_current_state() may be wrapped by:
1882
1883 prepare_to_wait();
1884 prepare_to_wait_exclusive();
1885
1886which therefore also imply a general memory barrier after setting the state.
1887The whole sequence above is available in various canned forms, all of which
1888interpolate the memory barrier in the right place:
1889
1890 wait_event();
1891 wait_event_interruptible();
1892 wait_event_interruptible_exclusive();
1893 wait_event_interruptible_timeout();
1894 wait_event_killable();
1895 wait_event_timeout();
1896 wait_on_bit();
1897 wait_on_bit_lock();
1898
1899
1900Secondly, code that performs a wake up normally follows something like this:
1901
1902 event_indicated = 1;
1903 wake_up(&event_wait_queue);
1904
1905or:
1906
1907 event_indicated = 1;
1908 wake_up_process(event_daemon);
1909
1910A write memory barrier is implied by wake_up() and co. if and only if they wake
1911something up. The barrier occurs before the task state is cleared, and so sits
1912between the STORE to indicate the event and the STORE to set TASK_RUNNING:
1913
1914 CPU 1 CPU 2
1915 =============================== ===============================
1916 set_current_state(); STORE event_indicated
1917 set_mb(); wake_up();
1918 STORE current->state <write barrier>
1919 <general barrier> STORE current->state
1920 LOAD event_indicated
1921
Paul E. McKenney5726ce02014-05-13 10:14:51 -07001922To repeat, this write memory barrier is present if and only if something
1923is actually awakened. To see this, consider the following sequence of
1924events, where X and Y are both initially zero:
1925
1926 CPU 1 CPU 2
1927 =============================== ===============================
1928 X = 1; STORE event_indicated
1929 smp_mb(); wake_up();
1930 Y = 1; wait_event(wq, Y == 1);
1931 wake_up(); load from Y sees 1, no memory barrier
1932 load from X might see 0
1933
1934In contrast, if a wakeup does occur, CPU 2's load from X would be guaranteed
1935to see 1.
1936
David Howells50fa6102009-04-28 15:01:38 +01001937The available waker functions include:
1938
1939 complete();
1940 wake_up();
1941 wake_up_all();
1942 wake_up_bit();
1943 wake_up_interruptible();
1944 wake_up_interruptible_all();
1945 wake_up_interruptible_nr();
1946 wake_up_interruptible_poll();
1947 wake_up_interruptible_sync();
1948 wake_up_interruptible_sync_poll();
1949 wake_up_locked();
1950 wake_up_locked_poll();
1951 wake_up_nr();
1952 wake_up_poll();
1953 wake_up_process();
1954
1955
1956[!] Note that the memory barriers implied by the sleeper and the waker do _not_
1957order multiple stores before the wake-up with respect to loads of those stored
1958values after the sleeper has called set_current_state(). For instance, if the
1959sleeper does:
1960
1961 set_current_state(TASK_INTERRUPTIBLE);
1962 if (event_indicated)
1963 break;
1964 __set_current_state(TASK_RUNNING);
1965 do_something(my_data);
1966
1967and the waker does:
1968
1969 my_data = value;
1970 event_indicated = 1;
1971 wake_up(&event_wait_queue);
1972
1973there's no guarantee that the change to event_indicated will be perceived by
1974the sleeper as coming after the change to my_data. In such a circumstance, the
1975code on both sides must interpolate its own memory barriers between the
1976separate data accesses. Thus the above sleeper ought to do:
1977
1978 set_current_state(TASK_INTERRUPTIBLE);
1979 if (event_indicated) {
1980 smp_rmb();
1981 do_something(my_data);
1982 }
1983
1984and the waker should do:
1985
1986 my_data = value;
1987 smp_wmb();
1988 event_indicated = 1;
1989 wake_up(&event_wait_queue);
1990
1991
David Howells108b42b2006-03-31 16:00:29 +01001992MISCELLANEOUS FUNCTIONS
1993-----------------------
1994
1995Other functions that imply barriers:
1996
1997 (*) schedule() and similar imply full memory barriers.
1998
David Howells108b42b2006-03-31 16:00:29 +01001999
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002000===================================
2001INTER-CPU ACQUIRING BARRIER EFFECTS
2002===================================
David Howells108b42b2006-03-31 16:00:29 +01002003
2004On SMP systems locking primitives give a more substantial form of barrier: one
2005that does affect memory access ordering on other CPUs, within the context of
2006conflict on any particular lock.
2007
2008
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002009ACQUIRES VS MEMORY ACCESSES
2010---------------------------
David Howells108b42b2006-03-31 16:00:29 +01002011
Aneesh Kumar79afecf2006-05-15 09:44:36 -07002012Consider the following: the system has a pair of spinlocks (M) and (Q), and
David Howells108b42b2006-03-31 16:00:29 +01002013three CPUs; then should the following sequence of events occur:
2014
2015 CPU 1 CPU 2
2016 =============================== ===============================
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002017 ACCESS_ONCE(*A) = a; ACCESS_ONCE(*E) = e;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002018 ACQUIRE M ACQUIRE Q
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002019 ACCESS_ONCE(*B) = b; ACCESS_ONCE(*F) = f;
2020 ACCESS_ONCE(*C) = c; ACCESS_ONCE(*G) = g;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002021 RELEASE M RELEASE Q
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002022 ACCESS_ONCE(*D) = d; ACCESS_ONCE(*H) = h;
David Howells108b42b2006-03-31 16:00:29 +01002023
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002024Then there is no guarantee as to what order CPU 3 will see the accesses to *A
David Howells108b42b2006-03-31 16:00:29 +01002025through *H occur in, other than the constraints imposed by the separate locks
2026on the separate CPUs. It might, for example, see:
2027
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002028 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
David Howells108b42b2006-03-31 16:00:29 +01002029
2030But it won't see any of:
2031
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002032 *B, *C or *D preceding ACQUIRE M
2033 *A, *B or *C following RELEASE M
2034 *F, *G or *H preceding ACQUIRE Q
2035 *E, *F or *G following RELEASE Q
David Howells108b42b2006-03-31 16:00:29 +01002036
2037
2038However, if the following occurs:
2039
2040 CPU 1 CPU 2
2041 =============================== ===============================
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002042 ACCESS_ONCE(*A) = a;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002043 ACQUIRE M [1]
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002044 ACCESS_ONCE(*B) = b;
2045 ACCESS_ONCE(*C) = c;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002046 RELEASE M [1]
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002047 ACCESS_ONCE(*D) = d; ACCESS_ONCE(*E) = e;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002048 ACQUIRE M [2]
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08002049 smp_mb__after_unlock_lock();
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002050 ACCESS_ONCE(*F) = f;
2051 ACCESS_ONCE(*G) = g;
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002052 RELEASE M [2]
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002053 ACCESS_ONCE(*H) = h;
David Howells108b42b2006-03-31 16:00:29 +01002054
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002055CPU 3 might see:
David Howells108b42b2006-03-31 16:00:29 +01002056
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002057 *E, ACQUIRE M [1], *C, *B, *A, RELEASE M [1],
2058 ACQUIRE M [2], *H, *F, *G, RELEASE M [2], *D
David Howells108b42b2006-03-31 16:00:29 +01002059
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002060But assuming CPU 1 gets the lock first, CPU 3 won't see any of:
David Howells108b42b2006-03-31 16:00:29 +01002061
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002062 *B, *C, *D, *F, *G or *H preceding ACQUIRE M [1]
2063 *A, *B or *C following RELEASE M [1]
2064 *F, *G or *H preceding ACQUIRE M [2]
2065 *A, *B, *C, *E, *F or *G following RELEASE M [2]
David Howells108b42b2006-03-31 16:00:29 +01002066
Paul E. McKenney17eb88e2013-12-11 13:59:09 -08002067Note that the smp_mb__after_unlock_lock() is critically important
2068here: Without it CPU 3 might see some of the above orderings.
2069Without smp_mb__after_unlock_lock(), the accesses are not guaranteed
2070to be seen in order unless CPU 3 holds lock M.
2071
David Howells108b42b2006-03-31 16:00:29 +01002072
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002073ACQUIRES VS I/O ACCESSES
2074------------------------
David Howells108b42b2006-03-31 16:00:29 +01002075
2076Under certain circumstances (especially involving NUMA), I/O accesses within
2077two spinlocked sections on two different CPUs may be seen as interleaved by the
2078PCI bridge, because the PCI bridge does not necessarily participate in the
2079cache-coherence protocol, and is therefore incapable of issuing the required
2080read memory barriers.
2081
2082For example:
2083
2084 CPU 1 CPU 2
2085 =============================== ===============================
2086 spin_lock(Q)
2087 writel(0, ADDR)
2088 writel(1, DATA);
2089 spin_unlock(Q);
2090 spin_lock(Q);
2091 writel(4, ADDR);
2092 writel(5, DATA);
2093 spin_unlock(Q);
2094
2095may be seen by the PCI bridge as follows:
2096
2097 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
2098
2099which would probably cause the hardware to malfunction.
2100
2101
2102What is necessary here is to intervene with an mmiowb() before dropping the
2103spinlock, for example:
2104
2105 CPU 1 CPU 2
2106 =============================== ===============================
2107 spin_lock(Q)
2108 writel(0, ADDR)
2109 writel(1, DATA);
2110 mmiowb();
2111 spin_unlock(Q);
2112 spin_lock(Q);
2113 writel(4, ADDR);
2114 writel(5, DATA);
2115 mmiowb();
2116 spin_unlock(Q);
2117
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002118this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
2119before either of the stores issued on CPU 2.
David Howells108b42b2006-03-31 16:00:29 +01002120
2121
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002122Furthermore, following a store by a load from the same device obviates the need
2123for the mmiowb(), because the load forces the store to complete before the load
David Howells108b42b2006-03-31 16:00:29 +01002124is performed:
2125
2126 CPU 1 CPU 2
2127 =============================== ===============================
2128 spin_lock(Q)
2129 writel(0, ADDR)
2130 a = readl(DATA);
2131 spin_unlock(Q);
2132 spin_lock(Q);
2133 writel(4, ADDR);
2134 b = readl(DATA);
2135 spin_unlock(Q);
2136
2137
2138See Documentation/DocBook/deviceiobook.tmpl for more information.
2139
2140
2141=================================
2142WHERE ARE MEMORY BARRIERS NEEDED?
2143=================================
2144
2145Under normal operation, memory operation reordering is generally not going to
2146be a problem as a single-threaded linear piece of code will still appear to
David Howells50fa6102009-04-28 15:01:38 +01002147work correctly, even if it's in an SMP kernel. There are, however, four
David Howells108b42b2006-03-31 16:00:29 +01002148circumstances in which reordering definitely _could_ be a problem:
2149
2150 (*) Interprocessor interaction.
2151
2152 (*) Atomic operations.
2153
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002154 (*) Accessing devices.
David Howells108b42b2006-03-31 16:00:29 +01002155
2156 (*) Interrupts.
2157
2158
2159INTERPROCESSOR INTERACTION
2160--------------------------
2161
2162When there's a system with more than one processor, more than one CPU in the
2163system may be working on the same data set at the same time. This can cause
2164synchronisation problems, and the usual way of dealing with them is to use
2165locks. Locks, however, are quite expensive, and so it may be preferable to
2166operate without the use of a lock if at all possible. In such a case
2167operations that affect both CPUs may have to be carefully ordered to prevent
2168a malfunction.
2169
2170Consider, for example, the R/W semaphore slow path. Here a waiting process is
2171queued on the semaphore, by virtue of it having a piece of its stack linked to
2172the semaphore's list of waiting processes:
2173
2174 struct rw_semaphore {
2175 ...
2176 spinlock_t lock;
2177 struct list_head waiters;
2178 };
2179
2180 struct rwsem_waiter {
2181 struct list_head list;
2182 struct task_struct *task;
2183 };
2184
2185To wake up a particular waiter, the up_read() or up_write() functions have to:
2186
2187 (1) read the next pointer from this waiter's record to know as to where the
2188 next waiter record is;
2189
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002190 (2) read the pointer to the waiter's task structure;
David Howells108b42b2006-03-31 16:00:29 +01002191
2192 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2193
2194 (4) call wake_up_process() on the task; and
2195
2196 (5) release the reference held on the waiter's task struct.
2197
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002198In other words, it has to perform this sequence of events:
David Howells108b42b2006-03-31 16:00:29 +01002199
2200 LOAD waiter->list.next;
2201 LOAD waiter->task;
2202 STORE waiter->task;
2203 CALL wakeup
2204 RELEASE task
2205
2206and if any of these steps occur out of order, then the whole thing may
2207malfunction.
2208
2209Once it has queued itself and dropped the semaphore lock, the waiter does not
2210get the lock again; it instead just waits for its task pointer to be cleared
2211before proceeding. Since the record is on the waiter's stack, this means that
2212if the task pointer is cleared _before_ the next pointer in the list is read,
2213another CPU might start processing the waiter and might clobber the waiter's
2214stack before the up*() function has a chance to read the next pointer.
2215
2216Consider then what might happen to the above sequence of events:
2217
2218 CPU 1 CPU 2
2219 =============================== ===============================
2220 down_xxx()
2221 Queue waiter
2222 Sleep
2223 up_yyy()
2224 LOAD waiter->task;
2225 STORE waiter->task;
2226 Woken up by other event
2227 <preempt>
2228 Resume processing
2229 down_xxx() returns
2230 call foo()
2231 foo() clobbers *waiter
2232 </preempt>
2233 LOAD waiter->list.next;
2234 --- OOPS ---
2235
2236This could be dealt with using the semaphore lock, but then the down_xxx()
2237function has to needlessly get the spinlock again after being woken up.
2238
2239The way to deal with this is to insert a general SMP memory barrier:
2240
2241 LOAD waiter->list.next;
2242 LOAD waiter->task;
2243 smp_mb();
2244 STORE waiter->task;
2245 CALL wakeup
2246 RELEASE task
2247
2248In this case, the barrier makes a guarantee that all memory accesses before the
2249barrier will appear to happen before all the memory accesses after the barrier
2250with respect to the other CPUs on the system. It does _not_ guarantee that all
2251the memory accesses before the barrier will be complete by the time the barrier
2252instruction itself is complete.
2253
2254On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2255compiler barrier, thus making sure the compiler emits the instructions in the
David Howells6bc39272006-06-25 05:49:22 -07002256right order without actually intervening in the CPU. Since there's only one
2257CPU, that CPU's dependency ordering logic will take care of everything else.
David Howells108b42b2006-03-31 16:00:29 +01002258
2259
2260ATOMIC OPERATIONS
2261-----------------
2262
David Howellsdbc87002006-04-10 22:54:23 -07002263Whilst they are technically interprocessor interaction considerations, atomic
2264operations are noted specially as some of them imply full memory barriers and
2265some don't, but they're very heavily relied on as a group throughout the
2266kernel.
2267
2268Any atomic operation that modifies some state in memory and returns information
2269about the state (old or new) implies an SMP-conditional general memory barrier
Nick Piggin26333572007-10-18 03:06:39 -07002270(smp_mb()) on each side of the actual operation (with the exception of
2271explicit lock operations, described later). These include:
David Howells108b42b2006-03-31 16:00:29 +01002272
2273 xchg();
2274 cmpxchg();
Paul E. McKenneyfb2b5812013-12-11 13:59:05 -08002275 atomic_xchg(); atomic_long_xchg();
2276 atomic_cmpxchg(); atomic_long_cmpxchg();
2277 atomic_inc_return(); atomic_long_inc_return();
2278 atomic_dec_return(); atomic_long_dec_return();
2279 atomic_add_return(); atomic_long_add_return();
2280 atomic_sub_return(); atomic_long_sub_return();
2281 atomic_inc_and_test(); atomic_long_inc_and_test();
2282 atomic_dec_and_test(); atomic_long_dec_and_test();
2283 atomic_sub_and_test(); atomic_long_sub_and_test();
2284 atomic_add_negative(); atomic_long_add_negative();
David Howellsdbc87002006-04-10 22:54:23 -07002285 test_and_set_bit();
2286 test_and_clear_bit();
2287 test_and_change_bit();
David Howells108b42b2006-03-31 16:00:29 +01002288
Paul E. McKenneyfb2b5812013-12-11 13:59:05 -08002289 /* when succeeds (returns 1) */
2290 atomic_add_unless(); atomic_long_add_unless();
2291
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002292These are used for such things as implementing ACQUIRE-class and RELEASE-class
David Howellsdbc87002006-04-10 22:54:23 -07002293operations and adjusting reference counters towards object destruction, and as
2294such the implicit memory barrier effects are necessary.
David Howells108b42b2006-03-31 16:00:29 +01002295
David Howells108b42b2006-03-31 16:00:29 +01002296
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002297The following operations are potential problems as they do _not_ imply memory
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002298barriers, but might be used for implementing such things as RELEASE-class
David Howellsdbc87002006-04-10 22:54:23 -07002299operations:
2300
2301 atomic_set();
David Howells108b42b2006-03-31 16:00:29 +01002302 set_bit();
2303 clear_bit();
2304 change_bit();
David Howellsdbc87002006-04-10 22:54:23 -07002305
2306With these the appropriate explicit memory barrier should be used if necessary
Peter Zijlstra1b156112014-03-13 19:00:35 +01002307(smp_mb__before_atomic() for instance).
David Howells108b42b2006-03-31 16:00:29 +01002308
2309
David Howellsdbc87002006-04-10 22:54:23 -07002310The following also do _not_ imply memory barriers, and so may require explicit
Peter Zijlstra1b156112014-03-13 19:00:35 +01002311memory barriers under some circumstances (smp_mb__before_atomic() for
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002312instance):
David Howells108b42b2006-03-31 16:00:29 +01002313
2314 atomic_add();
2315 atomic_sub();
2316 atomic_inc();
2317 atomic_dec();
2318
2319If they're used for statistics generation, then they probably don't need memory
2320barriers, unless there's a coupling between statistical data.
2321
2322If they're used for reference counting on an object to control its lifetime,
2323they probably don't need memory barriers because either the reference count
2324will be adjusted inside a locked section, or the caller will already hold
2325sufficient references to make the lock, and thus a memory barrier unnecessary.
2326
2327If they're used for constructing a lock of some description, then they probably
2328do need memory barriers as a lock primitive generally has to do things in a
2329specific order.
2330
David Howells108b42b2006-03-31 16:00:29 +01002331Basically, each usage case has to be carefully considered as to whether memory
David Howellsdbc87002006-04-10 22:54:23 -07002332barriers are needed or not.
2333
Nick Piggin26333572007-10-18 03:06:39 -07002334The following operations are special locking primitives:
2335
2336 test_and_set_bit_lock();
2337 clear_bit_unlock();
2338 __clear_bit_unlock();
2339
Peter Zijlstra2e4f5382013-11-06 14:57:36 +01002340These implement ACQUIRE-class and RELEASE-class operations. These should be used in
Nick Piggin26333572007-10-18 03:06:39 -07002341preference to other operations when implementing locking primitives, because
2342their implementations can be optimised on many architectures.
2343
David Howellsdbc87002006-04-10 22:54:23 -07002344[!] Note that special memory barrier primitives are available for these
2345situations because on some CPUs the atomic instructions used imply full memory
2346barriers, and so barrier instructions are superfluous in conjunction with them,
2347and in such cases the special barrier primitives will be no-ops.
David Howells108b42b2006-03-31 16:00:29 +01002348
2349See Documentation/atomic_ops.txt for more information.
2350
2351
2352ACCESSING DEVICES
2353-----------------
2354
2355Many devices can be memory mapped, and so appear to the CPU as if they're just
2356a set of memory locations. To control such a device, the driver usually has to
2357make the right memory accesses in exactly the right order.
2358
2359However, having a clever CPU or a clever compiler creates a potential problem
2360in that the carefully sequenced accesses in the driver code won't reach the
2361device in the requisite order if the CPU or the compiler thinks it is more
2362efficient to reorder, combine or merge accesses - something that would cause
2363the device to malfunction.
2364
2365Inside of the Linux kernel, I/O should be done through the appropriate accessor
2366routines - such as inb() or writel() - which know how to make such accesses
2367appropriately sequential. Whilst this, for the most part, renders the explicit
2368use of memory barriers unnecessary, there are a couple of situations where they
2369might be needed:
2370
2371 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
2372 so for _all_ general drivers locks should be used and mmiowb() must be
2373 issued prior to unlocking the critical section.
2374
2375 (2) If the accessor functions are used to refer to an I/O memory window with
2376 relaxed memory access properties, then _mandatory_ memory barriers are
2377 required to enforce ordering.
2378
2379See Documentation/DocBook/deviceiobook.tmpl for more information.
2380
2381
2382INTERRUPTS
2383----------
2384
2385A driver may be interrupted by its own interrupt service routine, and thus the
2386two parts of the driver may interfere with each other's attempts to control or
2387access the device.
2388
2389This may be alleviated - at least in part - by disabling local interrupts (a
2390form of locking), such that the critical operations are all contained within
2391the interrupt-disabled section in the driver. Whilst the driver's interrupt
2392routine is executing, the driver's core may not run on the same CPU, and its
2393interrupt is not permitted to happen again until the current interrupt has been
2394handled, thus the interrupt handler does not need to lock against that.
2395
2396However, consider a driver that was talking to an ethernet card that sports an
2397address register and a data register. If that driver's core talks to the card
2398under interrupt-disablement and then the driver's interrupt handler is invoked:
2399
2400 LOCAL IRQ DISABLE
2401 writew(ADDR, 3);
2402 writew(DATA, y);
2403 LOCAL IRQ ENABLE
2404 <interrupt>
2405 writew(ADDR, 4);
2406 q = readw(DATA);
2407 </interrupt>
2408
2409The store to the data register might happen after the second store to the
2410address register if ordering rules are sufficiently relaxed:
2411
2412 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
2413
2414
2415If ordering rules are relaxed, it must be assumed that accesses done inside an
2416interrupt disabled section may leak outside of it and may interleave with
2417accesses performed in an interrupt - and vice versa - unless implicit or
2418explicit barriers are used.
2419
2420Normally this won't be a problem because the I/O accesses done inside such
2421sections will include synchronous load operations on strictly ordered I/O
2422registers that form implicit I/O barriers. If this isn't sufficient then an
2423mmiowb() may need to be used explicitly.
2424
2425
2426A similar situation may occur between an interrupt routine and two routines
2427running on separate CPUs that communicate with each other. If such a case is
2428likely, then interrupt-disabling locks should be used to guarantee ordering.
2429
2430
2431==========================
2432KERNEL I/O BARRIER EFFECTS
2433==========================
2434
2435When accessing I/O memory, drivers should use the appropriate accessor
2436functions:
2437
2438 (*) inX(), outX():
2439
2440 These are intended to talk to I/O space rather than memory space, but
2441 that's primarily a CPU-specific concept. The i386 and x86_64 processors do
2442 indeed have special I/O space access cycles and instructions, but many
2443 CPUs don't have such a concept.
2444
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002445 The PCI bus, amongst others, defines an I/O space concept which - on such
2446 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
David Howells6bc39272006-06-25 05:49:22 -07002447 space. However, it may also be mapped as a virtual I/O space in the CPU's
2448 memory map, particularly on those CPUs that don't support alternate I/O
2449 spaces.
David Howells108b42b2006-03-31 16:00:29 +01002450
2451 Accesses to this space may be fully synchronous (as on i386), but
2452 intermediary bridges (such as the PCI host bridge) may not fully honour
2453 that.
2454
2455 They are guaranteed to be fully ordered with respect to each other.
2456
2457 They are not guaranteed to be fully ordered with respect to other types of
2458 memory and I/O operation.
2459
2460 (*) readX(), writeX():
2461
2462 Whether these are guaranteed to be fully ordered and uncombined with
2463 respect to each other on the issuing CPU depends on the characteristics
2464 defined for the memory window through which they're accessing. On later
2465 i386 architecture machines, for example, this is controlled by way of the
2466 MTRR registers.
2467
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002468 Ordinarily, these will be guaranteed to be fully ordered and uncombined,
David Howells108b42b2006-03-31 16:00:29 +01002469 provided they're not accessing a prefetchable device.
2470
2471 However, intermediary hardware (such as a PCI bridge) may indulge in
2472 deferral if it so wishes; to flush a store, a load from the same location
2473 is preferred[*], but a load from the same device or from configuration
2474 space should suffice for PCI.
2475
2476 [*] NOTE! attempting to load from the same location as was written to may
Ingo Molnare0edc782013-11-22 11:24:53 +01002477 cause a malfunction - consider the 16550 Rx/Tx serial registers for
2478 example.
David Howells108b42b2006-03-31 16:00:29 +01002479
2480 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
2481 force stores to be ordered.
2482
2483 Please refer to the PCI specification for more information on interactions
2484 between PCI transactions.
2485
Will Deacona8e0aea2013-09-04 12:30:08 +01002486 (*) readX_relaxed(), writeX_relaxed()
David Howells108b42b2006-03-31 16:00:29 +01002487
Will Deacona8e0aea2013-09-04 12:30:08 +01002488 These are similar to readX() and writeX(), but provide weaker memory
2489 ordering guarantees. Specifically, they do not guarantee ordering with
2490 respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee
2491 ordering with respect to LOCK or UNLOCK operations. If the latter is
2492 required, an mmiowb() barrier can be used. Note that relaxed accesses to
2493 the same peripheral are guaranteed to be ordered with respect to each
2494 other.
David Howells108b42b2006-03-31 16:00:29 +01002495
2496 (*) ioreadX(), iowriteX()
2497
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002498 These will perform appropriately for the type of access they're actually
David Howells108b42b2006-03-31 16:00:29 +01002499 doing, be it inX()/outX() or readX()/writeX().
2500
2501
2502========================================
2503ASSUMED MINIMUM EXECUTION ORDERING MODEL
2504========================================
2505
2506It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2507maintain the appearance of program causality with respect to itself. Some CPUs
2508(such as i386 or x86_64) are more constrained than others (such as powerpc or
2509frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2510of arch-specific code.
2511
2512This means that it must be considered that the CPU will execute its instruction
2513stream in any order it feels like - or even in parallel - provided that if an
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002514instruction in the stream depends on an earlier instruction, then that
David Howells108b42b2006-03-31 16:00:29 +01002515earlier instruction must be sufficiently complete[*] before the later
2516instruction may proceed; in other words: provided that the appearance of
2517causality is maintained.
2518
2519 [*] Some instructions have more than one effect - such as changing the
2520 condition codes, changing registers or changing memory - and different
2521 instructions may depend on different effects.
2522
2523A CPU may also discard any instruction sequence that winds up having no
2524ultimate effect. For example, if two adjacent instructions both load an
2525immediate value into the same register, the first may be discarded.
2526
2527
2528Similarly, it has to be assumed that compiler might reorder the instruction
2529stream in any way it sees fit, again provided the appearance of causality is
2530maintained.
2531
2532
2533============================
2534THE EFFECTS OF THE CPU CACHE
2535============================
2536
2537The way cached memory operations are perceived across the system is affected to
2538a certain extent by the caches that lie between CPUs and memory, and by the
2539memory coherence system that maintains the consistency of state in the system.
2540
2541As far as the way a CPU interacts with another part of the system through the
2542caches goes, the memory system has to include the CPU's caches, and memory
2543barriers for the most part act at the interface between the CPU and its cache
2544(memory barriers logically act on the dotted line in the following diagram):
2545
2546 <--- CPU ---> : <----------- Memory ----------->
2547 :
2548 +--------+ +--------+ : +--------+ +-----------+
2549 | | | | : | | | | +--------+
Ingo Molnare0edc782013-11-22 11:24:53 +01002550 | CPU | | Memory | : | CPU | | | | |
2551 | Core |--->| Access |----->| Cache |<-->| | | |
David Howells108b42b2006-03-31 16:00:29 +01002552 | | | Queue | : | | | |--->| Memory |
Ingo Molnare0edc782013-11-22 11:24:53 +01002553 | | | | : | | | | | |
2554 +--------+ +--------+ : +--------+ | | | |
David Howells108b42b2006-03-31 16:00:29 +01002555 : | Cache | +--------+
2556 : | Coherency |
2557 : | Mechanism | +--------+
2558 +--------+ +--------+ : +--------+ | | | |
2559 | | | | : | | | | | |
2560 | CPU | | Memory | : | CPU | | |--->| Device |
Ingo Molnare0edc782013-11-22 11:24:53 +01002561 | Core |--->| Access |----->| Cache |<-->| | | |
2562 | | | Queue | : | | | | | |
David Howells108b42b2006-03-31 16:00:29 +01002563 | | | | : | | | | +--------+
2564 +--------+ +--------+ : +--------+ +-----------+
2565 :
2566 :
2567
2568Although any particular load or store may not actually appear outside of the
2569CPU that issued it since it may have been satisfied within the CPU's own cache,
2570it will still appear as if the full memory access had taken place as far as the
2571other CPUs are concerned since the cache coherency mechanisms will migrate the
2572cacheline over to the accessing CPU and propagate the effects upon conflict.
2573
2574The CPU core may execute instructions in any order it deems fit, provided the
2575expected program causality appears to be maintained. Some of the instructions
2576generate load and store operations which then go into the queue of memory
2577accesses to be performed. The core may place these in the queue in any order
2578it wishes, and continue execution until it is forced to wait for an instruction
2579to complete.
2580
2581What memory barriers are concerned with is controlling the order in which
2582accesses cross from the CPU side of things to the memory side of things, and
2583the order in which the effects are perceived to happen by the other observers
2584in the system.
2585
2586[!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2587their own loads and stores as if they had happened in program order.
2588
2589[!] MMIO or other device accesses may bypass the cache system. This depends on
2590the properties of the memory window through which devices are accessed and/or
2591the use of any special device communication instructions the CPU may have.
2592
2593
2594CACHE COHERENCY
2595---------------
2596
2597Life isn't quite as simple as it may appear above, however: for while the
2598caches are expected to be coherent, there's no guarantee that that coherency
2599will be ordered. This means that whilst changes made on one CPU will
2600eventually become visible on all CPUs, there's no guarantee that they will
2601become apparent in the same order on those other CPUs.
2602
2603
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002604Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
2605has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
David Howells108b42b2006-03-31 16:00:29 +01002606
2607 :
2608 : +--------+
2609 : +---------+ | |
2610 +--------+ : +--->| Cache A |<------->| |
2611 | | : | +---------+ | |
2612 | CPU 1 |<---+ | |
2613 | | : | +---------+ | |
2614 +--------+ : +--->| Cache B |<------->| |
2615 : +---------+ | |
2616 : | Memory |
2617 : +---------+ | System |
2618 +--------+ : +--->| Cache C |<------->| |
2619 | | : | +---------+ | |
2620 | CPU 2 |<---+ | |
2621 | | : | +---------+ | |
2622 +--------+ : +--->| Cache D |<------->| |
2623 : +---------+ | |
2624 : +--------+
2625 :
2626
2627Imagine the system has the following properties:
2628
2629 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
2630 resident in memory;
2631
2632 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2633 resident in memory;
2634
2635 (*) whilst the CPU core is interrogating one cache, the other cache may be
2636 making use of the bus to access the rest of the system - perhaps to
2637 displace a dirty cacheline or to do a speculative load;
2638
2639 (*) each cache has a queue of operations that need to be applied to that cache
2640 to maintain coherency with the rest of the system;
2641
2642 (*) the coherency queue is not flushed by normal loads to lines already
2643 present in the cache, even though the contents of the queue may
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002644 potentially affect those loads.
David Howells108b42b2006-03-31 16:00:29 +01002645
2646Imagine, then, that two writes are made on the first CPU, with a write barrier
2647between them to guarantee that they will appear to reach that CPU's caches in
2648the requisite order:
2649
2650 CPU 1 CPU 2 COMMENT
2651 =============== =============== =======================================
2652 u == 0, v == 1 and p == &u, q == &u
2653 v = 2;
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002654 smp_wmb(); Make sure change to v is visible before
David Howells108b42b2006-03-31 16:00:29 +01002655 change to p
2656 <A:modify v=2> v is now in cache A exclusively
2657 p = &v;
2658 <B:modify p=&v> p is now in cache B exclusively
2659
2660The write memory barrier forces the other CPUs in the system to perceive that
2661the local CPU's caches have apparently been updated in the correct order. But
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002662now imagine that the second CPU wants to read those values:
David Howells108b42b2006-03-31 16:00:29 +01002663
2664 CPU 1 CPU 2 COMMENT
2665 =============== =============== =======================================
2666 ...
2667 q = p;
2668 x = *q;
2669
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002670The above pair of reads may then fail to happen in the expected order, as the
David Howells108b42b2006-03-31 16:00:29 +01002671cacheline holding p may get updated in one of the second CPU's caches whilst
2672the update to the cacheline holding v is delayed in the other of the second
2673CPU's caches by some other cache event:
2674
2675 CPU 1 CPU 2 COMMENT
2676 =============== =============== =======================================
2677 u == 0, v == 1 and p == &u, q == &u
2678 v = 2;
2679 smp_wmb();
2680 <A:modify v=2> <C:busy>
2681 <C:queue v=2>
Aneesh Kumar79afecf2006-05-15 09:44:36 -07002682 p = &v; q = p;
David Howells108b42b2006-03-31 16:00:29 +01002683 <D:request p>
2684 <B:modify p=&v> <D:commit p=&v>
Ingo Molnare0edc782013-11-22 11:24:53 +01002685 <D:read p>
David Howells108b42b2006-03-31 16:00:29 +01002686 x = *q;
2687 <C:read *q> Reads from v before v updated in cache
2688 <C:unbusy>
2689 <C:commit v=2>
2690
2691Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
2692no guarantee that, without intervention, the order of update will be the same
2693as that committed on CPU 1.
2694
2695
2696To intervene, we need to interpolate a data dependency barrier or a read
2697barrier between the loads. This will force the cache to commit its coherency
2698queue before processing any further requests:
2699
2700 CPU 1 CPU 2 COMMENT
2701 =============== =============== =======================================
2702 u == 0, v == 1 and p == &u, q == &u
2703 v = 2;
2704 smp_wmb();
2705 <A:modify v=2> <C:busy>
2706 <C:queue v=2>
Paolo 'Blaisorblade' Giarrusso3fda9822006-10-19 23:28:19 -07002707 p = &v; q = p;
David Howells108b42b2006-03-31 16:00:29 +01002708 <D:request p>
2709 <B:modify p=&v> <D:commit p=&v>
Ingo Molnare0edc782013-11-22 11:24:53 +01002710 <D:read p>
David Howells108b42b2006-03-31 16:00:29 +01002711 smp_read_barrier_depends()
2712 <C:unbusy>
2713 <C:commit v=2>
2714 x = *q;
2715 <C:read *q> Reads from v after v updated in cache
2716
2717
2718This sort of problem can be encountered on DEC Alpha processors as they have a
2719split cache that improves performance by making better use of the data bus.
2720Whilst most CPUs do imply a data dependency barrier on the read when a memory
2721access depends on a read, not all do, so it may not be relied on.
2722
2723Other CPUs may also have split caches, but must coordinate between the various
Matt LaPlante3f6dee92006-10-03 22:45:33 +02002724cachelets for normal memory accesses. The semantics of the Alpha removes the
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002725need for coordination in the absence of memory barriers.
David Howells108b42b2006-03-31 16:00:29 +01002726
2727
2728CACHE COHERENCY VS DMA
2729----------------------
2730
2731Not all systems maintain cache coherency with respect to devices doing DMA. In
2732such cases, a device attempting DMA may obtain stale data from RAM because
2733dirty cache lines may be resident in the caches of various CPUs, and may not
2734have been written back to RAM yet. To deal with this, the appropriate part of
2735the kernel must flush the overlapping bits of cache on each CPU (and maybe
2736invalidate them as well).
2737
2738In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2739cache lines being written back to RAM from a CPU's cache after the device has
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002740installed its own data, or cache lines present in the CPU's cache may simply
2741obscure the fact that RAM has been updated, until at such time as the cacheline
2742is discarded from the CPU's cache and reloaded. To deal with this, the
2743appropriate part of the kernel must invalidate the overlapping bits of the
David Howells108b42b2006-03-31 16:00:29 +01002744cache on each CPU.
2745
2746See Documentation/cachetlb.txt for more information on cache management.
2747
2748
2749CACHE COHERENCY VS MMIO
2750-----------------------
2751
2752Memory mapped I/O usually takes place through memory locations that are part of
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002753a window in the CPU's memory space that has different properties assigned than
David Howells108b42b2006-03-31 16:00:29 +01002754the usual RAM directed window.
2755
2756Amongst these properties is usually the fact that such accesses bypass the
2757caching entirely and go directly to the device buses. This means MMIO accesses
2758may, in effect, overtake accesses to cached memory that were emitted earlier.
2759A memory barrier isn't sufficient in such a case, but rather the cache must be
2760flushed between the cached memory write and the MMIO access if the two are in
2761any way dependent.
2762
2763
2764=========================
2765THE THINGS CPUS GET UP TO
2766=========================
2767
2768A programmer might take it for granted that the CPU will perform memory
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002769operations in exactly the order specified, so that if the CPU is, for example,
David Howells108b42b2006-03-31 16:00:29 +01002770given the following piece of code to execute:
2771
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002772 a = ACCESS_ONCE(*A);
2773 ACCESS_ONCE(*B) = b;
2774 c = ACCESS_ONCE(*C);
2775 d = ACCESS_ONCE(*D);
2776 ACCESS_ONCE(*E) = e;
David Howells108b42b2006-03-31 16:00:29 +01002777
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002778they would then expect that the CPU will complete the memory operation for each
David Howells108b42b2006-03-31 16:00:29 +01002779instruction before moving on to the next one, leading to a definite sequence of
2780operations as seen by external observers in the system:
2781
2782 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2783
2784
2785Reality is, of course, much messier. With many CPUs and compilers, the above
2786assumption doesn't hold because:
2787
2788 (*) loads are more likely to need to be completed immediately to permit
2789 execution progress, whereas stores can often be deferred without a
2790 problem;
2791
2792 (*) loads may be done speculatively, and the result discarded should it prove
2793 to have been unnecessary;
2794
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002795 (*) loads may be done speculatively, leading to the result having been fetched
2796 at the wrong time in the expected sequence of events;
David Howells108b42b2006-03-31 16:00:29 +01002797
2798 (*) the order of the memory accesses may be rearranged to promote better use
2799 of the CPU buses and caches;
2800
2801 (*) loads and stores may be combined to improve performance when talking to
2802 memory or I/O hardware that can do batched accesses of adjacent locations,
2803 thus cutting down on transaction setup costs (memory and PCI devices may
2804 both be able to do this); and
2805
2806 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2807 mechanisms may alleviate this - once the store has actually hit the cache
2808 - there's no guarantee that the coherency management will be propagated in
2809 order to other CPUs.
2810
2811So what another CPU, say, might actually observe from the above piece of code
2812is:
2813
2814 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2815
2816 (Where "LOAD {*C,*D}" is a combined load)
2817
2818
2819However, it is guaranteed that a CPU will be self-consistent: it will see its
2820_own_ accesses appear to be correctly ordered, without the need for a memory
2821barrier. For instance with the following code:
2822
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002823 U = ACCESS_ONCE(*A);
2824 ACCESS_ONCE(*A) = V;
2825 ACCESS_ONCE(*A) = W;
2826 X = ACCESS_ONCE(*A);
2827 ACCESS_ONCE(*A) = Y;
2828 Z = ACCESS_ONCE(*A);
David Howells108b42b2006-03-31 16:00:29 +01002829
2830and assuming no intervention by an external influence, it can be assumed that
2831the final result will appear to be:
2832
2833 U == the original value of *A
2834 X == W
2835 Z == Y
2836 *A == Y
2837
2838The code above may cause the CPU to generate the full sequence of memory
2839accesses:
2840
2841 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2842
2843in that order, but, without intervention, the sequence may have almost any
2844combination of elements combined or discarded, provided the program's view of
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002845the world remains consistent. Note that ACCESS_ONCE() is -not- optional
2846in the above example, as there are architectures where a given CPU might
Paul E. McKenney8dd853d2014-02-23 08:34:24 -08002847reorder successive loads to the same location. On such architectures,
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002848ACCESS_ONCE() does whatever is necessary to prevent this, for example, on
2849Itanium the volatile casts used by ACCESS_ONCE() cause GCC to emit the
2850special ld.acq and st.rel instructions that prevent such reordering.
David Howells108b42b2006-03-31 16:00:29 +01002851
2852The compiler may also combine, discard or defer elements of the sequence before
2853the CPU even sees them.
2854
2855For instance:
2856
2857 *A = V;
2858 *A = W;
2859
2860may be reduced to:
2861
2862 *A = W;
2863
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002864since, without either a write barrier or an ACCESS_ONCE(), it can be
2865assumed that the effect of the storage of V to *A is lost. Similarly:
David Howells108b42b2006-03-31 16:00:29 +01002866
2867 *A = Y;
2868 Z = *A;
2869
Paul E. McKenney2ecf8102013-12-11 13:59:04 -08002870may, without a memory barrier or an ACCESS_ONCE(), be reduced to:
David Howells108b42b2006-03-31 16:00:29 +01002871
2872 *A = Y;
2873 Z = Y;
2874
2875and the LOAD operation never appear outside of the CPU.
2876
2877
2878AND THEN THERE'S THE ALPHA
2879--------------------------
2880
2881The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2882some versions of the Alpha CPU have a split data cache, permitting them to have
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002883two semantically-related cache lines updated at separate times. This is where
David Howells108b42b2006-03-31 16:00:29 +01002884the data dependency barrier really becomes necessary as this synchronises both
2885caches with the memory coherence system, thus making it seem like pointer
2886changes vs new data occur in the right order.
2887
Jarek Poplawski81fc6322007-05-23 13:58:20 -07002888The Alpha defines the Linux kernel's memory barrier model.
David Howells108b42b2006-03-31 16:00:29 +01002889
2890See the subsection on "Cache Coherency" above.
2891
2892
David Howells90fddab2010-03-24 09:43:00 +00002893============
2894EXAMPLE USES
2895============
2896
2897CIRCULAR BUFFERS
2898----------------
2899
2900Memory barriers can be used to implement circular buffering without the need
2901of a lock to serialise the producer with the consumer. See:
2902
2903 Documentation/circular-buffers.txt
2904
2905for details.
2906
2907
David Howells108b42b2006-03-31 16:00:29 +01002908==========
2909REFERENCES
2910==========
2911
2912Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
2913Digital Press)
2914 Chapter 5.2: Physical Address Space Characteristics
2915 Chapter 5.4: Caches and Write Buffers
2916 Chapter 5.5: Data Sharing
2917 Chapter 5.6: Read/Write Ordering
2918
2919AMD64 Architecture Programmer's Manual Volume 2: System Programming
2920 Chapter 7.1: Memory-Access Ordering
2921 Chapter 7.4: Buffering and Combining Memory Writes
2922
2923IA-32 Intel Architecture Software Developer's Manual, Volume 3:
2924System Programming Guide
2925 Chapter 7.1: Locked Atomic Operations
2926 Chapter 7.2: Memory Ordering
2927 Chapter 7.4: Serializing Instructions
2928
2929The SPARC Architecture Manual, Version 9
2930 Chapter 8: Memory Models
2931 Appendix D: Formal Specification of the Memory Models
2932 Appendix J: Programming with the Memory Models
2933
2934UltraSPARC Programmer Reference Manual
2935 Chapter 5: Memory Accesses and Cacheability
2936 Chapter 15: Sparc-V9 Memory Models
2937
2938UltraSPARC III Cu User's Manual
2939 Chapter 9: Memory Models
2940
2941UltraSPARC IIIi Processor User's Manual
2942 Chapter 8: Memory Models
2943
2944UltraSPARC Architecture 2005
2945 Chapter 9: Memory
2946 Appendix D: Formal Specifications of the Memory Models
2947
2948UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
2949 Chapter 8: Memory Models
2950 Appendix F: Caches and Cache Coherency
2951
2952Solaris Internals, Core Kernel Architecture, p63-68:
2953 Chapter 3.3: Hardware Considerations for Locks and
2954 Synchronization
2955
2956Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
2957for Kernel Programmers:
2958 Chapter 13: Other Memory Models
2959
2960Intel Itanium Architecture Software Developer's Manual: Volume 1:
2961 Section 2.6: Speculation
2962 Section 4.4: Memory Access