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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/linkage.h>
21#include <linux/interrupt.h>
22#include <linux/spinlock.h>
23#include <linux/smp.h>
24#include <linux/mm.h>
25#include <linux/slab.h>
26#include <linux/kernel_stat.h>
27
28#include <asm/errno.h>
29#include <asm/signal.h>
30#include <asm/system.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031#include <asm/io.h>
32
33#include <asm/sibyte/sb1250_regs.h>
34#include <asm/sibyte/sb1250_int.h>
35#include <asm/sibyte/sb1250_uart.h>
36#include <asm/sibyte/sb1250_scd.h>
37#include <asm/sibyte/sb1250.h>
38
39/*
40 * These are the routines that handle all the low level interrupt stuff.
41 * Actions handled here are: initialization of the interrupt map, requesting of
42 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
43 * for interrupt lines
44 */
45
46
Linus Torvalds1da177e2005-04-16 15:20:36 -070047static void end_sb1250_irq(unsigned int irq);
48static void enable_sb1250_irq(unsigned int irq);
49static void disable_sb1250_irq(unsigned int irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -070050static void ack_sb1250_irq(unsigned int irq);
51#ifdef CONFIG_SMP
Andrew Isaacson942d0422005-06-22 16:01:09 -070052static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#endif
54
55#ifdef CONFIG_SIBYTE_HAS_LDT
56extern unsigned long ldt_eoi_space;
57#endif
58
59#ifdef CONFIG_KGDB
60static int kgdb_irq;
61
62/* Default to UART1 */
63int kgdb_port = 1;
64#ifdef CONFIG_SIBYTE_SB1250_DUART
65extern char sb1250_duart_present[];
66#endif
67#endif
68
Ralf Baechle94dee172006-07-02 14:41:42 +010069static struct irq_chip sb1250_irq_type = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +090070 .name = "SB1250-IMR",
Ralf Baechle8ab00b92005-02-28 13:39:57 +000071 .ack = ack_sb1250_irq,
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +090072 .mask = disable_sb1250_irq,
73 .mask_ack = ack_sb1250_irq,
74 .unmask = enable_sb1250_irq,
Ralf Baechle8ab00b92005-02-28 13:39:57 +000075 .end = end_sb1250_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -070076#ifdef CONFIG_SMP
Ralf Baechle8ab00b92005-02-28 13:39:57 +000077 .set_affinity = sb1250_set_affinity
Linus Torvalds1da177e2005-04-16 15:20:36 -070078#endif
79};
80
81/* Store the CPU id (not the logical number) */
82int sb1250_irq_owner[SB1250_NR_IRQS];
83
84DEFINE_SPINLOCK(sb1250_imr_lock);
85
86void sb1250_mask_irq(int cpu, int irq)
87{
88 unsigned long flags;
89 u64 cur_ints;
90
91 spin_lock_irqsave(&sb1250_imr_lock, flags);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +000092 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
93 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -070094 cur_ints |= (((u64) 1) << irq);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +000095 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
96 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -070097 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
98}
99
100void sb1250_unmask_irq(int cpu, int irq)
101{
102 unsigned long flags;
103 u64 cur_ints;
104
105 spin_lock_irqsave(&sb1250_imr_lock, flags);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000106 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
107 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108 cur_ints &= ~(((u64) 1) << irq);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000109 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
110 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
112}
113
114#ifdef CONFIG_SMP
Andrew Isaacson942d0422005-06-22 16:01:09 -0700115static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116{
117 int i = 0, old_cpu, cpu, int_on;
118 u64 cur_ints;
Ralf Baechle94dee172006-07-02 14:41:42 +0100119 struct irq_desc *desc = irq_desc + irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 unsigned long flags;
121
Andrew Isaacson942d0422005-06-22 16:01:09 -0700122 i = first_cpu(mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123
Andrew Isaacson942d0422005-06-22 16:01:09 -0700124 if (cpus_weight(mask) > 1) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
126 return;
127 }
128
129 /* Convert logical CPU to physical CPU */
130 cpu = cpu_logical_map(i);
131
132 /* Protect against other affinity changers and IMR manipulation */
133 spin_lock_irqsave(&desc->lock, flags);
134 spin_lock(&sb1250_imr_lock);
135
136 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
137 old_cpu = sb1250_irq_owner[irq];
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000138 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
139 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140 int_on = !(cur_ints & (((u64) 1) << irq));
141 if (int_on) {
142 /* If it was on, mask it */
143 cur_ints |= (((u64) 1) << irq);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000144 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
145 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146 }
147 sb1250_irq_owner[irq] = cpu;
148 if (int_on) {
149 /* unmask for the new CPU */
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000150 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
151 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152 cur_ints &= ~(((u64) 1) << irq);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000153 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
154 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155 }
156 spin_unlock(&sb1250_imr_lock);
157 spin_unlock_irqrestore(&desc->lock, flags);
158}
159#endif
160
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161/*****************************************************************************/
162
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163static void disable_sb1250_irq(unsigned int irq)
164{
165 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
166}
167
168static void enable_sb1250_irq(unsigned int irq)
169{
170 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
171}
172
173
174static void ack_sb1250_irq(unsigned int irq)
175{
176#ifdef CONFIG_SIBYTE_HAS_LDT
177 u64 pending;
178
179 /*
180 * If the interrupt was an HT interrupt, now is the time to
181 * clear it. NOTE: we assume the HT bridge was set up to
182 * deliver the interrupts to all CPUs (which makes affinity
183 * changing easier for us)
184 */
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000185 pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
186 R_IMR_LDT_INTERRUPT)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187 pending &= ((u64)1 << (irq));
188 if (pending) {
189 int i;
190 for (i=0; i<NR_CPUS; i++) {
191 int cpu;
192#ifdef CONFIG_SMP
193 cpu = cpu_logical_map(i);
194#else
195 cpu = i;
196#endif
197 /*
198 * Clear for all CPUs so an affinity switch
199 * doesn't find an old status
200 */
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000201 __raw_writeq(pending,
202 IOADDR(A_IMR_REGISTER(cpu,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 R_IMR_LDT_INTERRUPT_CLR)));
204 }
205
206 /*
207 * Generate EOI. For Pass 1 parts, EOI is a nop. For
208 * Pass 2, the LDT world may be edge-triggered, but
209 * this EOI shouldn't hurt. If they are
210 * level-sensitive, the EOI is required.
211 */
212 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
213 }
214#endif
215 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
216}
217
218
219static void end_sb1250_irq(unsigned int irq)
220{
221 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
222 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
223 }
224}
225
226
227void __init init_sb1250_irqs(void)
228{
229 int i;
230
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +0900231 for (i = 0; i < SB1250_NR_IRQS; i++) {
232 set_irq_chip(i, &sb1250_irq_type);
233 sb1250_irq_owner[i] = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234 }
235}
236
237
Ralf Baechle937a8012006-10-07 19:44:33 +0100238static irqreturn_t sb1250_dummy_handler(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239{
240 return IRQ_NONE;
241}
242
243static struct irqaction sb1250_dummy_action = {
244 .handler = sb1250_dummy_handler,
245 .flags = 0,
246 .mask = CPU_MASK_NONE,
247 .name = "sb1250-private",
248 .next = NULL,
249 .dev_id = 0
250};
251
252int sb1250_steal_irq(int irq)
253{
Ralf Baechle94dee172006-07-02 14:41:42 +0100254 struct irq_desc *desc = irq_desc + irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255 unsigned long flags;
256 int retval = 0;
257
258 if (irq >= SB1250_NR_IRQS)
259 return -EINVAL;
260
261 spin_lock_irqsave(&desc->lock,flags);
262 /* Don't allow sharing at all for these */
263 if (desc->action != NULL)
264 retval = -EBUSY;
265 else {
266 desc->action = &sb1250_dummy_action;
267 desc->depth = 0;
268 }
269 spin_unlock_irqrestore(&desc->lock,flags);
270 return 0;
271}
272
273/*
274 * arch_init_irq is called early in the boot sequence from init/main.c via
275 * init_IRQ. It is responsible for setting up the interrupt mapper and
276 * installing the handler that will be responsible for dispatching interrupts
277 * to the "right" place.
278 */
279/*
280 * For now, map all interrupts to IP[2]. We could save
281 * some cycles by parceling out system interrupts to different
282 * IP lines, but keep it simple for bringup. We'll also direct
283 * all interrupts to a single CPU; we should probably route
284 * PCI and LDT to one cpu and everything else to the other
285 * to balance the load a bit.
286 *
287 * On the second cpu, everything is set to IP5, which is
288 * ignored, EXCEPT the mailbox interrupt. That one is
289 * set to IP[2] so it is handled. This is needed so we
290 * can do cross-cpu function calls, as requred by SMP
291 */
292
293#define IMR_IP2_VAL K_INT_MAP_I0
294#define IMR_IP3_VAL K_INT_MAP_I1
295#define IMR_IP4_VAL K_INT_MAP_I2
296#define IMR_IP5_VAL K_INT_MAP_I3
297#define IMR_IP6_VAL K_INT_MAP_I4
298
299void __init arch_init_irq(void)
300{
301
302 unsigned int i;
303 u64 tmp;
304 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
305 STATUSF_IP1 | STATUSF_IP0;
306
307 /* Default everything to IP2 */
308 for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000309 __raw_writeq(IMR_IP2_VAL,
310 IOADDR(A_IMR_REGISTER(0,
311 R_IMR_INTERRUPT_MAP_BASE) +
312 (i << 3)));
313 __raw_writeq(IMR_IP2_VAL,
314 IOADDR(A_IMR_REGISTER(1,
315 R_IMR_INTERRUPT_MAP_BASE) +
316 (i << 3)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317 }
318
319 init_sb1250_irqs();
320
321 /*
322 * Map the high 16 bits of the mailbox registers to IP[3], for
323 * inter-cpu messages
324 */
325 /* Was I1 */
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000326 __raw_writeq(IMR_IP3_VAL,
327 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
328 (K_INT_MBOX_0 << 3)));
329 __raw_writeq(IMR_IP3_VAL,
330 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
331 (K_INT_MBOX_0 << 3)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332
333 /* Clear the mailboxes. The firmware may leave them dirty */
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000334 __raw_writeq(0xffffffffffffffffULL,
335 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
336 __raw_writeq(0xffffffffffffffffULL,
337 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338
339 /* Mask everything except the mailbox registers for both cpus */
340 tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000341 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
342 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343
344 sb1250_steal_irq(K_INT_MBOX_0);
345
346 /*
347 * Note that the timer interrupts are also mapped, but this is
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700348 * done in sb1250_time_init(). Also, the profiling driver
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349 * does its own management of IP7.
350 */
351
352#ifdef CONFIG_KGDB
353 imask |= STATUSF_IP6;
354#endif
355 /* Enable necessary IPs, disable the rest */
356 change_c0_status(ST0_IM, imask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357
358#ifdef CONFIG_KGDB
359 if (kgdb_flag) {
360 kgdb_irq = K_INT_UART_0 + kgdb_port;
361
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700362#ifdef CONFIG_SIBYTE_SB1250_DUART
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363 sb1250_duart_present[kgdb_port] = 0;
364#endif
365 /* Setup uart 1 settings, mapper */
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000366 __raw_writeq(M_DUART_IMR_BRK,
367 IOADDR(A_DUART_IMRREG(kgdb_port)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368
369 sb1250_steal_irq(kgdb_irq);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000370 __raw_writeq(IMR_IP6_VAL,
371 IOADDR(A_IMR_REGISTER(0,
372 R_IMR_INTERRUPT_MAP_BASE) +
373 (kgdb_irq << 3)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 sb1250_unmask_irq(0, kgdb_irq);
375 }
376#endif
377}
378
379#ifdef CONFIG_KGDB
380
381#include <linux/delay.h>
382
383#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
384#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
385
Ralf Baechle937a8012006-10-07 19:44:33 +0100386static void sb1250_kgdb_interrupt(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387{
388 /*
389 * Clear break-change status (allow some time for the remote
390 * host to stop the break, since we would see another
391 * interrupt on the end-of-break too)
392 */
393 kstat_this_cpu.irqs[kgdb_irq]++;
394 mdelay(500);
395 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
396 M_DUART_RX_EN | M_DUART_TX_EN);
Ralf Baechle937a8012006-10-07 19:44:33 +0100397 set_async_breakpoint(&get_irq_regs()->cp0_epc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398}
399
400#endif /* CONFIG_KGDB */
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100401
Ralf Baechle937a8012006-10-07 19:44:33 +0100402extern void sb1250_timer_interrupt(void);
403extern void sb1250_mailbox_interrupt(void);
Thiemo Seufer4fb60a42006-06-18 05:23:47 +0100404
Ralf Baechle937a8012006-10-07 19:44:33 +0100405asmlinkage void plat_irq_dispatch(void)
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100406{
407 unsigned int pending;
408
409#ifdef CONFIG_SIBYTE_SB1250_PROF
410 /* Set compare to count to silence count/compare timer interrupts */
Thiemo Seufer4fb60a42006-06-18 05:23:47 +0100411 write_c0_compare(read_c0_count());
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100412#endif
413
414 /*
415 * What a pain. We have to be really careful saving the upper 32 bits
416 * of any * register across function calls if we don't want them
417 * trashed--since were running in -o32, the calling routing never saves
418 * the full 64 bits of a register across a function call. Being the
419 * interrupt handler, we're guaranteed that interrupts are disabled
420 * during this code so we don't have to worry about random interrupts
421 * blasting the high 32 bits.
422 */
423
Thiemo Seufer119537c2007-03-19 00:13:37 +0000424 pending = read_c0_cause() & read_c0_status() & ST0_IM;
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100425
426#ifdef CONFIG_SIBYTE_SB1250_PROF
Thiemo Seufer6e61e852006-07-05 14:26:38 +0100427 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
Ralf Baechle937a8012006-10-07 19:44:33 +0100428 sbprof_cpu_intr();
Thiemo Seufer6e61e852006-07-05 14:26:38 +0100429 else
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100430#endif
431
432 if (pending & CAUSEF_IP4)
Ralf Baechle937a8012006-10-07 19:44:33 +0100433 sb1250_timer_interrupt();
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100434
435#ifdef CONFIG_SMP
Thiemo Seufer6e61e852006-07-05 14:26:38 +0100436 else if (pending & CAUSEF_IP3)
Ralf Baechle937a8012006-10-07 19:44:33 +0100437 sb1250_mailbox_interrupt();
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100438#endif
439
440#ifdef CONFIG_KGDB
Thiemo Seufer6e61e852006-07-05 14:26:38 +0100441 else if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
Ralf Baechle937a8012006-10-07 19:44:33 +0100442 sb1250_kgdb_interrupt();
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100443#endif
444
Thiemo Seufer6e61e852006-07-05 14:26:38 +0100445 else if (pending & CAUSEF_IP2) {
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100446 unsigned long long mask;
447
448 /*
449 * Default...we've hit an IP[2] interrupt, which means we've
450 * got to check the 1250 interrupt registers to figure out what
451 * to do. Need to detect which CPU we're on, now that
Thiemo Seufer4fb60a42006-06-18 05:23:47 +0100452 * smp_affinity is supported.
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100453 */
454 mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
455 R_IMR_INTERRUPT_STATUS_BASE)));
456 if (mask)
Ralf Baechle937a8012006-10-07 19:44:33 +0100457 do_IRQ(fls64(mask) - 1);
Maciej W. Rozyckid599def2006-10-03 12:42:02 +0100458 else
Ralf Baechle937a8012006-10-07 19:44:33 +0100459 spurious_interrupt();
Maciej W. Rozyckid599def2006-10-03 12:42:02 +0100460 } else
Ralf Baechle937a8012006-10-07 19:44:33 +0100461 spurious_interrupt();
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100462}