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Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +02001/*
Thierry Reding89184652014-04-16 09:24:44 +02002 * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved.
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +02003 *
Thierry Reding89184652014-04-16 09:24:44 +02004 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +02007 */
8
Thierry Reding804cb542015-03-27 11:07:27 +01009#include <linux/bitops.h>
Thierry Redingd1313e72015-01-23 09:49:25 +010010#include <linux/debugfs.h>
Thierry Redingbc5e6de2013-01-21 11:09:06 +010011#include <linux/err.h>
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020012#include <linux/iommu.h>
Thierry Reding89184652014-04-16 09:24:44 +020013#include <linux/kernel.h>
Hiroshi Doyu0760e8f2012-06-25 14:23:55 +030014#include <linux/of.h>
Thierry Reding89184652014-04-16 09:24:44 +020015#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include <linux/slab.h>
Thierry Reding306a7f92014-07-17 13:17:24 +020018
19#include <soc/tegra/ahb.h>
Thierry Reding89184652014-04-16 09:24:44 +020020#include <soc/tegra/mc.h>
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020021
Thierry Reding89184652014-04-16 09:24:44 +020022struct tegra_smmu {
23 void __iomem *regs;
24 struct device *dev;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020025
Thierry Reding89184652014-04-16 09:24:44 +020026 struct tegra_mc *mc;
27 const struct tegra_smmu_soc *soc;
Stephen Warrene6bc5932012-09-04 16:36:15 -060028
Thierry Reding804cb542015-03-27 11:07:27 +010029 unsigned long pfn_mask;
Thierry Reding11cec152015-08-06 14:20:31 +020030 unsigned long tlb_mask;
Thierry Reding804cb542015-03-27 11:07:27 +010031
Thierry Reding89184652014-04-16 09:24:44 +020032 unsigned long *asids;
33 struct mutex lock;
Stephen Warrene6bc5932012-09-04 16:36:15 -060034
Thierry Reding89184652014-04-16 09:24:44 +020035 struct list_head list;
Thierry Redingd1313e72015-01-23 09:49:25 +010036
37 struct dentry *debugfs;
Stephen Warrene6bc5932012-09-04 16:36:15 -060038};
39
Thierry Reding89184652014-04-16 09:24:44 +020040struct tegra_smmu_as {
Joerg Roedeld5f1a812015-03-26 13:43:12 +010041 struct iommu_domain domain;
Thierry Reding89184652014-04-16 09:24:44 +020042 struct tegra_smmu *smmu;
43 unsigned int use_count;
Russell King32924c72015-07-27 13:29:31 +010044 u32 *count;
Russell King853520f2015-07-27 13:29:26 +010045 struct page **pts;
Thierry Reding89184652014-04-16 09:24:44 +020046 struct page *pd;
Russell Kinge3c97192015-07-27 13:29:52 +010047 dma_addr_t pd_dma;
Thierry Reding89184652014-04-16 09:24:44 +020048 unsigned id;
49 u32 attr;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +030050};
51
Joerg Roedeld5f1a812015-03-26 13:43:12 +010052static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom)
53{
54 return container_of(dom, struct tegra_smmu_as, domain);
55}
56
Thierry Reding89184652014-04-16 09:24:44 +020057static inline void smmu_writel(struct tegra_smmu *smmu, u32 value,
58 unsigned long offset)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020059{
Thierry Reding89184652014-04-16 09:24:44 +020060 writel(value, smmu->regs + offset);
Joerg Roedelfe1229b2013-02-04 20:40:58 +010061}
62
Thierry Reding89184652014-04-16 09:24:44 +020063static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020064{
Thierry Reding89184652014-04-16 09:24:44 +020065 return readl(smmu->regs + offset);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +020066}
67
Thierry Reding89184652014-04-16 09:24:44 +020068#define SMMU_CONFIG 0x010
69#define SMMU_CONFIG_ENABLE (1 << 0)
70
71#define SMMU_TLB_CONFIG 0x14
72#define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29)
73#define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28)
Thierry Reding11cec152015-08-06 14:20:31 +020074#define SMMU_TLB_CONFIG_ACTIVE_LINES(smmu) \
75 ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask)
Thierry Reding89184652014-04-16 09:24:44 +020076
77#define SMMU_PTC_CONFIG 0x18
78#define SMMU_PTC_CONFIG_ENABLE (1 << 29)
79#define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24)
80#define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f)
81
82#define SMMU_PTB_ASID 0x01c
83#define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f)
84
85#define SMMU_PTB_DATA 0x020
Russell Kinge3c97192015-07-27 13:29:52 +010086#define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr))
Thierry Reding89184652014-04-16 09:24:44 +020087
Russell Kinge3c97192015-07-27 13:29:52 +010088#define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr))
Thierry Reding89184652014-04-16 09:24:44 +020089
90#define SMMU_TLB_FLUSH 0x030
91#define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0)
92#define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0)
93#define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0)
94#define SMMU_TLB_FLUSH_ASID(x) (((x) & 0x7f) << 24)
95#define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \
96 SMMU_TLB_FLUSH_VA_MATCH_SECTION)
97#define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \
98 SMMU_TLB_FLUSH_VA_MATCH_GROUP)
99#define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31)
100
101#define SMMU_PTC_FLUSH 0x034
102#define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0)
103#define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0)
104
105#define SMMU_PTC_FLUSH_HI 0x9b8
106#define SMMU_PTC_FLUSH_HI_MASK 0x3
107
108/* per-SWGROUP SMMU_*_ASID register */
109#define SMMU_ASID_ENABLE (1 << 31)
110#define SMMU_ASID_MASK 0x7f
111#define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK)
112
113/* page table definitions */
114#define SMMU_NUM_PDE 1024
115#define SMMU_NUM_PTE 1024
116
117#define SMMU_SIZE_PD (SMMU_NUM_PDE * 4)
118#define SMMU_SIZE_PT (SMMU_NUM_PTE * 4)
119
120#define SMMU_PDE_SHIFT 22
121#define SMMU_PTE_SHIFT 12
122
Thierry Reding89184652014-04-16 09:24:44 +0200123#define SMMU_PD_READABLE (1 << 31)
124#define SMMU_PD_WRITABLE (1 << 30)
125#define SMMU_PD_NONSECURE (1 << 29)
126
127#define SMMU_PDE_READABLE (1 << 31)
128#define SMMU_PDE_WRITABLE (1 << 30)
129#define SMMU_PDE_NONSECURE (1 << 29)
130#define SMMU_PDE_NEXT (1 << 28)
131
132#define SMMU_PTE_READABLE (1 << 31)
133#define SMMU_PTE_WRITABLE (1 << 30)
134#define SMMU_PTE_NONSECURE (1 << 29)
135
136#define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \
137 SMMU_PDE_NONSECURE)
138#define SMMU_PTE_ATTR (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \
139 SMMU_PTE_NONSECURE)
140
Russell King34d35f82015-07-27 13:29:16 +0100141static unsigned int iova_pd_index(unsigned long iova)
142{
143 return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1);
144}
145
146static unsigned int iova_pt_index(unsigned long iova)
147{
148 return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1);
149}
150
Russell Kinge3c97192015-07-27 13:29:52 +0100151static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr)
Russell King4b3c7d12015-07-27 13:29:36 +0100152{
Russell Kinge3c97192015-07-27 13:29:52 +0100153 addr >>= 12;
154 return (addr & smmu->pfn_mask) == addr;
155}
Russell King4b3c7d12015-07-27 13:29:36 +0100156
Russell Kinge3c97192015-07-27 13:29:52 +0100157static dma_addr_t smmu_pde_to_dma(u32 pde)
158{
159 return pde << 12;
Russell King4b3c7d12015-07-27 13:29:36 +0100160}
161
Russell Kingb8fe0382015-07-27 13:29:41 +0100162static void smmu_flush_ptc_all(struct tegra_smmu *smmu)
163{
164 smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
165}
166
Russell Kinge3c97192015-07-27 13:29:52 +0100167static inline void smmu_flush_ptc(struct tegra_smmu *smmu, dma_addr_t dma,
Thierry Reding89184652014-04-16 09:24:44 +0200168 unsigned long offset)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200169{
Thierry Reding89184652014-04-16 09:24:44 +0200170 u32 value;
Hiroshi Doyua6870e92013-01-31 10:14:10 +0200171
Russell Kingb8fe0382015-07-27 13:29:41 +0100172 offset &= ~(smmu->mc->soc->atom_size - 1);
Hiroshi Doyua6870e92013-01-31 10:14:10 +0200173
Russell Kingb8fe0382015-07-27 13:29:41 +0100174 if (smmu->mc->soc->num_address_bits > 32) {
Russell Kinge3c97192015-07-27 13:29:52 +0100175#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
176 value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200177#else
Russell Kingb8fe0382015-07-27 13:29:41 +0100178 value = 0;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200179#endif
Russell Kingb8fe0382015-07-27 13:29:41 +0100180 smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200181 }
Hiroshi DOYU9e971a02012-07-02 14:26:38 +0300182
Russell Kinge3c97192015-07-27 13:29:52 +0100183 value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR;
Thierry Reding89184652014-04-16 09:24:44 +0200184 smmu_writel(smmu, value, SMMU_PTC_FLUSH);
185}
186
187static inline void smmu_flush_tlb(struct tegra_smmu *smmu)
188{
189 smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH);
190}
191
192static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu,
193 unsigned long asid)
194{
195 u32 value;
196
197 value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
198 SMMU_TLB_FLUSH_VA_MATCH_ALL;
199 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
200}
201
202static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu,
203 unsigned long asid,
204 unsigned long iova)
205{
206 u32 value;
207
208 value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
209 SMMU_TLB_FLUSH_VA_SECTION(iova);
210 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
211}
212
213static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu,
214 unsigned long asid,
215 unsigned long iova)
216{
217 u32 value;
218
219 value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
220 SMMU_TLB_FLUSH_VA_GROUP(iova);
221 smmu_writel(smmu, value, SMMU_TLB_FLUSH);
222}
223
224static inline void smmu_flush(struct tegra_smmu *smmu)
225{
226 smmu_readl(smmu, SMMU_CONFIG);
227}
228
229static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp)
230{
231 unsigned long id;
232
233 mutex_lock(&smmu->lock);
234
235 id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids);
236 if (id >= smmu->soc->num_asids) {
237 mutex_unlock(&smmu->lock);
238 return -ENOSPC;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200239 }
Hiroshi DOYU9e971a02012-07-02 14:26:38 +0300240
Thierry Reding89184652014-04-16 09:24:44 +0200241 set_bit(id, smmu->asids);
242 *idp = id;
Hiroshi DOYU9e971a02012-07-02 14:26:38 +0300243
Thierry Reding89184652014-04-16 09:24:44 +0200244 mutex_unlock(&smmu->lock);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200245 return 0;
246}
247
Thierry Reding89184652014-04-16 09:24:44 +0200248static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200249{
Thierry Reding89184652014-04-16 09:24:44 +0200250 mutex_lock(&smmu->lock);
251 clear_bit(id, smmu->asids);
252 mutex_unlock(&smmu->lock);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200253}
254
Thierry Reding89184652014-04-16 09:24:44 +0200255static bool tegra_smmu_capable(enum iommu_cap cap)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200256{
Joerg Roedel7c2aa642014-09-05 10:51:37 +0200257 return false;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200258}
259
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100260static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200261{
Thierry Reding89184652014-04-16 09:24:44 +0200262 struct tegra_smmu_as *as;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200263
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100264 if (type != IOMMU_DOMAIN_UNMANAGED)
265 return NULL;
266
Thierry Reding89184652014-04-16 09:24:44 +0200267 as = kzalloc(sizeof(*as), GFP_KERNEL);
268 if (!as)
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100269 return NULL;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200270
Thierry Reding89184652014-04-16 09:24:44 +0200271 as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200272
Russell King707917c2015-07-27 13:30:02 +0100273 as->pd = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO);
Thierry Reding89184652014-04-16 09:24:44 +0200274 if (!as->pd) {
275 kfree(as);
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100276 return NULL;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200277 }
278
Russell King32924c72015-07-27 13:29:31 +0100279 as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL);
Thierry Reding89184652014-04-16 09:24:44 +0200280 if (!as->count) {
281 __free_page(as->pd);
282 kfree(as);
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100283 return NULL;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200284 }
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200285
Russell King853520f2015-07-27 13:29:26 +0100286 as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL);
287 if (!as->pts) {
Russell King32924c72015-07-27 13:29:31 +0100288 kfree(as->count);
Russell King853520f2015-07-27 13:29:26 +0100289 __free_page(as->pd);
290 kfree(as);
291 return NULL;
292 }
293
Thierry Reding471d9142015-03-27 11:07:25 +0100294 /* setup aperture */
Joerg Roedel7f65ef02015-04-02 13:33:19 +0200295 as->domain.geometry.aperture_start = 0;
296 as->domain.geometry.aperture_end = 0xffffffff;
297 as->domain.geometry.force_aperture = true;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200298
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100299 return &as->domain;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200300}
301
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100302static void tegra_smmu_domain_free(struct iommu_domain *domain)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200303{
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100304 struct tegra_smmu_as *as = to_smmu_as(domain);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200305
Thierry Reding89184652014-04-16 09:24:44 +0200306 /* TODO: free page directory and page tables */
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200307
Thierry Reding89184652014-04-16 09:24:44 +0200308 kfree(as);
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200309}
310
Thierry Reding89184652014-04-16 09:24:44 +0200311static const struct tegra_smmu_swgroup *
312tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup)
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300313{
Thierry Reding89184652014-04-16 09:24:44 +0200314 const struct tegra_smmu_swgroup *group = NULL;
315 unsigned int i;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300316
Thierry Reding89184652014-04-16 09:24:44 +0200317 for (i = 0; i < smmu->soc->num_swgroups; i++) {
318 if (smmu->soc->swgroups[i].swgroup == swgroup) {
319 group = &smmu->soc->swgroups[i];
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300320 break;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300321 }
322 }
323
Thierry Reding89184652014-04-16 09:24:44 +0200324 return group;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300325}
326
Thierry Reding89184652014-04-16 09:24:44 +0200327static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup,
328 unsigned int asid)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200329{
Thierry Reding89184652014-04-16 09:24:44 +0200330 const struct tegra_smmu_swgroup *group;
331 unsigned int i;
332 u32 value;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200333
Thierry Reding89184652014-04-16 09:24:44 +0200334 for (i = 0; i < smmu->soc->num_clients; i++) {
335 const struct tegra_mc_client *client = &smmu->soc->clients[i];
336
337 if (client->swgroup != swgroup)
338 continue;
339
340 value = smmu_readl(smmu, client->smmu.reg);
341 value |= BIT(client->smmu.bit);
342 smmu_writel(smmu, value, client->smmu.reg);
343 }
344
345 group = tegra_smmu_find_swgroup(smmu, swgroup);
346 if (group) {
347 value = smmu_readl(smmu, group->reg);
348 value &= ~SMMU_ASID_MASK;
349 value |= SMMU_ASID_VALUE(asid);
350 value |= SMMU_ASID_ENABLE;
351 smmu_writel(smmu, value, group->reg);
352 }
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200353}
354
Thierry Reding89184652014-04-16 09:24:44 +0200355static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup,
356 unsigned int asid)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200357{
Thierry Reding89184652014-04-16 09:24:44 +0200358 const struct tegra_smmu_swgroup *group;
359 unsigned int i;
360 u32 value;
361
362 group = tegra_smmu_find_swgroup(smmu, swgroup);
363 if (group) {
364 value = smmu_readl(smmu, group->reg);
365 value &= ~SMMU_ASID_MASK;
366 value |= SMMU_ASID_VALUE(asid);
367 value &= ~SMMU_ASID_ENABLE;
368 smmu_writel(smmu, value, group->reg);
369 }
370
371 for (i = 0; i < smmu->soc->num_clients; i++) {
372 const struct tegra_mc_client *client = &smmu->soc->clients[i];
373
374 if (client->swgroup != swgroup)
375 continue;
376
377 value = smmu_readl(smmu, client->smmu.reg);
378 value &= ~BIT(client->smmu.bit);
379 smmu_writel(smmu, value, client->smmu.reg);
380 }
381}
382
383static int tegra_smmu_as_prepare(struct tegra_smmu *smmu,
384 struct tegra_smmu_as *as)
385{
386 u32 value;
Hiroshi Doyu0760e8f2012-06-25 14:23:55 +0300387 int err;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200388
Thierry Reding89184652014-04-16 09:24:44 +0200389 if (as->use_count > 0) {
390 as->use_count++;
391 return 0;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200392 }
393
Russell Kinge3c97192015-07-27 13:29:52 +0100394 as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD,
395 DMA_TO_DEVICE);
396 if (dma_mapping_error(smmu->dev, as->pd_dma))
397 return -ENOMEM;
398
399 /* We can't handle 64-bit DMA addresses */
400 if (!smmu_dma_addr_valid(smmu, as->pd_dma)) {
401 err = -ENOMEM;
402 goto err_unmap;
403 }
404
Thierry Reding89184652014-04-16 09:24:44 +0200405 err = tegra_smmu_alloc_asid(smmu, &as->id);
406 if (err < 0)
Russell Kinge3c97192015-07-27 13:29:52 +0100407 goto err_unmap;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200408
Russell Kinge3c97192015-07-27 13:29:52 +0100409 smmu_flush_ptc(smmu, as->pd_dma, 0);
Thierry Reding89184652014-04-16 09:24:44 +0200410 smmu_flush_tlb_asid(smmu, as->id);
411
412 smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID);
Russell Kinge3c97192015-07-27 13:29:52 +0100413 value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr);
Thierry Reding89184652014-04-16 09:24:44 +0200414 smmu_writel(smmu, value, SMMU_PTB_DATA);
415 smmu_flush(smmu);
416
417 as->smmu = smmu;
418 as->use_count++;
419
420 return 0;
Russell Kinge3c97192015-07-27 13:29:52 +0100421
422err_unmap:
423 dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE);
424 return err;
Thierry Reding89184652014-04-16 09:24:44 +0200425}
426
427static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu,
428 struct tegra_smmu_as *as)
429{
430 if (--as->use_count > 0)
431 return;
432
433 tegra_smmu_free_asid(smmu, as->id);
Russell Kinge3c97192015-07-27 13:29:52 +0100434
435 dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE);
436
Thierry Reding89184652014-04-16 09:24:44 +0200437 as->smmu = NULL;
438}
439
440static int tegra_smmu_attach_dev(struct iommu_domain *domain,
441 struct device *dev)
442{
443 struct tegra_smmu *smmu = dev->archdata.iommu;
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100444 struct tegra_smmu_as *as = to_smmu_as(domain);
Thierry Reding89184652014-04-16 09:24:44 +0200445 struct device_node *np = dev->of_node;
446 struct of_phandle_args args;
447 unsigned int index = 0;
448 int err = 0;
449
450 while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
451 &args)) {
452 unsigned int swgroup = args.args[0];
453
454 if (args.np != smmu->dev->of_node) {
455 of_node_put(args.np);
456 continue;
457 }
458
459 of_node_put(args.np);
460
461 err = tegra_smmu_as_prepare(smmu, as);
462 if (err < 0)
463 return err;
464
465 tegra_smmu_enable(smmu, swgroup, as->id);
466 index++;
467 }
468
469 if (index == 0)
470 return -ENODEV;
471
472 return 0;
473}
474
475static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
476{
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100477 struct tegra_smmu_as *as = to_smmu_as(domain);
Thierry Reding89184652014-04-16 09:24:44 +0200478 struct device_node *np = dev->of_node;
479 struct tegra_smmu *smmu = as->smmu;
480 struct of_phandle_args args;
481 unsigned int index = 0;
482
483 while (!of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
484 &args)) {
485 unsigned int swgroup = args.args[0];
486
487 if (args.np != smmu->dev->of_node) {
488 of_node_put(args.np);
489 continue;
490 }
491
492 of_node_put(args.np);
493
494 tegra_smmu_disable(smmu, swgroup, as->id);
495 tegra_smmu_as_unprepare(smmu, as);
496 index++;
497 }
498}
499
Russell King4080e992015-07-27 13:30:12 +0100500static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova,
501 u32 value)
502{
503 unsigned int pd_index = iova_pd_index(iova);
504 struct tegra_smmu *smmu = as->smmu;
505 u32 *pd = page_address(as->pd);
506 unsigned long offset = pd_index * sizeof(*pd);
507
508 /* Set the page directory entry first */
509 pd[pd_index] = value;
510
511 /* The flush the page directory entry from caches */
512 dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset,
513 sizeof(*pd), DMA_TO_DEVICE);
514
515 /* And flush the iommu */
516 smmu_flush_ptc(smmu, as->pd_dma, offset);
517 smmu_flush_tlb_section(smmu, as->id, iova);
518 smmu_flush(smmu);
519}
520
Russell King0b42c7c2015-07-27 13:29:21 +0100521static u32 *tegra_smmu_pte_offset(struct page *pt_page, unsigned long iova)
522{
523 u32 *pt = page_address(pt_page);
524
525 return pt + iova_pt_index(iova);
526}
527
528static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova,
Russell Kinge3c97192015-07-27 13:29:52 +0100529 dma_addr_t *dmap)
Russell King0b42c7c2015-07-27 13:29:21 +0100530{
531 unsigned int pd_index = iova_pd_index(iova);
532 struct page *pt_page;
Russell Kinge3c97192015-07-27 13:29:52 +0100533 u32 *pd;
Russell King0b42c7c2015-07-27 13:29:21 +0100534
Russell King853520f2015-07-27 13:29:26 +0100535 pt_page = as->pts[pd_index];
536 if (!pt_page)
Russell King0b42c7c2015-07-27 13:29:21 +0100537 return NULL;
538
Russell Kinge3c97192015-07-27 13:29:52 +0100539 pd = page_address(as->pd);
540 *dmap = smmu_pde_to_dma(pd[pd_index]);
Russell King0b42c7c2015-07-27 13:29:21 +0100541
542 return tegra_smmu_pte_offset(pt_page, iova);
543}
544
Thierry Reding89184652014-04-16 09:24:44 +0200545static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova,
Russell Kinge3c97192015-07-27 13:29:52 +0100546 dma_addr_t *dmap)
Thierry Reding89184652014-04-16 09:24:44 +0200547{
Russell King34d35f82015-07-27 13:29:16 +0100548 unsigned int pde = iova_pd_index(iova);
Thierry Reding89184652014-04-16 09:24:44 +0200549 struct tegra_smmu *smmu = as->smmu;
Thierry Reding89184652014-04-16 09:24:44 +0200550
Russell King853520f2015-07-27 13:29:26 +0100551 if (!as->pts[pde]) {
Russell Kinge3c97192015-07-27 13:29:52 +0100552 struct page *page;
553 dma_addr_t dma;
554
Russell King707917c2015-07-27 13:30:02 +0100555 page = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO);
Thierry Reding89184652014-04-16 09:24:44 +0200556 if (!page)
557 return NULL;
558
Russell Kinge3c97192015-07-27 13:29:52 +0100559 dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT,
560 DMA_TO_DEVICE);
561 if (dma_mapping_error(smmu->dev, dma)) {
562 __free_page(page);
563 return NULL;
564 }
565
566 if (!smmu_dma_addr_valid(smmu, dma)) {
567 dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT,
568 DMA_TO_DEVICE);
569 __free_page(page);
570 return NULL;
571 }
572
Russell King853520f2015-07-27 13:29:26 +0100573 as->pts[pde] = page;
574
Russell King4080e992015-07-27 13:30:12 +0100575 tegra_smmu_set_pde(as, iova, SMMU_MK_PDE(dma, SMMU_PDE_ATTR |
576 SMMU_PDE_NEXT));
Russell Kinge3c97192015-07-27 13:29:52 +0100577
578 *dmap = dma;
Thierry Reding89184652014-04-16 09:24:44 +0200579 } else {
Russell King4080e992015-07-27 13:30:12 +0100580 u32 *pd = page_address(as->pd);
581
Russell Kinge3c97192015-07-27 13:29:52 +0100582 *dmap = smmu_pde_to_dma(pd[pde]);
Thierry Reding89184652014-04-16 09:24:44 +0200583 }
584
Russell King7ffc6f02015-08-06 14:56:39 +0200585 return tegra_smmu_pte_offset(as->pts[pde], iova);
586}
Russell King0b42c7c2015-07-27 13:29:21 +0100587
Russell King7ffc6f02015-08-06 14:56:39 +0200588static void tegra_smmu_pte_get_use(struct tegra_smmu_as *as, unsigned long iova)
589{
590 unsigned int pd_index = iova_pd_index(iova);
Thierry Reding89184652014-04-16 09:24:44 +0200591
Russell King7ffc6f02015-08-06 14:56:39 +0200592 as->count[pd_index]++;
Thierry Reding89184652014-04-16 09:24:44 +0200593}
594
Russell Kingb98e34f2015-07-27 13:29:05 +0100595static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova)
Thierry Reding89184652014-04-16 09:24:44 +0200596{
Russell King34d35f82015-07-27 13:29:16 +0100597 unsigned int pde = iova_pd_index(iova);
Russell King853520f2015-07-27 13:29:26 +0100598 struct page *page = as->pts[pde];
Thierry Reding89184652014-04-16 09:24:44 +0200599
600 /*
601 * When no entries in this page table are used anymore, return the
602 * memory page to the system.
603 */
Russell King32924c72015-07-27 13:29:31 +0100604 if (--as->count[pde] == 0) {
Russell King4080e992015-07-27 13:30:12 +0100605 struct tegra_smmu *smmu = as->smmu;
606 u32 *pd = page_address(as->pd);
Russell Kinge3c97192015-07-27 13:29:52 +0100607 dma_addr_t pte_dma = smmu_pde_to_dma(pd[pde]);
Thierry Reding89184652014-04-16 09:24:44 +0200608
Russell King4080e992015-07-27 13:30:12 +0100609 tegra_smmu_set_pde(as, iova, 0);
Russell Kingb98e34f2015-07-27 13:29:05 +0100610
Russell Kinge3c97192015-07-27 13:29:52 +0100611 dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE);
Russell Kingb98e34f2015-07-27 13:29:05 +0100612 __free_page(page);
Russell King853520f2015-07-27 13:29:26 +0100613 as->pts[pde] = NULL;
Thierry Reding89184652014-04-16 09:24:44 +0200614 }
615}
616
Russell King8482ee52015-07-27 13:29:10 +0100617static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova,
Russell Kinge3c97192015-07-27 13:29:52 +0100618 u32 *pte, dma_addr_t pte_dma, u32 val)
Russell King8482ee52015-07-27 13:29:10 +0100619{
620 struct tegra_smmu *smmu = as->smmu;
621 unsigned long offset = offset_in_page(pte);
622
623 *pte = val;
624
Russell Kinge3c97192015-07-27 13:29:52 +0100625 dma_sync_single_range_for_device(smmu->dev, pte_dma, offset,
626 4, DMA_TO_DEVICE);
627 smmu_flush_ptc(smmu, pte_dma, offset);
Russell King8482ee52015-07-27 13:29:10 +0100628 smmu_flush_tlb_group(smmu, as->id, iova);
629 smmu_flush(smmu);
630}
631
Thierry Reding89184652014-04-16 09:24:44 +0200632static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova,
633 phys_addr_t paddr, size_t size, int prot)
634{
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100635 struct tegra_smmu_as *as = to_smmu_as(domain);
Russell Kinge3c97192015-07-27 13:29:52 +0100636 dma_addr_t pte_dma;
Thierry Reding89184652014-04-16 09:24:44 +0200637 u32 *pte;
638
Russell Kinge3c97192015-07-27 13:29:52 +0100639 pte = as_get_pte(as, iova, &pte_dma);
Thierry Reding89184652014-04-16 09:24:44 +0200640 if (!pte)
Hiroshi Doyu0547c2f2012-06-25 14:23:57 +0300641 return -ENOMEM;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200642
Russell King7ffc6f02015-08-06 14:56:39 +0200643 /* If we aren't overwriting a pre-existing entry, increment use */
644 if (*pte == 0)
645 tegra_smmu_pte_get_use(as, iova);
646
Russell Kinge3c97192015-07-27 13:29:52 +0100647 tegra_smmu_set_pte(as, iova, pte, pte_dma,
Russell King8482ee52015-07-27 13:29:10 +0100648 __phys_to_pfn(paddr) | SMMU_PTE_ATTR);
Thierry Reding89184652014-04-16 09:24:44 +0200649
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200650 return 0;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200651}
652
Thierry Reding89184652014-04-16 09:24:44 +0200653static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
654 size_t size)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200655{
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100656 struct tegra_smmu_as *as = to_smmu_as(domain);
Russell Kinge3c97192015-07-27 13:29:52 +0100657 dma_addr_t pte_dma;
Thierry Reding89184652014-04-16 09:24:44 +0200658 u32 *pte;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200659
Russell Kinge3c97192015-07-27 13:29:52 +0100660 pte = tegra_smmu_pte_lookup(as, iova, &pte_dma);
Russell Kingb98e34f2015-07-27 13:29:05 +0100661 if (!pte || !*pte)
Thierry Reding89184652014-04-16 09:24:44 +0200662 return 0;
Hiroshi Doyu39abf8a2012-08-02 11:46:40 +0300663
Russell Kinge3c97192015-07-27 13:29:52 +0100664 tegra_smmu_set_pte(as, iova, pte, pte_dma, 0);
Russell Kingb98e34f2015-07-27 13:29:05 +0100665 tegra_smmu_pte_put_use(as, iova);
666
Thierry Reding89184652014-04-16 09:24:44 +0200667 return size;
668}
669
670static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain,
671 dma_addr_t iova)
672{
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100673 struct tegra_smmu_as *as = to_smmu_as(domain);
Thierry Reding89184652014-04-16 09:24:44 +0200674 unsigned long pfn;
Russell Kinge3c97192015-07-27 13:29:52 +0100675 dma_addr_t pte_dma;
Thierry Reding89184652014-04-16 09:24:44 +0200676 u32 *pte;
677
Russell Kinge3c97192015-07-27 13:29:52 +0100678 pte = tegra_smmu_pte_lookup(as, iova, &pte_dma);
Russell King91137852015-07-27 13:29:00 +0100679 if (!pte || !*pte)
680 return 0;
681
Thierry Reding804cb542015-03-27 11:07:27 +0100682 pfn = *pte & as->smmu->pfn_mask;
Thierry Reding89184652014-04-16 09:24:44 +0200683
684 return PFN_PHYS(pfn);
685}
686
687static struct tegra_smmu *tegra_smmu_find(struct device_node *np)
688{
689 struct platform_device *pdev;
690 struct tegra_mc *mc;
691
692 pdev = of_find_device_by_node(np);
693 if (!pdev)
694 return NULL;
695
696 mc = platform_get_drvdata(pdev);
697 if (!mc)
698 return NULL;
699
700 return mc->smmu;
701}
702
703static int tegra_smmu_add_device(struct device *dev)
704{
705 struct device_node *np = dev->of_node;
706 struct of_phandle_args args;
707 unsigned int index = 0;
708
709 while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index,
710 &args) == 0) {
711 struct tegra_smmu *smmu;
712
713 smmu = tegra_smmu_find(args.np);
714 if (smmu) {
715 /*
716 * Only a single IOMMU master interface is currently
717 * supported by the Linux kernel, so abort after the
718 * first match.
719 */
720 dev->archdata.iommu = smmu;
721 break;
722 }
723
724 index++;
725 }
726
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200727 return 0;
728}
729
Thierry Reding89184652014-04-16 09:24:44 +0200730static void tegra_smmu_remove_device(struct device *dev)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200731{
Thierry Reding89184652014-04-16 09:24:44 +0200732 dev->archdata.iommu = NULL;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200733}
734
Thierry Reding89184652014-04-16 09:24:44 +0200735static const struct iommu_ops tegra_smmu_ops = {
736 .capable = tegra_smmu_capable,
Joerg Roedeld5f1a812015-03-26 13:43:12 +0100737 .domain_alloc = tegra_smmu_domain_alloc,
738 .domain_free = tegra_smmu_domain_free,
Thierry Reding89184652014-04-16 09:24:44 +0200739 .attach_dev = tegra_smmu_attach_dev,
740 .detach_dev = tegra_smmu_detach_dev,
741 .add_device = tegra_smmu_add_device,
742 .remove_device = tegra_smmu_remove_device,
743 .map = tegra_smmu_map,
744 .unmap = tegra_smmu_unmap,
745 .map_sg = default_iommu_map_sg,
746 .iova_to_phys = tegra_smmu_iova_to_phys,
747
748 .pgsize_bitmap = SZ_4K,
749};
750
751static void tegra_smmu_ahb_enable(void)
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200752{
Thierry Reding89184652014-04-16 09:24:44 +0200753 static const struct of_device_id ahb_match[] = {
754 { .compatible = "nvidia,tegra30-ahb", },
755 { }
756 };
757 struct device_node *ahb;
758
759 ahb = of_find_matching_node(NULL, ahb_match);
760 if (ahb) {
761 tegra_ahb_enable_smmu(ahb);
762 of_node_put(ahb);
763 }
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200764}
765
Thierry Redingd1313e72015-01-23 09:49:25 +0100766static int tegra_smmu_swgroups_show(struct seq_file *s, void *data)
767{
768 struct tegra_smmu *smmu = s->private;
769 unsigned int i;
770 u32 value;
771
772 seq_printf(s, "swgroup enabled ASID\n");
773 seq_printf(s, "------------------------\n");
774
775 for (i = 0; i < smmu->soc->num_swgroups; i++) {
776 const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i];
777 const char *status;
778 unsigned int asid;
779
780 value = smmu_readl(smmu, group->reg);
781
782 if (value & SMMU_ASID_ENABLE)
783 status = "yes";
784 else
785 status = "no";
786
787 asid = value & SMMU_ASID_MASK;
788
789 seq_printf(s, "%-9s %-7s %#04x\n", group->name, status,
790 asid);
791 }
792
793 return 0;
794}
795
796static int tegra_smmu_swgroups_open(struct inode *inode, struct file *file)
797{
798 return single_open(file, tegra_smmu_swgroups_show, inode->i_private);
799}
800
801static const struct file_operations tegra_smmu_swgroups_fops = {
802 .open = tegra_smmu_swgroups_open,
803 .read = seq_read,
804 .llseek = seq_lseek,
805 .release = single_release,
806};
807
808static int tegra_smmu_clients_show(struct seq_file *s, void *data)
809{
810 struct tegra_smmu *smmu = s->private;
811 unsigned int i;
812 u32 value;
813
814 seq_printf(s, "client enabled\n");
815 seq_printf(s, "--------------------\n");
816
817 for (i = 0; i < smmu->soc->num_clients; i++) {
818 const struct tegra_mc_client *client = &smmu->soc->clients[i];
819 const char *status;
820
821 value = smmu_readl(smmu, client->smmu.reg);
822
823 if (value & BIT(client->smmu.bit))
824 status = "yes";
825 else
826 status = "no";
827
828 seq_printf(s, "%-12s %s\n", client->name, status);
829 }
830
831 return 0;
832}
833
834static int tegra_smmu_clients_open(struct inode *inode, struct file *file)
835{
836 return single_open(file, tegra_smmu_clients_show, inode->i_private);
837}
838
839static const struct file_operations tegra_smmu_clients_fops = {
840 .open = tegra_smmu_clients_open,
841 .read = seq_read,
842 .llseek = seq_lseek,
843 .release = single_release,
844};
845
846static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu)
847{
848 smmu->debugfs = debugfs_create_dir("smmu", NULL);
849 if (!smmu->debugfs)
850 return;
851
852 debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu,
853 &tegra_smmu_swgroups_fops);
854 debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu,
855 &tegra_smmu_clients_fops);
856}
857
858static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu)
859{
860 debugfs_remove_recursive(smmu->debugfs);
861}
862
Thierry Reding89184652014-04-16 09:24:44 +0200863struct tegra_smmu *tegra_smmu_probe(struct device *dev,
864 const struct tegra_smmu_soc *soc,
865 struct tegra_mc *mc)
866{
867 struct tegra_smmu *smmu;
868 size_t size;
869 u32 value;
870 int err;
Hiroshi DOYU7a31f6f2011-11-17 07:31:31 +0200871
Thierry Reding89184652014-04-16 09:24:44 +0200872 /* This can happen on Tegra20 which doesn't have an SMMU */
873 if (!soc)
874 return NULL;
875
876 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
877 if (!smmu)
878 return ERR_PTR(-ENOMEM);
879
880 /*
881 * This is a bit of a hack. Ideally we'd want to simply return this
882 * value. However the IOMMU registration process will attempt to add
883 * all devices to the IOMMU when bus_set_iommu() is called. In order
884 * not to rely on global variables to track the IOMMU instance, we
885 * set it here so that it can be looked up from the .add_device()
886 * callback via the IOMMU device's .drvdata field.
887 */
888 mc->smmu = smmu;
889
890 size = BITS_TO_LONGS(soc->num_asids) * sizeof(long);
891
892 smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL);
893 if (!smmu->asids)
894 return ERR_PTR(-ENOMEM);
895
896 mutex_init(&smmu->lock);
897
898 smmu->regs = mc->regs;
899 smmu->soc = soc;
900 smmu->dev = dev;
901 smmu->mc = mc;
902
Thierry Reding804cb542015-03-27 11:07:27 +0100903 smmu->pfn_mask = BIT_MASK(mc->soc->num_address_bits - PAGE_SHIFT) - 1;
904 dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n",
905 mc->soc->num_address_bits, smmu->pfn_mask);
Thierry Reding11cec152015-08-06 14:20:31 +0200906 smmu->tlb_mask = (smmu->soc->num_tlb_lines << 1) - 1;
907 dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines,
908 smmu->tlb_mask);
Thierry Reding804cb542015-03-27 11:07:27 +0100909
Thierry Reding89184652014-04-16 09:24:44 +0200910 value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f);
911
912 if (soc->supports_request_limit)
913 value |= SMMU_PTC_CONFIG_REQ_LIMIT(8);
914
915 smmu_writel(smmu, value, SMMU_PTC_CONFIG);
916
917 value = SMMU_TLB_CONFIG_HIT_UNDER_MISS |
Thierry Reding11cec152015-08-06 14:20:31 +0200918 SMMU_TLB_CONFIG_ACTIVE_LINES(smmu);
Thierry Reding89184652014-04-16 09:24:44 +0200919
920 if (soc->supports_round_robin_arbitration)
921 value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION;
922
923 smmu_writel(smmu, value, SMMU_TLB_CONFIG);
924
Russell Kingb8fe0382015-07-27 13:29:41 +0100925 smmu_flush_ptc_all(smmu);
Thierry Reding89184652014-04-16 09:24:44 +0200926 smmu_flush_tlb(smmu);
927 smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG);
928 smmu_flush(smmu);
929
930 tegra_smmu_ahb_enable();
931
932 err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops);
933 if (err < 0)
934 return ERR_PTR(err);
935
Thierry Redingd1313e72015-01-23 09:49:25 +0100936 if (IS_ENABLED(CONFIG_DEBUG_FS))
937 tegra_smmu_debugfs_init(smmu);
938
Thierry Reding89184652014-04-16 09:24:44 +0200939 return smmu;
940}
Thierry Redingd1313e72015-01-23 09:49:25 +0100941
942void tegra_smmu_remove(struct tegra_smmu *smmu)
943{
944 if (IS_ENABLED(CONFIG_DEBUG_FS))
945 tegra_smmu_debugfs_exit(smmu);
946}