Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 1 | # |
| 2 | # Processor families |
| 3 | # |
| 4 | config CPU_SH2 |
| 5 | bool |
Yoshinori Sato | 9d4436a | 2006-11-05 15:40:13 +0900 | [diff] [blame] | 6 | |
| 7 | config CPU_SH2A |
| 8 | bool |
| 9 | select CPU_SH2 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 10 | |
| 11 | config CPU_SH3 |
| 12 | bool |
| 13 | select CPU_HAS_INTEVT |
| 14 | select CPU_HAS_SR_RB |
| 15 | |
| 16 | config CPU_SH4 |
| 17 | bool |
| 18 | select CPU_HAS_INTEVT |
| 19 | select CPU_HAS_SR_RB |
Paul Mundt | 26b7a78 | 2006-12-28 10:31:48 +0900 | [diff] [blame] | 20 | select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 21 | |
| 22 | config CPU_SH4A |
| 23 | bool |
| 24 | select CPU_SH4 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 25 | |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 26 | config CPU_SH4AL_DSP |
| 27 | bool |
| 28 | select CPU_SH4A |
Paul Mundt | ac79fd5 | 2007-07-25 16:26:10 +0900 | [diff] [blame] | 29 | select CPU_HAS_DSP |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 30 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 31 | config CPU_SUBTYPE_ST40 |
| 32 | bool |
| 33 | select CPU_SH4 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 34 | |
Paul Mundt | 41504c3 | 2006-12-11 20:28:03 +0900 | [diff] [blame] | 35 | config CPU_SHX2 |
| 36 | bool |
| 37 | |
Paul Mundt | 2b1bd1a | 2007-06-20 18:27:10 +0900 | [diff] [blame] | 38 | config CPU_SHX3 |
| 39 | bool |
| 40 | |
Paul Mundt | f3d2229 | 2007-05-14 17:29:12 +0900 | [diff] [blame] | 41 | choice |
| 42 | prompt "Processor sub-type selection" |
| 43 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 44 | # |
| 45 | # Processor subtypes |
| 46 | # |
| 47 | |
Paul Mundt | f3d2229 | 2007-05-14 17:29:12 +0900 | [diff] [blame] | 48 | # SH-2 Processor Support |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 49 | |
Yoshinori Sato | 9d4436a | 2006-11-05 15:40:13 +0900 | [diff] [blame] | 50 | config CPU_SUBTYPE_SH7619 |
| 51 | bool "Support SH7619 processor" |
| 52 | select CPU_SH2 |
| 53 | |
Paul Mundt | f3d2229 | 2007-05-14 17:29:12 +0900 | [diff] [blame] | 54 | # SH-2A Processor Support |
Yoshinori Sato | 9d4436a | 2006-11-05 15:40:13 +0900 | [diff] [blame] | 55 | |
| 56 | config CPU_SUBTYPE_SH7206 |
| 57 | bool "Support SH7206 processor" |
| 58 | select CPU_SH2A |
| 59 | |
Paul Mundt | f3d2229 | 2007-05-14 17:29:12 +0900 | [diff] [blame] | 60 | # SH-3 Processor Support |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 61 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 62 | config CPU_SUBTYPE_SH7705 |
| 63 | bool "Support SH7705 processor" |
| 64 | select CPU_SH3 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 65 | |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 66 | config CPU_SUBTYPE_SH7706 |
| 67 | bool "Support SH7706 processor" |
| 68 | select CPU_SH3 |
| 69 | help |
| 70 | Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU. |
| 71 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 72 | config CPU_SUBTYPE_SH7707 |
| 73 | bool "Support SH7707 processor" |
| 74 | select CPU_SH3 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 75 | help |
| 76 | Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU. |
| 77 | |
| 78 | config CPU_SUBTYPE_SH7708 |
| 79 | bool "Support SH7708 processor" |
| 80 | select CPU_SH3 |
| 81 | help |
| 82 | Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or |
| 83 | if you have a 100 Mhz SH-3 HD6417708R CPU. |
| 84 | |
| 85 | config CPU_SUBTYPE_SH7709 |
| 86 | bool "Support SH7709 processor" |
| 87 | select CPU_SH3 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 88 | help |
| 89 | Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. |
| 90 | |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 91 | config CPU_SUBTYPE_SH7710 |
| 92 | bool "Support SH7710 processor" |
| 93 | select CPU_SH3 |
Paul Mundt | ac79fd5 | 2007-07-25 16:26:10 +0900 | [diff] [blame] | 94 | select CPU_HAS_DSP |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 95 | help |
| 96 | Select SH7710 if you have a SH3-DSP SH7710 CPU. |
| 97 | |
Nobuhiro Iwamatsu | 9465a54 | 2007-03-27 18:13:51 +0900 | [diff] [blame] | 98 | config CPU_SUBTYPE_SH7712 |
| 99 | bool "Support SH7712 processor" |
| 100 | select CPU_SH3 |
Paul Mundt | ac79fd5 | 2007-07-25 16:26:10 +0900 | [diff] [blame] | 101 | select CPU_HAS_DSP |
Nobuhiro Iwamatsu | 9465a54 | 2007-03-27 18:13:51 +0900 | [diff] [blame] | 102 | help |
| 103 | Select SH7712 if you have a SH3-DSP SH7712 CPU. |
| 104 | |
Markus Brunner | 3ea6bc3 | 2007-08-20 08:59:33 +0900 | [diff] [blame] | 105 | config CPU_SUBTYPE_SH7720 |
| 106 | bool "Support SH7720 processor" |
| 107 | select CPU_SH3 |
| 108 | select CPU_HAS_INTC_IRQ |
| 109 | select CPU_HAS_DSP |
| 110 | help |
| 111 | Select SH7720 if you have a SH3-DSP SH7720 CPU. |
| 112 | |
Paul Mundt | f3d2229 | 2007-05-14 17:29:12 +0900 | [diff] [blame] | 113 | # SH-4 Processor Support |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 114 | |
| 115 | config CPU_SUBTYPE_SH7750 |
| 116 | bool "Support SH7750 processor" |
| 117 | select CPU_SH4 |
| 118 | help |
| 119 | Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. |
| 120 | |
| 121 | config CPU_SUBTYPE_SH7091 |
| 122 | bool "Support SH7091 processor" |
| 123 | select CPU_SH4 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 124 | help |
| 125 | Select SH7091 if you have an SH-4 based Sega device (such as |
| 126 | the Dreamcast, Naomi, and Naomi 2). |
| 127 | |
| 128 | config CPU_SUBTYPE_SH7750R |
| 129 | bool "Support SH7750R processor" |
| 130 | select CPU_SH4 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 131 | |
| 132 | config CPU_SUBTYPE_SH7750S |
| 133 | bool "Support SH7750S processor" |
| 134 | select CPU_SH4 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 135 | |
| 136 | config CPU_SUBTYPE_SH7751 |
| 137 | bool "Support SH7751 processor" |
| 138 | select CPU_SH4 |
| 139 | help |
| 140 | Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, |
| 141 | or if you have a HD6417751R CPU. |
| 142 | |
| 143 | config CPU_SUBTYPE_SH7751R |
| 144 | bool "Support SH7751R processor" |
| 145 | select CPU_SH4 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 146 | |
| 147 | config CPU_SUBTYPE_SH7760 |
| 148 | bool "Support SH7760 processor" |
| 149 | select CPU_SH4 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 150 | |
| 151 | config CPU_SUBTYPE_SH4_202 |
| 152 | bool "Support SH4-202 processor" |
| 153 | select CPU_SH4 |
| 154 | |
Paul Mundt | f3d2229 | 2007-05-14 17:29:12 +0900 | [diff] [blame] | 155 | # ST40 Processor Support |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 156 | |
| 157 | config CPU_SUBTYPE_ST40STB1 |
| 158 | bool "Support ST40STB1/ST40RA processors" |
| 159 | select CPU_SUBTYPE_ST40 |
| 160 | help |
| 161 | Select ST40STB1 if you have a ST40RA CPU. |
| 162 | This was previously called the ST40STB1, hence the option name. |
| 163 | |
| 164 | config CPU_SUBTYPE_ST40GX1 |
| 165 | bool "Support ST40GX1 processor" |
| 166 | select CPU_SUBTYPE_ST40 |
| 167 | help |
| 168 | Select ST40GX1 if you have a ST40GX1 CPU. |
| 169 | |
Paul Mundt | f3d2229 | 2007-05-14 17:29:12 +0900 | [diff] [blame] | 170 | # SH-4A Processor Support |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 171 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 172 | config CPU_SUBTYPE_SH7770 |
| 173 | bool "Support SH7770 processor" |
| 174 | select CPU_SH4A |
| 175 | |
| 176 | config CPU_SUBTYPE_SH7780 |
| 177 | bool "Support SH7780 processor" |
| 178 | select CPU_SH4A |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 179 | |
Paul Mundt | b552c7e | 2006-11-20 14:14:29 +0900 | [diff] [blame] | 180 | config CPU_SUBTYPE_SH7785 |
| 181 | bool "Support SH7785 processor" |
| 182 | select CPU_SH4A |
Paul Mundt | 41504c3 | 2006-12-11 20:28:03 +0900 | [diff] [blame] | 183 | select CPU_SHX2 |
Paul Mundt | b552c7e | 2006-11-20 14:14:29 +0900 | [diff] [blame] | 184 | |
Paul Mundt | 2b1bd1a | 2007-06-20 18:27:10 +0900 | [diff] [blame] | 185 | config CPU_SUBTYPE_SHX3 |
| 186 | bool "Support SH-X3 processor" |
| 187 | select CPU_SH4A |
| 188 | select CPU_SHX3 |
Paul Mundt | 7da3b8e | 2007-08-01 17:52:47 +0900 | [diff] [blame] | 189 | select ARCH_SPARSEMEM_ENABLE |
| 190 | select SYS_SUPPORTS_NUMA |
Paul Mundt | 2b1bd1a | 2007-06-20 18:27:10 +0900 | [diff] [blame] | 191 | |
Paul Mundt | f3d2229 | 2007-05-14 17:29:12 +0900 | [diff] [blame] | 192 | # SH4AL-DSP Processor Support |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 193 | |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 194 | config CPU_SUBTYPE_SH7343 |
| 195 | bool "Support SH7343 processor" |
| 196 | select CPU_SH4AL_DSP |
| 197 | |
Paul Mundt | 41504c3 | 2006-12-11 20:28:03 +0900 | [diff] [blame] | 198 | config CPU_SUBTYPE_SH7722 |
| 199 | bool "Support SH7722 processor" |
| 200 | select CPU_SH4AL_DSP |
| 201 | select CPU_SHX2 |
Paul Mundt | 520588f | 2007-06-06 17:58:56 +0900 | [diff] [blame] | 202 | select ARCH_SPARSEMEM_ENABLE |
Paul Mundt | 357d594 | 2007-06-11 15:32:07 +0900 | [diff] [blame] | 203 | select SYS_SUPPORTS_NUMA |
Paul Mundt | 41504c3 | 2006-12-11 20:28:03 +0900 | [diff] [blame] | 204 | |
Paul Mundt | f3d2229 | 2007-05-14 17:29:12 +0900 | [diff] [blame] | 205 | endchoice |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 206 | |
| 207 | menu "Memory management options" |
| 208 | |
Paul Mundt | 5f8c990 | 2007-05-08 11:55:21 +0900 | [diff] [blame] | 209 | config QUICKLIST |
| 210 | def_bool y |
| 211 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 212 | config MMU |
| 213 | bool "Support for memory management hardware" |
| 214 | depends on !CPU_SH2 |
| 215 | default y |
| 216 | help |
| 217 | Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to |
| 218 | boot on these systems, this option must not be set. |
| 219 | |
| 220 | On other systems (such as the SH-3 and 4) where an MMU exists, |
| 221 | turning this off will boot the kernel on these machines with the |
| 222 | MMU implicitly switched off. |
| 223 | |
Paul Mundt | e7f93a3 | 2006-09-27 17:19:13 +0900 | [diff] [blame] | 224 | config PAGE_OFFSET |
| 225 | hex |
| 226 | default "0x80000000" if MMU |
| 227 | default "0x00000000" |
| 228 | |
| 229 | config MEMORY_START |
| 230 | hex "Physical memory start address" |
| 231 | default "0x08000000" |
| 232 | ---help--- |
| 233 | Computers built with Hitachi SuperH processors always |
| 234 | map the ROM starting at address zero. But the processor |
| 235 | does not specify the range that RAM takes. |
| 236 | |
| 237 | The physical memory (RAM) start address will be automatically |
| 238 | set to 08000000. Other platforms, such as the Solution Engine |
| 239 | boards typically map RAM at 0C000000. |
| 240 | |
| 241 | Tweak this only when porting to a new machine which does not |
| 242 | already have a defconfig. Changing it from the known correct |
| 243 | value on any of the known systems will only lead to disaster. |
| 244 | |
| 245 | config MEMORY_SIZE |
| 246 | hex "Physical memory size" |
| 247 | default "0x00400000" |
| 248 | help |
| 249 | This sets the default memory size assumed by your SH kernel. It can |
| 250 | be overridden as normal by the 'mem=' argument on the kernel command |
| 251 | line. If unsure, consult your board specifications or just leave it |
| 252 | as 0x00400000 which was the default value before this became |
| 253 | configurable. |
| 254 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 255 | config 32BIT |
| 256 | bool "Support 32-bit physical addressing through PMB" |
Paul Mundt | 50f63f2 | 2007-06-15 18:30:42 +0900 | [diff] [blame] | 257 | depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 258 | default y |
| 259 | help |
| 260 | If you say Y here, physical addressing will be extended to |
| 261 | 32-bits through the SH-4A PMB. If this is not set, legacy |
| 262 | 29-bit physical addressing will be used. |
| 263 | |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 264 | config X2TLB |
| 265 | bool "Enable extended TLB mode" |
Paul Mundt | 41504c3 | 2006-12-11 20:28:03 +0900 | [diff] [blame] | 266 | depends on CPU_SHX2 && MMU && EXPERIMENTAL |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 267 | help |
| 268 | Selecting this option will enable the extended mode of the SH-X2 |
| 269 | TLB. For legacy SH-X behaviour and interoperability, say N. For |
| 270 | all of the fun new features and a willingless to submit bug reports, |
| 271 | say Y. |
| 272 | |
Paul Mundt | 19f9a34 | 2006-09-27 18:33:49 +0900 | [diff] [blame] | 273 | config VSYSCALL |
| 274 | bool "Support vsyscall page" |
| 275 | depends on MMU |
| 276 | default y |
| 277 | help |
| 278 | This will enable support for the kernel mapping a vDSO page |
| 279 | in process space, and subsequently handing down the entry point |
| 280 | to the libc through the ELF auxiliary vector. |
| 281 | |
| 282 | From the kernel side this is used for the signal trampoline. |
| 283 | For systems with an MMU that can afford to give up a page, |
| 284 | (the default value) say Y. |
| 285 | |
Paul Mundt | b241cb0 | 2007-06-06 17:52:19 +0900 | [diff] [blame] | 286 | config NUMA |
| 287 | bool "Non Uniform Memory Access (NUMA) Support" |
Paul Mundt | 357d594 | 2007-06-11 15:32:07 +0900 | [diff] [blame] | 288 | depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL |
Paul Mundt | b241cb0 | 2007-06-06 17:52:19 +0900 | [diff] [blame] | 289 | default n |
| 290 | help |
| 291 | Some SH systems have many various memories scattered around |
| 292 | the address space, each with varying latencies. This enables |
| 293 | support for these blocks by binding them to nodes and allowing |
| 294 | memory policies to be used for prioritizing and controlling |
| 295 | allocation behaviour. |
| 296 | |
Paul Mundt | 0106662 | 2007-03-28 16:38:13 +0900 | [diff] [blame] | 297 | config NODES_SHIFT |
| 298 | int |
Paul Mundt | 9904494 | 2007-08-08 16:45:07 +0900 | [diff] [blame] | 299 | default "3" if CPU_SUBTYPE_SHX3 |
Paul Mundt | 0106662 | 2007-03-28 16:38:13 +0900 | [diff] [blame] | 300 | default "1" |
| 301 | depends on NEED_MULTIPLE_NODES |
| 302 | |
| 303 | config ARCH_FLATMEM_ENABLE |
| 304 | def_bool y |
Paul Mundt | 357d594 | 2007-06-11 15:32:07 +0900 | [diff] [blame] | 305 | depends on !NUMA |
Paul Mundt | 0106662 | 2007-03-28 16:38:13 +0900 | [diff] [blame] | 306 | |
Paul Mundt | dfbb904 | 2007-05-23 17:48:36 +0900 | [diff] [blame] | 307 | config ARCH_SPARSEMEM_ENABLE |
| 308 | def_bool y |
| 309 | select SPARSEMEM_STATIC |
| 310 | |
| 311 | config ARCH_SPARSEMEM_DEFAULT |
| 312 | def_bool y |
| 313 | |
Paul Mundt | 1ce7ddd | 2007-05-09 13:20:52 +0900 | [diff] [blame] | 314 | config MAX_ACTIVE_REGIONS |
| 315 | int |
Paul Mundt | 7da3b8e | 2007-08-01 17:52:47 +0900 | [diff] [blame] | 316 | default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM) |
Paul Mundt | 520588f | 2007-06-06 17:58:56 +0900 | [diff] [blame] | 317 | default "2" if (CPU_SUBTYPE_SH7722 && SPARSEMEM) |
Paul Mundt | 1ce7ddd | 2007-05-09 13:20:52 +0900 | [diff] [blame] | 318 | default "1" |
| 319 | |
Paul Mundt | 0106662 | 2007-03-28 16:38:13 +0900 | [diff] [blame] | 320 | config ARCH_POPULATES_NODE_MAP |
| 321 | def_bool y |
| 322 | |
Paul Mundt | dfbb904 | 2007-05-23 17:48:36 +0900 | [diff] [blame] | 323 | config ARCH_SELECT_MEMORY_MODEL |
| 324 | def_bool y |
| 325 | |
Paul Mundt | 33d63bd | 2007-06-07 11:32:52 +0900 | [diff] [blame] | 326 | config ARCH_ENABLE_MEMORY_HOTPLUG |
| 327 | def_bool y |
| 328 | depends on SPARSEMEM |
| 329 | |
| 330 | config ARCH_MEMORY_PROBE |
| 331 | def_bool y |
| 332 | depends on MEMORY_HOTPLUG |
| 333 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 334 | choice |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 335 | prompt "Kernel page size" |
| 336 | default PAGE_SIZE_4KB |
| 337 | |
| 338 | config PAGE_SIZE_4KB |
| 339 | bool "4kB" |
| 340 | help |
| 341 | This is the default page size used by all SuperH CPUs. |
| 342 | |
| 343 | config PAGE_SIZE_8KB |
| 344 | bool "8kB" |
| 345 | depends on EXPERIMENTAL && X2TLB |
| 346 | help |
| 347 | This enables 8kB pages as supported by SH-X2 and later MMUs. |
| 348 | |
| 349 | config PAGE_SIZE_64KB |
| 350 | bool "64kB" |
| 351 | depends on EXPERIMENTAL && CPU_SH4 |
| 352 | help |
| 353 | This enables support for 64kB pages, possible on all SH-4 |
| 354 | CPUs and later. Highly experimental, not recommended. |
| 355 | |
| 356 | endchoice |
| 357 | |
| 358 | choice |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 359 | prompt "HugeTLB page size" |
| 360 | depends on HUGETLB_PAGE && CPU_SH4 && MMU |
| 361 | default HUGETLB_PAGE_SIZE_64K |
| 362 | |
| 363 | config HUGETLB_PAGE_SIZE_64K |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 364 | bool "64kB" |
| 365 | |
| 366 | config HUGETLB_PAGE_SIZE_256K |
| 367 | bool "256kB" |
| 368 | depends on X2TLB |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 369 | |
| 370 | config HUGETLB_PAGE_SIZE_1MB |
| 371 | bool "1MB" |
| 372 | |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 373 | config HUGETLB_PAGE_SIZE_4MB |
| 374 | bool "4MB" |
| 375 | depends on X2TLB |
| 376 | |
| 377 | config HUGETLB_PAGE_SIZE_64MB |
| 378 | bool "64MB" |
| 379 | depends on X2TLB |
| 380 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 381 | endchoice |
| 382 | |
| 383 | source "mm/Kconfig" |
| 384 | |
| 385 | endmenu |
| 386 | |
| 387 | menu "Cache configuration" |
| 388 | |
| 389 | config SH7705_CACHE_32KB |
| 390 | bool "Enable 32KB cache size for SH7705" |
| 391 | depends on CPU_SUBTYPE_SH7705 |
| 392 | default y |
| 393 | |
| 394 | config SH_DIRECT_MAPPED |
| 395 | bool "Use direct-mapped caching" |
| 396 | default n |
| 397 | help |
| 398 | Selecting this option will configure the caches to be direct-mapped, |
| 399 | even if the cache supports a 2 or 4-way mode. This is useful primarily |
| 400 | for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R, |
| 401 | SH4-202, SH4-501, etc.) |
| 402 | |
| 403 | Turn this option off for platforms that do not have a direct-mapped |
| 404 | cache, and you have no need to run the caches in such a configuration. |
| 405 | |
Paul Mundt | e7bd34a | 2007-07-31 17:07:28 +0900 | [diff] [blame] | 406 | choice |
| 407 | prompt "Cache mode" |
| 408 | default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 |
| 409 | default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A) |
| 410 | |
| 411 | config CACHE_WRITEBACK |
| 412 | bool "Write-back" |
| 413 | depends on CPU_SH2A || CPU_SH3 || CPU_SH4 |
| 414 | |
| 415 | config CACHE_WRITETHROUGH |
| 416 | bool "Write-through" |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 417 | help |
| 418 | Selecting this option will configure the caches in write-through |
| 419 | mode, as opposed to the default write-back configuration. |
| 420 | |
| 421 | Since there's sill some aliasing issues on SH-4, this option will |
| 422 | unfortunately still require the majority of flushing functions to |
| 423 | be implemented to deal with aliasing. |
| 424 | |
| 425 | If unsure, say N. |
| 426 | |
Paul Mundt | e7bd34a | 2007-07-31 17:07:28 +0900 | [diff] [blame] | 427 | config CACHE_OFF |
| 428 | bool "Off" |
| 429 | |
| 430 | endchoice |
| 431 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 432 | endmenu |