blob: 55813d6150c7ecc47ab0aa63e78e53e278e7f40b [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_PGTABLE_32_H
10#define _ASM_PGTABLE_32_H
11
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <asm/addrspace.h>
13#include <asm/page.h>
14
15#include <linux/linkage.h>
16#include <asm/cachectl.h>
17#include <asm/fixmap.h>
18
Ralf Baechlec6e8b582005-02-10 12:19:59 +000019#include <asm-generic/pgtable-nopmd.h>
20
Linus Torvalds1da177e2005-04-16 15:20:36 -070021/*
22 * - add_wired_entry() add a fixed TLB entry, and move wired register
23 */
24extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
25 unsigned long entryhi, unsigned long pagemask);
26
27/*
28 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
29 * starting at the top and working down. This is for populating the
30 * TLB before trap_init() puts the TLB miss handler in place. It
31 * should be used only for entries matching the actual page tables,
32 * to prevent inconsistencies.
33 */
34extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
35 unsigned long entryhi, unsigned long pagemask);
36
37
38/* Basically we have the same two-level (which is the logical three level
39 * Linux page table layout folded) page tables as the i386. Some day
40 * when we have proper page coloring support we can have a 1% quicker
41 * tlb refill handling mechanism, but for now it is a bit slower but
42 * works even with the cache aliasing problem the R4k and above have.
43 */
44
Linus Torvalds1da177e2005-04-16 15:20:36 -070045/* PGDIR_SHIFT determines what a third-level page table entry can map */
Ralf Baechle4c8081e42007-07-31 21:47:03 +010046#define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
48#define PGDIR_MASK (~(PGDIR_SIZE-1))
49
50/*
51 * Entries per page directory level: we use two-level, so
Ralf Baechlec6e8b582005-02-10 12:19:59 +000052 * we don't really have any PUD/PMD directory physically.
Linus Torvalds1da177e2005-04-16 15:20:36 -070053 */
Ralf Baechle99e480d2007-08-01 15:46:18 +010054#define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
55#define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
Ralf Baechlec6e8b582005-02-10 12:19:59 +000056#define PUD_ORDER aieeee_attempt_to_allocate_pud
57#define PMD_ORDER 1
Linus Torvalds1da177e2005-04-16 15:20:36 -070058#define PTE_ORDER 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070059
Jack Tan52919252008-09-23 22:52:34 +080060#define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -070061#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
62
63#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
Hugh Dickinsd455a362005-04-19 13:29:23 -070064#define FIRST_USER_ADDRESS 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070065
Thiemo Seuferf29244a2005-02-21 11:11:32 +000066#define VMALLOC_START MAP_BASE
Linus Torvalds1da177e2005-04-16 15:20:36 -070067
Ralf Baechle2ac74012008-03-10 09:31:50 +000068#define PKMAP_BASE (0xfe000000UL)
69
Linus Torvalds1da177e2005-04-16 15:20:36 -070070#ifdef CONFIG_HIGHMEM
71# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
72#else
73# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
74#endif
75
76#ifdef CONFIG_64BIT_PHYS_ADDR
77#define pte_ERROR(e) \
78 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
79#else
80#define pte_ERROR(e) \
81 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
82#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070083#define pgd_ERROR(e) \
84 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
85
86extern void load_pgd(unsigned long pg_dir);
87
88extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
89
90/*
91 * Empty pgd/pmd entries point to the invalid_pte_table.
92 */
93static inline int pmd_none(pmd_t pmd)
94{
95 return pmd_val(pmd) == (unsigned long) invalid_pte_table;
96}
97
98#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
99
100static inline int pmd_present(pmd_t pmd)
101{
102 return pmd_val(pmd) != (unsigned long) invalid_pte_table;
103}
104
105static inline void pmd_clear(pmd_t *pmdp)
106{
107 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
108}
109
Chris Dearman962f4802007-09-19 00:46:32 +0100110#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111#define pte_page(x) pfn_to_page(pte_pfn(x))
112#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
113static inline pte_t
114pfn_pte(unsigned long pfn, pgprot_t prot)
115{
116 pte_t pte;
117 pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
118 pte.pte_low = pgprot_val(prot);
119 return pte;
120}
121
122#else
123
124#define pte_page(x) pfn_to_page(pte_pfn(x))
125
126#ifdef CONFIG_CPU_VR41XX
127#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
128#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
129#else
130#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
Ralf Baechle533330b2005-08-17 10:11:10 +0000131#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132#endif
Chris Dearman962f4802007-09-19 00:46:32 +0100133#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134
135#define __pgd_offset(address) pgd_index(address)
Thiemo Seuferf29244a2005-02-21 11:11:32 +0000136#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
138
139/* to find an entry in a kernel page-table-directory */
140#define pgd_offset_k(address) pgd_offset(&init_mm, address)
141
Thiemo Seuferf29244a2005-02-21 11:11:32 +0000142#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143
144/* to find an entry in a page-table-directory */
Ralf Baechle21a151d2007-10-11 23:46:15 +0100145#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147/* Find an entry in the third-level page table.. */
148#define __pte_offset(address) \
149 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
150#define pte_offset(dir, address) \
Franck Bui-Huu5b70a312006-12-05 10:39:56 +0100151 ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
152#define pte_offset_kernel(dir, address) \
153 ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154
155#define pte_offset_map(dir, address) \
156 ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
157#define pte_offset_map_nested(dir, address) \
158 ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
159#define pte_unmap(pte) ((void)(pte))
160#define pte_unmap_nested(pte) ((void)(pte))
161
162#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
163
164/* Swap entries must have VALID bit cleared. */
165#define __swp_type(x) (((x).val >> 10) & 0x1f)
166#define __swp_offset(x) ((x).val >> 15)
167#define __swp_entry(type,offset) \
168 ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
169
170/*
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400171 * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172 */
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400173#define PTE_FILE_MAX_BITS 28
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400175#define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) | \
176 (((_pte).pte >> 2 ) & 0x38) | \
177 (((_pte).pte >> 10) << 6 ))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400179#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) | \
180 (((off) & 0x38) << 2 ) | \
181 (((off) >> 6 ) << 10) | \
182 _PAGE_FILE })
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183
184#else
185
186/* Swap entries must have VALID and GLOBAL bits cleared. */
Sergei Shtylyov6ebba0e2006-05-27 20:43:04 +0400187#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
188#define __swp_type(x) (((x).val >> 2) & 0x1f)
189#define __swp_offset(x) ((x).val >> 7)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190#define __swp_entry(type,offset) \
Sergei Shtylyov6ebba0e2006-05-27 20:43:04 +0400191 ((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
192#else
193#define __swp_type(x) (((x).val >> 8) & 0x1f)
194#define __swp_offset(x) ((x).val >> 13)
195#define __swp_entry(type,offset) \
196 ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
197#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400199#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200/*
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400201 * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 */
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400203#define PTE_FILE_MAX_BITS 30
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400205#define pte_to_pgoff(_pte) ((_pte).pte_high >> 2)
206#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 })
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207
208#else
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400209/*
210 * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
211 */
212#define PTE_FILE_MAX_BITS 28
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213
Sergei Shtylyov7cb710c2006-05-27 22:39:39 +0400214#define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) | \
215 (((_pte).pte >> 2) & 0x8) | \
216 (((_pte).pte >> 8) << 4))
217
218#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) | \
219 (((off) & 0x8) << 2) | \
220 (((off) >> 4) << 8) | \
221 _PAGE_FILE })
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222#endif
223
224#endif
225
Sergei Shtylyov6ebba0e2006-05-27 20:43:04 +0400226#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
227#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
228#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
229#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
231#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
Sergei Shtylyov6ebba0e2006-05-27 20:43:04 +0400232#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233
234#endif /* _ASM_PGTABLE_32_H */