Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include "drmP.h" |
| 27 | #include "radeon_drm.h" |
| 28 | #include "radeon.h" |
| 29 | |
| 30 | #include "atom.h" |
| 31 | #include "atom-bits.h" |
| 32 | |
| 33 | /* from radeon_encoder.c */ |
| 34 | extern uint32_t |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 35 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, |
| 36 | uint8_t dac); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 37 | extern void radeon_link_encoder_connector(struct drm_device *dev); |
| 38 | extern void |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 39 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, |
Alex Deucher | 36868bd | 2011-01-06 21:19:21 -0500 | [diff] [blame] | 40 | uint32_t supported_device, u16 caps); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 41 | |
| 42 | /* from radeon_connector.c */ |
| 43 | extern void |
| 44 | radeon_add_atom_connector(struct drm_device *dev, |
| 45 | uint32_t connector_id, |
| 46 | uint32_t supported_device, |
| 47 | int connector_type, |
| 48 | struct radeon_i2c_bus_rec *i2c_bus, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 49 | uint32_t igp_lane_info, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 50 | uint16_t connector_object_id, |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 51 | struct radeon_hpd *hpd, |
| 52 | struct radeon_router *router); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 53 | |
| 54 | /* from radeon_legacy_encoder.c */ |
| 55 | extern void |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 56 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 57 | uint32_t supported_device); |
| 58 | |
Alex Deucher | e83753b | 2012-03-20 17:18:08 -0400 | [diff] [blame] | 59 | /* local */ |
| 60 | static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
| 61 | u16 voltage_id, u16 *voltage); |
| 62 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 63 | union atom_supported_devices { |
| 64 | struct _ATOM_SUPPORTED_DEVICES_INFO info; |
| 65 | struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; |
| 66 | struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; |
| 67 | }; |
| 68 | |
Alex Deucher | 21240f9 | 2011-11-21 12:41:21 -0500 | [diff] [blame] | 69 | static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev, |
| 70 | ATOM_GPIO_I2C_ASSIGMENT *gpio, |
| 71 | u8 index) |
| 72 | { |
| 73 | /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */ |
| 74 | if ((rdev->family == CHIP_R420) || |
| 75 | (rdev->family == CHIP_R423) || |
| 76 | (rdev->family == CHIP_RV410)) { |
| 77 | if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || |
| 78 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || |
| 79 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { |
| 80 | gpio->ucClkMaskShift = 0x19; |
| 81 | gpio->ucDataMaskShift = 0x18; |
| 82 | } |
| 83 | } |
| 84 | |
| 85 | /* some evergreen boards have bad data for this entry */ |
| 86 | if (ASIC_IS_DCE4(rdev)) { |
| 87 | if ((index == 7) && |
| 88 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && |
| 89 | (gpio->sucI2cId.ucAccess == 0)) { |
| 90 | gpio->sucI2cId.ucAccess = 0x97; |
| 91 | gpio->ucDataMaskShift = 8; |
| 92 | gpio->ucDataEnShift = 8; |
| 93 | gpio->ucDataY_Shift = 8; |
| 94 | gpio->ucDataA_Shift = 8; |
| 95 | } |
| 96 | } |
| 97 | |
| 98 | /* some DCE3 boards have bad data for this entry */ |
| 99 | if (ASIC_IS_DCE3(rdev)) { |
| 100 | if ((index == 4) && |
| 101 | (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && |
| 102 | (gpio->sucI2cId.ucAccess == 0x94)) |
| 103 | gpio->sucI2cId.ucAccess = 0x14; |
| 104 | } |
| 105 | } |
| 106 | |
| 107 | static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) |
| 108 | { |
| 109 | struct radeon_i2c_bus_rec i2c; |
| 110 | |
| 111 | memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); |
| 112 | |
| 113 | i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; |
| 114 | i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; |
| 115 | i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; |
| 116 | i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; |
| 117 | i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; |
| 118 | i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; |
| 119 | i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; |
| 120 | i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; |
| 121 | i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); |
| 122 | i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); |
| 123 | i2c.en_clk_mask = (1 << gpio->ucClkEnShift); |
| 124 | i2c.en_data_mask = (1 << gpio->ucDataEnShift); |
| 125 | i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); |
| 126 | i2c.y_data_mask = (1 << gpio->ucDataY_Shift); |
| 127 | i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); |
| 128 | i2c.a_data_mask = (1 << gpio->ucDataA_Shift); |
| 129 | |
| 130 | if (gpio->sucI2cId.sbfAccess.bfHW_Capable) |
| 131 | i2c.hw_capable = true; |
| 132 | else |
| 133 | i2c.hw_capable = false; |
| 134 | |
| 135 | if (gpio->sucI2cId.ucAccess == 0xa0) |
| 136 | i2c.mm_i2c = true; |
| 137 | else |
| 138 | i2c.mm_i2c = false; |
| 139 | |
| 140 | i2c.i2c_id = gpio->sucI2cId.ucAccess; |
| 141 | |
| 142 | if (i2c.mask_clk_reg) |
| 143 | i2c.valid = true; |
| 144 | else |
| 145 | i2c.valid = false; |
| 146 | |
| 147 | return i2c; |
| 148 | } |
| 149 | |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 150 | static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 151 | uint8_t id) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 152 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 153 | struct atom_context *ctx = rdev->mode_info.atom_context; |
Alex Deucher | 6a93cb2 | 2009-11-23 17:39:28 -0500 | [diff] [blame] | 154 | ATOM_GPIO_I2C_ASSIGMENT *gpio; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 155 | struct radeon_i2c_bus_rec i2c; |
| 156 | int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); |
| 157 | struct _ATOM_GPIO_I2C_INFO *i2c_info; |
Alex Deucher | 95beb69 | 2010-04-01 19:08:47 +0000 | [diff] [blame] | 158 | uint16_t data_offset, size; |
| 159 | int i, num_indices; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 160 | |
| 161 | memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); |
| 162 | i2c.valid = false; |
| 163 | |
Alex Deucher | 95beb69 | 2010-04-01 19:08:47 +0000 | [diff] [blame] | 164 | if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 165 | i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 166 | |
Alex Deucher | 95beb69 | 2010-04-01 19:08:47 +0000 | [diff] [blame] | 167 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
| 168 | sizeof(ATOM_GPIO_I2C_ASSIGMENT); |
| 169 | |
| 170 | for (i = 0; i < num_indices; i++) { |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 171 | gpio = &i2c_info->asGPIO_Info[i]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 172 | |
Alex Deucher | 21240f9 | 2011-11-21 12:41:21 -0500 | [diff] [blame] | 173 | radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); |
Alex Deucher | 3074adc | 2010-11-30 00:15:10 -0500 | [diff] [blame] | 174 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 175 | if (gpio->sucI2cId.ucAccess == id) { |
Alex Deucher | 21240f9 | 2011-11-21 12:41:21 -0500 | [diff] [blame] | 176 | i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 177 | break; |
| 178 | } |
Alex Deucher | d3f420d | 2009-12-08 14:30:49 -0500 | [diff] [blame] | 179 | } |
| 180 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 181 | |
| 182 | return i2c; |
| 183 | } |
| 184 | |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 185 | void radeon_atombios_i2c_init(struct radeon_device *rdev) |
| 186 | { |
| 187 | struct atom_context *ctx = rdev->mode_info.atom_context; |
| 188 | ATOM_GPIO_I2C_ASSIGMENT *gpio; |
| 189 | struct radeon_i2c_bus_rec i2c; |
| 190 | int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); |
| 191 | struct _ATOM_GPIO_I2C_INFO *i2c_info; |
| 192 | uint16_t data_offset, size; |
| 193 | int i, num_indices; |
| 194 | char stmp[32]; |
| 195 | |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 196 | if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { |
| 197 | i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); |
| 198 | |
| 199 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
| 200 | sizeof(ATOM_GPIO_I2C_ASSIGMENT); |
| 201 | |
| 202 | for (i = 0; i < num_indices; i++) { |
| 203 | gpio = &i2c_info->asGPIO_Info[i]; |
Alex Deucher | ea39302 | 2010-08-27 16:04:29 -0400 | [diff] [blame] | 204 | |
Alex Deucher | 21240f9 | 2011-11-21 12:41:21 -0500 | [diff] [blame] | 205 | radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); |
Alex Deucher | d724502 | 2011-11-21 12:10:14 -0500 | [diff] [blame] | 206 | |
Alex Deucher | 21240f9 | 2011-11-21 12:41:21 -0500 | [diff] [blame] | 207 | i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); |
Alex Deucher | ea39302 | 2010-08-27 16:04:29 -0400 | [diff] [blame] | 208 | |
Alex Deucher | 21240f9 | 2011-11-21 12:41:21 -0500 | [diff] [blame] | 209 | if (i2c.valid) { |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 210 | sprintf(stmp, "0x%x", i2c.i2c_id); |
| 211 | rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp); |
| 212 | } |
| 213 | } |
| 214 | } |
| 215 | } |
| 216 | |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 217 | static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 218 | u8 id) |
| 219 | { |
| 220 | struct atom_context *ctx = rdev->mode_info.atom_context; |
| 221 | struct radeon_gpio_rec gpio; |
| 222 | int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); |
| 223 | struct _ATOM_GPIO_PIN_LUT *gpio_info; |
| 224 | ATOM_GPIO_PIN_ASSIGNMENT *pin; |
| 225 | u16 data_offset, size; |
| 226 | int i, num_indices; |
| 227 | |
| 228 | memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); |
| 229 | gpio.valid = false; |
| 230 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 231 | if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { |
| 232 | gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 233 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 234 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
| 235 | sizeof(ATOM_GPIO_PIN_ASSIGNMENT); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 236 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 237 | for (i = 0; i < num_indices; i++) { |
| 238 | pin = &gpio_info->asGPIO_Pin[i]; |
| 239 | if (id == pin->ucGPIO_ID) { |
| 240 | gpio.id = pin->ucGPIO_ID; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 241 | gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 242 | gpio.mask = (1 << pin->ucGpioPinBitShift); |
| 243 | gpio.valid = true; |
| 244 | break; |
| 245 | } |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 246 | } |
| 247 | } |
| 248 | |
| 249 | return gpio; |
| 250 | } |
| 251 | |
| 252 | static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, |
| 253 | struct radeon_gpio_rec *gpio) |
| 254 | { |
| 255 | struct radeon_hpd hpd; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 256 | u32 reg; |
| 257 | |
Jean Delvare | 1d978da | 2010-08-15 14:11:24 +0200 | [diff] [blame] | 258 | memset(&hpd, 0, sizeof(struct radeon_hpd)); |
| 259 | |
Alex Deucher | 82d118e | 2012-03-20 17:18:01 -0400 | [diff] [blame] | 260 | if (ASIC_IS_DCE6(rdev)) |
| 261 | reg = SI_DC_GPIO_HPD_A; |
| 262 | else if (ASIC_IS_DCE4(rdev)) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 263 | reg = EVERGREEN_DC_GPIO_HPD_A; |
| 264 | else |
| 265 | reg = AVIVO_DC_GPIO_HPD_A; |
| 266 | |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 267 | hpd.gpio = *gpio; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 268 | if (gpio->reg == reg) { |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 269 | switch(gpio->mask) { |
| 270 | case (1 << 0): |
| 271 | hpd.hpd = RADEON_HPD_1; |
| 272 | break; |
| 273 | case (1 << 8): |
| 274 | hpd.hpd = RADEON_HPD_2; |
| 275 | break; |
| 276 | case (1 << 16): |
| 277 | hpd.hpd = RADEON_HPD_3; |
| 278 | break; |
| 279 | case (1 << 24): |
| 280 | hpd.hpd = RADEON_HPD_4; |
| 281 | break; |
| 282 | case (1 << 26): |
| 283 | hpd.hpd = RADEON_HPD_5; |
| 284 | break; |
| 285 | case (1 << 28): |
| 286 | hpd.hpd = RADEON_HPD_6; |
| 287 | break; |
| 288 | default: |
| 289 | hpd.hpd = RADEON_HPD_NONE; |
| 290 | break; |
| 291 | } |
| 292 | } else |
| 293 | hpd.hpd = RADEON_HPD_NONE; |
| 294 | return hpd; |
| 295 | } |
| 296 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 297 | static bool radeon_atom_apply_quirks(struct drm_device *dev, |
| 298 | uint32_t supported_device, |
| 299 | int *connector_type, |
Alex Deucher | 848577e | 2009-07-08 16:15:30 -0400 | [diff] [blame] | 300 | struct radeon_i2c_bus_rec *i2c_bus, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 301 | uint16_t *line_mux, |
| 302 | struct radeon_hpd *hpd) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 303 | { |
| 304 | |
| 305 | /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ |
| 306 | if ((dev->pdev->device == 0x791e) && |
| 307 | (dev->pdev->subsystem_vendor == 0x1043) && |
| 308 | (dev->pdev->subsystem_device == 0x826d)) { |
| 309 | if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && |
| 310 | (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) |
| 311 | *connector_type = DRM_MODE_CONNECTOR_DVID; |
| 312 | } |
| 313 | |
Alex Deucher | c86a903 | 2010-02-18 14:14:58 -0500 | [diff] [blame] | 314 | /* Asrock RS600 board lists the DVI port as HDMI */ |
| 315 | if ((dev->pdev->device == 0x7941) && |
| 316 | (dev->pdev->subsystem_vendor == 0x1849) && |
| 317 | (dev->pdev->subsystem_device == 0x7941)) { |
| 318 | if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && |
| 319 | (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) |
| 320 | *connector_type = DRM_MODE_CONNECTOR_DVID; |
| 321 | } |
| 322 | |
Alex Deucher | f36fce0 | 2010-09-27 11:33:00 -0400 | [diff] [blame] | 323 | /* MSI K9A2GM V2/V3 board has no HDMI or DVI */ |
| 324 | if ((dev->pdev->device == 0x796e) && |
| 325 | (dev->pdev->subsystem_vendor == 0x1462) && |
| 326 | (dev->pdev->subsystem_device == 0x7302)) { |
| 327 | if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) || |
| 328 | (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) |
| 329 | return false; |
| 330 | } |
| 331 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 332 | /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ |
| 333 | if ((dev->pdev->device == 0x7941) && |
| 334 | (dev->pdev->subsystem_vendor == 0x147b) && |
| 335 | (dev->pdev->subsystem_device == 0x2412)) { |
| 336 | if (*connector_type == DRM_MODE_CONNECTOR_DVII) |
| 337 | return false; |
| 338 | } |
| 339 | |
| 340 | /* Falcon NW laptop lists vga ddc line for LVDS */ |
| 341 | if ((dev->pdev->device == 0x5653) && |
| 342 | (dev->pdev->subsystem_vendor == 0x1462) && |
| 343 | (dev->pdev->subsystem_device == 0x0291)) { |
Alex Deucher | 848577e | 2009-07-08 16:15:30 -0400 | [diff] [blame] | 344 | if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 345 | i2c_bus->valid = false; |
Alex Deucher | 848577e | 2009-07-08 16:15:30 -0400 | [diff] [blame] | 346 | *line_mux = 53; |
| 347 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 348 | } |
| 349 | |
Alex Deucher | 4e3f9b78 | 2009-12-01 14:49:50 -0500 | [diff] [blame] | 350 | /* HIS X1300 is DVI+VGA, not DVI+DVI */ |
| 351 | if ((dev->pdev->device == 0x7146) && |
| 352 | (dev->pdev->subsystem_vendor == 0x17af) && |
| 353 | (dev->pdev->subsystem_device == 0x2058)) { |
| 354 | if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) |
| 355 | return false; |
| 356 | } |
| 357 | |
Dave Airlie | aa1a750 | 2009-12-04 11:51:34 +1000 | [diff] [blame] | 358 | /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ |
| 359 | if ((dev->pdev->device == 0x7142) && |
| 360 | (dev->pdev->subsystem_vendor == 0x1458) && |
| 361 | (dev->pdev->subsystem_device == 0x2134)) { |
| 362 | if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) |
| 363 | return false; |
| 364 | } |
| 365 | |
| 366 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 367 | /* Funky macbooks */ |
| 368 | if ((dev->pdev->device == 0x71C5) && |
| 369 | (dev->pdev->subsystem_vendor == 0x106b) && |
| 370 | (dev->pdev->subsystem_device == 0x0080)) { |
| 371 | if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || |
| 372 | (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) |
| 373 | return false; |
Alex Deucher | e1e8a5d | 2010-03-26 17:14:37 -0400 | [diff] [blame] | 374 | if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) |
| 375 | *line_mux = 0x90; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 376 | } |
| 377 | |
Alex Deucher | be23da8 | 2011-01-18 18:26:11 +0000 | [diff] [blame] | 378 | /* mac rv630, rv730, others */ |
| 379 | if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) && |
| 380 | (*connector_type == DRM_MODE_CONNECTOR_DVII)) { |
| 381 | *connector_type = DRM_MODE_CONNECTOR_9PinDIN; |
| 382 | *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1; |
Alex Deucher | f598aa7 | 2011-01-04 00:43:39 -0500 | [diff] [blame] | 383 | } |
| 384 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 385 | /* ASUS HD 3600 XT board lists the DVI port as HDMI */ |
| 386 | if ((dev->pdev->device == 0x9598) && |
| 387 | (dev->pdev->subsystem_vendor == 0x1043) && |
| 388 | (dev->pdev->subsystem_device == 0x01da)) { |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 389 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
Alex Deucher | d42571e | 2009-09-11 15:27:14 -0400 | [diff] [blame] | 390 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 391 | } |
| 392 | } |
| 393 | |
Alex Deucher | e153b70 | 2010-07-20 18:07:22 -0400 | [diff] [blame] | 394 | /* ASUS HD 3600 board lists the DVI port as HDMI */ |
| 395 | if ((dev->pdev->device == 0x9598) && |
| 396 | (dev->pdev->subsystem_vendor == 0x1043) && |
| 397 | (dev->pdev->subsystem_device == 0x01e4)) { |
| 398 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
| 399 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
| 400 | } |
| 401 | } |
| 402 | |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 403 | /* ASUS HD 3450 board lists the DVI port as HDMI */ |
| 404 | if ((dev->pdev->device == 0x95C5) && |
| 405 | (dev->pdev->subsystem_vendor == 0x1043) && |
| 406 | (dev->pdev->subsystem_device == 0x01e2)) { |
| 407 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
Alex Deucher | d42571e | 2009-09-11 15:27:14 -0400 | [diff] [blame] | 408 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 409 | } |
| 410 | } |
| 411 | |
| 412 | /* some BIOSes seem to report DAC on HDMI - usually this is a board with |
| 413 | * HDMI + VGA reporting as HDMI |
| 414 | */ |
| 415 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
| 416 | if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { |
| 417 | *connector_type = DRM_MODE_CONNECTOR_VGA; |
| 418 | *line_mux = 0; |
| 419 | } |
| 420 | } |
| 421 | |
Alex Deucher | 4f87af4 | 2011-05-04 11:41:47 -0400 | [diff] [blame] | 422 | /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port |
Alex Deucher | 2f299d5 | 2011-01-04 17:42:20 -0500 | [diff] [blame] | 423 | * on the laptop and a DVI port on the docking station and |
| 424 | * both share the same encoder, hpd pin, and ddc line. |
| 425 | * So while the bios table is technically correct, |
| 426 | * we drop the DVI port here since xrandr has no concept of |
| 427 | * encoders and will try and drive both connectors |
| 428 | * with different crtcs which isn't possible on the hardware |
| 429 | * side and leaves no crtcs for LVDS or VGA. |
| 430 | */ |
Alex Deucher | 4f87af4 | 2011-05-04 11:41:47 -0400 | [diff] [blame] | 431 | if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) && |
Alex Deucher | 3e5f8ff | 2009-11-17 17:12:10 -0500 | [diff] [blame] | 432 | (dev->pdev->subsystem_vendor == 0x1025) && |
| 433 | (dev->pdev->subsystem_device == 0x013c)) { |
| 434 | if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && |
Alex Deucher | 9ea2c4b | 2010-08-06 00:27:44 -0400 | [diff] [blame] | 435 | (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) { |
Alex Deucher | 2f299d5 | 2011-01-04 17:42:20 -0500 | [diff] [blame] | 436 | /* actually it's a DVI-D port not DVI-I */ |
Alex Deucher | 3e5f8ff | 2009-11-17 17:12:10 -0500 | [diff] [blame] | 437 | *connector_type = DRM_MODE_CONNECTOR_DVID; |
Alex Deucher | 2f299d5 | 2011-01-04 17:42:20 -0500 | [diff] [blame] | 438 | return false; |
Alex Deucher | 9ea2c4b | 2010-08-06 00:27:44 -0400 | [diff] [blame] | 439 | } |
Alex Deucher | 3e5f8ff | 2009-11-17 17:12:10 -0500 | [diff] [blame] | 440 | } |
| 441 | |
Dave Airlie | efa8450 | 2010-02-09 09:06:00 +1000 | [diff] [blame] | 442 | /* XFX Pine Group device rv730 reports no VGA DDC lines |
| 443 | * even though they are wired up to record 0x93 |
| 444 | */ |
| 445 | if ((dev->pdev->device == 0x9498) && |
| 446 | (dev->pdev->subsystem_vendor == 0x1682) && |
| 447 | (dev->pdev->subsystem_device == 0x2452)) { |
| 448 | struct radeon_device *rdev = dev->dev_private; |
| 449 | *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); |
| 450 | } |
Alex Deucher | 4c1b2d2 | 2012-03-16 12:22:10 -0400 | [diff] [blame] | 451 | |
| 452 | /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ |
| 453 | if ((dev->pdev->device == 0x9802) && |
| 454 | (dev->pdev->subsystem_vendor == 0x1734) && |
| 455 | (dev->pdev->subsystem_device == 0x11bd)) { |
| 456 | if (*connector_type == DRM_MODE_CONNECTOR_VGA) { |
| 457 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
| 458 | *line_mux = 0x3103; |
| 459 | } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) { |
| 460 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
| 461 | } |
| 462 | } |
| 463 | |
| 464 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 465 | return true; |
| 466 | } |
| 467 | |
| 468 | const int supported_devices_connector_convert[] = { |
| 469 | DRM_MODE_CONNECTOR_Unknown, |
| 470 | DRM_MODE_CONNECTOR_VGA, |
| 471 | DRM_MODE_CONNECTOR_DVII, |
| 472 | DRM_MODE_CONNECTOR_DVID, |
| 473 | DRM_MODE_CONNECTOR_DVIA, |
| 474 | DRM_MODE_CONNECTOR_SVIDEO, |
| 475 | DRM_MODE_CONNECTOR_Composite, |
| 476 | DRM_MODE_CONNECTOR_LVDS, |
| 477 | DRM_MODE_CONNECTOR_Unknown, |
| 478 | DRM_MODE_CONNECTOR_Unknown, |
| 479 | DRM_MODE_CONNECTOR_HDMIA, |
| 480 | DRM_MODE_CONNECTOR_HDMIB, |
| 481 | DRM_MODE_CONNECTOR_Unknown, |
| 482 | DRM_MODE_CONNECTOR_Unknown, |
| 483 | DRM_MODE_CONNECTOR_9PinDIN, |
| 484 | DRM_MODE_CONNECTOR_DisplayPort |
| 485 | }; |
| 486 | |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 487 | const uint16_t supported_devices_connector_object_id_convert[] = { |
| 488 | CONNECTOR_OBJECT_ID_NONE, |
| 489 | CONNECTOR_OBJECT_ID_VGA, |
| 490 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ |
| 491 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ |
| 492 | CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ |
| 493 | CONNECTOR_OBJECT_ID_COMPOSITE, |
| 494 | CONNECTOR_OBJECT_ID_SVIDEO, |
| 495 | CONNECTOR_OBJECT_ID_LVDS, |
| 496 | CONNECTOR_OBJECT_ID_9PIN_DIN, |
| 497 | CONNECTOR_OBJECT_ID_9PIN_DIN, |
| 498 | CONNECTOR_OBJECT_ID_DISPLAYPORT, |
| 499 | CONNECTOR_OBJECT_ID_HDMI_TYPE_A, |
| 500 | CONNECTOR_OBJECT_ID_HDMI_TYPE_B, |
| 501 | CONNECTOR_OBJECT_ID_SVIDEO |
| 502 | }; |
| 503 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 504 | const int object_connector_convert[] = { |
| 505 | DRM_MODE_CONNECTOR_Unknown, |
| 506 | DRM_MODE_CONNECTOR_DVII, |
| 507 | DRM_MODE_CONNECTOR_DVII, |
| 508 | DRM_MODE_CONNECTOR_DVID, |
| 509 | DRM_MODE_CONNECTOR_DVID, |
| 510 | DRM_MODE_CONNECTOR_VGA, |
| 511 | DRM_MODE_CONNECTOR_Composite, |
| 512 | DRM_MODE_CONNECTOR_SVIDEO, |
| 513 | DRM_MODE_CONNECTOR_Unknown, |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 514 | DRM_MODE_CONNECTOR_Unknown, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 515 | DRM_MODE_CONNECTOR_9PinDIN, |
| 516 | DRM_MODE_CONNECTOR_Unknown, |
| 517 | DRM_MODE_CONNECTOR_HDMIA, |
| 518 | DRM_MODE_CONNECTOR_HDMIB, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 519 | DRM_MODE_CONNECTOR_LVDS, |
| 520 | DRM_MODE_CONNECTOR_9PinDIN, |
| 521 | DRM_MODE_CONNECTOR_Unknown, |
| 522 | DRM_MODE_CONNECTOR_Unknown, |
| 523 | DRM_MODE_CONNECTOR_Unknown, |
Alex Deucher | 196c58d | 2010-01-07 14:22:32 -0500 | [diff] [blame] | 524 | DRM_MODE_CONNECTOR_DisplayPort, |
| 525 | DRM_MODE_CONNECTOR_eDP, |
| 526 | DRM_MODE_CONNECTOR_Unknown |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 527 | }; |
| 528 | |
| 529 | bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) |
| 530 | { |
| 531 | struct radeon_device *rdev = dev->dev_private; |
| 532 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 533 | struct atom_context *ctx = mode_info->atom_context; |
| 534 | int index = GetIndexIntoMasterTable(DATA, Object_Header); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 535 | u16 size, data_offset; |
| 536 | u8 frev, crev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 537 | ATOM_CONNECTOR_OBJECT_TABLE *con_obj; |
Alex Deucher | 36868bd | 2011-01-06 21:19:21 -0500 | [diff] [blame] | 538 | ATOM_ENCODER_OBJECT_TABLE *enc_obj; |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 539 | ATOM_OBJECT_TABLE *router_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 540 | ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; |
| 541 | ATOM_OBJECT_HEADER *obj_header; |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 542 | int i, j, k, path_size, device_support; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 543 | int connector_type; |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 544 | u16 igp_lane_info, conn_id, connector_object_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 545 | struct radeon_i2c_bus_rec ddc_bus; |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 546 | struct radeon_router router; |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 547 | struct radeon_gpio_rec gpio; |
| 548 | struct radeon_hpd hpd; |
| 549 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 550 | if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 551 | return false; |
| 552 | |
| 553 | if (crev < 2) |
| 554 | return false; |
| 555 | |
| 556 | obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); |
| 557 | path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) |
| 558 | (ctx->bios + data_offset + |
| 559 | le16_to_cpu(obj_header->usDisplayPathTableOffset)); |
| 560 | con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) |
| 561 | (ctx->bios + data_offset + |
| 562 | le16_to_cpu(obj_header->usConnectorObjectTableOffset)); |
Alex Deucher | 36868bd | 2011-01-06 21:19:21 -0500 | [diff] [blame] | 563 | enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) |
| 564 | (ctx->bios + data_offset + |
| 565 | le16_to_cpu(obj_header->usEncoderObjectTableOffset)); |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 566 | router_obj = (ATOM_OBJECT_TABLE *) |
| 567 | (ctx->bios + data_offset + |
| 568 | le16_to_cpu(obj_header->usRouterObjectTableOffset)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 569 | device_support = le16_to_cpu(obj_header->usDeviceSupport); |
| 570 | |
| 571 | path_size = 0; |
| 572 | for (i = 0; i < path_obj->ucNumOfDispPath; i++) { |
| 573 | uint8_t *addr = (uint8_t *) path_obj->asDispPath; |
| 574 | ATOM_DISPLAY_OBJECT_PATH *path; |
| 575 | addr += path_size; |
| 576 | path = (ATOM_DISPLAY_OBJECT_PATH *) addr; |
| 577 | path_size += le16_to_cpu(path->usSize); |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 578 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 579 | if (device_support & le16_to_cpu(path->usDeviceTag)) { |
| 580 | uint8_t con_obj_id, con_obj_num, con_obj_type; |
| 581 | |
| 582 | con_obj_id = |
| 583 | (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) |
| 584 | >> OBJECT_ID_SHIFT; |
| 585 | con_obj_num = |
| 586 | (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) |
| 587 | >> ENUM_ID_SHIFT; |
| 588 | con_obj_type = |
| 589 | (le16_to_cpu(path->usConnObjectId) & |
| 590 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; |
| 591 | |
Dave Airlie | 4bbd497 | 2009-09-25 08:56:12 +1000 | [diff] [blame] | 592 | /* TODO CV support */ |
| 593 | if (le16_to_cpu(path->usDeviceTag) == |
| 594 | ATOM_DEVICE_CV_SUPPORT) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 595 | continue; |
| 596 | |
Alex Deucher | ee59f2b | 2009-11-05 13:11:46 -0500 | [diff] [blame] | 597 | /* IGP chips */ |
| 598 | if ((rdev->flags & RADEON_IS_IGP) && |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 599 | (con_obj_id == |
| 600 | CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { |
| 601 | uint16_t igp_offset = 0; |
| 602 | ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; |
| 603 | |
| 604 | index = |
| 605 | GetIndexIntoMasterTable(DATA, |
| 606 | IntegratedSystemInfo); |
| 607 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 608 | if (atom_parse_data_header(ctx, index, &size, &frev, |
| 609 | &crev, &igp_offset)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 610 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 611 | if (crev >= 2) { |
| 612 | igp_obj = |
| 613 | (ATOM_INTEGRATED_SYSTEM_INFO_V2 |
| 614 | *) (ctx->bios + igp_offset); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 615 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 616 | if (igp_obj) { |
| 617 | uint32_t slot_config, ct; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 618 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 619 | if (con_obj_num == 1) |
| 620 | slot_config = |
| 621 | igp_obj-> |
| 622 | ulDDISlot1Config; |
| 623 | else |
| 624 | slot_config = |
| 625 | igp_obj-> |
| 626 | ulDDISlot2Config; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 627 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 628 | ct = (slot_config >> 16) & 0xff; |
| 629 | connector_type = |
| 630 | object_connector_convert |
| 631 | [ct]; |
| 632 | connector_object_id = ct; |
| 633 | igp_lane_info = |
| 634 | slot_config & 0xffff; |
| 635 | } else |
| 636 | continue; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 637 | } else |
| 638 | continue; |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 639 | } else { |
| 640 | igp_lane_info = 0; |
| 641 | connector_type = |
| 642 | object_connector_convert[con_obj_id]; |
| 643 | connector_object_id = con_obj_id; |
| 644 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 645 | } else { |
| 646 | igp_lane_info = 0; |
| 647 | connector_type = |
| 648 | object_connector_convert[con_obj_id]; |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 649 | connector_object_id = con_obj_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 650 | } |
| 651 | |
| 652 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
| 653 | continue; |
| 654 | |
Tyson Whitehead | bdd91b2 | 2010-11-08 16:08:30 +0000 | [diff] [blame] | 655 | router.ddc_valid = false; |
| 656 | router.cd_valid = false; |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 657 | for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { |
| 658 | uint8_t grph_obj_id, grph_obj_num, grph_obj_type; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 659 | |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 660 | grph_obj_id = |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 661 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
| 662 | OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 663 | grph_obj_num = |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 664 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
| 665 | ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 666 | grph_obj_type = |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 667 | (le16_to_cpu(path->usGraphicObjIds[j]) & |
| 668 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; |
| 669 | |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 670 | if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { |
Alex Deucher | 36868bd | 2011-01-06 21:19:21 -0500 | [diff] [blame] | 671 | for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { |
| 672 | u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); |
| 673 | if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { |
| 674 | ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) |
| 675 | (ctx->bios + data_offset + |
| 676 | le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); |
| 677 | ATOM_ENCODER_CAP_RECORD *cap_record; |
| 678 | u16 caps = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 679 | |
John Lindgren | 97ea530 | 2011-03-24 23:28:31 +0000 | [diff] [blame] | 680 | while (record->ucRecordSize > 0 && |
| 681 | record->ucRecordType > 0 && |
Alex Deucher | 36868bd | 2011-01-06 21:19:21 -0500 | [diff] [blame] | 682 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { |
| 683 | switch (record->ucRecordType) { |
| 684 | case ATOM_ENCODER_CAP_RECORD_TYPE: |
| 685 | cap_record =(ATOM_ENCODER_CAP_RECORD *) |
| 686 | record; |
| 687 | caps = le16_to_cpu(cap_record->usEncoderCap); |
| 688 | break; |
| 689 | } |
| 690 | record = (ATOM_COMMON_RECORD_HEADER *) |
| 691 | ((char *)record + record->ucRecordSize); |
| 692 | } |
| 693 | radeon_add_atom_encoder(dev, |
| 694 | encoder_obj, |
| 695 | le16_to_cpu |
| 696 | (path-> |
| 697 | usDeviceTag), |
| 698 | caps); |
| 699 | } |
| 700 | } |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 701 | } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 702 | for (k = 0; k < router_obj->ucNumberOfObjects; k++) { |
Tyson Whitehead | bdd91b2 | 2010-11-08 16:08:30 +0000 | [diff] [blame] | 703 | u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 704 | if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { |
| 705 | ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) |
| 706 | (ctx->bios + data_offset + |
| 707 | le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); |
| 708 | ATOM_I2C_RECORD *i2c_record; |
| 709 | ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; |
| 710 | ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; |
Alex Deucher | fb939df | 2010-11-08 16:08:29 +0000 | [diff] [blame] | 711 | ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 712 | ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = |
| 713 | (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) |
| 714 | (ctx->bios + data_offset + |
| 715 | le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); |
| 716 | int enum_id; |
| 717 | |
| 718 | router.router_id = router_obj_id; |
| 719 | for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst; |
| 720 | enum_id++) { |
| 721 | if (le16_to_cpu(path->usConnObjectId) == |
| 722 | le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id])) |
| 723 | break; |
| 724 | } |
| 725 | |
John Lindgren | 97ea530 | 2011-03-24 23:28:31 +0000 | [diff] [blame] | 726 | while (record->ucRecordSize > 0 && |
| 727 | record->ucRecordType > 0 && |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 728 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { |
| 729 | switch (record->ucRecordType) { |
| 730 | case ATOM_I2C_RECORD_TYPE: |
| 731 | i2c_record = |
| 732 | (ATOM_I2C_RECORD *) |
| 733 | record; |
| 734 | i2c_config = |
| 735 | (ATOM_I2C_ID_CONFIG_ACCESS *) |
| 736 | &i2c_record->sucI2cId; |
| 737 | router.i2c_info = |
| 738 | radeon_lookup_i2c_gpio(rdev, |
| 739 | i2c_config-> |
| 740 | ucAccess); |
| 741 | router.i2c_addr = i2c_record->ucI2CAddr >> 1; |
| 742 | break; |
| 743 | case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: |
| 744 | ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) |
| 745 | record; |
Alex Deucher | fb939df | 2010-11-08 16:08:29 +0000 | [diff] [blame] | 746 | router.ddc_valid = true; |
| 747 | router.ddc_mux_type = ddc_path->ucMuxType; |
| 748 | router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; |
| 749 | router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; |
| 750 | break; |
| 751 | case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: |
| 752 | cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) |
| 753 | record; |
| 754 | router.cd_valid = true; |
| 755 | router.cd_mux_type = cd_path->ucMuxType; |
| 756 | router.cd_mux_control_pin = cd_path->ucMuxControlPin; |
| 757 | router.cd_mux_state = cd_path->ucMuxState[enum_id]; |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 758 | break; |
| 759 | } |
| 760 | record = (ATOM_COMMON_RECORD_HEADER *) |
| 761 | ((char *)record + record->ucRecordSize); |
| 762 | } |
| 763 | } |
| 764 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 765 | } |
| 766 | } |
| 767 | |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 768 | /* look up gpio for ddc, hpd */ |
Alex Deucher | 2bfcc0f | 2010-05-18 19:26:46 -0400 | [diff] [blame] | 769 | ddc_bus.valid = false; |
| 770 | hpd.hpd = RADEON_HPD_NONE; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 771 | if ((le16_to_cpu(path->usDeviceTag) & |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 772 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 773 | for (j = 0; j < con_obj->ucNumberOfObjects; j++) { |
| 774 | if (le16_to_cpu(path->usConnObjectId) == |
| 775 | le16_to_cpu(con_obj->asObjects[j]. |
| 776 | usObjectID)) { |
| 777 | ATOM_COMMON_RECORD_HEADER |
| 778 | *record = |
| 779 | (ATOM_COMMON_RECORD_HEADER |
| 780 | *) |
| 781 | (ctx->bios + data_offset + |
| 782 | le16_to_cpu(con_obj-> |
| 783 | asObjects[j]. |
| 784 | usRecordOffset)); |
| 785 | ATOM_I2C_RECORD *i2c_record; |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 786 | ATOM_HPD_INT_RECORD *hpd_record; |
Alex Deucher | d3f420d | 2009-12-08 14:30:49 -0500 | [diff] [blame] | 787 | ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; |
Alex Deucher | 6a93cb2 | 2009-11-23 17:39:28 -0500 | [diff] [blame] | 788 | |
John Lindgren | 97ea530 | 2011-03-24 23:28:31 +0000 | [diff] [blame] | 789 | while (record->ucRecordSize > 0 && |
| 790 | record->ucRecordType > 0 && |
| 791 | record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 792 | switch (record->ucRecordType) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 793 | case ATOM_I2C_RECORD_TYPE: |
| 794 | i2c_record = |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 795 | (ATOM_I2C_RECORD *) |
| 796 | record; |
Alex Deucher | d3f420d | 2009-12-08 14:30:49 -0500 | [diff] [blame] | 797 | i2c_config = |
| 798 | (ATOM_I2C_ID_CONFIG_ACCESS *) |
| 799 | &i2c_record->sucI2cId; |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 800 | ddc_bus = radeon_lookup_i2c_gpio(rdev, |
Alex Deucher | d3f420d | 2009-12-08 14:30:49 -0500 | [diff] [blame] | 801 | i2c_config-> |
| 802 | ucAccess); |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 803 | break; |
| 804 | case ATOM_HPD_INT_RECORD_TYPE: |
| 805 | hpd_record = |
| 806 | (ATOM_HPD_INT_RECORD *) |
| 807 | record; |
| 808 | gpio = radeon_lookup_gpio(rdev, |
| 809 | hpd_record->ucHPDIntGPIOID); |
| 810 | hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); |
| 811 | hpd.plugged_state = hpd_record->ucPlugged_PinState; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 812 | break; |
| 813 | } |
| 814 | record = |
| 815 | (ATOM_COMMON_RECORD_HEADER |
| 816 | *) ((char *)record |
| 817 | + |
| 818 | record-> |
| 819 | ucRecordSize); |
| 820 | } |
| 821 | break; |
| 822 | } |
| 823 | } |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 824 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 825 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 826 | /* needed for aux chan transactions */ |
Alex Deucher | 8e36ed0 | 2010-05-18 19:26:47 -0400 | [diff] [blame] | 827 | ddc_bus.hpd = hpd.hpd; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 828 | |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 829 | conn_id = le16_to_cpu(path->usConnObjectId); |
| 830 | |
| 831 | if (!radeon_atom_apply_quirks |
| 832 | (dev, le16_to_cpu(path->usDeviceTag), &connector_type, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 833 | &ddc_bus, &conn_id, &hpd)) |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 834 | continue; |
| 835 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 836 | radeon_add_atom_connector(dev, |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 837 | conn_id, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 838 | le16_to_cpu(path-> |
| 839 | usDeviceTag), |
| 840 | connector_type, &ddc_bus, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 841 | igp_lane_info, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 842 | connector_object_id, |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 843 | &hpd, |
| 844 | &router); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 845 | |
| 846 | } |
| 847 | } |
| 848 | |
| 849 | radeon_link_encoder_connector(dev); |
| 850 | |
| 851 | return true; |
| 852 | } |
| 853 | |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 854 | static uint16_t atombios_get_connector_object_id(struct drm_device *dev, |
| 855 | int connector_type, |
| 856 | uint16_t devices) |
| 857 | { |
| 858 | struct radeon_device *rdev = dev->dev_private; |
| 859 | |
| 860 | if (rdev->flags & RADEON_IS_IGP) { |
| 861 | return supported_devices_connector_object_id_convert |
| 862 | [connector_type]; |
| 863 | } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || |
| 864 | (connector_type == DRM_MODE_CONNECTOR_DVID)) && |
| 865 | (devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
| 866 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 867 | struct atom_context *ctx = mode_info->atom_context; |
| 868 | int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); |
| 869 | uint16_t size, data_offset; |
| 870 | uint8_t frev, crev; |
| 871 | ATOM_XTMDS_INFO *xtmds; |
| 872 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 873 | if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { |
| 874 | xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 875 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 876 | if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { |
| 877 | if (connector_type == DRM_MODE_CONNECTOR_DVII) |
| 878 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; |
| 879 | else |
| 880 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; |
| 881 | } else { |
| 882 | if (connector_type == DRM_MODE_CONNECTOR_DVII) |
| 883 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
| 884 | else |
| 885 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; |
| 886 | } |
| 887 | } else |
| 888 | return supported_devices_connector_object_id_convert |
| 889 | [connector_type]; |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 890 | } else { |
| 891 | return supported_devices_connector_object_id_convert |
| 892 | [connector_type]; |
| 893 | } |
| 894 | } |
| 895 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 896 | struct bios_connector { |
| 897 | bool valid; |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 898 | uint16_t line_mux; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 899 | uint16_t devices; |
| 900 | int connector_type; |
| 901 | struct radeon_i2c_bus_rec ddc_bus; |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 902 | struct radeon_hpd hpd; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 903 | }; |
| 904 | |
| 905 | bool radeon_get_atom_connector_info_from_supported_devices_table(struct |
| 906 | drm_device |
| 907 | *dev) |
| 908 | { |
| 909 | struct radeon_device *rdev = dev->dev_private; |
| 910 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 911 | struct atom_context *ctx = mode_info->atom_context; |
| 912 | int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); |
| 913 | uint16_t size, data_offset; |
| 914 | uint8_t frev, crev; |
| 915 | uint16_t device_support; |
| 916 | uint8_t dac; |
| 917 | union atom_supported_devices *supported_devices; |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 918 | int i, j, max_device; |
Prarit Bhargava | f49d273 | 2010-05-24 10:24:07 +1000 | [diff] [blame] | 919 | struct bios_connector *bios_connectors; |
| 920 | size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 921 | struct radeon_router router; |
| 922 | |
Alex Deucher | fb939df | 2010-11-08 16:08:29 +0000 | [diff] [blame] | 923 | router.ddc_valid = false; |
| 924 | router.cd_valid = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 925 | |
Prarit Bhargava | f49d273 | 2010-05-24 10:24:07 +1000 | [diff] [blame] | 926 | bios_connectors = kzalloc(bc_size, GFP_KERNEL); |
| 927 | if (!bios_connectors) |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 928 | return false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 929 | |
Prarit Bhargava | f49d273 | 2010-05-24 10:24:07 +1000 | [diff] [blame] | 930 | if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, |
| 931 | &data_offset)) { |
| 932 | kfree(bios_connectors); |
| 933 | return false; |
| 934 | } |
| 935 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 936 | supported_devices = |
| 937 | (union atom_supported_devices *)(ctx->bios + data_offset); |
| 938 | |
| 939 | device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); |
| 940 | |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 941 | if (frev > 1) |
| 942 | max_device = ATOM_MAX_SUPPORTED_DEVICE; |
| 943 | else |
| 944 | max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; |
| 945 | |
| 946 | for (i = 0; i < max_device; i++) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 947 | ATOM_CONNECTOR_INFO_I2C ci = |
| 948 | supported_devices->info.asConnInfo[i]; |
| 949 | |
| 950 | bios_connectors[i].valid = false; |
| 951 | |
| 952 | if (!(device_support & (1 << i))) { |
| 953 | continue; |
| 954 | } |
| 955 | |
| 956 | if (i == ATOM_DEVICE_CV_INDEX) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 957 | DRM_DEBUG_KMS("Skipping Component Video\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 958 | continue; |
| 959 | } |
| 960 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 961 | bios_connectors[i].connector_type = |
| 962 | supported_devices_connector_convert[ci.sucConnectorInfo. |
| 963 | sbfAccess. |
| 964 | bfConnectorType]; |
| 965 | |
| 966 | if (bios_connectors[i].connector_type == |
| 967 | DRM_MODE_CONNECTOR_Unknown) |
| 968 | continue; |
| 969 | |
| 970 | dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; |
| 971 | |
Alex Deucher | d3f420d | 2009-12-08 14:30:49 -0500 | [diff] [blame] | 972 | bios_connectors[i].line_mux = |
| 973 | ci.sucI2cId.ucAccess; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 974 | |
| 975 | /* give tv unique connector ids */ |
| 976 | if (i == ATOM_DEVICE_TV1_INDEX) { |
| 977 | bios_connectors[i].ddc_bus.valid = false; |
| 978 | bios_connectors[i].line_mux = 50; |
| 979 | } else if (i == ATOM_DEVICE_TV2_INDEX) { |
| 980 | bios_connectors[i].ddc_bus.valid = false; |
| 981 | bios_connectors[i].line_mux = 51; |
| 982 | } else if (i == ATOM_DEVICE_CV_INDEX) { |
| 983 | bios_connectors[i].ddc_bus.valid = false; |
| 984 | bios_connectors[i].line_mux = 52; |
| 985 | } else |
| 986 | bios_connectors[i].ddc_bus = |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 987 | radeon_lookup_i2c_gpio(rdev, |
| 988 | bios_connectors[i].line_mux); |
| 989 | |
| 990 | if ((crev > 1) && (frev > 1)) { |
| 991 | u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; |
| 992 | switch (isb) { |
| 993 | case 0x4: |
| 994 | bios_connectors[i].hpd.hpd = RADEON_HPD_1; |
| 995 | break; |
| 996 | case 0xa: |
| 997 | bios_connectors[i].hpd.hpd = RADEON_HPD_2; |
| 998 | break; |
| 999 | default: |
| 1000 | bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; |
| 1001 | break; |
| 1002 | } |
| 1003 | } else { |
| 1004 | if (i == ATOM_DEVICE_DFP1_INDEX) |
| 1005 | bios_connectors[i].hpd.hpd = RADEON_HPD_1; |
| 1006 | else if (i == ATOM_DEVICE_DFP2_INDEX) |
| 1007 | bios_connectors[i].hpd.hpd = RADEON_HPD_2; |
| 1008 | else |
| 1009 | bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; |
| 1010 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1011 | |
| 1012 | /* Always set the connector type to VGA for CRT1/CRT2. if they are |
| 1013 | * shared with a DVI port, we'll pick up the DVI connector when we |
| 1014 | * merge the outputs. Some bioses incorrectly list VGA ports as DVI. |
| 1015 | */ |
| 1016 | if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) |
| 1017 | bios_connectors[i].connector_type = |
| 1018 | DRM_MODE_CONNECTOR_VGA; |
| 1019 | |
| 1020 | if (!radeon_atom_apply_quirks |
| 1021 | (dev, (1 << i), &bios_connectors[i].connector_type, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1022 | &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, |
| 1023 | &bios_connectors[i].hpd)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1024 | continue; |
| 1025 | |
| 1026 | bios_connectors[i].valid = true; |
| 1027 | bios_connectors[i].devices = (1 << i); |
| 1028 | |
| 1029 | if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) |
| 1030 | radeon_add_atom_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1031 | radeon_get_encoder_enum(dev, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1032 | (1 << i), |
| 1033 | dac), |
Alex Deucher | 36868bd | 2011-01-06 21:19:21 -0500 | [diff] [blame] | 1034 | (1 << i), |
| 1035 | 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1036 | else |
| 1037 | radeon_add_legacy_encoder(dev, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1038 | radeon_get_encoder_enum(dev, |
Alex Deucher | f56cd64 | 2009-12-18 11:28:22 -0500 | [diff] [blame] | 1039 | (1 << i), |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1040 | dac), |
| 1041 | (1 << i)); |
| 1042 | } |
| 1043 | |
| 1044 | /* combine shared connectors */ |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1045 | for (i = 0; i < max_device; i++) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1046 | if (bios_connectors[i].valid) { |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1047 | for (j = 0; j < max_device; j++) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1048 | if (bios_connectors[j].valid && (i != j)) { |
| 1049 | if (bios_connectors[i].line_mux == |
| 1050 | bios_connectors[j].line_mux) { |
Alex Deucher | f56cd64 | 2009-12-18 11:28:22 -0500 | [diff] [blame] | 1051 | /* make sure not to combine LVDS */ |
| 1052 | if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 1053 | bios_connectors[i].line_mux = 53; |
| 1054 | bios_connectors[i].ddc_bus.valid = false; |
| 1055 | continue; |
| 1056 | } |
| 1057 | if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 1058 | bios_connectors[j].line_mux = 53; |
| 1059 | bios_connectors[j].ddc_bus.valid = false; |
| 1060 | continue; |
| 1061 | } |
| 1062 | /* combine analog and digital for DVI-I */ |
| 1063 | if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && |
| 1064 | (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || |
| 1065 | ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && |
| 1066 | (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { |
| 1067 | bios_connectors[i].devices |= |
| 1068 | bios_connectors[j].devices; |
| 1069 | bios_connectors[i].connector_type = |
| 1070 | DRM_MODE_CONNECTOR_DVII; |
| 1071 | if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1072 | bios_connectors[i].hpd = |
| 1073 | bios_connectors[j].hpd; |
Alex Deucher | f56cd64 | 2009-12-18 11:28:22 -0500 | [diff] [blame] | 1074 | bios_connectors[j].valid = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1075 | } |
| 1076 | } |
| 1077 | } |
| 1078 | } |
| 1079 | } |
| 1080 | } |
| 1081 | |
| 1082 | /* add the connectors */ |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1083 | for (i = 0; i < max_device; i++) { |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1084 | if (bios_connectors[i].valid) { |
| 1085 | uint16_t connector_object_id = |
| 1086 | atombios_get_connector_object_id(dev, |
| 1087 | bios_connectors[i].connector_type, |
| 1088 | bios_connectors[i].devices); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1089 | radeon_add_atom_connector(dev, |
| 1090 | bios_connectors[i].line_mux, |
| 1091 | bios_connectors[i].devices, |
| 1092 | bios_connectors[i]. |
| 1093 | connector_type, |
| 1094 | &bios_connectors[i].ddc_bus, |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1095 | 0, |
Alex Deucher | eed45b3 | 2009-12-04 14:45:27 -0500 | [diff] [blame] | 1096 | connector_object_id, |
Alex Deucher | 26b5bc9 | 2010-08-05 21:21:18 -0400 | [diff] [blame] | 1097 | &bios_connectors[i].hpd, |
| 1098 | &router); |
Alex Deucher | b75fad0 | 2009-11-05 13:16:01 -0500 | [diff] [blame] | 1099 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1100 | } |
| 1101 | |
| 1102 | radeon_link_encoder_connector(dev); |
| 1103 | |
Prarit Bhargava | f49d273 | 2010-05-24 10:24:07 +1000 | [diff] [blame] | 1104 | kfree(bios_connectors); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1105 | return true; |
| 1106 | } |
| 1107 | |
| 1108 | union firmware_info { |
| 1109 | ATOM_FIRMWARE_INFO info; |
| 1110 | ATOM_FIRMWARE_INFO_V1_2 info_12; |
| 1111 | ATOM_FIRMWARE_INFO_V1_3 info_13; |
| 1112 | ATOM_FIRMWARE_INFO_V1_4 info_14; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1113 | ATOM_FIRMWARE_INFO_V2_1 info_21; |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 1114 | ATOM_FIRMWARE_INFO_V2_2 info_22; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1115 | }; |
| 1116 | |
| 1117 | bool radeon_atom_get_clock_info(struct drm_device *dev) |
| 1118 | { |
| 1119 | struct radeon_device *rdev = dev->dev_private; |
| 1120 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1121 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); |
| 1122 | union firmware_info *firmware_info; |
| 1123 | uint8_t frev, crev; |
| 1124 | struct radeon_pll *p1pll = &rdev->clock.p1pll; |
| 1125 | struct radeon_pll *p2pll = &rdev->clock.p2pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1126 | struct radeon_pll *dcpll = &rdev->clock.dcpll; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1127 | struct radeon_pll *spll = &rdev->clock.spll; |
| 1128 | struct radeon_pll *mpll = &rdev->clock.mpll; |
| 1129 | uint16_t data_offset; |
| 1130 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1131 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 1132 | &frev, &crev, &data_offset)) { |
| 1133 | firmware_info = |
| 1134 | (union firmware_info *)(mode_info->atom_context->bios + |
| 1135 | data_offset); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1136 | /* pixel clocks */ |
| 1137 | p1pll->reference_freq = |
| 1138 | le16_to_cpu(firmware_info->info.usReferenceClock); |
| 1139 | p1pll->reference_div = 0; |
| 1140 | |
Mathias Fröhlich | bc293e5 | 2009-10-19 17:49:49 -0400 | [diff] [blame] | 1141 | if (crev < 2) |
| 1142 | p1pll->pll_out_min = |
| 1143 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); |
| 1144 | else |
| 1145 | p1pll->pll_out_min = |
| 1146 | le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1147 | p1pll->pll_out_max = |
| 1148 | le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); |
| 1149 | |
Alex Deucher | 86cb2bb | 2010-03-08 12:55:16 -0500 | [diff] [blame] | 1150 | if (crev >= 4) { |
| 1151 | p1pll->lcd_pll_out_min = |
| 1152 | le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; |
| 1153 | if (p1pll->lcd_pll_out_min == 0) |
| 1154 | p1pll->lcd_pll_out_min = p1pll->pll_out_min; |
| 1155 | p1pll->lcd_pll_out_max = |
| 1156 | le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; |
| 1157 | if (p1pll->lcd_pll_out_max == 0) |
| 1158 | p1pll->lcd_pll_out_max = p1pll->pll_out_max; |
| 1159 | } else { |
| 1160 | p1pll->lcd_pll_out_min = p1pll->pll_out_min; |
| 1161 | p1pll->lcd_pll_out_max = p1pll->pll_out_max; |
| 1162 | } |
| 1163 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1164 | if (p1pll->pll_out_min == 0) { |
| 1165 | if (ASIC_IS_AVIVO(rdev)) |
| 1166 | p1pll->pll_out_min = 64800; |
| 1167 | else |
| 1168 | p1pll->pll_out_min = 20000; |
| 1169 | } |
| 1170 | |
| 1171 | p1pll->pll_in_min = |
| 1172 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); |
| 1173 | p1pll->pll_in_max = |
| 1174 | le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); |
| 1175 | |
| 1176 | *p2pll = *p1pll; |
| 1177 | |
| 1178 | /* system clock */ |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 1179 | if (ASIC_IS_DCE4(rdev)) |
| 1180 | spll->reference_freq = |
| 1181 | le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); |
| 1182 | else |
| 1183 | spll->reference_freq = |
| 1184 | le16_to_cpu(firmware_info->info.usReferenceClock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1185 | spll->reference_div = 0; |
| 1186 | |
| 1187 | spll->pll_out_min = |
| 1188 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); |
| 1189 | spll->pll_out_max = |
| 1190 | le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); |
| 1191 | |
| 1192 | /* ??? */ |
| 1193 | if (spll->pll_out_min == 0) { |
| 1194 | if (ASIC_IS_AVIVO(rdev)) |
| 1195 | spll->pll_out_min = 64800; |
| 1196 | else |
| 1197 | spll->pll_out_min = 20000; |
| 1198 | } |
| 1199 | |
| 1200 | spll->pll_in_min = |
| 1201 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); |
| 1202 | spll->pll_in_max = |
| 1203 | le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); |
| 1204 | |
| 1205 | /* memory clock */ |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 1206 | if (ASIC_IS_DCE4(rdev)) |
| 1207 | mpll->reference_freq = |
| 1208 | le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); |
| 1209 | else |
| 1210 | mpll->reference_freq = |
| 1211 | le16_to_cpu(firmware_info->info.usReferenceClock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1212 | mpll->reference_div = 0; |
| 1213 | |
| 1214 | mpll->pll_out_min = |
| 1215 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); |
| 1216 | mpll->pll_out_max = |
| 1217 | le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); |
| 1218 | |
| 1219 | /* ??? */ |
| 1220 | if (mpll->pll_out_min == 0) { |
| 1221 | if (ASIC_IS_AVIVO(rdev)) |
| 1222 | mpll->pll_out_min = 64800; |
| 1223 | else |
| 1224 | mpll->pll_out_min = 20000; |
| 1225 | } |
| 1226 | |
| 1227 | mpll->pll_in_min = |
| 1228 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); |
| 1229 | mpll->pll_in_max = |
| 1230 | le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); |
| 1231 | |
| 1232 | rdev->clock.default_sclk = |
| 1233 | le32_to_cpu(firmware_info->info.ulDefaultEngineClock); |
| 1234 | rdev->clock.default_mclk = |
| 1235 | le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); |
| 1236 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1237 | if (ASIC_IS_DCE4(rdev)) { |
| 1238 | rdev->clock.default_dispclk = |
| 1239 | le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 1240 | if (rdev->clock.default_dispclk == 0) { |
| 1241 | if (ASIC_IS_DCE5(rdev)) |
| 1242 | rdev->clock.default_dispclk = 54000; /* 540 Mhz */ |
| 1243 | else |
| 1244 | rdev->clock.default_dispclk = 60000; /* 600 Mhz */ |
| 1245 | } |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1246 | rdev->clock.dp_extclk = |
| 1247 | le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); |
| 1248 | } |
| 1249 | *dcpll = *p1pll; |
| 1250 | |
Alex Deucher | b20f9be | 2011-06-08 13:01:11 -0400 | [diff] [blame] | 1251 | rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); |
| 1252 | if (rdev->clock.max_pixel_clock == 0) |
| 1253 | rdev->clock.max_pixel_clock = 40000; |
| 1254 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1255 | return true; |
| 1256 | } |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1257 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1258 | return false; |
| 1259 | } |
| 1260 | |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 1261 | union igp_info { |
| 1262 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; |
| 1263 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; |
| 1264 | }; |
| 1265 | |
| 1266 | bool radeon_atombios_sideport_present(struct radeon_device *rdev) |
| 1267 | { |
| 1268 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1269 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); |
| 1270 | union igp_info *igp_info; |
| 1271 | u8 frev, crev; |
| 1272 | u16 data_offset; |
| 1273 | |
Alex Deucher | 4c70b2e | 2010-08-02 19:39:15 -0400 | [diff] [blame] | 1274 | /* sideport is AMD only */ |
| 1275 | if (rdev->family == CHIP_RS600) |
| 1276 | return false; |
| 1277 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1278 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 1279 | &frev, &crev, &data_offset)) { |
| 1280 | igp_info = (union igp_info *)(mode_info->atom_context->bios + |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 1281 | data_offset); |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 1282 | switch (crev) { |
| 1283 | case 1: |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 1284 | if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) |
Alex Deucher | 4c70b2e | 2010-08-02 19:39:15 -0400 | [diff] [blame] | 1285 | return true; |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 1286 | break; |
| 1287 | case 2: |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 1288 | if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 1289 | return true; |
| 1290 | break; |
| 1291 | default: |
| 1292 | DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); |
| 1293 | break; |
| 1294 | } |
| 1295 | } |
| 1296 | return false; |
| 1297 | } |
| 1298 | |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1299 | bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
| 1300 | struct radeon_encoder_int_tmds *tmds) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1301 | { |
| 1302 | struct drm_device *dev = encoder->base.dev; |
| 1303 | struct radeon_device *rdev = dev->dev_private; |
| 1304 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1305 | int index = GetIndexIntoMasterTable(DATA, TMDS_Info); |
| 1306 | uint16_t data_offset; |
| 1307 | struct _ATOM_TMDS_INFO *tmds_info; |
| 1308 | uint8_t frev, crev; |
| 1309 | uint16_t maxfreq; |
| 1310 | int i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1311 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1312 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 1313 | &frev, &crev, &data_offset)) { |
| 1314 | tmds_info = |
| 1315 | (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + |
| 1316 | data_offset); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1317 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1318 | maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); |
| 1319 | for (i = 0; i < 4; i++) { |
| 1320 | tmds->tmds_pll[i].freq = |
| 1321 | le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); |
| 1322 | tmds->tmds_pll[i].value = |
| 1323 | tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; |
| 1324 | tmds->tmds_pll[i].value |= |
| 1325 | (tmds_info->asMiscInfo[i]. |
| 1326 | ucPLL_VCO_Gain & 0x3f) << 6; |
| 1327 | tmds->tmds_pll[i].value |= |
| 1328 | (tmds_info->asMiscInfo[i]. |
| 1329 | ucPLL_DutyCycle & 0xf) << 12; |
| 1330 | tmds->tmds_pll[i].value |= |
| 1331 | (tmds_info->asMiscInfo[i]. |
| 1332 | ucPLL_VoltageSwing & 0xf) << 16; |
| 1333 | |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1334 | DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1335 | tmds->tmds_pll[i].freq, |
| 1336 | tmds->tmds_pll[i].value); |
| 1337 | |
| 1338 | if (maxfreq == tmds->tmds_pll[i].freq) { |
| 1339 | tmds->tmds_pll[i].freq = 0xffffffff; |
| 1340 | break; |
| 1341 | } |
| 1342 | } |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1343 | return true; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1344 | } |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1345 | return false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1346 | } |
| 1347 | |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1348 | bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, |
| 1349 | struct radeon_atom_ss *ss, |
| 1350 | int id) |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 1351 | { |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 1352 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1353 | int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1354 | uint16_t data_offset, size; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 1355 | struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; |
| 1356 | uint8_t frev, crev; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1357 | int i, num_indices; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 1358 | |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1359 | memset(ss, 0, sizeof(struct radeon_atom_ss)); |
| 1360 | if (atom_parse_data_header(mode_info->atom_context, index, &size, |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1361 | &frev, &crev, &data_offset)) { |
| 1362 | ss_info = |
| 1363 | (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 1364 | |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1365 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
| 1366 | sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 1367 | |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1368 | for (i = 0; i < num_indices; i++) { |
Alex Deucher | 279b215 | 2009-12-08 14:07:03 -0500 | [diff] [blame] | 1369 | if (ss_info->asSS_Info[i].ucSS_Id == id) { |
| 1370 | ss->percentage = |
| 1371 | le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage); |
| 1372 | ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType; |
| 1373 | ss->step = ss_info->asSS_Info[i].ucSS_Step; |
| 1374 | ss->delay = ss_info->asSS_Info[i].ucSS_Delay; |
| 1375 | ss->range = ss_info->asSS_Info[i].ucSS_Range; |
| 1376 | ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1377 | return true; |
Alex Deucher | 279b215 | 2009-12-08 14:07:03 -0500 | [diff] [blame] | 1378 | } |
| 1379 | } |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 1380 | } |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1381 | return false; |
| 1382 | } |
| 1383 | |
Alex Deucher | 4339c44 | 2010-11-22 17:56:25 -0500 | [diff] [blame] | 1384 | static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev, |
| 1385 | struct radeon_atom_ss *ss, |
| 1386 | int id) |
| 1387 | { |
| 1388 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1389 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); |
| 1390 | u16 data_offset, size; |
| 1391 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info; |
| 1392 | u8 frev, crev; |
| 1393 | u16 percentage = 0, rate = 0; |
| 1394 | |
| 1395 | /* get any igp specific overrides */ |
| 1396 | if (atom_parse_data_header(mode_info->atom_context, index, &size, |
| 1397 | &frev, &crev, &data_offset)) { |
| 1398 | igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *) |
| 1399 | (mode_info->atom_context->bios + data_offset); |
| 1400 | switch (id) { |
| 1401 | case ASIC_INTERNAL_SS_ON_TMDS: |
| 1402 | percentage = le16_to_cpu(igp_info->usDVISSPercentage); |
| 1403 | rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz); |
| 1404 | break; |
| 1405 | case ASIC_INTERNAL_SS_ON_HDMI: |
| 1406 | percentage = le16_to_cpu(igp_info->usHDMISSPercentage); |
| 1407 | rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz); |
| 1408 | break; |
| 1409 | case ASIC_INTERNAL_SS_ON_LVDS: |
| 1410 | percentage = le16_to_cpu(igp_info->usLvdsSSPercentage); |
| 1411 | rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz); |
| 1412 | break; |
| 1413 | } |
| 1414 | if (percentage) |
| 1415 | ss->percentage = percentage; |
| 1416 | if (rate) |
| 1417 | ss->rate = rate; |
| 1418 | } |
| 1419 | } |
| 1420 | |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1421 | union asic_ss_info { |
| 1422 | struct _ATOM_ASIC_INTERNAL_SS_INFO info; |
| 1423 | struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; |
| 1424 | struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; |
| 1425 | }; |
| 1426 | |
| 1427 | bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, |
| 1428 | struct radeon_atom_ss *ss, |
| 1429 | int id, u32 clock) |
| 1430 | { |
| 1431 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1432 | int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); |
| 1433 | uint16_t data_offset, size; |
| 1434 | union asic_ss_info *ss_info; |
| 1435 | uint8_t frev, crev; |
| 1436 | int i, num_indices; |
| 1437 | |
| 1438 | memset(ss, 0, sizeof(struct radeon_atom_ss)); |
| 1439 | if (atom_parse_data_header(mode_info->atom_context, index, &size, |
| 1440 | &frev, &crev, &data_offset)) { |
| 1441 | |
| 1442 | ss_info = |
| 1443 | (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); |
| 1444 | |
| 1445 | switch (frev) { |
| 1446 | case 1: |
| 1447 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
| 1448 | sizeof(ATOM_ASIC_SS_ASSIGNMENT); |
| 1449 | |
| 1450 | for (i = 0; i < num_indices; i++) { |
| 1451 | if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) && |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 1452 | (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) { |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1453 | ss->percentage = |
| 1454 | le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage); |
| 1455 | ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode; |
| 1456 | ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz); |
| 1457 | return true; |
| 1458 | } |
| 1459 | } |
| 1460 | break; |
| 1461 | case 2: |
| 1462 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
| 1463 | sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); |
| 1464 | for (i = 0; i < num_indices; i++) { |
| 1465 | if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) && |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 1466 | (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) { |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1467 | ss->percentage = |
| 1468 | le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage); |
| 1469 | ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode; |
| 1470 | ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz); |
| 1471 | return true; |
| 1472 | } |
| 1473 | } |
| 1474 | break; |
| 1475 | case 3: |
| 1476 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / |
| 1477 | sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); |
| 1478 | for (i = 0; i < num_indices; i++) { |
| 1479 | if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) && |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 1480 | (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) { |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1481 | ss->percentage = |
| 1482 | le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage); |
| 1483 | ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode; |
| 1484 | ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz); |
Alex Deucher | 4339c44 | 2010-11-22 17:56:25 -0500 | [diff] [blame] | 1485 | if (rdev->flags & RADEON_IS_IGP) |
| 1486 | radeon_atombios_get_igp_ss_overrides(rdev, ss, id); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1487 | return true; |
| 1488 | } |
| 1489 | } |
| 1490 | break; |
| 1491 | default: |
| 1492 | DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); |
| 1493 | break; |
| 1494 | } |
| 1495 | |
| 1496 | } |
| 1497 | return false; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 1498 | } |
| 1499 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1500 | union lvds_info { |
| 1501 | struct _ATOM_LVDS_INFO info; |
| 1502 | struct _ATOM_LVDS_INFO_V12 info_12; |
| 1503 | }; |
| 1504 | |
| 1505 | struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct |
| 1506 | radeon_encoder |
| 1507 | *encoder) |
| 1508 | { |
| 1509 | struct drm_device *dev = encoder->base.dev; |
| 1510 | struct radeon_device *rdev = dev->dev_private; |
| 1511 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1512 | int index = GetIndexIntoMasterTable(DATA, LVDS_Info); |
Alex Deucher | 7dde8a19 | 2009-11-30 01:40:24 -0500 | [diff] [blame] | 1513 | uint16_t data_offset, misc; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1514 | union lvds_info *lvds_info; |
| 1515 | uint8_t frev, crev; |
| 1516 | struct radeon_encoder_atom_dig *lvds = NULL; |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1517 | int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1518 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1519 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 1520 | &frev, &crev, &data_offset)) { |
| 1521 | lvds_info = |
| 1522 | (union lvds_info *)(mode_info->atom_context->bios + data_offset); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1523 | lvds = |
| 1524 | kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
| 1525 | |
| 1526 | if (!lvds) |
| 1527 | return NULL; |
| 1528 | |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1529 | lvds->native_mode.clock = |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1530 | le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1531 | lvds->native_mode.hdisplay = |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1532 | le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1533 | lvds->native_mode.vdisplay = |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1534 | le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1535 | lvds->native_mode.htotal = lvds->native_mode.hdisplay + |
| 1536 | le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); |
| 1537 | lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + |
| 1538 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); |
| 1539 | lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + |
| 1540 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); |
| 1541 | lvds->native_mode.vtotal = lvds->native_mode.vdisplay + |
| 1542 | le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); |
| 1543 | lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + |
Alex Deucher | 1ff26a3 | 2010-05-18 00:23:15 -0400 | [diff] [blame] | 1544 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1545 | lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + |
| 1546 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1547 | lvds->panel_pwr_delay = |
| 1548 | le16_to_cpu(lvds_info->info.usOffDelayInMs); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1549 | lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; |
Alex Deucher | 7dde8a19 | 2009-11-30 01:40:24 -0500 | [diff] [blame] | 1550 | |
| 1551 | misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); |
| 1552 | if (misc & ATOM_VSYNC_POLARITY) |
| 1553 | lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
| 1554 | if (misc & ATOM_HSYNC_POLARITY) |
| 1555 | lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
| 1556 | if (misc & ATOM_COMPOSITESYNC) |
| 1557 | lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; |
| 1558 | if (misc & ATOM_INTERLACE) |
| 1559 | lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
| 1560 | if (misc & ATOM_DOUBLE_CLOCK_MODE) |
| 1561 | lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; |
| 1562 | |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 1563 | lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); |
| 1564 | lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); |
Alex Deucher | 7a868e1 | 2010-12-08 22:13:05 -0500 | [diff] [blame] | 1565 | |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 1566 | /* set crtc values */ |
| 1567 | drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1568 | |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1569 | lvds->lcd_ss_id = lvds_info->info.ucSS_Id; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 1570 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1571 | encoder->native_mode = lvds->native_mode; |
Alex Deucher | 5137ee9 | 2010-08-12 18:58:47 -0400 | [diff] [blame] | 1572 | |
| 1573 | if (encoder_enum == 2) |
| 1574 | lvds->linkb = true; |
| 1575 | else |
| 1576 | lvds->linkb = false; |
| 1577 | |
Alex Deucher | c324acd | 2010-12-08 22:13:06 -0500 | [diff] [blame] | 1578 | /* parse the lcd record table */ |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 1579 | if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { |
Alex Deucher | c324acd | 2010-12-08 22:13:06 -0500 | [diff] [blame] | 1580 | ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; |
| 1581 | ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; |
| 1582 | bool bad_record = false; |
Alex Deucher | 05fa7ea | 2011-05-11 14:02:07 -0400 | [diff] [blame] | 1583 | u8 *record; |
| 1584 | |
| 1585 | if ((frev == 1) && (crev < 2)) |
| 1586 | /* absolute */ |
| 1587 | record = (u8 *)(mode_info->atom_context->bios + |
| 1588 | le16_to_cpu(lvds_info->info.usModePatchTableOffset)); |
| 1589 | else |
| 1590 | /* relative */ |
| 1591 | record = (u8 *)(mode_info->atom_context->bios + |
| 1592 | data_offset + |
| 1593 | le16_to_cpu(lvds_info->info.usModePatchTableOffset)); |
Alex Deucher | c324acd | 2010-12-08 22:13:06 -0500 | [diff] [blame] | 1594 | while (*record != ATOM_RECORD_END_TYPE) { |
| 1595 | switch (*record) { |
| 1596 | case LCD_MODE_PATCH_RECORD_MODE_TYPE: |
| 1597 | record += sizeof(ATOM_PATCH_RECORD_MODE); |
| 1598 | break; |
| 1599 | case LCD_RTS_RECORD_TYPE: |
| 1600 | record += sizeof(ATOM_LCD_RTS_RECORD); |
| 1601 | break; |
| 1602 | case LCD_CAP_RECORD_TYPE: |
| 1603 | record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); |
| 1604 | break; |
| 1605 | case LCD_FAKE_EDID_PATCH_RECORD_TYPE: |
| 1606 | fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; |
| 1607 | if (fake_edid_record->ucFakeEDIDLength) { |
| 1608 | struct edid *edid; |
| 1609 | int edid_size = |
| 1610 | max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength); |
| 1611 | edid = kmalloc(edid_size, GFP_KERNEL); |
| 1612 | if (edid) { |
| 1613 | memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], |
| 1614 | fake_edid_record->ucFakeEDIDLength); |
| 1615 | |
Dave Airlie | eaa4f5e | 2011-05-01 20:16:30 +1000 | [diff] [blame] | 1616 | if (drm_edid_is_valid(edid)) { |
Alex Deucher | c324acd | 2010-12-08 22:13:06 -0500 | [diff] [blame] | 1617 | rdev->mode_info.bios_hardcoded_edid = edid; |
Dave Airlie | eaa4f5e | 2011-05-01 20:16:30 +1000 | [diff] [blame] | 1618 | rdev->mode_info.bios_hardcoded_edid_size = edid_size; |
| 1619 | } else |
Alex Deucher | c324acd | 2010-12-08 22:13:06 -0500 | [diff] [blame] | 1620 | kfree(edid); |
| 1621 | } |
| 1622 | } |
| 1623 | record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD); |
| 1624 | break; |
| 1625 | case LCD_PANEL_RESOLUTION_RECORD_TYPE: |
| 1626 | panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; |
| 1627 | lvds->native_mode.width_mm = panel_res_record->usHSize; |
| 1628 | lvds->native_mode.height_mm = panel_res_record->usVSize; |
| 1629 | record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); |
| 1630 | break; |
| 1631 | default: |
| 1632 | DRM_ERROR("Bad LCD record %d\n", *record); |
| 1633 | bad_record = true; |
| 1634 | break; |
| 1635 | } |
| 1636 | if (bad_record) |
| 1637 | break; |
| 1638 | } |
| 1639 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1640 | } |
| 1641 | return lvds; |
| 1642 | } |
| 1643 | |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1644 | struct radeon_encoder_primary_dac * |
| 1645 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) |
| 1646 | { |
| 1647 | struct drm_device *dev = encoder->base.dev; |
| 1648 | struct radeon_device *rdev = dev->dev_private; |
| 1649 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1650 | int index = GetIndexIntoMasterTable(DATA, CompassionateData); |
| 1651 | uint16_t data_offset; |
| 1652 | struct _COMPASSIONATE_DATA *dac_info; |
| 1653 | uint8_t frev, crev; |
| 1654 | uint8_t bg, dac; |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1655 | struct radeon_encoder_primary_dac *p_dac = NULL; |
| 1656 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1657 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 1658 | &frev, &crev, &data_offset)) { |
| 1659 | dac_info = (struct _COMPASSIONATE_DATA *) |
| 1660 | (mode_info->atom_context->bios + data_offset); |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1661 | |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1662 | p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); |
| 1663 | |
| 1664 | if (!p_dac) |
| 1665 | return NULL; |
| 1666 | |
| 1667 | bg = dac_info->ucDAC1_BG_Adjustment; |
| 1668 | dac = dac_info->ucDAC1_DAC_Adjustment; |
| 1669 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
| 1670 | |
| 1671 | } |
| 1672 | return p_dac; |
| 1673 | } |
| 1674 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1675 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1676 | struct drm_display_mode *mode) |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1677 | { |
| 1678 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1679 | ATOM_ANALOG_TV_INFO *tv_info; |
| 1680 | ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; |
| 1681 | ATOM_DTD_FORMAT *dtd_timings; |
| 1682 | int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); |
| 1683 | u8 frev, crev; |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1684 | u16 data_offset, misc; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1685 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1686 | if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, |
| 1687 | &frev, &crev, &data_offset)) |
| 1688 | return false; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1689 | |
| 1690 | switch (crev) { |
| 1691 | case 1: |
| 1692 | tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); |
Dan Carpenter | 0031c41 | 2010-04-27 14:11:04 -0700 | [diff] [blame] | 1693 | if (index >= MAX_SUPPORTED_TV_TIMING) |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1694 | return false; |
| 1695 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1696 | mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); |
| 1697 | mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); |
| 1698 | mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); |
| 1699 | mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + |
| 1700 | le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1701 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1702 | mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); |
| 1703 | mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); |
| 1704 | mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); |
| 1705 | mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + |
| 1706 | le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1707 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1708 | mode->flags = 0; |
| 1709 | misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); |
| 1710 | if (misc & ATOM_VSYNC_POLARITY) |
| 1711 | mode->flags |= DRM_MODE_FLAG_NVSYNC; |
| 1712 | if (misc & ATOM_HSYNC_POLARITY) |
| 1713 | mode->flags |= DRM_MODE_FLAG_NHSYNC; |
| 1714 | if (misc & ATOM_COMPOSITESYNC) |
| 1715 | mode->flags |= DRM_MODE_FLAG_CSYNC; |
| 1716 | if (misc & ATOM_INTERLACE) |
| 1717 | mode->flags |= DRM_MODE_FLAG_INTERLACE; |
| 1718 | if (misc & ATOM_DOUBLE_CLOCK_MODE) |
| 1719 | mode->flags |= DRM_MODE_FLAG_DBLSCAN; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1720 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1721 | mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1722 | |
| 1723 | if (index == 1) { |
| 1724 | /* PAL timings appear to have wrong values for totals */ |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1725 | mode->crtc_htotal -= 1; |
| 1726 | mode->crtc_vtotal -= 1; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1727 | } |
| 1728 | break; |
| 1729 | case 2: |
| 1730 | tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); |
Dan Carpenter | 0031c41 | 2010-04-27 14:11:04 -0700 | [diff] [blame] | 1731 | if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1732 | return false; |
| 1733 | |
| 1734 | dtd_timings = &tv_info_v1_2->aModeTimings[index]; |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1735 | mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + |
| 1736 | le16_to_cpu(dtd_timings->usHBlanking_Time); |
| 1737 | mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); |
| 1738 | mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + |
| 1739 | le16_to_cpu(dtd_timings->usHSyncOffset); |
| 1740 | mode->crtc_hsync_end = mode->crtc_hsync_start + |
| 1741 | le16_to_cpu(dtd_timings->usHSyncWidth); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1742 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1743 | mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + |
| 1744 | le16_to_cpu(dtd_timings->usVBlanking_Time); |
| 1745 | mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); |
| 1746 | mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + |
| 1747 | le16_to_cpu(dtd_timings->usVSyncOffset); |
| 1748 | mode->crtc_vsync_end = mode->crtc_vsync_start + |
| 1749 | le16_to_cpu(dtd_timings->usVSyncWidth); |
| 1750 | |
| 1751 | mode->flags = 0; |
| 1752 | misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); |
| 1753 | if (misc & ATOM_VSYNC_POLARITY) |
| 1754 | mode->flags |= DRM_MODE_FLAG_NVSYNC; |
| 1755 | if (misc & ATOM_HSYNC_POLARITY) |
| 1756 | mode->flags |= DRM_MODE_FLAG_NHSYNC; |
| 1757 | if (misc & ATOM_COMPOSITESYNC) |
| 1758 | mode->flags |= DRM_MODE_FLAG_CSYNC; |
| 1759 | if (misc & ATOM_INTERLACE) |
| 1760 | mode->flags |= DRM_MODE_FLAG_INTERLACE; |
| 1761 | if (misc & ATOM_DOUBLE_CLOCK_MODE) |
| 1762 | mode->flags |= DRM_MODE_FLAG_DBLSCAN; |
| 1763 | |
| 1764 | mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1765 | break; |
| 1766 | } |
| 1767 | return true; |
| 1768 | } |
| 1769 | |
Alex Deucher | d79766f | 2009-12-17 19:00:29 -0500 | [diff] [blame] | 1770 | enum radeon_tv_std |
| 1771 | radeon_atombios_get_tv_info(struct radeon_device *rdev) |
| 1772 | { |
| 1773 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1774 | int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); |
| 1775 | uint16_t data_offset; |
| 1776 | uint8_t frev, crev; |
| 1777 | struct _ATOM_ANALOG_TV_INFO *tv_info; |
| 1778 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
| 1779 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1780 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 1781 | &frev, &crev, &data_offset)) { |
Alex Deucher | d79766f | 2009-12-17 19:00:29 -0500 | [diff] [blame] | 1782 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1783 | tv_info = (struct _ATOM_ANALOG_TV_INFO *) |
| 1784 | (mode_info->atom_context->bios + data_offset); |
Alex Deucher | d79766f | 2009-12-17 19:00:29 -0500 | [diff] [blame] | 1785 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1786 | switch (tv_info->ucTV_BootUpDefaultStandard) { |
| 1787 | case ATOM_TV_NTSC: |
| 1788 | tv_std = TV_STD_NTSC; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 1789 | DRM_DEBUG_KMS("Default TV standard: NTSC\n"); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1790 | break; |
| 1791 | case ATOM_TV_NTSCJ: |
| 1792 | tv_std = TV_STD_NTSC_J; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 1793 | DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1794 | break; |
| 1795 | case ATOM_TV_PAL: |
| 1796 | tv_std = TV_STD_PAL; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 1797 | DRM_DEBUG_KMS("Default TV standard: PAL\n"); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1798 | break; |
| 1799 | case ATOM_TV_PALM: |
| 1800 | tv_std = TV_STD_PAL_M; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 1801 | DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1802 | break; |
| 1803 | case ATOM_TV_PALN: |
| 1804 | tv_std = TV_STD_PAL_N; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 1805 | DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1806 | break; |
| 1807 | case ATOM_TV_PALCN: |
| 1808 | tv_std = TV_STD_PAL_CN; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 1809 | DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1810 | break; |
| 1811 | case ATOM_TV_PAL60: |
| 1812 | tv_std = TV_STD_PAL_60; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 1813 | DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1814 | break; |
| 1815 | case ATOM_TV_SECAM: |
| 1816 | tv_std = TV_STD_SECAM; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 1817 | DRM_DEBUG_KMS("Default TV standard: SECAM\n"); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1818 | break; |
| 1819 | default: |
| 1820 | tv_std = TV_STD_NTSC; |
Alex Deucher | 40f76d8 | 2010-10-07 22:38:42 -0400 | [diff] [blame] | 1821 | DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1822 | break; |
| 1823 | } |
Alex Deucher | d79766f | 2009-12-17 19:00:29 -0500 | [diff] [blame] | 1824 | } |
| 1825 | return tv_std; |
| 1826 | } |
| 1827 | |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1828 | struct radeon_encoder_tv_dac * |
| 1829 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) |
| 1830 | { |
| 1831 | struct drm_device *dev = encoder->base.dev; |
| 1832 | struct radeon_device *rdev = dev->dev_private; |
| 1833 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1834 | int index = GetIndexIntoMasterTable(DATA, CompassionateData); |
| 1835 | uint16_t data_offset; |
| 1836 | struct _COMPASSIONATE_DATA *dac_info; |
| 1837 | uint8_t frev, crev; |
| 1838 | uint8_t bg, dac; |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1839 | struct radeon_encoder_tv_dac *tv_dac = NULL; |
| 1840 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1841 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 1842 | &frev, &crev, &data_offset)) { |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1843 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 1844 | dac_info = (struct _COMPASSIONATE_DATA *) |
| 1845 | (mode_info->atom_context->bios + data_offset); |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1846 | |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1847 | tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); |
| 1848 | |
| 1849 | if (!tv_dac) |
| 1850 | return NULL; |
| 1851 | |
| 1852 | bg = dac_info->ucDAC2_CRT2_BG_Adjustment; |
| 1853 | dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; |
| 1854 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); |
| 1855 | |
| 1856 | bg = dac_info->ucDAC2_PAL_BG_Adjustment; |
| 1857 | dac = dac_info->ucDAC2_PAL_DAC_Adjustment; |
| 1858 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
| 1859 | |
| 1860 | bg = dac_info->ucDAC2_NTSC_BG_Adjustment; |
| 1861 | dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; |
| 1862 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
| 1863 | |
Alex Deucher | d79766f | 2009-12-17 19:00:29 -0500 | [diff] [blame] | 1864 | tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1865 | } |
| 1866 | return tv_dac; |
| 1867 | } |
| 1868 | |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 1869 | static const char *thermal_controller_names[] = { |
| 1870 | "NONE", |
Alex Deucher | 678e7df | 2010-04-22 14:17:56 -0400 | [diff] [blame] | 1871 | "lm63", |
| 1872 | "adm1032", |
| 1873 | "adm1030", |
| 1874 | "max6649", |
| 1875 | "lm64", |
| 1876 | "f75375", |
| 1877 | "asc7xxx", |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 1878 | }; |
| 1879 | |
| 1880 | static const char *pp_lib_thermal_controller_names[] = { |
| 1881 | "NONE", |
Alex Deucher | 678e7df | 2010-04-22 14:17:56 -0400 | [diff] [blame] | 1882 | "lm63", |
| 1883 | "adm1032", |
| 1884 | "adm1030", |
| 1885 | "max6649", |
| 1886 | "lm64", |
| 1887 | "f75375", |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 1888 | "RV6xx", |
| 1889 | "RV770", |
Alex Deucher | 678e7df | 2010-04-22 14:17:56 -0400 | [diff] [blame] | 1890 | "adt7473", |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 1891 | "NONE", |
Alex Deucher | 49f6598 | 2010-03-24 16:39:45 -0400 | [diff] [blame] | 1892 | "External GPIO", |
| 1893 | "Evergreen", |
Alex Deucher | b0e6641 | 2010-11-22 17:56:35 -0500 | [diff] [blame] | 1894 | "emc2103", |
| 1895 | "Sumo", |
Alex Deucher | 4fddba1 | 2011-01-06 21:19:22 -0500 | [diff] [blame] | 1896 | "Northern Islands", |
Alex Deucher | 14607d0 | 2012-03-20 17:18:09 -0400 | [diff] [blame^] | 1897 | "Southern Islands", |
| 1898 | "lm96163", |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 1899 | }; |
| 1900 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1901 | union power_info { |
| 1902 | struct _ATOM_POWERPLAY_INFO info; |
| 1903 | struct _ATOM_POWERPLAY_INFO_V2 info_2; |
| 1904 | struct _ATOM_POWERPLAY_INFO_V3 info_3; |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 1905 | struct _ATOM_PPLIB_POWERPLAYTABLE pplib; |
Alex Deucher | b0e6641 | 2010-11-22 17:56:35 -0500 | [diff] [blame] | 1906 | struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; |
| 1907 | struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 1908 | }; |
| 1909 | |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 1910 | union pplib_clock_info { |
| 1911 | struct _ATOM_PPLIB_R600_CLOCK_INFO r600; |
| 1912 | struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; |
| 1913 | struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; |
Alex Deucher | b0e6641 | 2010-11-22 17:56:35 -0500 | [diff] [blame] | 1914 | struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; |
Alex Deucher | 14607d0 | 2012-03-20 17:18:09 -0400 | [diff] [blame^] | 1915 | struct _ATOM_PPLIB_SI_CLOCK_INFO si; |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 1916 | }; |
| 1917 | |
| 1918 | union pplib_power_state { |
| 1919 | struct _ATOM_PPLIB_STATE v1; |
| 1920 | struct _ATOM_PPLIB_STATE_V2 v2; |
| 1921 | }; |
| 1922 | |
| 1923 | static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev, |
| 1924 | int state_index, |
| 1925 | u32 misc, u32 misc2) |
| 1926 | { |
| 1927 | rdev->pm.power_state[state_index].misc = misc; |
| 1928 | rdev->pm.power_state[state_index].misc2 = misc2; |
| 1929 | /* order matters! */ |
| 1930 | if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) |
| 1931 | rdev->pm.power_state[state_index].type = |
| 1932 | POWER_STATE_TYPE_POWERSAVE; |
| 1933 | if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) |
| 1934 | rdev->pm.power_state[state_index].type = |
| 1935 | POWER_STATE_TYPE_BATTERY; |
| 1936 | if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) |
| 1937 | rdev->pm.power_state[state_index].type = |
| 1938 | POWER_STATE_TYPE_BATTERY; |
| 1939 | if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) |
| 1940 | rdev->pm.power_state[state_index].type = |
| 1941 | POWER_STATE_TYPE_BALANCED; |
| 1942 | if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { |
| 1943 | rdev->pm.power_state[state_index].type = |
| 1944 | POWER_STATE_TYPE_PERFORMANCE; |
| 1945 | rdev->pm.power_state[state_index].flags &= |
| 1946 | ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
| 1947 | } |
| 1948 | if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) |
| 1949 | rdev->pm.power_state[state_index].type = |
| 1950 | POWER_STATE_TYPE_BALANCED; |
| 1951 | if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { |
| 1952 | rdev->pm.power_state[state_index].type = |
| 1953 | POWER_STATE_TYPE_DEFAULT; |
| 1954 | rdev->pm.default_power_state_index = state_index; |
| 1955 | rdev->pm.power_state[state_index].default_clock_mode = |
| 1956 | &rdev->pm.power_state[state_index].clock_info[0]; |
| 1957 | } else if (state_index == 0) { |
| 1958 | rdev->pm.power_state[state_index].clock_info[0].flags |= |
| 1959 | RADEON_PM_MODE_NO_DISPLAY; |
| 1960 | } |
| 1961 | } |
| 1962 | |
| 1963 | static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) |
| 1964 | { |
| 1965 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 1966 | u32 misc, misc2 = 0; |
| 1967 | int num_modes = 0, i; |
| 1968 | int state_index = 0; |
| 1969 | struct radeon_i2c_bus_rec i2c_bus; |
| 1970 | union power_info *power_info; |
| 1971 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); |
| 1972 | u16 data_offset; |
| 1973 | u8 frev, crev; |
| 1974 | |
| 1975 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 1976 | &frev, &crev, &data_offset)) |
| 1977 | return state_index; |
| 1978 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); |
| 1979 | |
| 1980 | /* add the i2c bus for thermal/fan chip */ |
| 1981 | if (power_info->info.ucOverdriveThermalController > 0) { |
| 1982 | DRM_INFO("Possible %s thermal controller at 0x%02x\n", |
| 1983 | thermal_controller_names[power_info->info.ucOverdriveThermalController], |
| 1984 | power_info->info.ucOverdriveControllerAddress >> 1); |
| 1985 | i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); |
| 1986 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
| 1987 | if (rdev->pm.i2c_bus) { |
| 1988 | struct i2c_board_info info = { }; |
| 1989 | const char *name = thermal_controller_names[power_info->info. |
| 1990 | ucOverdriveThermalController]; |
| 1991 | info.addr = power_info->info.ucOverdriveControllerAddress >> 1; |
| 1992 | strlcpy(info.type, name, sizeof(info.type)); |
| 1993 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); |
| 1994 | } |
| 1995 | } |
| 1996 | num_modes = power_info->info.ucNumOfPowerModeEntries; |
| 1997 | if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) |
| 1998 | num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; |
Alex Deucher | 0975b16 | 2011-02-02 18:42:03 -0500 | [diff] [blame] | 1999 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL); |
| 2000 | if (!rdev->pm.power_state) |
| 2001 | return state_index; |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2002 | /* last mode is usually default, array is low to high */ |
| 2003 | for (i = 0; i < num_modes; i++) { |
Alex Deucher | 6991b8f | 2011-11-14 17:52:51 -0500 | [diff] [blame] | 2004 | rdev->pm.power_state[state_index].clock_info = |
| 2005 | kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); |
| 2006 | if (!rdev->pm.power_state[state_index].clock_info) |
| 2007 | return state_index; |
| 2008 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2009 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
| 2010 | switch (frev) { |
| 2011 | case 1: |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2012 | rdev->pm.power_state[state_index].clock_info[0].mclk = |
| 2013 | le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); |
| 2014 | rdev->pm.power_state[state_index].clock_info[0].sclk = |
| 2015 | le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); |
| 2016 | /* skip invalid modes */ |
| 2017 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
| 2018 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
| 2019 | continue; |
| 2020 | rdev->pm.power_state[state_index].pcie_lanes = |
| 2021 | power_info->info.asPowerPlayInfo[i].ucNumPciELanes; |
| 2022 | misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); |
| 2023 | if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || |
| 2024 | (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { |
| 2025 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
| 2026 | VOLTAGE_GPIO; |
| 2027 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = |
| 2028 | radeon_lookup_gpio(rdev, |
| 2029 | power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); |
| 2030 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) |
| 2031 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
| 2032 | true; |
| 2033 | else |
| 2034 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
| 2035 | false; |
| 2036 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { |
| 2037 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
| 2038 | VOLTAGE_VDDC; |
| 2039 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = |
| 2040 | power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; |
| 2041 | } |
| 2042 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
| 2043 | radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0); |
| 2044 | state_index++; |
| 2045 | break; |
| 2046 | case 2: |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2047 | rdev->pm.power_state[state_index].clock_info[0].mclk = |
| 2048 | le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); |
| 2049 | rdev->pm.power_state[state_index].clock_info[0].sclk = |
| 2050 | le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); |
| 2051 | /* skip invalid modes */ |
| 2052 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
| 2053 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
| 2054 | continue; |
| 2055 | rdev->pm.power_state[state_index].pcie_lanes = |
| 2056 | power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; |
| 2057 | misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); |
| 2058 | misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); |
| 2059 | if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || |
| 2060 | (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { |
| 2061 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
| 2062 | VOLTAGE_GPIO; |
| 2063 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = |
| 2064 | radeon_lookup_gpio(rdev, |
| 2065 | power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); |
| 2066 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) |
| 2067 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
| 2068 | true; |
| 2069 | else |
| 2070 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
| 2071 | false; |
| 2072 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { |
| 2073 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
| 2074 | VOLTAGE_VDDC; |
| 2075 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = |
| 2076 | power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; |
| 2077 | } |
| 2078 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
| 2079 | radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); |
| 2080 | state_index++; |
| 2081 | break; |
| 2082 | case 3: |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2083 | rdev->pm.power_state[state_index].clock_info[0].mclk = |
| 2084 | le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); |
| 2085 | rdev->pm.power_state[state_index].clock_info[0].sclk = |
| 2086 | le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); |
| 2087 | /* skip invalid modes */ |
| 2088 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
| 2089 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
| 2090 | continue; |
| 2091 | rdev->pm.power_state[state_index].pcie_lanes = |
| 2092 | power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; |
| 2093 | misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); |
| 2094 | misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); |
| 2095 | if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || |
| 2096 | (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { |
| 2097 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
| 2098 | VOLTAGE_GPIO; |
| 2099 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = |
| 2100 | radeon_lookup_gpio(rdev, |
| 2101 | power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); |
| 2102 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) |
| 2103 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
| 2104 | true; |
| 2105 | else |
| 2106 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
| 2107 | false; |
| 2108 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { |
| 2109 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = |
| 2110 | VOLTAGE_VDDC; |
| 2111 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = |
| 2112 | power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; |
| 2113 | if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { |
| 2114 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = |
| 2115 | true; |
| 2116 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = |
| 2117 | power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; |
| 2118 | } |
| 2119 | } |
| 2120 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
| 2121 | radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); |
| 2122 | state_index++; |
| 2123 | break; |
| 2124 | } |
| 2125 | } |
| 2126 | /* last mode is usually default */ |
| 2127 | if (rdev->pm.default_power_state_index == -1) { |
| 2128 | rdev->pm.power_state[state_index - 1].type = |
| 2129 | POWER_STATE_TYPE_DEFAULT; |
| 2130 | rdev->pm.default_power_state_index = state_index - 1; |
| 2131 | rdev->pm.power_state[state_index - 1].default_clock_mode = |
| 2132 | &rdev->pm.power_state[state_index - 1].clock_info[0]; |
| 2133 | rdev->pm.power_state[state_index].flags &= |
| 2134 | ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
| 2135 | rdev->pm.power_state[state_index].misc = 0; |
| 2136 | rdev->pm.power_state[state_index].misc2 = 0; |
| 2137 | } |
| 2138 | return state_index; |
| 2139 | } |
| 2140 | |
| 2141 | static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev, |
| 2142 | ATOM_PPLIB_THERMALCONTROLLER *controller) |
| 2143 | { |
| 2144 | struct radeon_i2c_bus_rec i2c_bus; |
| 2145 | |
| 2146 | /* add the i2c bus for thermal/fan chip */ |
| 2147 | if (controller->ucType > 0) { |
| 2148 | if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { |
| 2149 | DRM_INFO("Internal thermal controller %s fan control\n", |
| 2150 | (controller->ucFanParameters & |
| 2151 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
| 2152 | rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; |
| 2153 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { |
| 2154 | DRM_INFO("Internal thermal controller %s fan control\n", |
| 2155 | (controller->ucFanParameters & |
| 2156 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
| 2157 | rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; |
| 2158 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { |
| 2159 | DRM_INFO("Internal thermal controller %s fan control\n", |
| 2160 | (controller->ucFanParameters & |
| 2161 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
| 2162 | rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; |
Alex Deucher | b0e6641 | 2010-11-22 17:56:35 -0500 | [diff] [blame] | 2163 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { |
| 2164 | DRM_INFO("Internal thermal controller %s fan control\n", |
| 2165 | (controller->ucFanParameters & |
| 2166 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
| 2167 | rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; |
Alex Deucher | 4fddba1 | 2011-01-06 21:19:22 -0500 | [diff] [blame] | 2168 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { |
| 2169 | DRM_INFO("Internal thermal controller %s fan control\n", |
| 2170 | (controller->ucFanParameters & |
| 2171 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
| 2172 | rdev->pm.int_thermal_type = THERMAL_TYPE_NI; |
Alex Deucher | 14607d0 | 2012-03-20 17:18:09 -0400 | [diff] [blame^] | 2173 | } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { |
| 2174 | DRM_INFO("Internal thermal controller %s fan control\n", |
| 2175 | (controller->ucFanParameters & |
| 2176 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
| 2177 | rdev->pm.int_thermal_type = THERMAL_TYPE_SI; |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2178 | } else if ((controller->ucType == |
| 2179 | ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) || |
| 2180 | (controller->ucType == |
Alex Deucher | b0e6641 | 2010-11-22 17:56:35 -0500 | [diff] [blame] | 2181 | ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) || |
| 2182 | (controller->ucType == |
| 2183 | ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) { |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2184 | DRM_INFO("Special thermal controller config\n"); |
| 2185 | } else { |
| 2186 | DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", |
| 2187 | pp_lib_thermal_controller_names[controller->ucType], |
| 2188 | controller->ucI2cAddress >> 1, |
| 2189 | (controller->ucFanParameters & |
| 2190 | ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); |
| 2191 | i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); |
| 2192 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
| 2193 | if (rdev->pm.i2c_bus) { |
| 2194 | struct i2c_board_info info = { }; |
| 2195 | const char *name = pp_lib_thermal_controller_names[controller->ucType]; |
| 2196 | info.addr = controller->ucI2cAddress >> 1; |
| 2197 | strlcpy(info.type, name, sizeof(info.type)); |
| 2198 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); |
| 2199 | } |
| 2200 | } |
| 2201 | } |
| 2202 | } |
| 2203 | |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 2204 | static void radeon_atombios_get_default_voltages(struct radeon_device *rdev, |
| 2205 | u16 *vddc, u16 *vddci) |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2206 | { |
| 2207 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 2208 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); |
| 2209 | u8 frev, crev; |
| 2210 | u16 data_offset; |
| 2211 | union firmware_info *firmware_info; |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 2212 | |
| 2213 | *vddc = 0; |
| 2214 | *vddci = 0; |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2215 | |
| 2216 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 2217 | &frev, &crev, &data_offset)) { |
| 2218 | firmware_info = |
| 2219 | (union firmware_info *)(mode_info->atom_context->bios + |
| 2220 | data_offset); |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 2221 | *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); |
| 2222 | if ((frev == 2) && (crev >= 2)) |
| 2223 | *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2224 | } |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2225 | } |
| 2226 | |
| 2227 | static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, |
| 2228 | int state_index, int mode_index, |
| 2229 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) |
| 2230 | { |
| 2231 | int j; |
| 2232 | u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); |
| 2233 | u32 misc2 = le16_to_cpu(non_clock_info->usClassification); |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 2234 | u16 vddc, vddci; |
| 2235 | |
| 2236 | radeon_atombios_get_default_voltages(rdev, &vddc, &vddci); |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2237 | |
| 2238 | rdev->pm.power_state[state_index].misc = misc; |
| 2239 | rdev->pm.power_state[state_index].misc2 = misc2; |
| 2240 | rdev->pm.power_state[state_index].pcie_lanes = |
| 2241 | ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> |
| 2242 | ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; |
| 2243 | switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { |
| 2244 | case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: |
| 2245 | rdev->pm.power_state[state_index].type = |
| 2246 | POWER_STATE_TYPE_BATTERY; |
| 2247 | break; |
| 2248 | case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: |
| 2249 | rdev->pm.power_state[state_index].type = |
| 2250 | POWER_STATE_TYPE_BALANCED; |
| 2251 | break; |
| 2252 | case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: |
| 2253 | rdev->pm.power_state[state_index].type = |
| 2254 | POWER_STATE_TYPE_PERFORMANCE; |
| 2255 | break; |
| 2256 | case ATOM_PPLIB_CLASSIFICATION_UI_NONE: |
| 2257 | if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) |
| 2258 | rdev->pm.power_state[state_index].type = |
| 2259 | POWER_STATE_TYPE_PERFORMANCE; |
| 2260 | break; |
| 2261 | } |
| 2262 | rdev->pm.power_state[state_index].flags = 0; |
| 2263 | if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) |
| 2264 | rdev->pm.power_state[state_index].flags |= |
| 2265 | RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
| 2266 | if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { |
| 2267 | rdev->pm.power_state[state_index].type = |
| 2268 | POWER_STATE_TYPE_DEFAULT; |
| 2269 | rdev->pm.default_power_state_index = state_index; |
| 2270 | rdev->pm.power_state[state_index].default_clock_mode = |
| 2271 | &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; |
Alex Deucher | 8f3f1c9 | 2011-11-04 10:09:43 -0400 | [diff] [blame] | 2272 | if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) { |
Alex Deucher | 9ace9f7 | 2011-01-06 21:19:26 -0500 | [diff] [blame] | 2273 | /* NI chips post without MC ucode, so default clocks are strobe mode only */ |
| 2274 | rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; |
| 2275 | rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; |
| 2276 | rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 2277 | rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; |
Alex Deucher | 9ace9f7 | 2011-01-06 21:19:26 -0500 | [diff] [blame] | 2278 | } else { |
| 2279 | /* patch the table values with the default slck/mclk from firmware info */ |
| 2280 | for (j = 0; j < mode_index; j++) { |
| 2281 | rdev->pm.power_state[state_index].clock_info[j].mclk = |
| 2282 | rdev->clock.default_mclk; |
| 2283 | rdev->pm.power_state[state_index].clock_info[j].sclk = |
| 2284 | rdev->clock.default_sclk; |
| 2285 | if (vddc) |
| 2286 | rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = |
| 2287 | vddc; |
| 2288 | } |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2289 | } |
| 2290 | } |
| 2291 | } |
| 2292 | |
| 2293 | static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, |
| 2294 | int state_index, int mode_index, |
| 2295 | union pplib_clock_info *clock_info) |
| 2296 | { |
| 2297 | u32 sclk, mclk; |
Alex Deucher | e83753b | 2012-03-20 17:18:08 -0400 | [diff] [blame] | 2298 | u16 vddc; |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2299 | |
| 2300 | if (rdev->flags & RADEON_IS_IGP) { |
Alex Deucher | b0e6641 | 2010-11-22 17:56:35 -0500 | [diff] [blame] | 2301 | if (rdev->family >= CHIP_PALM) { |
| 2302 | sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); |
| 2303 | sclk |= clock_info->sumo.ucEngineClockHigh << 16; |
| 2304 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; |
| 2305 | } else { |
| 2306 | sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); |
| 2307 | sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; |
| 2308 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; |
| 2309 | } |
Alex Deucher | 14607d0 | 2012-03-20 17:18:09 -0400 | [diff] [blame^] | 2310 | } else if (ASIC_IS_DCE6(rdev)) { |
| 2311 | sclk = le16_to_cpu(clock_info->si.usEngineClockLow); |
| 2312 | sclk |= clock_info->si.ucEngineClockHigh << 16; |
| 2313 | mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); |
| 2314 | mclk |= clock_info->si.ucMemoryClockHigh << 16; |
| 2315 | rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; |
| 2316 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; |
| 2317 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = |
| 2318 | VOLTAGE_SW; |
| 2319 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = |
| 2320 | le16_to_cpu(clock_info->si.usVDDC); |
| 2321 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = |
| 2322 | le16_to_cpu(clock_info->si.usVDDCI); |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2323 | } else if (ASIC_IS_DCE4(rdev)) { |
| 2324 | sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); |
| 2325 | sclk |= clock_info->evergreen.ucEngineClockHigh << 16; |
| 2326 | mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); |
| 2327 | mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; |
| 2328 | rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; |
| 2329 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; |
| 2330 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = |
| 2331 | VOLTAGE_SW; |
| 2332 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 2333 | le16_to_cpu(clock_info->evergreen.usVDDC); |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 2334 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = |
| 2335 | le16_to_cpu(clock_info->evergreen.usVDDCI); |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2336 | } else { |
| 2337 | sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); |
| 2338 | sclk |= clock_info->r600.ucEngineClockHigh << 16; |
| 2339 | mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); |
| 2340 | mclk |= clock_info->r600.ucMemoryClockHigh << 16; |
| 2341 | rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; |
| 2342 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; |
| 2343 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = |
| 2344 | VOLTAGE_SW; |
| 2345 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 2346 | le16_to_cpu(clock_info->r600.usVDDC); |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2347 | } |
| 2348 | |
Alex Deucher | ee4017f | 2011-06-23 12:19:32 -0400 | [diff] [blame] | 2349 | /* patch up vddc if necessary */ |
Alex Deucher | e83753b | 2012-03-20 17:18:08 -0400 | [diff] [blame] | 2350 | switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) { |
| 2351 | case ATOM_VIRTUAL_VOLTAGE_ID0: |
| 2352 | case ATOM_VIRTUAL_VOLTAGE_ID1: |
| 2353 | case ATOM_VIRTUAL_VOLTAGE_ID2: |
| 2354 | case ATOM_VIRTUAL_VOLTAGE_ID3: |
| 2355 | if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, |
| 2356 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage, |
| 2357 | &vddc) == 0) |
Alex Deucher | ee4017f | 2011-06-23 12:19:32 -0400 | [diff] [blame] | 2358 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; |
Alex Deucher | e83753b | 2012-03-20 17:18:08 -0400 | [diff] [blame] | 2359 | break; |
| 2360 | default: |
| 2361 | break; |
Alex Deucher | ee4017f | 2011-06-23 12:19:32 -0400 | [diff] [blame] | 2362 | } |
| 2363 | |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2364 | if (rdev->flags & RADEON_IS_IGP) { |
| 2365 | /* skip invalid modes */ |
| 2366 | if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) |
| 2367 | return false; |
| 2368 | } else { |
| 2369 | /* skip invalid modes */ |
| 2370 | if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || |
| 2371 | (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) |
| 2372 | return false; |
| 2373 | } |
| 2374 | return true; |
| 2375 | } |
| 2376 | |
| 2377 | static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) |
| 2378 | { |
| 2379 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 2380 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; |
| 2381 | union pplib_power_state *power_state; |
| 2382 | int i, j; |
| 2383 | int state_index = 0, mode_index = 0; |
| 2384 | union pplib_clock_info *clock_info; |
| 2385 | bool valid; |
| 2386 | union power_info *power_info; |
| 2387 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); |
| 2388 | u16 data_offset; |
| 2389 | u8 frev, crev; |
| 2390 | |
| 2391 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 2392 | &frev, &crev, &data_offset)) |
| 2393 | return state_index; |
| 2394 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); |
| 2395 | |
| 2396 | radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); |
Alex Deucher | 0975b16 | 2011-02-02 18:42:03 -0500 | [diff] [blame] | 2397 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * |
| 2398 | power_info->pplib.ucNumStates, GFP_KERNEL); |
| 2399 | if (!rdev->pm.power_state) |
| 2400 | return state_index; |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2401 | /* first mode is usually default, followed by low to high */ |
| 2402 | for (i = 0; i < power_info->pplib.ucNumStates; i++) { |
| 2403 | mode_index = 0; |
| 2404 | power_state = (union pplib_power_state *) |
| 2405 | (mode_info->atom_context->bios + data_offset + |
| 2406 | le16_to_cpu(power_info->pplib.usStateArrayOffset) + |
| 2407 | i * power_info->pplib.ucStateEntrySize); |
| 2408 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) |
| 2409 | (mode_info->atom_context->bios + data_offset + |
| 2410 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + |
| 2411 | (power_state->v1.ucNonClockStateIndex * |
| 2412 | power_info->pplib.ucNonClockSize)); |
Alex Deucher | 8f3f1c9 | 2011-11-04 10:09:43 -0400 | [diff] [blame] | 2413 | rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * |
| 2414 | ((power_info->pplib.ucStateEntrySize - 1) ? |
| 2415 | (power_info->pplib.ucStateEntrySize - 1) : 1), |
| 2416 | GFP_KERNEL); |
| 2417 | if (!rdev->pm.power_state[i].clock_info) |
| 2418 | return state_index; |
| 2419 | if (power_info->pplib.ucStateEntrySize - 1) { |
| 2420 | for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { |
| 2421 | clock_info = (union pplib_clock_info *) |
| 2422 | (mode_info->atom_context->bios + data_offset + |
| 2423 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + |
| 2424 | (power_state->v1.ucClockStateIndices[j] * |
| 2425 | power_info->pplib.ucClockInfoSize)); |
| 2426 | valid = radeon_atombios_parse_pplib_clock_info(rdev, |
| 2427 | state_index, mode_index, |
| 2428 | clock_info); |
| 2429 | if (valid) |
| 2430 | mode_index++; |
| 2431 | } |
| 2432 | } else { |
| 2433 | rdev->pm.power_state[state_index].clock_info[0].mclk = |
| 2434 | rdev->clock.default_mclk; |
| 2435 | rdev->pm.power_state[state_index].clock_info[0].sclk = |
| 2436 | rdev->clock.default_sclk; |
| 2437 | mode_index++; |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2438 | } |
| 2439 | rdev->pm.power_state[state_index].num_clock_modes = mode_index; |
| 2440 | if (mode_index) { |
| 2441 | radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, |
| 2442 | non_clock_info); |
| 2443 | state_index++; |
| 2444 | } |
| 2445 | } |
| 2446 | /* if multiple clock modes, mark the lowest as no display */ |
| 2447 | for (i = 0; i < state_index; i++) { |
| 2448 | if (rdev->pm.power_state[i].num_clock_modes > 1) |
| 2449 | rdev->pm.power_state[i].clock_info[0].flags |= |
| 2450 | RADEON_PM_MODE_NO_DISPLAY; |
| 2451 | } |
| 2452 | /* first mode is usually default */ |
| 2453 | if (rdev->pm.default_power_state_index == -1) { |
| 2454 | rdev->pm.power_state[0].type = |
| 2455 | POWER_STATE_TYPE_DEFAULT; |
| 2456 | rdev->pm.default_power_state_index = 0; |
| 2457 | rdev->pm.power_state[0].default_clock_mode = |
| 2458 | &rdev->pm.power_state[0].clock_info[0]; |
| 2459 | } |
| 2460 | return state_index; |
| 2461 | } |
| 2462 | |
Alex Deucher | b0e6641 | 2010-11-22 17:56:35 -0500 | [diff] [blame] | 2463 | static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) |
| 2464 | { |
| 2465 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 2466 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; |
| 2467 | union pplib_power_state *power_state; |
| 2468 | int i, j, non_clock_array_index, clock_array_index; |
| 2469 | int state_index = 0, mode_index = 0; |
| 2470 | union pplib_clock_info *clock_info; |
Alex Deucher | f734688 | 2012-03-20 17:17:58 -0400 | [diff] [blame] | 2471 | struct _StateArray *state_array; |
| 2472 | struct _ClockInfoArray *clock_info_array; |
| 2473 | struct _NonClockInfoArray *non_clock_info_array; |
Alex Deucher | b0e6641 | 2010-11-22 17:56:35 -0500 | [diff] [blame] | 2474 | bool valid; |
| 2475 | union power_info *power_info; |
| 2476 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); |
| 2477 | u16 data_offset; |
| 2478 | u8 frev, crev; |
| 2479 | |
| 2480 | if (!atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 2481 | &frev, &crev, &data_offset)) |
| 2482 | return state_index; |
| 2483 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); |
| 2484 | |
| 2485 | radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); |
Alex Deucher | f734688 | 2012-03-20 17:17:58 -0400 | [diff] [blame] | 2486 | state_array = (struct _StateArray *) |
Alex Deucher | b0e6641 | 2010-11-22 17:56:35 -0500 | [diff] [blame] | 2487 | (mode_info->atom_context->bios + data_offset + |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 2488 | le16_to_cpu(power_info->pplib.usStateArrayOffset)); |
Alex Deucher | f734688 | 2012-03-20 17:17:58 -0400 | [diff] [blame] | 2489 | clock_info_array = (struct _ClockInfoArray *) |
Alex Deucher | b0e6641 | 2010-11-22 17:56:35 -0500 | [diff] [blame] | 2490 | (mode_info->atom_context->bios + data_offset + |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 2491 | le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); |
Alex Deucher | f734688 | 2012-03-20 17:17:58 -0400 | [diff] [blame] | 2492 | non_clock_info_array = (struct _NonClockInfoArray *) |
Alex Deucher | b0e6641 | 2010-11-22 17:56:35 -0500 | [diff] [blame] | 2493 | (mode_info->atom_context->bios + data_offset + |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 2494 | le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); |
Alex Deucher | 0975b16 | 2011-02-02 18:42:03 -0500 | [diff] [blame] | 2495 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * |
| 2496 | state_array->ucNumEntries, GFP_KERNEL); |
| 2497 | if (!rdev->pm.power_state) |
| 2498 | return state_index; |
Alex Deucher | b0e6641 | 2010-11-22 17:56:35 -0500 | [diff] [blame] | 2499 | for (i = 0; i < state_array->ucNumEntries; i++) { |
| 2500 | mode_index = 0; |
| 2501 | power_state = (union pplib_power_state *)&state_array->states[i]; |
| 2502 | /* XXX this might be an inagua bug... */ |
| 2503 | non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */ |
| 2504 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) |
| 2505 | &non_clock_info_array->nonClockInfo[non_clock_array_index]; |
Alex Deucher | 8f3f1c9 | 2011-11-04 10:09:43 -0400 | [diff] [blame] | 2506 | rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * |
| 2507 | (power_state->v2.ucNumDPMLevels ? |
| 2508 | power_state->v2.ucNumDPMLevels : 1), |
| 2509 | GFP_KERNEL); |
| 2510 | if (!rdev->pm.power_state[i].clock_info) |
| 2511 | return state_index; |
| 2512 | if (power_state->v2.ucNumDPMLevels) { |
| 2513 | for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { |
| 2514 | clock_array_index = power_state->v2.clockInfoIndex[j]; |
| 2515 | /* XXX this might be an inagua bug... */ |
| 2516 | if (clock_array_index >= clock_info_array->ucNumEntries) |
| 2517 | continue; |
| 2518 | clock_info = (union pplib_clock_info *) |
Alex Deucher | f734688 | 2012-03-20 17:17:58 -0400 | [diff] [blame] | 2519 | &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; |
Alex Deucher | 8f3f1c9 | 2011-11-04 10:09:43 -0400 | [diff] [blame] | 2520 | valid = radeon_atombios_parse_pplib_clock_info(rdev, |
| 2521 | state_index, mode_index, |
| 2522 | clock_info); |
| 2523 | if (valid) |
| 2524 | mode_index++; |
| 2525 | } |
| 2526 | } else { |
| 2527 | rdev->pm.power_state[state_index].clock_info[0].mclk = |
| 2528 | rdev->clock.default_mclk; |
| 2529 | rdev->pm.power_state[state_index].clock_info[0].sclk = |
| 2530 | rdev->clock.default_sclk; |
| 2531 | mode_index++; |
Alex Deucher | b0e6641 | 2010-11-22 17:56:35 -0500 | [diff] [blame] | 2532 | } |
| 2533 | rdev->pm.power_state[state_index].num_clock_modes = mode_index; |
| 2534 | if (mode_index) { |
| 2535 | radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, |
| 2536 | non_clock_info); |
| 2537 | state_index++; |
| 2538 | } |
| 2539 | } |
| 2540 | /* if multiple clock modes, mark the lowest as no display */ |
| 2541 | for (i = 0; i < state_index; i++) { |
| 2542 | if (rdev->pm.power_state[i].num_clock_modes > 1) |
| 2543 | rdev->pm.power_state[i].clock_info[0].flags |= |
| 2544 | RADEON_PM_MODE_NO_DISPLAY; |
| 2545 | } |
| 2546 | /* first mode is usually default */ |
| 2547 | if (rdev->pm.default_power_state_index == -1) { |
| 2548 | rdev->pm.power_state[0].type = |
| 2549 | POWER_STATE_TYPE_DEFAULT; |
| 2550 | rdev->pm.default_power_state_index = 0; |
| 2551 | rdev->pm.power_state[0].default_clock_mode = |
| 2552 | &rdev->pm.power_state[0].clock_info[0]; |
| 2553 | } |
| 2554 | return state_index; |
| 2555 | } |
| 2556 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2557 | void radeon_atombios_get_power_modes(struct radeon_device *rdev) |
| 2558 | { |
| 2559 | struct radeon_mode_info *mode_info = &rdev->mode_info; |
| 2560 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); |
| 2561 | u16 data_offset; |
| 2562 | u8 frev, crev; |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2563 | int state_index = 0; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2564 | |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 2565 | rdev->pm.default_power_state_index = -1; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2566 | |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 2567 | if (atom_parse_data_header(mode_info->atom_context, index, NULL, |
| 2568 | &frev, &crev, &data_offset)) { |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2569 | switch (frev) { |
| 2570 | case 1: |
| 2571 | case 2: |
| 2572 | case 3: |
| 2573 | state_index = radeon_atombios_parse_power_table_1_3(rdev); |
| 2574 | break; |
| 2575 | case 4: |
| 2576 | case 5: |
| 2577 | state_index = radeon_atombios_parse_power_table_4_5(rdev); |
| 2578 | break; |
Alex Deucher | b0e6641 | 2010-11-22 17:56:35 -0500 | [diff] [blame] | 2579 | case 6: |
| 2580 | state_index = radeon_atombios_parse_power_table_6(rdev); |
| 2581 | break; |
Alex Deucher | 560154e | 2010-11-22 17:56:34 -0500 | [diff] [blame] | 2582 | default: |
| 2583 | break; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2584 | } |
| 2585 | } else { |
Alex Deucher | 0975b16 | 2011-02-02 18:42:03 -0500 | [diff] [blame] | 2586 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); |
| 2587 | if (rdev->pm.power_state) { |
Alex Deucher | 8f3f1c9 | 2011-11-04 10:09:43 -0400 | [diff] [blame] | 2588 | rdev->pm.power_state[0].clock_info = |
| 2589 | kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); |
| 2590 | if (rdev->pm.power_state[0].clock_info) { |
| 2591 | /* add the default mode */ |
| 2592 | rdev->pm.power_state[state_index].type = |
| 2593 | POWER_STATE_TYPE_DEFAULT; |
| 2594 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
| 2595 | rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; |
| 2596 | rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; |
| 2597 | rdev->pm.power_state[state_index].default_clock_mode = |
| 2598 | &rdev->pm.power_state[state_index].clock_info[0]; |
| 2599 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
| 2600 | rdev->pm.power_state[state_index].pcie_lanes = 16; |
| 2601 | rdev->pm.default_power_state_index = state_index; |
| 2602 | rdev->pm.power_state[state_index].flags = 0; |
| 2603 | state_index++; |
| 2604 | } |
Alex Deucher | 0975b16 | 2011-02-02 18:42:03 -0500 | [diff] [blame] | 2605 | } |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2606 | } |
Alex Deucher | 02b17cc | 2010-04-22 13:25:06 -0400 | [diff] [blame] | 2607 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2608 | rdev->pm.num_power_states = state_index; |
Rafał Miłecki | 9038dfd | 2010-02-20 23:15:04 +0000 | [diff] [blame] | 2609 | |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 2610 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
| 2611 | rdev->pm.current_clock_mode_index = 0; |
Alexander Müller | 4376eee | 2011-12-30 12:55:48 -0500 | [diff] [blame] | 2612 | if (rdev->pm.default_power_state_index >= 0) |
| 2613 | rdev->pm.current_vddc = |
| 2614 | rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; |
| 2615 | else |
| 2616 | rdev->pm.current_vddc = 0; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 2617 | } |
| 2618 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2619 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) |
| 2620 | { |
| 2621 | DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; |
| 2622 | int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); |
| 2623 | |
| 2624 | args.ucEnable = enable; |
| 2625 | |
| 2626 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 2627 | } |
| 2628 | |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 2629 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) |
| 2630 | { |
| 2631 | GET_ENGINE_CLOCK_PS_ALLOCATION args; |
| 2632 | int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); |
| 2633 | |
| 2634 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 2635 | return le32_to_cpu(args.ulReturnEngineClock); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 2636 | } |
| 2637 | |
| 2638 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) |
| 2639 | { |
| 2640 | GET_MEMORY_CLOCK_PS_ALLOCATION args; |
| 2641 | int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); |
| 2642 | |
| 2643 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 2644 | return le32_to_cpu(args.ulReturnMemoryClock); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 2645 | } |
| 2646 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2647 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, |
| 2648 | uint32_t eng_clock) |
| 2649 | { |
| 2650 | SET_ENGINE_CLOCK_PS_ALLOCATION args; |
| 2651 | int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); |
| 2652 | |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 2653 | args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2654 | |
| 2655 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 2656 | } |
| 2657 | |
| 2658 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, |
| 2659 | uint32_t mem_clock) |
| 2660 | { |
| 2661 | SET_MEMORY_CLOCK_PS_ALLOCATION args; |
| 2662 | int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); |
| 2663 | |
| 2664 | if (rdev->flags & RADEON_IS_IGP) |
| 2665 | return; |
| 2666 | |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 2667 | args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2668 | |
| 2669 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 2670 | } |
| 2671 | |
Alex Deucher | 7ac9aa5 | 2010-05-27 19:25:54 -0400 | [diff] [blame] | 2672 | union set_voltage { |
| 2673 | struct _SET_VOLTAGE_PS_ALLOCATION alloc; |
| 2674 | struct _SET_VOLTAGE_PARAMETERS v1; |
| 2675 | struct _SET_VOLTAGE_PARAMETERS_V2 v2; |
Alex Deucher | e83753b | 2012-03-20 17:18:08 -0400 | [diff] [blame] | 2676 | struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; |
Alex Deucher | 7ac9aa5 | 2010-05-27 19:25:54 -0400 | [diff] [blame] | 2677 | }; |
| 2678 | |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 2679 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) |
Alex Deucher | 7ac9aa5 | 2010-05-27 19:25:54 -0400 | [diff] [blame] | 2680 | { |
| 2681 | union set_voltage args; |
| 2682 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 2683 | u8 frev, crev, volt_index = voltage_level; |
Alex Deucher | 7ac9aa5 | 2010-05-27 19:25:54 -0400 | [diff] [blame] | 2684 | |
| 2685 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
| 2686 | return; |
| 2687 | |
Alex Deucher | a377e18 | 2011-06-20 13:00:31 -0400 | [diff] [blame] | 2688 | /* 0xff01 is a flag rather then an actual voltage */ |
| 2689 | if (voltage_level == 0xff01) |
| 2690 | return; |
| 2691 | |
Alex Deucher | 7ac9aa5 | 2010-05-27 19:25:54 -0400 | [diff] [blame] | 2692 | switch (crev) { |
| 2693 | case 1: |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 2694 | args.v1.ucVoltageType = voltage_type; |
Alex Deucher | 7ac9aa5 | 2010-05-27 19:25:54 -0400 | [diff] [blame] | 2695 | args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; |
| 2696 | args.v1.ucVoltageIndex = volt_index; |
| 2697 | break; |
| 2698 | case 2: |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 2699 | args.v2.ucVoltageType = voltage_type; |
Alex Deucher | 7ac9aa5 | 2010-05-27 19:25:54 -0400 | [diff] [blame] | 2700 | args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 2701 | args.v2.usVoltageLevel = cpu_to_le16(voltage_level); |
Alex Deucher | 7ac9aa5 | 2010-05-27 19:25:54 -0400 | [diff] [blame] | 2702 | break; |
Alex Deucher | e83753b | 2012-03-20 17:18:08 -0400 | [diff] [blame] | 2703 | case 3: |
| 2704 | args.v3.ucVoltageType = voltage_type; |
| 2705 | args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; |
| 2706 | args.v3.usVoltageLevel = cpu_to_le16(voltage_level); |
| 2707 | break; |
Alex Deucher | 7ac9aa5 | 2010-05-27 19:25:54 -0400 | [diff] [blame] | 2708 | default: |
| 2709 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
| 2710 | return; |
| 2711 | } |
| 2712 | |
| 2713 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 2714 | } |
| 2715 | |
Alex Deucher | e83753b | 2012-03-20 17:18:08 -0400 | [diff] [blame] | 2716 | static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
| 2717 | u16 voltage_id, u16 *voltage) |
Alex Deucher | ee4017f | 2011-06-23 12:19:32 -0400 | [diff] [blame] | 2718 | { |
| 2719 | union set_voltage args; |
| 2720 | int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); |
| 2721 | u8 frev, crev; |
Alex Deucher | 7ac9aa5 | 2010-05-27 19:25:54 -0400 | [diff] [blame] | 2722 | |
Alex Deucher | ee4017f | 2011-06-23 12:19:32 -0400 | [diff] [blame] | 2723 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
| 2724 | return -EINVAL; |
| 2725 | |
| 2726 | switch (crev) { |
| 2727 | case 1: |
| 2728 | return -EINVAL; |
| 2729 | case 2: |
| 2730 | args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; |
| 2731 | args.v2.ucVoltageMode = 0; |
| 2732 | args.v2.usVoltageLevel = 0; |
| 2733 | |
| 2734 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 2735 | |
| 2736 | *voltage = le16_to_cpu(args.v2.usVoltageLevel); |
| 2737 | break; |
Alex Deucher | e83753b | 2012-03-20 17:18:08 -0400 | [diff] [blame] | 2738 | case 3: |
| 2739 | args.v3.ucVoltageType = voltage_type; |
| 2740 | args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; |
| 2741 | args.v3.usVoltageLevel = cpu_to_le16(voltage_id); |
| 2742 | |
| 2743 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 2744 | |
| 2745 | *voltage = le16_to_cpu(args.v3.usVoltageLevel); |
| 2746 | break; |
Alex Deucher | ee4017f | 2011-06-23 12:19:32 -0400 | [diff] [blame] | 2747 | default: |
| 2748 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
| 2749 | return -EINVAL; |
| 2750 | } |
| 2751 | |
| 2752 | return 0; |
| 2753 | } |
Alex Deucher | 7ac9aa5 | 2010-05-27 19:25:54 -0400 | [diff] [blame] | 2754 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2755 | void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) |
| 2756 | { |
| 2757 | struct radeon_device *rdev = dev->dev_private; |
| 2758 | uint32_t bios_2_scratch, bios_6_scratch; |
| 2759 | |
| 2760 | if (rdev->family >= CHIP_R600) { |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 2761 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2762 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
| 2763 | } else { |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 2764 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2765 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
| 2766 | } |
| 2767 | |
| 2768 | /* let the bios control the backlight */ |
| 2769 | bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; |
| 2770 | |
| 2771 | /* tell the bios not to handle mode switching */ |
Alex Deucher | 8736476 | 2011-02-02 19:46:06 -0500 | [diff] [blame] | 2772 | bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2773 | |
| 2774 | if (rdev->family >= CHIP_R600) { |
| 2775 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); |
| 2776 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
| 2777 | } else { |
| 2778 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); |
| 2779 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
| 2780 | } |
| 2781 | |
| 2782 | } |
| 2783 | |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 2784 | void radeon_save_bios_scratch_regs(struct radeon_device *rdev) |
| 2785 | { |
| 2786 | uint32_t scratch_reg; |
| 2787 | int i; |
| 2788 | |
| 2789 | if (rdev->family >= CHIP_R600) |
| 2790 | scratch_reg = R600_BIOS_0_SCRATCH; |
| 2791 | else |
| 2792 | scratch_reg = RADEON_BIOS_0_SCRATCH; |
| 2793 | |
| 2794 | for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) |
| 2795 | rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); |
| 2796 | } |
| 2797 | |
| 2798 | void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) |
| 2799 | { |
| 2800 | uint32_t scratch_reg; |
| 2801 | int i; |
| 2802 | |
| 2803 | if (rdev->family >= CHIP_R600) |
| 2804 | scratch_reg = R600_BIOS_0_SCRATCH; |
| 2805 | else |
| 2806 | scratch_reg = RADEON_BIOS_0_SCRATCH; |
| 2807 | |
| 2808 | for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) |
| 2809 | WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); |
| 2810 | } |
| 2811 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2812 | void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) |
| 2813 | { |
| 2814 | struct drm_device *dev = encoder->dev; |
| 2815 | struct radeon_device *rdev = dev->dev_private; |
| 2816 | uint32_t bios_6_scratch; |
| 2817 | |
| 2818 | if (rdev->family >= CHIP_R600) |
| 2819 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
| 2820 | else |
| 2821 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
| 2822 | |
Alex Deucher | 8736476 | 2011-02-02 19:46:06 -0500 | [diff] [blame] | 2823 | if (lock) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2824 | bios_6_scratch |= ATOM_S6_CRITICAL_STATE; |
Alex Deucher | 8736476 | 2011-02-02 19:46:06 -0500 | [diff] [blame] | 2825 | bios_6_scratch &= ~ATOM_S6_ACC_MODE; |
| 2826 | } else { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2827 | bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; |
Alex Deucher | 8736476 | 2011-02-02 19:46:06 -0500 | [diff] [blame] | 2828 | bios_6_scratch |= ATOM_S6_ACC_MODE; |
| 2829 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2830 | |
| 2831 | if (rdev->family >= CHIP_R600) |
| 2832 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
| 2833 | else |
| 2834 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
| 2835 | } |
| 2836 | |
| 2837 | /* at some point we may want to break this out into individual functions */ |
| 2838 | void |
| 2839 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, |
| 2840 | struct drm_encoder *encoder, |
| 2841 | bool connected) |
| 2842 | { |
| 2843 | struct drm_device *dev = connector->dev; |
| 2844 | struct radeon_device *rdev = dev->dev_private; |
| 2845 | struct radeon_connector *radeon_connector = |
| 2846 | to_radeon_connector(connector); |
| 2847 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 2848 | uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; |
| 2849 | |
| 2850 | if (rdev->family >= CHIP_R600) { |
| 2851 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
| 2852 | bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); |
| 2853 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
| 2854 | } else { |
| 2855 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
| 2856 | bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); |
| 2857 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
| 2858 | } |
| 2859 | |
| 2860 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && |
| 2861 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { |
| 2862 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2863 | DRM_DEBUG_KMS("TV1 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2864 | bios_3_scratch |= ATOM_S3_TV1_ACTIVE; |
| 2865 | bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; |
| 2866 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2867 | DRM_DEBUG_KMS("TV1 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2868 | bios_0_scratch &= ~ATOM_S0_TV1_MASK; |
| 2869 | bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; |
| 2870 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; |
| 2871 | } |
| 2872 | } |
| 2873 | if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && |
| 2874 | (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { |
| 2875 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2876 | DRM_DEBUG_KMS("CV connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2877 | bios_3_scratch |= ATOM_S3_CV_ACTIVE; |
| 2878 | bios_6_scratch |= ATOM_S6_ACC_REQ_CV; |
| 2879 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2880 | DRM_DEBUG_KMS("CV disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2881 | bios_0_scratch &= ~ATOM_S0_CV_MASK; |
| 2882 | bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; |
| 2883 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; |
| 2884 | } |
| 2885 | } |
| 2886 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && |
| 2887 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { |
| 2888 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2889 | DRM_DEBUG_KMS("LCD1 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2890 | bios_0_scratch |= ATOM_S0_LCD1; |
| 2891 | bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; |
| 2892 | bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; |
| 2893 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2894 | DRM_DEBUG_KMS("LCD1 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2895 | bios_0_scratch &= ~ATOM_S0_LCD1; |
| 2896 | bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; |
| 2897 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; |
| 2898 | } |
| 2899 | } |
| 2900 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && |
| 2901 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { |
| 2902 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2903 | DRM_DEBUG_KMS("CRT1 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2904 | bios_0_scratch |= ATOM_S0_CRT1_COLOR; |
| 2905 | bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; |
| 2906 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; |
| 2907 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2908 | DRM_DEBUG_KMS("CRT1 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2909 | bios_0_scratch &= ~ATOM_S0_CRT1_MASK; |
| 2910 | bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; |
| 2911 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; |
| 2912 | } |
| 2913 | } |
| 2914 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && |
| 2915 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { |
| 2916 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2917 | DRM_DEBUG_KMS("CRT2 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2918 | bios_0_scratch |= ATOM_S0_CRT2_COLOR; |
| 2919 | bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; |
| 2920 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; |
| 2921 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2922 | DRM_DEBUG_KMS("CRT2 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2923 | bios_0_scratch &= ~ATOM_S0_CRT2_MASK; |
| 2924 | bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; |
| 2925 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; |
| 2926 | } |
| 2927 | } |
| 2928 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && |
| 2929 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { |
| 2930 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2931 | DRM_DEBUG_KMS("DFP1 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2932 | bios_0_scratch |= ATOM_S0_DFP1; |
| 2933 | bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; |
| 2934 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; |
| 2935 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2936 | DRM_DEBUG_KMS("DFP1 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2937 | bios_0_scratch &= ~ATOM_S0_DFP1; |
| 2938 | bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; |
| 2939 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; |
| 2940 | } |
| 2941 | } |
| 2942 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && |
| 2943 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
| 2944 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2945 | DRM_DEBUG_KMS("DFP2 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2946 | bios_0_scratch |= ATOM_S0_DFP2; |
| 2947 | bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; |
| 2948 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; |
| 2949 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2950 | DRM_DEBUG_KMS("DFP2 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2951 | bios_0_scratch &= ~ATOM_S0_DFP2; |
| 2952 | bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; |
| 2953 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; |
| 2954 | } |
| 2955 | } |
| 2956 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && |
| 2957 | (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { |
| 2958 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2959 | DRM_DEBUG_KMS("DFP3 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2960 | bios_0_scratch |= ATOM_S0_DFP3; |
| 2961 | bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; |
| 2962 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; |
| 2963 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2964 | DRM_DEBUG_KMS("DFP3 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2965 | bios_0_scratch &= ~ATOM_S0_DFP3; |
| 2966 | bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; |
| 2967 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; |
| 2968 | } |
| 2969 | } |
| 2970 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && |
| 2971 | (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { |
| 2972 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2973 | DRM_DEBUG_KMS("DFP4 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2974 | bios_0_scratch |= ATOM_S0_DFP4; |
| 2975 | bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; |
| 2976 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; |
| 2977 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2978 | DRM_DEBUG_KMS("DFP4 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2979 | bios_0_scratch &= ~ATOM_S0_DFP4; |
| 2980 | bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; |
| 2981 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; |
| 2982 | } |
| 2983 | } |
| 2984 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && |
| 2985 | (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { |
| 2986 | if (connected) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2987 | DRM_DEBUG_KMS("DFP5 connected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2988 | bios_0_scratch |= ATOM_S0_DFP5; |
| 2989 | bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; |
| 2990 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; |
| 2991 | } else { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 2992 | DRM_DEBUG_KMS("DFP5 disconnected\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2993 | bios_0_scratch &= ~ATOM_S0_DFP5; |
| 2994 | bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; |
| 2995 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; |
| 2996 | } |
| 2997 | } |
Alex Deucher | 6f9f8a6 | 2012-02-13 08:59:41 -0500 | [diff] [blame] | 2998 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) && |
| 2999 | (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) { |
| 3000 | if (connected) { |
| 3001 | DRM_DEBUG_KMS("DFP6 connected\n"); |
| 3002 | bios_0_scratch |= ATOM_S0_DFP6; |
| 3003 | bios_3_scratch |= ATOM_S3_DFP6_ACTIVE; |
| 3004 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6; |
| 3005 | } else { |
| 3006 | DRM_DEBUG_KMS("DFP6 disconnected\n"); |
| 3007 | bios_0_scratch &= ~ATOM_S0_DFP6; |
| 3008 | bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE; |
| 3009 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6; |
| 3010 | } |
| 3011 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3012 | |
| 3013 | if (rdev->family >= CHIP_R600) { |
| 3014 | WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); |
| 3015 | WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); |
| 3016 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
| 3017 | } else { |
| 3018 | WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); |
| 3019 | WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); |
| 3020 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
| 3021 | } |
| 3022 | } |
| 3023 | |
| 3024 | void |
| 3025 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) |
| 3026 | { |
| 3027 | struct drm_device *dev = encoder->dev; |
| 3028 | struct radeon_device *rdev = dev->dev_private; |
| 3029 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 3030 | uint32_t bios_3_scratch; |
| 3031 | |
Alex Deucher | 6f9f8a6 | 2012-02-13 08:59:41 -0500 | [diff] [blame] | 3032 | if (ASIC_IS_DCE4(rdev)) |
| 3033 | return; |
| 3034 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3035 | if (rdev->family >= CHIP_R600) |
| 3036 | bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); |
| 3037 | else |
| 3038 | bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); |
| 3039 | |
| 3040 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
| 3041 | bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; |
| 3042 | bios_3_scratch |= (crtc << 18); |
| 3043 | } |
| 3044 | if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { |
| 3045 | bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; |
| 3046 | bios_3_scratch |= (crtc << 24); |
| 3047 | } |
| 3048 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
| 3049 | bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; |
| 3050 | bios_3_scratch |= (crtc << 16); |
| 3051 | } |
| 3052 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
| 3053 | bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; |
| 3054 | bios_3_scratch |= (crtc << 20); |
| 3055 | } |
| 3056 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
| 3057 | bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; |
| 3058 | bios_3_scratch |= (crtc << 17); |
| 3059 | } |
| 3060 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { |
| 3061 | bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; |
| 3062 | bios_3_scratch |= (crtc << 19); |
| 3063 | } |
| 3064 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { |
| 3065 | bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; |
| 3066 | bios_3_scratch |= (crtc << 23); |
| 3067 | } |
| 3068 | if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { |
| 3069 | bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; |
| 3070 | bios_3_scratch |= (crtc << 25); |
| 3071 | } |
| 3072 | |
| 3073 | if (rdev->family >= CHIP_R600) |
| 3074 | WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); |
| 3075 | else |
| 3076 | WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); |
| 3077 | } |
| 3078 | |
| 3079 | void |
| 3080 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) |
| 3081 | { |
| 3082 | struct drm_device *dev = encoder->dev; |
| 3083 | struct radeon_device *rdev = dev->dev_private; |
| 3084 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 3085 | uint32_t bios_2_scratch; |
| 3086 | |
Alex Deucher | 3ac0eb6 | 2012-02-19 21:42:03 -0500 | [diff] [blame] | 3087 | if (ASIC_IS_DCE4(rdev)) |
| 3088 | return; |
| 3089 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 3090 | if (rdev->family >= CHIP_R600) |
| 3091 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
| 3092 | else |
| 3093 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
| 3094 | |
| 3095 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
| 3096 | if (on) |
| 3097 | bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; |
| 3098 | else |
| 3099 | bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; |
| 3100 | } |
| 3101 | if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { |
| 3102 | if (on) |
| 3103 | bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; |
| 3104 | else |
| 3105 | bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; |
| 3106 | } |
| 3107 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
| 3108 | if (on) |
| 3109 | bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; |
| 3110 | else |
| 3111 | bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; |
| 3112 | } |
| 3113 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
| 3114 | if (on) |
| 3115 | bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; |
| 3116 | else |
| 3117 | bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; |
| 3118 | } |
| 3119 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
| 3120 | if (on) |
| 3121 | bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; |
| 3122 | else |
| 3123 | bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; |
| 3124 | } |
| 3125 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { |
| 3126 | if (on) |
| 3127 | bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; |
| 3128 | else |
| 3129 | bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; |
| 3130 | } |
| 3131 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { |
| 3132 | if (on) |
| 3133 | bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; |
| 3134 | else |
| 3135 | bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; |
| 3136 | } |
| 3137 | if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { |
| 3138 | if (on) |
| 3139 | bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; |
| 3140 | else |
| 3141 | bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; |
| 3142 | } |
| 3143 | if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { |
| 3144 | if (on) |
| 3145 | bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; |
| 3146 | else |
| 3147 | bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; |
| 3148 | } |
| 3149 | if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { |
| 3150 | if (on) |
| 3151 | bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; |
| 3152 | else |
| 3153 | bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; |
| 3154 | } |
| 3155 | |
| 3156 | if (rdev->family >= CHIP_R600) |
| 3157 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); |
| 3158 | else |
| 3159 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); |
| 3160 | } |