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AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001/*
2 * QTI CE device driver.
3 *
4 * Copyright (c) 2010-2017, The Linux Foundation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/mman.h>
16#include <linux/types.h>
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
19#include <linux/kernel.h>
20#include <linux/dmapool.h>
21#include <linux/interrupt.h>
22#include <linux/spinlock.h>
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/fs.h>
26#include <linux/miscdevice.h>
27#include <linux/uaccess.h>
28#include <linux/debugfs.h>
29#include <linux/scatterlist.h>
30#include <linux/crypto.h>
31#include <linux/platform_data/qcom_crypto_device.h>
32#include <linux/msm-bus.h>
33#include <linux/qcedev.h>
34
35#include <crypto/hash.h>
36#include "qcedevi.h"
37#include "qce.h"
38
39#include <linux/compat.h>
40#include "compat_qcedev.h"
41
42#define CACHE_LINE_SIZE 32
43#define CE_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE
44
45static uint8_t _std_init_vector_sha1_uint8[] = {
46 0x67, 0x45, 0x23, 0x01, 0xEF, 0xCD, 0xAB, 0x89,
47 0x98, 0xBA, 0xDC, 0xFE, 0x10, 0x32, 0x54, 0x76,
48 0xC3, 0xD2, 0xE1, 0xF0
49};
50/* standard initialization vector for SHA-256, source: FIPS 180-2 */
51static uint8_t _std_init_vector_sha256_uint8[] = {
52 0x6A, 0x09, 0xE6, 0x67, 0xBB, 0x67, 0xAE, 0x85,
53 0x3C, 0x6E, 0xF3, 0x72, 0xA5, 0x4F, 0xF5, 0x3A,
54 0x51, 0x0E, 0x52, 0x7F, 0x9B, 0x05, 0x68, 0x8C,
55 0x1F, 0x83, 0xD9, 0xAB, 0x5B, 0xE0, 0xCD, 0x19
56};
57
58static DEFINE_MUTEX(send_cmd_lock);
59static DEFINE_MUTEX(qcedev_sent_bw_req);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +053060static DEFINE_MUTEX(hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -070061
AnilKumar Chimatae5e60512017-05-03 14:06:59 -070062static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
63{
64 unsigned int control_flag;
65 int ret = 0;
66
67 if (podev->ce_support.req_bw_before_clk) {
68 if (enable)
69 control_flag = QCE_BW_REQUEST_FIRST;
70 else
71 control_flag = QCE_CLK_DISABLE_FIRST;
72 } else {
73 if (enable)
74 control_flag = QCE_CLK_ENABLE_FIRST;
75 else
76 control_flag = QCE_BW_REQUEST_RESET_FIRST;
77 }
78
79 switch (control_flag) {
80 case QCE_CLK_ENABLE_FIRST:
81 ret = qce_enable_clk(podev->qce);
82 if (ret) {
83 pr_err("%s Unable enable clk\n", __func__);
84 return ret;
85 }
86 ret = msm_bus_scale_client_update_request(
87 podev->bus_scale_handle, 1);
88 if (ret) {
89 pr_err("%s Unable to set high bw\n", __func__);
90 ret = qce_disable_clk(podev->qce);
91 if (ret)
92 pr_err("%s Unable disable clk\n", __func__);
93 return ret;
94 }
95 break;
96 case QCE_BW_REQUEST_FIRST:
97 ret = msm_bus_scale_client_update_request(
98 podev->bus_scale_handle, 1);
99 if (ret) {
100 pr_err("%s Unable to set high bw\n", __func__);
101 return ret;
102 }
103 ret = qce_enable_clk(podev->qce);
104 if (ret) {
105 pr_err("%s Unable enable clk\n", __func__);
106 ret = msm_bus_scale_client_update_request(
107 podev->bus_scale_handle, 0);
108 if (ret)
109 pr_err("%s Unable to set low bw\n", __func__);
110 return ret;
111 }
112 break;
113 case QCE_CLK_DISABLE_FIRST:
114 ret = qce_disable_clk(podev->qce);
115 if (ret) {
116 pr_err("%s Unable to disable clk\n", __func__);
117 return ret;
118 }
119 ret = msm_bus_scale_client_update_request(
120 podev->bus_scale_handle, 0);
121 if (ret) {
122 pr_err("%s Unable to set low bw\n", __func__);
123 ret = qce_enable_clk(podev->qce);
124 if (ret)
125 pr_err("%s Unable enable clk\n", __func__);
126 return ret;
127 }
128 break;
129 case QCE_BW_REQUEST_RESET_FIRST:
130 ret = msm_bus_scale_client_update_request(
131 podev->bus_scale_handle, 0);
132 if (ret) {
133 pr_err("%s Unable to set low bw\n", __func__);
134 return ret;
135 }
136 ret = qce_disable_clk(podev->qce);
137 if (ret) {
138 pr_err("%s Unable to disable clk\n", __func__);
139 ret = msm_bus_scale_client_update_request(
140 podev->bus_scale_handle, 1);
141 if (ret)
142 pr_err("%s Unable to set high bw\n", __func__);
143 return ret;
144 }
145 break;
146 default:
147 return -ENOENT;
148 }
149
150 return 0;
151}
152
AnilKumar Chimatae78789a2017-04-07 12:18:46 -0700153static void qcedev_ce_high_bw_req(struct qcedev_control *podev,
154 bool high_bw_req)
155{
156 int ret = 0;
157
158 mutex_lock(&qcedev_sent_bw_req);
159 if (high_bw_req) {
160 if (podev->high_bw_req_count == 0) {
AnilKumar Chimatae5e60512017-05-03 14:06:59 -0700161 ret = qcedev_control_clocks(podev, true);
162 if (ret)
163 goto exit_unlock_mutex;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -0700164 }
165 podev->high_bw_req_count++;
166 } else {
167 if (podev->high_bw_req_count == 1) {
AnilKumar Chimatae5e60512017-05-03 14:06:59 -0700168 ret = qcedev_control_clocks(podev, false);
169 if (ret)
170 goto exit_unlock_mutex;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -0700171 }
172 podev->high_bw_req_count--;
173 }
AnilKumar Chimatae5e60512017-05-03 14:06:59 -0700174
175exit_unlock_mutex:
AnilKumar Chimatae78789a2017-04-07 12:18:46 -0700176 mutex_unlock(&qcedev_sent_bw_req);
177}
178
179#define QCEDEV_MAGIC 0x56434544 /* "qced" */
180
181static int qcedev_open(struct inode *inode, struct file *file);
182static int qcedev_release(struct inode *inode, struct file *file);
183static int start_cipher_req(struct qcedev_control *podev);
184static int start_sha_req(struct qcedev_control *podev);
185static inline long qcedev_ioctl(struct file *file,
186 unsigned int cmd, unsigned long arg);
187
188#ifdef CONFIG_COMPAT
189#include "compat_qcedev.c"
190#else
191#define compat_qcedev_ioctl NULL
192#endif
193
194static const struct file_operations qcedev_fops = {
195 .owner = THIS_MODULE,
196 .unlocked_ioctl = qcedev_ioctl,
197 .compat_ioctl = compat_qcedev_ioctl,
198 .open = qcedev_open,
199 .release = qcedev_release,
200};
201
202static struct qcedev_control qce_dev[] = {
203 {
204 .miscdevice = {
205 .minor = MISC_DYNAMIC_MINOR,
206 .name = "qce",
207 .fops = &qcedev_fops,
208 },
209 .magic = QCEDEV_MAGIC,
210 },
211};
212
213#define MAX_QCE_DEVICE ARRAY_SIZE(qce_dev)
214#define DEBUG_MAX_FNAME 16
215#define DEBUG_MAX_RW_BUF 1024
216
217struct qcedev_stat {
218 u32 qcedev_dec_success;
219 u32 qcedev_dec_fail;
220 u32 qcedev_enc_success;
221 u32 qcedev_enc_fail;
222 u32 qcedev_sha_success;
223 u32 qcedev_sha_fail;
224};
225
226static struct qcedev_stat _qcedev_stat;
227static struct dentry *_debug_dent;
228static char _debug_read_buf[DEBUG_MAX_RW_BUF];
229static int _debug_qcedev;
230
231static struct qcedev_control *qcedev_minor_to_control(unsigned int n)
232{
233 int i;
234
235 for (i = 0; i < MAX_QCE_DEVICE; i++) {
236 if (qce_dev[i].miscdevice.minor == n)
237 return &qce_dev[i];
238 }
239 return NULL;
240}
241
242static int qcedev_open(struct inode *inode, struct file *file)
243{
244 struct qcedev_handle *handle;
245 struct qcedev_control *podev;
246
247 podev = qcedev_minor_to_control(MINOR(inode->i_rdev));
248 if (podev == NULL) {
249 pr_err("%s: no such device %d\n", __func__,
250 MINOR(inode->i_rdev));
251 return -ENOENT;
252 }
253
254 handle = kzalloc(sizeof(struct qcedev_handle), GFP_KERNEL);
255 if (handle == NULL)
256 return -ENOMEM;
257
258 handle->cntl = podev;
259 file->private_data = handle;
260 if (podev->platform_support.bus_scale_table != NULL)
261 qcedev_ce_high_bw_req(podev, true);
262 return 0;
263}
264
265static int qcedev_release(struct inode *inode, struct file *file)
266{
267 struct qcedev_control *podev;
268 struct qcedev_handle *handle;
269
270 handle = file->private_data;
271 podev = handle->cntl;
272 if (podev != NULL && podev->magic != QCEDEV_MAGIC) {
mohamed sunfeerc6b8e6d2017-06-29 15:13:34 +0530273 pr_err("%s: invalid handle %pK\n",
AnilKumar Chimatae78789a2017-04-07 12:18:46 -0700274 __func__, podev);
275 }
276 kzfree(handle);
277 file->private_data = NULL;
278 if (podev != NULL && podev->platform_support.bus_scale_table != NULL)
279 qcedev_ce_high_bw_req(podev, false);
280 return 0;
281}
282
283static void req_done(unsigned long data)
284{
285 struct qcedev_control *podev = (struct qcedev_control *)data;
286 struct qcedev_async_req *areq;
287 unsigned long flags = 0;
288 struct qcedev_async_req *new_req = NULL;
289 int ret = 0;
290
291 spin_lock_irqsave(&podev->lock, flags);
292 areq = podev->active_command;
293 podev->active_command = NULL;
294
295again:
296 if (!list_empty(&podev->ready_commands)) {
297 new_req = container_of(podev->ready_commands.next,
298 struct qcedev_async_req, list);
299 list_del(&new_req->list);
300 podev->active_command = new_req;
301 new_req->err = 0;
302 if (new_req->op_type == QCEDEV_CRYPTO_OPER_CIPHER)
303 ret = start_cipher_req(podev);
304 else
305 ret = start_sha_req(podev);
306 }
307
308 spin_unlock_irqrestore(&podev->lock, flags);
309
310 if (areq)
311 complete(&areq->complete);
312
313 if (new_req && ret) {
314 complete(&new_req->complete);
315 spin_lock_irqsave(&podev->lock, flags);
316 podev->active_command = NULL;
317 areq = NULL;
318 ret = 0;
319 new_req = NULL;
320 goto again;
321 }
322}
323
324void qcedev_sha_req_cb(void *cookie, unsigned char *digest,
325 unsigned char *authdata, int ret)
326{
327 struct qcedev_sha_req *areq;
328 struct qcedev_control *pdev;
329 struct qcedev_handle *handle;
330
331 uint32_t *auth32 = (uint32_t *)authdata;
332
333 areq = (struct qcedev_sha_req *) cookie;
334 handle = (struct qcedev_handle *) areq->cookie;
335 pdev = handle->cntl;
336
337 if (digest)
338 memcpy(&handle->sha_ctxt.digest[0], digest, 32);
339
340 if (authdata) {
341 handle->sha_ctxt.auth_data[0] = auth32[0];
342 handle->sha_ctxt.auth_data[1] = auth32[1];
AnilKumar Chimatae78789a2017-04-07 12:18:46 -0700343 }
344
345 tasklet_schedule(&pdev->done_tasklet);
346};
347
348
349void qcedev_cipher_req_cb(void *cookie, unsigned char *icv,
350 unsigned char *iv, int ret)
351{
352 struct qcedev_cipher_req *areq;
353 struct qcedev_handle *handle;
354 struct qcedev_control *podev;
355 struct qcedev_async_req *qcedev_areq;
356
357 areq = (struct qcedev_cipher_req *) cookie;
358 handle = (struct qcedev_handle *) areq->cookie;
359 podev = handle->cntl;
360 qcedev_areq = podev->active_command;
361
362 if (iv)
363 memcpy(&qcedev_areq->cipher_op_req.iv[0], iv,
364 qcedev_areq->cipher_op_req.ivlen);
365 tasklet_schedule(&podev->done_tasklet);
366};
367
368static int start_cipher_req(struct qcedev_control *podev)
369{
370 struct qcedev_async_req *qcedev_areq;
371 struct qce_req creq;
372 int ret = 0;
373
374 /* start the command on the podev->active_command */
375 qcedev_areq = podev->active_command;
376 qcedev_areq->cipher_req.cookie = qcedev_areq->handle;
377 if (qcedev_areq->cipher_op_req.use_pmem == QCEDEV_USE_PMEM) {
378 pr_err("%s: Use of PMEM is not supported\n", __func__);
379 goto unsupported;
380 }
381 creq.pmem = NULL;
382 switch (qcedev_areq->cipher_op_req.alg) {
383 case QCEDEV_ALG_DES:
384 creq.alg = CIPHER_ALG_DES;
385 break;
386 case QCEDEV_ALG_3DES:
387 creq.alg = CIPHER_ALG_3DES;
388 break;
389 case QCEDEV_ALG_AES:
390 creq.alg = CIPHER_ALG_AES;
391 break;
392 default:
393 return -EINVAL;
394 };
395
396 switch (qcedev_areq->cipher_op_req.mode) {
397 case QCEDEV_AES_MODE_CBC:
398 case QCEDEV_DES_MODE_CBC:
399 creq.mode = QCE_MODE_CBC;
400 break;
401 case QCEDEV_AES_MODE_ECB:
402 case QCEDEV_DES_MODE_ECB:
403 creq.mode = QCE_MODE_ECB;
404 break;
405 case QCEDEV_AES_MODE_CTR:
406 creq.mode = QCE_MODE_CTR;
407 break;
408 case QCEDEV_AES_MODE_XTS:
409 creq.mode = QCE_MODE_XTS;
410 break;
411 default:
412 return -EINVAL;
413 };
414
415 if ((creq.alg == CIPHER_ALG_AES) &&
416 (creq.mode == QCE_MODE_CTR)) {
417 creq.dir = QCE_ENCRYPT;
418 } else {
419 if (qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC)
420 creq.dir = QCE_ENCRYPT;
421 else
422 creq.dir = QCE_DECRYPT;
423 }
424
425 creq.iv = &qcedev_areq->cipher_op_req.iv[0];
426 creq.ivsize = qcedev_areq->cipher_op_req.ivlen;
427
428 creq.enckey = &qcedev_areq->cipher_op_req.enckey[0];
429 creq.encklen = qcedev_areq->cipher_op_req.encklen;
430
431 creq.cryptlen = qcedev_areq->cipher_op_req.data_len;
432
433 if (qcedev_areq->cipher_op_req.encklen == 0) {
434 if ((qcedev_areq->cipher_op_req.op == QCEDEV_OPER_ENC_NO_KEY)
435 || (qcedev_areq->cipher_op_req.op ==
436 QCEDEV_OPER_DEC_NO_KEY))
437 creq.op = QCE_REQ_ABLK_CIPHER_NO_KEY;
438 else {
439 int i;
440
441 for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
442 if (qcedev_areq->cipher_op_req.enckey[i] != 0)
443 break;
444 }
445
446 if ((podev->platform_support.hw_key_support == 1) &&
447 (i == QCEDEV_MAX_KEY_SIZE))
448 creq.op = QCE_REQ_ABLK_CIPHER;
449 else {
450 ret = -EINVAL;
451 goto unsupported;
452 }
453 }
454 } else {
455 creq.op = QCE_REQ_ABLK_CIPHER;
456 }
457
458 creq.qce_cb = qcedev_cipher_req_cb;
459 creq.areq = (void *)&qcedev_areq->cipher_req;
460 creq.flags = 0;
461 ret = qce_ablk_cipher_req(podev->qce, &creq);
462unsupported:
463 if (ret)
464 qcedev_areq->err = -ENXIO;
465 else
466 qcedev_areq->err = 0;
467 return ret;
468};
469
470static int start_sha_req(struct qcedev_control *podev)
471{
472 struct qcedev_async_req *qcedev_areq;
473 struct qce_sha_req sreq;
474 int ret = 0;
475 struct qcedev_handle *handle;
476
477 /* start the command on the podev->active_command */
478 qcedev_areq = podev->active_command;
479 handle = qcedev_areq->handle;
480
481 switch (qcedev_areq->sha_op_req.alg) {
482 case QCEDEV_ALG_SHA1:
483 sreq.alg = QCE_HASH_SHA1;
484 break;
485 case QCEDEV_ALG_SHA256:
486 sreq.alg = QCE_HASH_SHA256;
487 break;
488 case QCEDEV_ALG_SHA1_HMAC:
489 if (podev->ce_support.sha_hmac) {
490 sreq.alg = QCE_HASH_SHA1_HMAC;
491 sreq.authkey = &handle->sha_ctxt.authkey[0];
492 sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
493
494 } else {
495 sreq.alg = QCE_HASH_SHA1;
496 sreq.authkey = NULL;
497 }
498 break;
499 case QCEDEV_ALG_SHA256_HMAC:
500 if (podev->ce_support.sha_hmac) {
501 sreq.alg = QCE_HASH_SHA256_HMAC;
502 sreq.authkey = &handle->sha_ctxt.authkey[0];
503 sreq.authklen = QCEDEV_MAX_SHA_BLOCK_SIZE;
504 } else {
505 sreq.alg = QCE_HASH_SHA256;
506 sreq.authkey = NULL;
507 }
508 break;
509 case QCEDEV_ALG_AES_CMAC:
510 sreq.alg = QCE_HASH_AES_CMAC;
511 sreq.authkey = &handle->sha_ctxt.authkey[0];
512 sreq.authklen = qcedev_areq->sha_op_req.authklen;
513 break;
514 default:
515 pr_err("Algorithm %d not supported, exiting\n",
516 qcedev_areq->sha_op_req.alg);
517 return -EINVAL;
518 };
519
520 qcedev_areq->sha_req.cookie = handle;
521
522 sreq.qce_cb = qcedev_sha_req_cb;
523 if (qcedev_areq->sha_op_req.alg != QCEDEV_ALG_AES_CMAC) {
524 sreq.auth_data[0] = handle->sha_ctxt.auth_data[0];
525 sreq.auth_data[1] = handle->sha_ctxt.auth_data[1];
526 sreq.auth_data[2] = handle->sha_ctxt.auth_data[2];
527 sreq.auth_data[3] = handle->sha_ctxt.auth_data[3];
528 sreq.digest = &handle->sha_ctxt.digest[0];
529 sreq.first_blk = handle->sha_ctxt.first_blk;
530 sreq.last_blk = handle->sha_ctxt.last_blk;
531 }
532 sreq.size = qcedev_areq->sha_req.sreq.nbytes;
533 sreq.src = qcedev_areq->sha_req.sreq.src;
534 sreq.areq = (void *)&qcedev_areq->sha_req;
535 sreq.flags = 0;
536
537 ret = qce_process_sha_req(podev->qce, &sreq);
538
539 if (ret)
540 qcedev_areq->err = -ENXIO;
541 else
542 qcedev_areq->err = 0;
543 return ret;
544};
545
546static int submit_req(struct qcedev_async_req *qcedev_areq,
547 struct qcedev_handle *handle)
548{
549 struct qcedev_control *podev;
550 unsigned long flags = 0;
551 int ret = 0;
552 struct qcedev_stat *pstat;
553
554 qcedev_areq->err = 0;
555 podev = handle->cntl;
556
557 spin_lock_irqsave(&podev->lock, flags);
558
559 if (podev->active_command == NULL) {
560 podev->active_command = qcedev_areq;
561 if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_CIPHER)
562 ret = start_cipher_req(podev);
563 else
564 ret = start_sha_req(podev);
565 } else {
566 list_add_tail(&qcedev_areq->list, &podev->ready_commands);
567 }
568
569 if (ret != 0)
570 podev->active_command = NULL;
571
572 spin_unlock_irqrestore(&podev->lock, flags);
573
574 if (ret == 0)
575 wait_for_completion(&qcedev_areq->complete);
576
577 if (ret)
578 qcedev_areq->err = -EIO;
579
580 pstat = &_qcedev_stat;
581 if (qcedev_areq->op_type == QCEDEV_CRYPTO_OPER_CIPHER) {
582 switch (qcedev_areq->cipher_op_req.op) {
583 case QCEDEV_OPER_DEC:
584 if (qcedev_areq->err)
585 pstat->qcedev_dec_fail++;
586 else
587 pstat->qcedev_dec_success++;
588 break;
589 case QCEDEV_OPER_ENC:
590 if (qcedev_areq->err)
591 pstat->qcedev_enc_fail++;
592 else
593 pstat->qcedev_enc_success++;
594 break;
595 default:
596 break;
597 };
598 } else {
599 if (qcedev_areq->err)
600 pstat->qcedev_sha_fail++;
601 else
602 pstat->qcedev_sha_success++;
603 }
604
605 return qcedev_areq->err;
606}
607
608static int qcedev_sha_init(struct qcedev_async_req *areq,
609 struct qcedev_handle *handle)
610{
611 struct qcedev_sha_ctxt *sha_ctxt = &handle->sha_ctxt;
612
613 memset(sha_ctxt, 0, sizeof(struct qcedev_sha_ctxt));
614 sha_ctxt->first_blk = 1;
615
616 if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
617 (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)) {
618 memcpy(&sha_ctxt->digest[0],
619 &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
620 sha_ctxt->diglen = SHA1_DIGEST_SIZE;
621 } else {
622 if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA256) ||
623 (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)) {
624 memcpy(&sha_ctxt->digest[0],
625 &_std_init_vector_sha256_uint8[0],
626 SHA256_DIGEST_SIZE);
627 sha_ctxt->diglen = SHA256_DIGEST_SIZE;
628 }
629 }
630 sha_ctxt->init_done = true;
631 return 0;
632}
633
634
635static int qcedev_sha_update_max_xfer(struct qcedev_async_req *qcedev_areq,
636 struct qcedev_handle *handle,
637 struct scatterlist *sg_src)
638{
639 int err = 0;
640 int i = 0;
641 uint32_t total;
642
643 uint8_t *user_src = NULL;
644 uint8_t *k_src = NULL;
645 uint8_t *k_buf_src = NULL;
646 uint8_t *k_align_src = NULL;
647
648 uint32_t sha_pad_len = 0;
649 uint32_t trailing_buf_len = 0;
650 uint32_t t_buf = handle->sha_ctxt.trailing_buf_len;
651 uint32_t sha_block_size;
652
653 total = qcedev_areq->sha_op_req.data_len + t_buf;
654
655 if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1)
656 sha_block_size = SHA1_BLOCK_SIZE;
657 else
658 sha_block_size = SHA256_BLOCK_SIZE;
659
660 if (total <= sha_block_size) {
661 uint32_t len = qcedev_areq->sha_op_req.data_len;
662
663 i = 0;
664
665 k_src = &handle->sha_ctxt.trailing_buf[t_buf];
666
667 /* Copy data from user src(s) */
668 while (len > 0) {
669 user_src =
670 (void __user *)qcedev_areq->sha_op_req.data[i].vaddr;
671 if (user_src && copy_from_user(k_src,
672 (void __user *)user_src,
673 qcedev_areq->sha_op_req.data[i].len))
674 return -EFAULT;
675
676 len -= qcedev_areq->sha_op_req.data[i].len;
677 k_src += qcedev_areq->sha_op_req.data[i].len;
678 i++;
679 }
680 handle->sha_ctxt.trailing_buf_len = total;
681
682 return 0;
683 }
684
685
686 k_buf_src = kmalloc(total + CACHE_LINE_SIZE * 2,
687 GFP_KERNEL);
688 if (k_buf_src == NULL)
689 return -ENOMEM;
690
691 k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
692 CACHE_LINE_SIZE);
693 k_src = k_align_src;
694
695 /* check for trailing buffer from previous updates and append it */
696 if (t_buf > 0) {
697 memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
698 t_buf);
699 k_src += t_buf;
700 }
701
702 /* Copy data from user src(s) */
703 user_src = (void __user *)qcedev_areq->sha_op_req.data[0].vaddr;
704 if (user_src && copy_from_user(k_src,
705 (void __user *)user_src,
706 qcedev_areq->sha_op_req.data[0].len)) {
707 kzfree(k_buf_src);
708 return -EFAULT;
709 }
710 k_src += qcedev_areq->sha_op_req.data[0].len;
711 for (i = 1; i < qcedev_areq->sha_op_req.entries; i++) {
712 user_src = (void __user *)qcedev_areq->sha_op_req.data[i].vaddr;
713 if (user_src && copy_from_user(k_src,
714 (void __user *)user_src,
715 qcedev_areq->sha_op_req.data[i].len)) {
716 kzfree(k_buf_src);
717 return -EFAULT;
718 }
719 k_src += qcedev_areq->sha_op_req.data[i].len;
720 }
721
722 /* get new trailing buffer */
723 sha_pad_len = ALIGN(total, CE_SHA_BLOCK_SIZE) - total;
724 trailing_buf_len = CE_SHA_BLOCK_SIZE - sha_pad_len;
725
726 qcedev_areq->sha_req.sreq.src = sg_src;
727 sg_set_buf(qcedev_areq->sha_req.sreq.src, k_align_src,
728 total-trailing_buf_len);
729 sg_mark_end(qcedev_areq->sha_req.sreq.src);
730
731 qcedev_areq->sha_req.sreq.nbytes = total - trailing_buf_len;
732
733 /* update sha_ctxt trailing buf content to new trailing buf */
734 if (trailing_buf_len > 0) {
735 memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
736 memcpy(&handle->sha_ctxt.trailing_buf[0],
737 (k_src - trailing_buf_len),
738 trailing_buf_len);
739 }
740 handle->sha_ctxt.trailing_buf_len = trailing_buf_len;
741
742 err = submit_req(qcedev_areq, handle);
743
744 handle->sha_ctxt.last_blk = 0;
745 handle->sha_ctxt.first_blk = 0;
746
747 kzfree(k_buf_src);
748 return err;
749}
750
751static int qcedev_sha_update(struct qcedev_async_req *qcedev_areq,
752 struct qcedev_handle *handle,
753 struct scatterlist *sg_src)
754{
755 int err = 0;
756 int i = 0;
757 int j = 0;
758 int k = 0;
759 int num_entries = 0;
760 uint32_t total = 0;
761
762 if (handle->sha_ctxt.init_done == false) {
763 pr_err("%s Init was not called\n", __func__);
764 return -EINVAL;
765 }
766
767 if (qcedev_areq->sha_op_req.data_len > QCE_MAX_OPER_DATA) {
768
769 struct qcedev_sha_op_req *saved_req;
770 struct qcedev_sha_op_req req;
771 struct qcedev_sha_op_req *sreq = &qcedev_areq->sha_op_req;
772
773 /* save the original req structure */
774 saved_req =
775 kmalloc(sizeof(struct qcedev_sha_op_req), GFP_KERNEL);
776 if (saved_req == NULL) {
777 pr_err("%s:Can't Allocate mem:saved_req 0x%lx\n",
778 __func__, (uintptr_t)saved_req);
779 return -ENOMEM;
780 }
781 memcpy(&req, sreq, sizeof(struct qcedev_sha_op_req));
782 memcpy(saved_req, sreq, sizeof(struct qcedev_sha_op_req));
783
784 i = 0;
785 /* Address 32 KB at a time */
786 while ((i < req.entries) && (err == 0)) {
787 if (sreq->data[i].len > QCE_MAX_OPER_DATA) {
788 sreq->data[0].len = QCE_MAX_OPER_DATA;
789 if (i > 0) {
790 sreq->data[0].vaddr =
791 sreq->data[i].vaddr;
792 }
793
794 sreq->data_len = QCE_MAX_OPER_DATA;
795 sreq->entries = 1;
796
797 err = qcedev_sha_update_max_xfer(qcedev_areq,
798 handle, sg_src);
799
800 sreq->data[i].len = req.data[i].len -
801 QCE_MAX_OPER_DATA;
802 sreq->data[i].vaddr = req.data[i].vaddr +
803 QCE_MAX_OPER_DATA;
804 req.data[i].vaddr = sreq->data[i].vaddr;
805 req.data[i].len = sreq->data[i].len;
806 } else {
807 total = 0;
808 for (j = i; j < req.entries; j++) {
809 num_entries++;
810 if ((total + sreq->data[j].len) >=
811 QCE_MAX_OPER_DATA) {
812 sreq->data[j].len =
813 (QCE_MAX_OPER_DATA - total);
814 total = QCE_MAX_OPER_DATA;
815 break;
816 }
817 total += sreq->data[j].len;
818 }
819
820 sreq->data_len = total;
821 if (i > 0)
822 for (k = 0; k < num_entries; k++) {
823 sreq->data[k].len =
824 sreq->data[i+k].len;
825 sreq->data[k].vaddr =
826 sreq->data[i+k].vaddr;
827 }
828 sreq->entries = num_entries;
829
830 i = j;
831 err = qcedev_sha_update_max_xfer(qcedev_areq,
832 handle, sg_src);
833 num_entries = 0;
834
835 sreq->data[i].vaddr = req.data[i].vaddr +
836 sreq->data[i].len;
837 sreq->data[i].len = req.data[i].len -
838 sreq->data[i].len;
839 req.data[i].vaddr = sreq->data[i].vaddr;
840 req.data[i].len = sreq->data[i].len;
841
842 if (sreq->data[i].len == 0)
843 i++;
844 }
845 } /* end of while ((i < req.entries) && (err == 0)) */
846
847 /* Restore the original req structure */
848 for (i = 0; i < saved_req->entries; i++) {
849 sreq->data[i].len = saved_req->data[i].len;
850 sreq->data[i].vaddr = saved_req->data[i].vaddr;
851 }
852 sreq->entries = saved_req->entries;
853 sreq->data_len = saved_req->data_len;
854 kzfree(saved_req);
855 } else
856 err = qcedev_sha_update_max_xfer(qcedev_areq, handle, sg_src);
857
858 return err;
859}
860
861static int qcedev_sha_final(struct qcedev_async_req *qcedev_areq,
862 struct qcedev_handle *handle)
863{
864 int err = 0;
865 struct scatterlist sg_src;
866 uint32_t total;
867 uint8_t *k_buf_src = NULL;
868 uint8_t *k_align_src = NULL;
869
870 if (handle->sha_ctxt.init_done == false) {
871 pr_err("%s Init was not called\n", __func__);
872 return -EINVAL;
873 }
874
875 handle->sha_ctxt.last_blk = 1;
876
877 total = handle->sha_ctxt.trailing_buf_len;
878
879 if (total) {
880 k_buf_src = kmalloc(total + CACHE_LINE_SIZE * 2,
881 GFP_KERNEL);
882 if (k_buf_src == NULL)
883 return -ENOMEM;
884
885 k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
886 CACHE_LINE_SIZE);
887 memcpy(k_align_src, &handle->sha_ctxt.trailing_buf[0], total);
888 }
889 qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
890 sg_set_buf(qcedev_areq->sha_req.sreq.src, k_align_src, total);
891 sg_mark_end(qcedev_areq->sha_req.sreq.src);
892
893 qcedev_areq->sha_req.sreq.nbytes = total;
894
895 err = submit_req(qcedev_areq, handle);
896
897 handle->sha_ctxt.first_blk = 0;
898 handle->sha_ctxt.last_blk = 0;
899 handle->sha_ctxt.auth_data[0] = 0;
900 handle->sha_ctxt.auth_data[1] = 0;
901 handle->sha_ctxt.trailing_buf_len = 0;
902 handle->sha_ctxt.init_done = false;
903 memset(&handle->sha_ctxt.trailing_buf[0], 0, 64);
904
905 kzfree(k_buf_src);
906 return err;
907}
908
909static int qcedev_hash_cmac(struct qcedev_async_req *qcedev_areq,
910 struct qcedev_handle *handle,
911 struct scatterlist *sg_src)
912{
913 int err = 0;
914 int i = 0;
915 uint32_t total;
916
917 uint8_t *user_src = NULL;
918 uint8_t *k_src = NULL;
919 uint8_t *k_buf_src = NULL;
920
921 total = qcedev_areq->sha_op_req.data_len;
922
923 if (copy_from_user(&handle->sha_ctxt.authkey[0],
924 (void __user *)qcedev_areq->sha_op_req.authkey,
925 qcedev_areq->sha_op_req.authklen))
926 return -EFAULT;
927
928
929 k_buf_src = kmalloc(total, GFP_KERNEL);
930 if (k_buf_src == NULL)
931 return -ENOMEM;
932
933 k_src = k_buf_src;
934
935 /* Copy data from user src(s) */
936 user_src = (void __user *)qcedev_areq->sha_op_req.data[0].vaddr;
937 for (i = 0; i < qcedev_areq->sha_op_req.entries; i++) {
938 user_src =
939 (void __user *)qcedev_areq->sha_op_req.data[i].vaddr;
940 if (user_src && copy_from_user(k_src, (void __user *)user_src,
941 qcedev_areq->sha_op_req.data[i].len)) {
942 kzfree(k_buf_src);
943 return -EFAULT;
944 }
945 k_src += qcedev_areq->sha_op_req.data[i].len;
946 }
947
948 qcedev_areq->sha_req.sreq.src = sg_src;
949 sg_set_buf(qcedev_areq->sha_req.sreq.src, k_buf_src, total);
950 sg_mark_end(qcedev_areq->sha_req.sreq.src);
951
952 qcedev_areq->sha_req.sreq.nbytes = total;
953 handle->sha_ctxt.diglen = qcedev_areq->sha_op_req.diglen;
954 err = submit_req(qcedev_areq, handle);
955
956 kzfree(k_buf_src);
957 return err;
958}
959
960static int qcedev_set_hmac_auth_key(struct qcedev_async_req *areq,
961 struct qcedev_handle *handle,
962 struct scatterlist *sg_src)
963{
964 int err = 0;
965
966 if (areq->sha_op_req.authklen <= QCEDEV_MAX_KEY_SIZE) {
967 qcedev_sha_init(areq, handle);
968 if (copy_from_user(&handle->sha_ctxt.authkey[0],
969 (void __user *)areq->sha_op_req.authkey,
970 areq->sha_op_req.authklen))
971 return -EFAULT;
972 } else {
973 struct qcedev_async_req authkey_areq;
974 uint8_t authkey[QCEDEV_MAX_SHA_BLOCK_SIZE];
975
976 init_completion(&authkey_areq.complete);
977
978 authkey_areq.sha_op_req.entries = 1;
979 authkey_areq.sha_op_req.data[0].vaddr =
980 areq->sha_op_req.authkey;
981 authkey_areq.sha_op_req.data[0].len = areq->sha_op_req.authklen;
982 authkey_areq.sha_op_req.data_len = areq->sha_op_req.authklen;
983 authkey_areq.sha_op_req.diglen = 0;
984 authkey_areq.handle = handle;
985
986 memset(&authkey_areq.sha_op_req.digest[0], 0,
987 QCEDEV_MAX_SHA_DIGEST);
988 if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
989 authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA1;
990 if (areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC)
991 authkey_areq.sha_op_req.alg = QCEDEV_ALG_SHA256;
992
993 authkey_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
994
995 qcedev_sha_init(&authkey_areq, handle);
996 err = qcedev_sha_update(&authkey_areq, handle, sg_src);
997 if (!err)
998 err = qcedev_sha_final(&authkey_areq, handle);
999 else
1000 return err;
1001 memcpy(&authkey[0], &handle->sha_ctxt.digest[0],
1002 handle->sha_ctxt.diglen);
1003 qcedev_sha_init(areq, handle);
1004
1005 memcpy(&handle->sha_ctxt.authkey[0], &authkey[0],
1006 handle->sha_ctxt.diglen);
1007 }
1008 return err;
1009}
1010
1011static int qcedev_hmac_get_ohash(struct qcedev_async_req *qcedev_areq,
1012 struct qcedev_handle *handle)
1013{
1014 int err = 0;
1015 struct scatterlist sg_src;
1016 uint8_t *k_src = NULL;
1017 uint32_t sha_block_size = 0;
1018 uint32_t sha_digest_size = 0;
1019
1020 if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
1021 sha_digest_size = SHA1_DIGEST_SIZE;
1022 sha_block_size = SHA1_BLOCK_SIZE;
1023 } else {
1024 if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
1025 sha_digest_size = SHA256_DIGEST_SIZE;
1026 sha_block_size = SHA256_BLOCK_SIZE;
1027 }
1028 }
1029 k_src = kmalloc(sha_block_size, GFP_KERNEL);
1030 if (k_src == NULL)
1031 return -ENOMEM;
1032
1033 /* check for trailing buffer from previous updates and append it */
1034 memcpy(k_src, &handle->sha_ctxt.trailing_buf[0],
1035 handle->sha_ctxt.trailing_buf_len);
1036
1037 qcedev_areq->sha_req.sreq.src = (struct scatterlist *) &sg_src;
1038 sg_set_buf(qcedev_areq->sha_req.sreq.src, k_src, sha_block_size);
1039 sg_mark_end(qcedev_areq->sha_req.sreq.src);
1040
1041 qcedev_areq->sha_req.sreq.nbytes = sha_block_size;
1042 memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
1043 memcpy(&handle->sha_ctxt.trailing_buf[0], &handle->sha_ctxt.digest[0],
1044 sha_digest_size);
1045 handle->sha_ctxt.trailing_buf_len = sha_digest_size;
1046
1047 handle->sha_ctxt.first_blk = 1;
1048 handle->sha_ctxt.last_blk = 0;
1049 handle->sha_ctxt.auth_data[0] = 0;
1050 handle->sha_ctxt.auth_data[1] = 0;
1051
1052 if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC) {
1053 memcpy(&handle->sha_ctxt.digest[0],
1054 &_std_init_vector_sha1_uint8[0], SHA1_DIGEST_SIZE);
1055 handle->sha_ctxt.diglen = SHA1_DIGEST_SIZE;
1056 }
1057
1058 if (qcedev_areq->sha_op_req.alg == QCEDEV_ALG_SHA256_HMAC) {
1059 memcpy(&handle->sha_ctxt.digest[0],
1060 &_std_init_vector_sha256_uint8[0], SHA256_DIGEST_SIZE);
1061 handle->sha_ctxt.diglen = SHA256_DIGEST_SIZE;
1062 }
1063 err = submit_req(qcedev_areq, handle);
1064
1065 handle->sha_ctxt.last_blk = 0;
1066 handle->sha_ctxt.first_blk = 0;
1067
1068 kzfree(k_src);
1069 return err;
1070}
1071
1072static int qcedev_hmac_update_iokey(struct qcedev_async_req *areq,
1073 struct qcedev_handle *handle, bool ikey)
1074{
1075 int i;
1076 uint32_t constant;
1077 uint32_t sha_block_size;
1078
1079 if (ikey)
1080 constant = 0x36;
1081 else
1082 constant = 0x5c;
1083
1084 if (areq->sha_op_req.alg == QCEDEV_ALG_SHA1_HMAC)
1085 sha_block_size = SHA1_BLOCK_SIZE;
1086 else
1087 sha_block_size = SHA256_BLOCK_SIZE;
1088
1089 memset(&handle->sha_ctxt.trailing_buf[0], 0, sha_block_size);
1090 for (i = 0; i < sha_block_size; i++)
1091 handle->sha_ctxt.trailing_buf[i] =
1092 (handle->sha_ctxt.authkey[i] ^ constant);
1093
1094 handle->sha_ctxt.trailing_buf_len = sha_block_size;
1095 return 0;
1096}
1097
1098static int qcedev_hmac_init(struct qcedev_async_req *areq,
1099 struct qcedev_handle *handle,
1100 struct scatterlist *sg_src)
1101{
1102 int err;
1103 struct qcedev_control *podev = handle->cntl;
1104
1105 err = qcedev_set_hmac_auth_key(areq, handle, sg_src);
1106 if (err)
1107 return err;
1108 if (!podev->ce_support.sha_hmac)
1109 qcedev_hmac_update_iokey(areq, handle, true);
1110 return 0;
1111}
1112
1113static int qcedev_hmac_final(struct qcedev_async_req *areq,
1114 struct qcedev_handle *handle)
1115{
1116 int err;
1117 struct qcedev_control *podev = handle->cntl;
1118
1119 err = qcedev_sha_final(areq, handle);
1120 if (podev->ce_support.sha_hmac)
1121 return err;
1122
1123 qcedev_hmac_update_iokey(areq, handle, false);
1124 err = qcedev_hmac_get_ohash(areq, handle);
1125 if (err)
1126 return err;
1127 err = qcedev_sha_final(areq, handle);
1128
1129 return err;
1130}
1131
1132static int qcedev_hash_init(struct qcedev_async_req *areq,
1133 struct qcedev_handle *handle,
1134 struct scatterlist *sg_src)
1135{
1136 if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
1137 (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
1138 return qcedev_sha_init(areq, handle);
1139 else
1140 return qcedev_hmac_init(areq, handle, sg_src);
1141}
1142
1143static int qcedev_hash_update(struct qcedev_async_req *qcedev_areq,
1144 struct qcedev_handle *handle,
1145 struct scatterlist *sg_src)
1146{
1147 return qcedev_sha_update(qcedev_areq, handle, sg_src);
1148}
1149
1150static int qcedev_hash_final(struct qcedev_async_req *areq,
1151 struct qcedev_handle *handle)
1152{
1153 if ((areq->sha_op_req.alg == QCEDEV_ALG_SHA1) ||
1154 (areq->sha_op_req.alg == QCEDEV_ALG_SHA256))
1155 return qcedev_sha_final(areq, handle);
1156 else
1157 return qcedev_hmac_final(areq, handle);
1158}
1159
1160static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq,
1161 int *di, struct qcedev_handle *handle,
1162 uint8_t *k_align_src)
1163{
1164 int err = 0;
1165 int i = 0;
1166 int dst_i = *di;
1167 struct scatterlist sg_src;
1168 uint32_t byteoffset = 0;
1169 uint8_t *user_src = NULL;
1170 uint8_t *k_align_dst = k_align_src;
1171 struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
1172
1173
1174 if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
1175 byteoffset = areq->cipher_op_req.byteoffset;
1176
1177 user_src = (void __user *)areq->cipher_op_req.vbuf.src[0].vaddr;
1178 if (user_src && copy_from_user((k_align_src + byteoffset),
1179 (void __user *)user_src,
1180 areq->cipher_op_req.vbuf.src[0].len))
1181 return -EFAULT;
1182
1183 k_align_src += byteoffset + areq->cipher_op_req.vbuf.src[0].len;
1184
1185 for (i = 1; i < areq->cipher_op_req.entries; i++) {
1186 user_src =
1187 (void __user *)areq->cipher_op_req.vbuf.src[i].vaddr;
1188 if (user_src && copy_from_user(k_align_src,
1189 (void __user *)user_src,
1190 areq->cipher_op_req.vbuf.src[i].len)) {
1191 return -EFAULT;
1192 }
1193 k_align_src += areq->cipher_op_req.vbuf.src[i].len;
1194 }
1195
1196 /* restore src beginning */
1197 k_align_src = k_align_dst;
1198 areq->cipher_op_req.data_len += byteoffset;
1199
1200 areq->cipher_req.creq.src = (struct scatterlist *) &sg_src;
1201 areq->cipher_req.creq.dst = (struct scatterlist *) &sg_src;
1202
1203 /* In place encryption/decryption */
1204 sg_set_buf(areq->cipher_req.creq.src,
1205 k_align_dst,
1206 areq->cipher_op_req.data_len);
1207 sg_mark_end(areq->cipher_req.creq.src);
1208
1209 areq->cipher_req.creq.nbytes = areq->cipher_op_req.data_len;
1210 areq->cipher_req.creq.info = areq->cipher_op_req.iv;
1211 areq->cipher_op_req.entries = 1;
1212
1213 err = submit_req(areq, handle);
1214
1215 /* copy data to destination buffer*/
1216 creq->data_len -= byteoffset;
1217
1218 while (creq->data_len > 0) {
1219 if (creq->vbuf.dst[dst_i].len <= creq->data_len) {
1220 if (err == 0 && copy_to_user(
1221 (void __user *)creq->vbuf.dst[dst_i].vaddr,
1222 (k_align_dst + byteoffset),
1223 creq->vbuf.dst[dst_i].len))
1224 return -EFAULT;
1225
1226 k_align_dst += creq->vbuf.dst[dst_i].len +
1227 byteoffset;
1228 creq->data_len -= creq->vbuf.dst[dst_i].len;
1229 dst_i++;
1230 } else {
1231 if (err == 0 && copy_to_user(
1232 (void __user *)creq->vbuf.dst[dst_i].vaddr,
1233 (k_align_dst + byteoffset),
1234 creq->data_len))
1235 return -EFAULT;
1236
1237 k_align_dst += creq->data_len;
1238 creq->vbuf.dst[dst_i].len -= creq->data_len;
1239 creq->vbuf.dst[dst_i].vaddr += creq->data_len;
1240 creq->data_len = 0;
1241 }
1242 }
1243 *di = dst_i;
1244
1245 return err;
1246};
1247
1248static int qcedev_vbuf_ablk_cipher(struct qcedev_async_req *areq,
1249 struct qcedev_handle *handle)
1250{
1251 int err = 0;
1252 int di = 0;
1253 int i = 0;
1254 int j = 0;
1255 int k = 0;
1256 uint32_t byteoffset = 0;
1257 int num_entries = 0;
1258 uint32_t total = 0;
1259 uint32_t len;
1260 uint8_t *k_buf_src = NULL;
1261 uint8_t *k_align_src = NULL;
1262 uint32_t max_data_xfer;
1263 struct qcedev_cipher_op_req *saved_req;
1264 struct qcedev_cipher_op_req *creq = &areq->cipher_op_req;
1265
1266 total = 0;
1267
1268 if (areq->cipher_op_req.mode == QCEDEV_AES_MODE_CTR)
1269 byteoffset = areq->cipher_op_req.byteoffset;
1270 k_buf_src = kmalloc(QCE_MAX_OPER_DATA + CACHE_LINE_SIZE * 2,
1271 GFP_KERNEL);
1272 if (k_buf_src == NULL)
1273 return -ENOMEM;
1274 k_align_src = (uint8_t *)ALIGN(((uintptr_t)k_buf_src),
1275 CACHE_LINE_SIZE);
1276 max_data_xfer = QCE_MAX_OPER_DATA - byteoffset;
1277
1278 saved_req = kmalloc(sizeof(struct qcedev_cipher_op_req), GFP_KERNEL);
1279 if (saved_req == NULL) {
1280 kzfree(k_buf_src);
1281 return -ENOMEM;
1282
1283 }
1284 memcpy(saved_req, creq, sizeof(struct qcedev_cipher_op_req));
1285
1286 if (areq->cipher_op_req.data_len > max_data_xfer) {
1287 struct qcedev_cipher_op_req req;
1288
1289 /* save the original req structure */
1290 memcpy(&req, creq, sizeof(struct qcedev_cipher_op_req));
1291
1292 i = 0;
1293 /* Address 32 KB at a time */
1294 while ((i < req.entries) && (err == 0)) {
1295 if (creq->vbuf.src[i].len > max_data_xfer) {
1296 creq->vbuf.src[0].len = max_data_xfer;
1297 if (i > 0) {
1298 creq->vbuf.src[0].vaddr =
1299 creq->vbuf.src[i].vaddr;
1300 }
1301
1302 creq->data_len = max_data_xfer;
1303 creq->entries = 1;
1304
1305 err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
1306 &di, handle, k_align_src);
1307 if (err < 0) {
1308 kzfree(k_buf_src);
1309 kzfree(saved_req);
1310 return err;
1311 }
1312
1313 creq->vbuf.src[i].len = req.vbuf.src[i].len -
1314 max_data_xfer;
1315 creq->vbuf.src[i].vaddr =
1316 req.vbuf.src[i].vaddr +
1317 max_data_xfer;
1318 req.vbuf.src[i].vaddr =
1319 creq->vbuf.src[i].vaddr;
1320 req.vbuf.src[i].len = creq->vbuf.src[i].len;
1321
1322 } else {
1323 total = areq->cipher_op_req.byteoffset;
1324 for (j = i; j < req.entries; j++) {
1325 num_entries++;
1326 if ((total + creq->vbuf.src[j].len)
1327 >= max_data_xfer) {
1328 creq->vbuf.src[j].len =
1329 max_data_xfer - total;
1330 total = max_data_xfer;
1331 break;
1332 }
1333 total += creq->vbuf.src[j].len;
1334 }
1335
1336 creq->data_len = total;
1337 if (i > 0)
1338 for (k = 0; k < num_entries; k++) {
1339 creq->vbuf.src[k].len =
1340 creq->vbuf.src[i+k].len;
1341 creq->vbuf.src[k].vaddr =
1342 creq->vbuf.src[i+k].vaddr;
1343 }
1344 creq->entries = num_entries;
1345
1346 i = j;
1347 err = qcedev_vbuf_ablk_cipher_max_xfer(areq,
1348 &di, handle, k_align_src);
1349 if (err < 0) {
1350 kzfree(k_buf_src);
1351 kzfree(saved_req);
1352 return err;
1353 }
1354
1355 num_entries = 0;
1356 areq->cipher_op_req.byteoffset = 0;
1357
1358 creq->vbuf.src[i].vaddr = req.vbuf.src[i].vaddr
1359 + creq->vbuf.src[i].len;
1360 creq->vbuf.src[i].len = req.vbuf.src[i].len -
1361 creq->vbuf.src[i].len;
1362
1363 req.vbuf.src[i].vaddr =
1364 creq->vbuf.src[i].vaddr;
1365 req.vbuf.src[i].len = creq->vbuf.src[i].len;
1366
1367 if (creq->vbuf.src[i].len == 0)
1368 i++;
1369 }
1370
1371 areq->cipher_op_req.byteoffset = 0;
1372 max_data_xfer = QCE_MAX_OPER_DATA;
1373 byteoffset = 0;
1374
1375 } /* end of while ((i < req.entries) && (err == 0)) */
1376 } else
1377 err = qcedev_vbuf_ablk_cipher_max_xfer(areq, &di, handle,
1378 k_align_src);
1379
1380 /* Restore the original req structure */
1381 for (i = 0; i < saved_req->entries; i++) {
1382 creq->vbuf.src[i].len = saved_req->vbuf.src[i].len;
1383 creq->vbuf.src[i].vaddr = saved_req->vbuf.src[i].vaddr;
1384 }
1385 for (len = 0, i = 0; len < saved_req->data_len; i++) {
1386 creq->vbuf.dst[i].len = saved_req->vbuf.dst[i].len;
1387 creq->vbuf.dst[i].vaddr = saved_req->vbuf.dst[i].vaddr;
1388 len += saved_req->vbuf.dst[i].len;
1389 }
1390 creq->entries = saved_req->entries;
1391 creq->data_len = saved_req->data_len;
1392 creq->byteoffset = saved_req->byteoffset;
1393
1394 kzfree(saved_req);
1395 kzfree(k_buf_src);
1396 return err;
1397
1398}
1399
1400static int qcedev_check_cipher_key(struct qcedev_cipher_op_req *req,
1401 struct qcedev_control *podev)
1402{
1403 /* if intending to use HW key make sure key fields are set
1404 * correctly and HW key is indeed supported in target
1405 */
1406 if (req->encklen == 0) {
1407 int i;
1408
1409 for (i = 0; i < QCEDEV_MAX_KEY_SIZE; i++) {
1410 if (req->enckey[i]) {
1411 pr_err("%s: Invalid key: non-zero key input\n",
1412 __func__);
1413 goto error;
1414 }
1415 }
1416 if ((req->op != QCEDEV_OPER_ENC_NO_KEY) &&
1417 (req->op != QCEDEV_OPER_DEC_NO_KEY))
1418 if (!podev->platform_support.hw_key_support) {
1419 pr_err("%s: Invalid op %d\n", __func__,
1420 (uint32_t)req->op);
1421 goto error;
1422 }
1423 } else {
1424 if (req->encklen == QCEDEV_AES_KEY_192) {
1425 if (!podev->ce_support.aes_key_192) {
1426 pr_err("%s: AES-192 not supported\n", __func__);
1427 goto error;
1428 }
1429 } else {
1430 /* if not using HW key make sure key
1431 * length is valid
1432 */
1433 if (req->mode == QCEDEV_AES_MODE_XTS) {
1434 if ((req->encklen != QCEDEV_AES_KEY_128*2) &&
1435 (req->encklen != QCEDEV_AES_KEY_256*2)) {
1436 pr_err("%s: unsupported key size: %d\n",
1437 __func__, req->encklen);
1438 goto error;
1439 }
1440 } else {
1441 if ((req->encklen != QCEDEV_AES_KEY_128) &&
1442 (req->encklen != QCEDEV_AES_KEY_256)) {
1443 pr_err("%s: unsupported key size %d\n",
1444 __func__, req->encklen);
1445 goto error;
1446 }
1447 }
1448 }
1449 }
1450 return 0;
1451error:
1452 return -EINVAL;
1453}
1454
1455static int qcedev_check_cipher_params(struct qcedev_cipher_op_req *req,
1456 struct qcedev_control *podev)
1457{
1458 uint32_t total = 0;
1459 uint32_t i;
1460
1461 if (req->use_pmem) {
1462 pr_err("%s: Use of PMEM is not supported\n", __func__);
1463 goto error;
1464 }
1465 if ((req->entries == 0) || (req->data_len == 0) ||
1466 (req->entries > QCEDEV_MAX_BUFFERS)) {
1467 pr_err("%s: Invalid cipher length/entries\n", __func__);
1468 goto error;
1469 }
1470 if ((req->alg >= QCEDEV_ALG_LAST) ||
1471 (req->mode >= QCEDEV_AES_DES_MODE_LAST)) {
1472 pr_err("%s: Invalid algorithm %d\n", __func__,
1473 (uint32_t)req->alg);
1474 goto error;
1475 }
1476 if ((req->mode == QCEDEV_AES_MODE_XTS) &&
1477 (!podev->ce_support.aes_xts)) {
1478 pr_err("%s: XTS algorithm is not supported\n", __func__);
1479 goto error;
1480 }
1481 if (req->alg == QCEDEV_ALG_AES) {
1482 if (qcedev_check_cipher_key(req, podev))
1483 goto error;
1484
1485 }
1486 /* if using a byteoffset, make sure it is CTR mode using vbuf */
1487 if (req->byteoffset) {
1488 if (req->mode != QCEDEV_AES_MODE_CTR) {
1489 pr_err("%s: Operation on byte offset not supported\n",
1490 __func__);
1491 goto error;
1492 }
1493 if (req->byteoffset >= AES_CE_BLOCK_SIZE) {
1494 pr_err("%s: Invalid byte offset\n", __func__);
1495 goto error;
1496 }
1497 total = req->byteoffset;
1498 for (i = 0; i < req->entries; i++) {
1499 if (total > U32_MAX - req->vbuf.src[i].len) {
1500 pr_err("%s:Integer overflow on total src len\n",
1501 __func__);
1502 goto error;
1503 }
1504 total += req->vbuf.src[i].len;
1505 }
1506 }
1507
1508 if (req->data_len < req->byteoffset) {
1509 pr_err("%s: req data length %u is less than byteoffset %u\n",
1510 __func__, req->data_len, req->byteoffset);
1511 goto error;
1512 }
1513
1514 /* Ensure IV size */
1515 if (req->ivlen > QCEDEV_MAX_IV_SIZE) {
1516 pr_err("%s: ivlen is not correct: %u\n", __func__, req->ivlen);
1517 goto error;
1518 }
1519
1520 /* Ensure Key size */
1521 if (req->encklen > QCEDEV_MAX_KEY_SIZE) {
1522 pr_err("%s: Klen is not correct: %u\n", __func__, req->encklen);
1523 goto error;
1524 }
1525
1526 /* Ensure zer ivlen for ECB mode */
1527 if (req->ivlen > 0) {
1528 if ((req->mode == QCEDEV_AES_MODE_ECB) ||
1529 (req->mode == QCEDEV_DES_MODE_ECB)) {
1530 pr_err("%s: Expecting a zero length IV\n", __func__);
1531 goto error;
1532 }
1533 } else {
1534 if ((req->mode != QCEDEV_AES_MODE_ECB) &&
1535 (req->mode != QCEDEV_DES_MODE_ECB)) {
1536 pr_err("%s: Expecting a non-zero ength IV\n", __func__);
1537 goto error;
1538 }
1539 }
1540 /* Check for sum of all dst length is equal to data_len */
1541 for (i = 0, total = 0; i < req->entries; i++) {
1542 if (!req->vbuf.dst[i].vaddr && req->vbuf.dst[i].len) {
1543 pr_err("%s: NULL req dst vbuf[%d] with length %d\n",
1544 __func__, i, req->vbuf.dst[i].len);
1545 goto error;
1546 }
1547 if (req->vbuf.dst[i].len >= U32_MAX - total) {
1548 pr_err("%s: Integer overflow on total req dst vbuf length\n",
1549 __func__);
1550 goto error;
1551 }
1552 total += req->vbuf.dst[i].len;
1553 }
1554 if (total != req->data_len) {
1555 pr_err("%s: Total (i=%d) dst(%d) buf size != data_len (%d)\n",
1556 __func__, i, total, req->data_len);
1557 goto error;
1558 }
1559 /* Check for sum of all src length is equal to data_len */
1560 for (i = 0, total = 0; i < req->entries; i++) {
1561 if (!req->vbuf.src[i].vaddr && req->vbuf.src[i].len) {
1562 pr_err("%s: NULL req src vbuf[%d] with length %d\n",
1563 __func__, i, req->vbuf.src[i].len);
1564 goto error;
1565 }
1566 if (req->vbuf.src[i].len > U32_MAX - total) {
1567 pr_err("%s: Integer overflow on total req src vbuf length\n",
1568 __func__);
1569 goto error;
1570 }
1571 total += req->vbuf.src[i].len;
1572 }
1573 if (total != req->data_len) {
1574 pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
1575 __func__, total, req->data_len);
1576 goto error;
1577 }
1578 return 0;
1579error:
1580 return -EINVAL;
1581
1582}
1583
1584static int qcedev_check_sha_params(struct qcedev_sha_op_req *req,
1585 struct qcedev_control *podev)
1586{
1587 uint32_t total = 0;
1588 uint32_t i;
1589
1590 if ((req->alg == QCEDEV_ALG_AES_CMAC) &&
1591 (!podev->ce_support.cmac)) {
1592 pr_err("%s: CMAC not supported\n", __func__);
1593 goto sha_error;
1594 }
1595 if ((!req->entries) || (req->entries > QCEDEV_MAX_BUFFERS)) {
1596 pr_err("%s: Invalid num entries (%d)\n",
1597 __func__, req->entries);
1598 goto sha_error;
1599 }
1600
1601 if (req->alg >= QCEDEV_ALG_SHA_ALG_LAST) {
1602 pr_err("%s: Invalid algorithm (%d)\n", __func__, req->alg);
1603 goto sha_error;
1604 }
1605 if ((req->alg == QCEDEV_ALG_SHA1_HMAC) ||
1606 (req->alg == QCEDEV_ALG_SHA1_HMAC)) {
1607 if (req->authkey == NULL) {
1608 pr_err("%s: Invalid authkey pointer\n", __func__);
1609 goto sha_error;
1610 }
1611 if (req->authklen <= 0) {
1612 pr_err("%s: Invalid authkey length (%d)\n",
1613 __func__, req->authklen);
1614 goto sha_error;
1615 }
1616 }
1617
1618 if (req->alg == QCEDEV_ALG_AES_CMAC) {
1619 if ((req->authklen != QCEDEV_AES_KEY_128) &&
1620 (req->authklen != QCEDEV_AES_KEY_256)) {
1621 pr_err("%s: unsupported key length\n", __func__);
1622 goto sha_error;
1623 }
1624 }
1625
1626 /* Check for sum of all src length is equal to data_len */
1627 for (i = 0, total = 0; i < req->entries; i++) {
1628 if (req->data[i].len > U32_MAX - total) {
1629 pr_err("%s: Integer overflow on total req buf length\n",
1630 __func__);
1631 goto sha_error;
1632 }
1633 total += req->data[i].len;
1634 }
1635
1636 if (total != req->data_len) {
1637 pr_err("%s: Total src(%d) buf size != data_len (%d)\n",
1638 __func__, total, req->data_len);
1639 goto sha_error;
1640 }
1641 return 0;
1642sha_error:
1643 return -EINVAL;
1644}
1645
1646static inline long qcedev_ioctl(struct file *file,
1647 unsigned int cmd, unsigned long arg)
1648{
1649 int err = 0;
1650 struct qcedev_handle *handle;
1651 struct qcedev_control *podev;
1652 struct qcedev_async_req qcedev_areq;
1653 struct qcedev_stat *pstat;
1654
1655 handle = file->private_data;
1656 podev = handle->cntl;
1657 qcedev_areq.handle = handle;
1658 if (podev == NULL || podev->magic != QCEDEV_MAGIC) {
mohamed sunfeerc6b8e6d2017-06-29 15:13:34 +05301659 pr_err("%s: invalid handle %pK\n",
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001660 __func__, podev);
1661 return -ENOENT;
1662 }
1663
1664 /* Verify user arguments. */
1665 if (_IOC_TYPE(cmd) != QCEDEV_IOC_MAGIC)
1666 return -ENOTTY;
1667
1668 init_completion(&qcedev_areq.complete);
1669 pstat = &_qcedev_stat;
1670
1671 switch (cmd) {
1672 case QCEDEV_IOCTL_ENC_REQ:
1673 case QCEDEV_IOCTL_DEC_REQ:
1674 if (copy_from_user(&qcedev_areq.cipher_op_req,
1675 (void __user *)arg,
1676 sizeof(struct qcedev_cipher_op_req)))
1677 return -EFAULT;
1678 qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_CIPHER;
1679
1680 if (qcedev_check_cipher_params(&qcedev_areq.cipher_op_req,
1681 podev))
1682 return -EINVAL;
1683
1684 err = qcedev_vbuf_ablk_cipher(&qcedev_areq, handle);
1685 if (err)
1686 return err;
1687 if (copy_to_user((void __user *)arg,
1688 &qcedev_areq.cipher_op_req,
1689 sizeof(struct qcedev_cipher_op_req)))
1690 return -EFAULT;
1691 break;
1692
1693 case QCEDEV_IOCTL_SHA_INIT_REQ:
1694 {
1695 struct scatterlist sg_src;
1696
1697 if (copy_from_user(&qcedev_areq.sha_op_req,
1698 (void __user *)arg,
1699 sizeof(struct qcedev_sha_op_req)))
1700 return -EFAULT;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301701 mutex_lock(&hash_access_lock);
1702 if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) {
1703 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001704 return -EINVAL;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301705 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001706 qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
1707 err = qcedev_hash_init(&qcedev_areq, handle, &sg_src);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301708 if (err) {
1709 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001710 return err;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301711 }
1712 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001713 if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,
1714 sizeof(struct qcedev_sha_op_req)))
1715 return -EFAULT;
1716 }
1717 handle->sha_ctxt.init_done = true;
1718 break;
1719 case QCEDEV_IOCTL_GET_CMAC_REQ:
1720 if (!podev->ce_support.cmac)
1721 return -ENOTTY;
1722 case QCEDEV_IOCTL_SHA_UPDATE_REQ:
1723 {
1724 struct scatterlist sg_src;
1725
1726 if (copy_from_user(&qcedev_areq.sha_op_req,
1727 (void __user *)arg,
1728 sizeof(struct qcedev_sha_op_req)))
1729 return -EFAULT;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301730 mutex_lock(&hash_access_lock);
1731 if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) {
1732 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001733 return -EINVAL;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301734 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001735 qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
1736
1737 if (qcedev_areq.sha_op_req.alg == QCEDEV_ALG_AES_CMAC) {
1738 err = qcedev_hash_cmac(&qcedev_areq, handle, &sg_src);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301739 if (err) {
1740 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001741 return err;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301742 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001743 } else {
1744 if (handle->sha_ctxt.init_done == false) {
1745 pr_err("%s Init was not called\n", __func__);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301746 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001747 return -EINVAL;
1748 }
1749 err = qcedev_hash_update(&qcedev_areq, handle, &sg_src);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301750 if (err) {
1751 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001752 return err;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301753 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001754 }
1755
1756 if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
1757 pr_err("Invalid sha_ctxt.diglen %d\n",
1758 handle->sha_ctxt.diglen);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301759 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001760 return -EINVAL;
1761 }
1762 memcpy(&qcedev_areq.sha_op_req.digest[0],
1763 &handle->sha_ctxt.digest[0],
1764 handle->sha_ctxt.diglen);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301765 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001766 if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,
1767 sizeof(struct qcedev_sha_op_req)))
1768 return -EFAULT;
1769 }
1770 break;
1771
1772 case QCEDEV_IOCTL_SHA_FINAL_REQ:
1773
1774 if (handle->sha_ctxt.init_done == false) {
1775 pr_err("%s Init was not called\n", __func__);
1776 return -EINVAL;
1777 }
1778 if (copy_from_user(&qcedev_areq.sha_op_req,
1779 (void __user *)arg,
1780 sizeof(struct qcedev_sha_op_req)))
1781 return -EFAULT;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301782 mutex_lock(&hash_access_lock);
1783 if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) {
1784 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001785 return -EINVAL;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301786 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001787 qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
1788 err = qcedev_hash_final(&qcedev_areq, handle);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301789 if (err) {
1790 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001791 return err;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301792 }
Brahmaji K2ec40862017-05-15 16:02:15 +05301793 if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
1794 pr_err("Invalid sha_ctxt.diglen %d\n",
1795 handle->sha_ctxt.diglen);
1796 mutex_unlock(&hash_access_lock);
1797 return -EINVAL;
1798 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001799 qcedev_areq.sha_op_req.diglen = handle->sha_ctxt.diglen;
1800 memcpy(&qcedev_areq.sha_op_req.digest[0],
1801 &handle->sha_ctxt.digest[0],
1802 handle->sha_ctxt.diglen);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301803 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001804 if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,
1805 sizeof(struct qcedev_sha_op_req)))
1806 return -EFAULT;
1807 handle->sha_ctxt.init_done = false;
1808 break;
1809
1810 case QCEDEV_IOCTL_GET_SHA_REQ:
1811 {
1812 struct scatterlist sg_src;
1813
1814 if (copy_from_user(&qcedev_areq.sha_op_req,
1815 (void __user *)arg,
1816 sizeof(struct qcedev_sha_op_req)))
1817 return -EFAULT;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301818 mutex_lock(&hash_access_lock);
1819 if (qcedev_check_sha_params(&qcedev_areq.sha_op_req, podev)) {
1820 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001821 return -EINVAL;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301822 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001823 qcedev_areq.op_type = QCEDEV_CRYPTO_OPER_SHA;
1824 qcedev_hash_init(&qcedev_areq, handle, &sg_src);
1825 err = qcedev_hash_update(&qcedev_areq, handle, &sg_src);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301826 if (err) {
1827 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001828 return err;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301829 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001830 err = qcedev_hash_final(&qcedev_areq, handle);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301831 if (err) {
1832 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001833 return err;
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301834 }
Brahmaji K2ec40862017-05-15 16:02:15 +05301835 if (handle->sha_ctxt.diglen > QCEDEV_MAX_SHA_DIGEST) {
1836 pr_err("Invalid sha_ctxt.diglen %d\n",
1837 handle->sha_ctxt.diglen);
1838 mutex_unlock(&hash_access_lock);
1839 return -EINVAL;
1840 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001841 qcedev_areq.sha_op_req.diglen = handle->sha_ctxt.diglen;
1842 memcpy(&qcedev_areq.sha_op_req.digest[0],
1843 &handle->sha_ctxt.digest[0],
1844 handle->sha_ctxt.diglen);
AnilKumar Chimatab9805a32017-03-13 16:13:47 +05301845 mutex_unlock(&hash_access_lock);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001846 if (copy_to_user((void __user *)arg, &qcedev_areq.sha_op_req,
1847 sizeof(struct qcedev_sha_op_req)))
1848 return -EFAULT;
1849 }
1850 break;
1851
1852 default:
1853 return -ENOTTY;
1854 }
1855
1856 return err;
1857}
1858
1859static int qcedev_probe(struct platform_device *pdev)
1860{
1861 void *handle = NULL;
1862 int rc = 0;
1863 struct qcedev_control *podev;
1864 struct msm_ce_hw_support *platform_support;
1865
1866 podev = &qce_dev[0];
1867
1868 podev->high_bw_req_count = 0;
1869 INIT_LIST_HEAD(&podev->ready_commands);
1870 podev->active_command = NULL;
1871
1872 spin_lock_init(&podev->lock);
1873
1874 tasklet_init(&podev->done_tasklet, req_done, (unsigned long)podev);
1875
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001876 podev->platform_support.bus_scale_table = (struct msm_bus_scale_pdata *)
1877 msm_bus_cl_get_pdata(pdev);
1878 if (!podev->platform_support.bus_scale_table) {
1879 pr_err("bus_scale_table is NULL\n");
1880 return -ENODATA;
1881 }
1882 podev->bus_scale_handle = msm_bus_scale_register_client(
1883 (struct msm_bus_scale_pdata *)
1884 podev->platform_support.bus_scale_table);
1885 if (!podev->bus_scale_handle) {
1886 pr_err("%s not able to get bus scale\n", __func__);
1887 return -ENOMEM;
1888 }
1889
1890 rc = msm_bus_scale_client_update_request(podev->bus_scale_handle, 1);
1891 if (rc) {
1892 pr_err("%s Unable to set to high bandwidth\n", __func__);
1893 goto exit_unregister_bus_scale;
1894 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001895 handle = qce_open(pdev, &rc);
1896 if (handle == NULL) {
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001897 rc = -ENODEV;
1898 goto exit_scale_busbandwidth;
1899 }
1900 rc = msm_bus_scale_client_update_request(podev->bus_scale_handle, 0);
1901 if (rc) {
1902 pr_err("%s Unable to set to low bandwidth\n", __func__);
1903 goto exit_qce_close;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001904 }
1905
1906 podev->qce = handle;
1907 podev->pdev = pdev;
1908 platform_set_drvdata(pdev, podev);
1909
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001910 qce_hw_support(podev->qce, &podev->ce_support);
1911 if (podev->ce_support.bam) {
1912 podev->platform_support.ce_shared = 0;
1913 podev->platform_support.shared_ce_resource = 0;
1914 podev->platform_support.hw_key_support =
1915 podev->ce_support.hw_key;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001916 podev->platform_support.sha_hmac = 1;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001917 } else {
1918 platform_support =
1919 (struct msm_ce_hw_support *)pdev->dev.platform_data;
1920 podev->platform_support.ce_shared = platform_support->ce_shared;
1921 podev->platform_support.shared_ce_resource =
1922 platform_support->shared_ce_resource;
1923 podev->platform_support.hw_key_support =
1924 platform_support->hw_key_support;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001925 podev->platform_support.sha_hmac = platform_support->sha_hmac;
1926 }
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001927
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001928 rc = misc_register(&podev->miscdevice);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001929 if (rc >= 0)
1930 return 0;
1931
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001932 misc_deregister(&podev->miscdevice);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001933
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001934exit_qce_close:
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001935 if (handle)
1936 qce_close(handle);
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001937exit_scale_busbandwidth:
1938 msm_bus_scale_client_update_request(podev->bus_scale_handle, 0);
1939exit_unregister_bus_scale:
1940 if (podev->platform_support.bus_scale_table != NULL)
1941 msm_bus_scale_unregister_client(podev->bus_scale_handle);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001942 platform_set_drvdata(pdev, NULL);
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001943 podev->pdev = NULL;
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001944 podev->qce = NULL;
1945
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001946 return rc;
1947};
1948
1949static int qcedev_remove(struct platform_device *pdev)
1950{
1951 struct qcedev_control *podev;
1952
1953 podev = platform_get_drvdata(pdev);
1954 if (!podev)
1955 return 0;
1956 if (podev->qce)
1957 qce_close(podev->qce);
1958
1959 if (podev->platform_support.bus_scale_table != NULL)
1960 msm_bus_scale_unregister_client(podev->bus_scale_handle);
1961
1962 if (podev->miscdevice.minor != MISC_DYNAMIC_MINOR)
1963 misc_deregister(&podev->miscdevice);
1964 tasklet_kill(&podev->done_tasklet);
1965 return 0;
1966};
1967
1968static int qcedev_suspend(struct platform_device *pdev, pm_message_t state)
1969{
1970 struct qcedev_control *podev;
1971 int ret;
1972
1973 podev = platform_get_drvdata(pdev);
1974
1975 if (!podev || !podev->platform_support.bus_scale_table)
1976 return 0;
1977
1978 mutex_lock(&qcedev_sent_bw_req);
1979 if (podev->high_bw_req_count) {
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07001980 ret = qcedev_control_clocks(podev, false);
1981 if (ret)
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001982 goto suspend_exit;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07001983 }
1984
1985suspend_exit:
1986 mutex_unlock(&qcedev_sent_bw_req);
1987 return 0;
1988}
1989
1990static int qcedev_resume(struct platform_device *pdev)
1991{
1992 struct qcedev_control *podev;
1993 int ret;
1994
1995 podev = platform_get_drvdata(pdev);
1996
1997 if (!podev || !podev->platform_support.bus_scale_table)
1998 return 0;
1999
2000 mutex_lock(&qcedev_sent_bw_req);
2001 if (podev->high_bw_req_count) {
AnilKumar Chimatae5e60512017-05-03 14:06:59 -07002002 ret = qcedev_control_clocks(podev, true);
2003 if (ret)
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07002004 goto resume_exit;
AnilKumar Chimatae78789a2017-04-07 12:18:46 -07002005 }
2006
2007resume_exit:
2008 mutex_unlock(&qcedev_sent_bw_req);
2009 return 0;
2010}
2011
2012static const struct of_device_id qcedev_match[] = {
2013 { .compatible = "qcom,qcedev",
2014 },
2015 {}
2016};
2017
2018static struct platform_driver qcedev_plat_driver = {
2019 .probe = qcedev_probe,
2020 .remove = qcedev_remove,
2021 .suspend = qcedev_suspend,
2022 .resume = qcedev_resume,
2023 .driver = {
2024 .name = "qce",
2025 .owner = THIS_MODULE,
2026 .of_match_table = qcedev_match,
2027 },
2028};
2029
2030static int _disp_stats(int id)
2031{
2032 struct qcedev_stat *pstat;
2033 int len = 0;
2034
2035 pstat = &_qcedev_stat;
2036 len = scnprintf(_debug_read_buf, DEBUG_MAX_RW_BUF - 1,
2037 "\nQTI QCE dev driver %d Statistics:\n",
2038 id + 1);
2039
2040 len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
2041 " Encryption operation success : %d\n",
2042 pstat->qcedev_enc_success);
2043 len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
2044 " Encryption operation fail : %d\n",
2045 pstat->qcedev_enc_fail);
2046 len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
2047 " Decryption operation success : %d\n",
2048 pstat->qcedev_dec_success);
2049
2050 len += scnprintf(_debug_read_buf + len, DEBUG_MAX_RW_BUF - len - 1,
2051 " Encryption operation fail : %d\n",
2052 pstat->qcedev_dec_fail);
2053
2054 return len;
2055}
2056
2057static int _debug_stats_open(struct inode *inode, struct file *file)
2058{
2059 file->private_data = inode->i_private;
2060 return 0;
2061}
2062
2063static ssize_t _debug_stats_read(struct file *file, char __user *buf,
2064 size_t count, loff_t *ppos)
2065{
2066 ssize_t rc = -EINVAL;
2067 int qcedev = *((int *) file->private_data);
2068 int len;
2069
2070 len = _disp_stats(qcedev);
2071
2072 if (len <= count)
2073 rc = simple_read_from_buffer((void __user *) buf, len,
2074 ppos, (void *) _debug_read_buf, len);
2075 return rc;
2076}
2077
2078static ssize_t _debug_stats_write(struct file *file, const char __user *buf,
2079 size_t count, loff_t *ppos)
2080{
2081 memset((char *)&_qcedev_stat, 0, sizeof(struct qcedev_stat));
2082 return count;
2083};
2084
2085static const struct file_operations _debug_stats_ops = {
2086 .open = _debug_stats_open,
2087 .read = _debug_stats_read,
2088 .write = _debug_stats_write,
2089};
2090
2091static int _qcedev_debug_init(void)
2092{
2093 int rc;
2094 char name[DEBUG_MAX_FNAME];
2095 struct dentry *dent;
2096
2097 _debug_dent = debugfs_create_dir("qcedev", NULL);
2098 if (IS_ERR(_debug_dent)) {
2099 pr_err("qcedev debugfs_create_dir fail, error %ld\n",
2100 PTR_ERR(_debug_dent));
2101 return PTR_ERR(_debug_dent);
2102 }
2103
2104 snprintf(name, DEBUG_MAX_FNAME-1, "stats-%d", 1);
2105 _debug_qcedev = 0;
2106 dent = debugfs_create_file(name, 0644, _debug_dent,
2107 &_debug_qcedev, &_debug_stats_ops);
2108 if (dent == NULL) {
2109 pr_err("qcedev debugfs_create_file fail, error %ld\n",
2110 PTR_ERR(dent));
2111 rc = PTR_ERR(dent);
2112 goto err;
2113 }
2114 return 0;
2115err:
2116 debugfs_remove_recursive(_debug_dent);
2117 return rc;
2118}
2119
2120static int qcedev_init(void)
2121{
2122 int rc;
2123
2124 rc = _qcedev_debug_init();
2125 if (rc)
2126 return rc;
2127 return platform_driver_register(&qcedev_plat_driver);
2128}
2129
2130static void qcedev_exit(void)
2131{
2132 debugfs_remove_recursive(_debug_dent);
2133 platform_driver_unregister(&qcedev_plat_driver);
2134}
2135
2136MODULE_LICENSE("GPL v2");
2137MODULE_DESCRIPTION("QTI DEV Crypto driver");
2138
2139module_init(qcedev_init);
2140module_exit(qcedev_exit);