David Daney | 8860fb8 | 2009-04-23 17:44:37 -0700 | [diff] [blame] | 1 | /***********************license start*************** |
| 2 | * Author: Cavium Networks |
| 3 | * |
| 4 | * Contact: support@caviumnetworks.com |
| 5 | * This file is part of the OCTEON SDK |
| 6 | * |
David Daney | aa32a95 | 2010-10-07 16:03:40 -0700 | [diff] [blame] | 7 | * Copyright (c) 2003-2010 Cavium Networks |
David Daney | 8860fb8 | 2009-04-23 17:44:37 -0700 | [diff] [blame] | 8 | * |
| 9 | * This file is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License, Version 2, as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This file is distributed in the hope that it will be useful, but |
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty |
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or |
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more |
| 17 | * details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this file; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 22 | * or visit http://www.gnu.org/licenses/. |
| 23 | * |
| 24 | * This file may also be available under a different license from Cavium. |
| 25 | * Contact Cavium Networks for more information |
| 26 | ***********************license end**************************************/ |
| 27 | |
| 28 | #ifndef __CVMX_PESCX_DEFS_H__ |
| 29 | #define __CVMX_PESCX_DEFS_H__ |
| 30 | |
David Daney | aa32a95 | 2010-10-07 16:03:40 -0700 | [diff] [blame] | 31 | #define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull) |
| 32 | #define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull) |
| 33 | #define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull) |
| 34 | #define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull) |
| 35 | #define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull) |
| 36 | #define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull) |
| 37 | #define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull) |
| 38 | #define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull) |
| 39 | #define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull) |
| 40 | #define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull) |
| 41 | #define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull) |
| 42 | #define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull) |
| 43 | #define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull) |
| 44 | #define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16) |
| 45 | #define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16) |
| 46 | #define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull) |
David Daney | 8860fb8 | 2009-04-23 17:44:37 -0700 | [diff] [blame] | 47 | |
| 48 | union cvmx_pescx_bist_status { |
| 49 | uint64_t u64; |
| 50 | struct cvmx_pescx_bist_status_s { |
| 51 | uint64_t reserved_13_63:51; |
| 52 | uint64_t rqdata5:1; |
| 53 | uint64_t ctlp_or:1; |
| 54 | uint64_t ntlp_or:1; |
| 55 | uint64_t ptlp_or:1; |
| 56 | uint64_t retry:1; |
| 57 | uint64_t rqdata0:1; |
| 58 | uint64_t rqdata1:1; |
| 59 | uint64_t rqdata2:1; |
| 60 | uint64_t rqdata3:1; |
| 61 | uint64_t rqdata4:1; |
| 62 | uint64_t rqhdr1:1; |
| 63 | uint64_t rqhdr0:1; |
| 64 | uint64_t sot:1; |
| 65 | } s; |
| 66 | struct cvmx_pescx_bist_status_s cn52xx; |
| 67 | struct cvmx_pescx_bist_status_cn52xxp1 { |
| 68 | uint64_t reserved_12_63:52; |
| 69 | uint64_t ctlp_or:1; |
| 70 | uint64_t ntlp_or:1; |
| 71 | uint64_t ptlp_or:1; |
| 72 | uint64_t retry:1; |
| 73 | uint64_t rqdata0:1; |
| 74 | uint64_t rqdata1:1; |
| 75 | uint64_t rqdata2:1; |
| 76 | uint64_t rqdata3:1; |
| 77 | uint64_t rqdata4:1; |
| 78 | uint64_t rqhdr1:1; |
| 79 | uint64_t rqhdr0:1; |
| 80 | uint64_t sot:1; |
| 81 | } cn52xxp1; |
| 82 | struct cvmx_pescx_bist_status_s cn56xx; |
| 83 | struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1; |
| 84 | }; |
| 85 | |
| 86 | union cvmx_pescx_bist_status2 { |
| 87 | uint64_t u64; |
| 88 | struct cvmx_pescx_bist_status2_s { |
| 89 | uint64_t reserved_14_63:50; |
| 90 | uint64_t cto_p2e:1; |
| 91 | uint64_t e2p_cpl:1; |
| 92 | uint64_t e2p_n:1; |
| 93 | uint64_t e2p_p:1; |
| 94 | uint64_t e2p_rsl:1; |
| 95 | uint64_t dbg_p2e:1; |
| 96 | uint64_t peai_p2e:1; |
| 97 | uint64_t rsl_p2e:1; |
| 98 | uint64_t pef_tpf1:1; |
| 99 | uint64_t pef_tpf0:1; |
| 100 | uint64_t pef_tnf:1; |
| 101 | uint64_t pef_tcf1:1; |
| 102 | uint64_t pef_tc0:1; |
| 103 | uint64_t ppf:1; |
| 104 | } s; |
| 105 | struct cvmx_pescx_bist_status2_s cn52xx; |
| 106 | struct cvmx_pescx_bist_status2_s cn52xxp1; |
| 107 | struct cvmx_pescx_bist_status2_s cn56xx; |
| 108 | struct cvmx_pescx_bist_status2_s cn56xxp1; |
| 109 | }; |
| 110 | |
| 111 | union cvmx_pescx_cfg_rd { |
| 112 | uint64_t u64; |
| 113 | struct cvmx_pescx_cfg_rd_s { |
| 114 | uint64_t data:32; |
| 115 | uint64_t addr:32; |
| 116 | } s; |
| 117 | struct cvmx_pescx_cfg_rd_s cn52xx; |
| 118 | struct cvmx_pescx_cfg_rd_s cn52xxp1; |
| 119 | struct cvmx_pescx_cfg_rd_s cn56xx; |
| 120 | struct cvmx_pescx_cfg_rd_s cn56xxp1; |
| 121 | }; |
| 122 | |
| 123 | union cvmx_pescx_cfg_wr { |
| 124 | uint64_t u64; |
| 125 | struct cvmx_pescx_cfg_wr_s { |
| 126 | uint64_t data:32; |
| 127 | uint64_t addr:32; |
| 128 | } s; |
| 129 | struct cvmx_pescx_cfg_wr_s cn52xx; |
| 130 | struct cvmx_pescx_cfg_wr_s cn52xxp1; |
| 131 | struct cvmx_pescx_cfg_wr_s cn56xx; |
| 132 | struct cvmx_pescx_cfg_wr_s cn56xxp1; |
| 133 | }; |
| 134 | |
| 135 | union cvmx_pescx_cpl_lut_valid { |
| 136 | uint64_t u64; |
| 137 | struct cvmx_pescx_cpl_lut_valid_s { |
| 138 | uint64_t reserved_32_63:32; |
| 139 | uint64_t tag:32; |
| 140 | } s; |
| 141 | struct cvmx_pescx_cpl_lut_valid_s cn52xx; |
| 142 | struct cvmx_pescx_cpl_lut_valid_s cn52xxp1; |
| 143 | struct cvmx_pescx_cpl_lut_valid_s cn56xx; |
| 144 | struct cvmx_pescx_cpl_lut_valid_s cn56xxp1; |
| 145 | }; |
| 146 | |
| 147 | union cvmx_pescx_ctl_status { |
| 148 | uint64_t u64; |
| 149 | struct cvmx_pescx_ctl_status_s { |
| 150 | uint64_t reserved_28_63:36; |
| 151 | uint64_t dnum:5; |
| 152 | uint64_t pbus:8; |
| 153 | uint64_t qlm_cfg:2; |
| 154 | uint64_t lane_swp:1; |
| 155 | uint64_t pm_xtoff:1; |
| 156 | uint64_t pm_xpme:1; |
| 157 | uint64_t ob_p_cmd:1; |
| 158 | uint64_t reserved_7_8:2; |
| 159 | uint64_t nf_ecrc:1; |
| 160 | uint64_t dly_one:1; |
| 161 | uint64_t lnk_enb:1; |
| 162 | uint64_t ro_ctlp:1; |
| 163 | uint64_t reserved_2_2:1; |
| 164 | uint64_t inv_ecrc:1; |
| 165 | uint64_t inv_lcrc:1; |
| 166 | } s; |
| 167 | struct cvmx_pescx_ctl_status_s cn52xx; |
| 168 | struct cvmx_pescx_ctl_status_s cn52xxp1; |
| 169 | struct cvmx_pescx_ctl_status_cn56xx { |
| 170 | uint64_t reserved_28_63:36; |
| 171 | uint64_t dnum:5; |
| 172 | uint64_t pbus:8; |
| 173 | uint64_t qlm_cfg:2; |
| 174 | uint64_t reserved_12_12:1; |
| 175 | uint64_t pm_xtoff:1; |
| 176 | uint64_t pm_xpme:1; |
| 177 | uint64_t ob_p_cmd:1; |
| 178 | uint64_t reserved_7_8:2; |
| 179 | uint64_t nf_ecrc:1; |
| 180 | uint64_t dly_one:1; |
| 181 | uint64_t lnk_enb:1; |
| 182 | uint64_t ro_ctlp:1; |
| 183 | uint64_t reserved_2_2:1; |
| 184 | uint64_t inv_ecrc:1; |
| 185 | uint64_t inv_lcrc:1; |
| 186 | } cn56xx; |
| 187 | struct cvmx_pescx_ctl_status_cn56xx cn56xxp1; |
| 188 | }; |
| 189 | |
| 190 | union cvmx_pescx_ctl_status2 { |
| 191 | uint64_t u64; |
| 192 | struct cvmx_pescx_ctl_status2_s { |
| 193 | uint64_t reserved_2_63:62; |
| 194 | uint64_t pclk_run:1; |
| 195 | uint64_t pcierst:1; |
| 196 | } s; |
| 197 | struct cvmx_pescx_ctl_status2_s cn52xx; |
| 198 | struct cvmx_pescx_ctl_status2_cn52xxp1 { |
| 199 | uint64_t reserved_1_63:63; |
| 200 | uint64_t pcierst:1; |
| 201 | } cn52xxp1; |
| 202 | struct cvmx_pescx_ctl_status2_s cn56xx; |
| 203 | struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1; |
| 204 | }; |
| 205 | |
| 206 | union cvmx_pescx_dbg_info { |
| 207 | uint64_t u64; |
| 208 | struct cvmx_pescx_dbg_info_s { |
| 209 | uint64_t reserved_31_63:33; |
| 210 | uint64_t ecrc_e:1; |
| 211 | uint64_t rawwpp:1; |
| 212 | uint64_t racpp:1; |
| 213 | uint64_t ramtlp:1; |
| 214 | uint64_t rarwdns:1; |
| 215 | uint64_t caar:1; |
| 216 | uint64_t racca:1; |
| 217 | uint64_t racur:1; |
| 218 | uint64_t rauc:1; |
| 219 | uint64_t rqo:1; |
| 220 | uint64_t fcuv:1; |
| 221 | uint64_t rpe:1; |
| 222 | uint64_t fcpvwt:1; |
| 223 | uint64_t dpeoosd:1; |
| 224 | uint64_t rtwdle:1; |
| 225 | uint64_t rdwdle:1; |
| 226 | uint64_t mre:1; |
| 227 | uint64_t rte:1; |
| 228 | uint64_t acto:1; |
| 229 | uint64_t rvdm:1; |
| 230 | uint64_t rumep:1; |
| 231 | uint64_t rptamrc:1; |
| 232 | uint64_t rpmerc:1; |
| 233 | uint64_t rfemrc:1; |
| 234 | uint64_t rnfemrc:1; |
| 235 | uint64_t rcemrc:1; |
| 236 | uint64_t rpoison:1; |
| 237 | uint64_t recrce:1; |
| 238 | uint64_t rtlplle:1; |
| 239 | uint64_t rtlpmal:1; |
| 240 | uint64_t spoison:1; |
| 241 | } s; |
| 242 | struct cvmx_pescx_dbg_info_s cn52xx; |
| 243 | struct cvmx_pescx_dbg_info_s cn52xxp1; |
| 244 | struct cvmx_pescx_dbg_info_s cn56xx; |
| 245 | struct cvmx_pescx_dbg_info_s cn56xxp1; |
| 246 | }; |
| 247 | |
| 248 | union cvmx_pescx_dbg_info_en { |
| 249 | uint64_t u64; |
| 250 | struct cvmx_pescx_dbg_info_en_s { |
| 251 | uint64_t reserved_31_63:33; |
| 252 | uint64_t ecrc_e:1; |
| 253 | uint64_t rawwpp:1; |
| 254 | uint64_t racpp:1; |
| 255 | uint64_t ramtlp:1; |
| 256 | uint64_t rarwdns:1; |
| 257 | uint64_t caar:1; |
| 258 | uint64_t racca:1; |
| 259 | uint64_t racur:1; |
| 260 | uint64_t rauc:1; |
| 261 | uint64_t rqo:1; |
| 262 | uint64_t fcuv:1; |
| 263 | uint64_t rpe:1; |
| 264 | uint64_t fcpvwt:1; |
| 265 | uint64_t dpeoosd:1; |
| 266 | uint64_t rtwdle:1; |
| 267 | uint64_t rdwdle:1; |
| 268 | uint64_t mre:1; |
| 269 | uint64_t rte:1; |
| 270 | uint64_t acto:1; |
| 271 | uint64_t rvdm:1; |
| 272 | uint64_t rumep:1; |
| 273 | uint64_t rptamrc:1; |
| 274 | uint64_t rpmerc:1; |
| 275 | uint64_t rfemrc:1; |
| 276 | uint64_t rnfemrc:1; |
| 277 | uint64_t rcemrc:1; |
| 278 | uint64_t rpoison:1; |
| 279 | uint64_t recrce:1; |
| 280 | uint64_t rtlplle:1; |
| 281 | uint64_t rtlpmal:1; |
| 282 | uint64_t spoison:1; |
| 283 | } s; |
| 284 | struct cvmx_pescx_dbg_info_en_s cn52xx; |
| 285 | struct cvmx_pescx_dbg_info_en_s cn52xxp1; |
| 286 | struct cvmx_pescx_dbg_info_en_s cn56xx; |
| 287 | struct cvmx_pescx_dbg_info_en_s cn56xxp1; |
| 288 | }; |
| 289 | |
| 290 | union cvmx_pescx_diag_status { |
| 291 | uint64_t u64; |
| 292 | struct cvmx_pescx_diag_status_s { |
| 293 | uint64_t reserved_4_63:60; |
| 294 | uint64_t pm_dst:1; |
| 295 | uint64_t pm_stat:1; |
| 296 | uint64_t pm_en:1; |
| 297 | uint64_t aux_en:1; |
| 298 | } s; |
| 299 | struct cvmx_pescx_diag_status_s cn52xx; |
| 300 | struct cvmx_pescx_diag_status_s cn52xxp1; |
| 301 | struct cvmx_pescx_diag_status_s cn56xx; |
| 302 | struct cvmx_pescx_diag_status_s cn56xxp1; |
| 303 | }; |
| 304 | |
| 305 | union cvmx_pescx_p2n_bar0_start { |
| 306 | uint64_t u64; |
| 307 | struct cvmx_pescx_p2n_bar0_start_s { |
| 308 | uint64_t addr:50; |
| 309 | uint64_t reserved_0_13:14; |
| 310 | } s; |
| 311 | struct cvmx_pescx_p2n_bar0_start_s cn52xx; |
| 312 | struct cvmx_pescx_p2n_bar0_start_s cn52xxp1; |
| 313 | struct cvmx_pescx_p2n_bar0_start_s cn56xx; |
| 314 | struct cvmx_pescx_p2n_bar0_start_s cn56xxp1; |
| 315 | }; |
| 316 | |
| 317 | union cvmx_pescx_p2n_bar1_start { |
| 318 | uint64_t u64; |
| 319 | struct cvmx_pescx_p2n_bar1_start_s { |
| 320 | uint64_t addr:38; |
| 321 | uint64_t reserved_0_25:26; |
| 322 | } s; |
| 323 | struct cvmx_pescx_p2n_bar1_start_s cn52xx; |
| 324 | struct cvmx_pescx_p2n_bar1_start_s cn52xxp1; |
| 325 | struct cvmx_pescx_p2n_bar1_start_s cn56xx; |
| 326 | struct cvmx_pescx_p2n_bar1_start_s cn56xxp1; |
| 327 | }; |
| 328 | |
| 329 | union cvmx_pescx_p2n_bar2_start { |
| 330 | uint64_t u64; |
| 331 | struct cvmx_pescx_p2n_bar2_start_s { |
| 332 | uint64_t addr:25; |
| 333 | uint64_t reserved_0_38:39; |
| 334 | } s; |
| 335 | struct cvmx_pescx_p2n_bar2_start_s cn52xx; |
| 336 | struct cvmx_pescx_p2n_bar2_start_s cn52xxp1; |
| 337 | struct cvmx_pescx_p2n_bar2_start_s cn56xx; |
| 338 | struct cvmx_pescx_p2n_bar2_start_s cn56xxp1; |
| 339 | }; |
| 340 | |
| 341 | union cvmx_pescx_p2p_barx_end { |
| 342 | uint64_t u64; |
| 343 | struct cvmx_pescx_p2p_barx_end_s { |
| 344 | uint64_t addr:52; |
| 345 | uint64_t reserved_0_11:12; |
| 346 | } s; |
| 347 | struct cvmx_pescx_p2p_barx_end_s cn52xx; |
| 348 | struct cvmx_pescx_p2p_barx_end_s cn52xxp1; |
| 349 | struct cvmx_pescx_p2p_barx_end_s cn56xx; |
| 350 | struct cvmx_pescx_p2p_barx_end_s cn56xxp1; |
| 351 | }; |
| 352 | |
| 353 | union cvmx_pescx_p2p_barx_start { |
| 354 | uint64_t u64; |
| 355 | struct cvmx_pescx_p2p_barx_start_s { |
| 356 | uint64_t addr:52; |
| 357 | uint64_t reserved_0_11:12; |
| 358 | } s; |
| 359 | struct cvmx_pescx_p2p_barx_start_s cn52xx; |
| 360 | struct cvmx_pescx_p2p_barx_start_s cn52xxp1; |
| 361 | struct cvmx_pescx_p2p_barx_start_s cn56xx; |
| 362 | struct cvmx_pescx_p2p_barx_start_s cn56xxp1; |
| 363 | }; |
| 364 | |
| 365 | union cvmx_pescx_tlp_credits { |
| 366 | uint64_t u64; |
| 367 | struct cvmx_pescx_tlp_credits_s { |
| 368 | uint64_t reserved_0_63:64; |
| 369 | } s; |
| 370 | struct cvmx_pescx_tlp_credits_cn52xx { |
| 371 | uint64_t reserved_56_63:8; |
| 372 | uint64_t peai_ppf:8; |
| 373 | uint64_t pesc_cpl:8; |
| 374 | uint64_t pesc_np:8; |
| 375 | uint64_t pesc_p:8; |
| 376 | uint64_t npei_cpl:8; |
| 377 | uint64_t npei_np:8; |
| 378 | uint64_t npei_p:8; |
| 379 | } cn52xx; |
| 380 | struct cvmx_pescx_tlp_credits_cn52xxp1 { |
| 381 | uint64_t reserved_38_63:26; |
| 382 | uint64_t peai_ppf:8; |
| 383 | uint64_t pesc_cpl:5; |
| 384 | uint64_t pesc_np:5; |
| 385 | uint64_t pesc_p:5; |
| 386 | uint64_t npei_cpl:5; |
| 387 | uint64_t npei_np:5; |
| 388 | uint64_t npei_p:5; |
| 389 | } cn52xxp1; |
| 390 | struct cvmx_pescx_tlp_credits_cn52xx cn56xx; |
| 391 | struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1; |
| 392 | }; |
| 393 | |
| 394 | #endif |