Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * Carsten Langgaard, carstenl@mips.com |
| 7 | * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. |
| 8 | * Copyright (C) 2001 Ralf Baechle |
Deng-Cheng Zhu | 1336113 | 2013-10-30 15:52:10 -0500 | [diff] [blame] | 9 | * Copyright (C) 2013 Imagination Technologies Ltd. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | * Routines for generic manipulation of the interrupts found on the MIPS |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 12 | * Malta board. The interrupt controller is located in the South Bridge |
| 13 | * a PIIX4 device with two internal 82C95 interrupt controllers. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | */ |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/irq.h> |
| 17 | #include <linux/sched.h> |
Ralf Baechle | 631330f | 2009-06-19 14:05:26 +0100 | [diff] [blame] | 18 | #include <linux/smp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #include <linux/interrupt.h> |
Dmitri Vorobiev | 54bf038 | 2008-01-24 19:52:49 +0300 | [diff] [blame] | 20 | #include <linux/io.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | #include <linux/kernel_stat.h> |
Ahmed S. Darwish | 25b8ac3 | 2007-02-05 04:42:11 +0200 | [diff] [blame] | 22 | #include <linux/kernel.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | #include <linux/random.h> |
| 24 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 25 | #include <asm/traps.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | #include <asm/i8259.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 27 | #include <asm/irq_cpu.h> |
Ralf Baechle | ba38cdf | 2006-10-15 09:17:43 +0100 | [diff] [blame] | 28 | #include <asm/irq_regs.h> |
Paul Burton | 237036d | 2014-01-15 10:31:54 +0000 | [diff] [blame] | 29 | #include <asm/mips-cm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include <asm/mips-boards/malta.h> |
| 31 | #include <asm/mips-boards/maltaint.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | #include <asm/gt64120.h> |
| 33 | #include <asm/mips-boards/generic.h> |
| 34 | #include <asm/mips-boards/msc01_pci.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 35 | #include <asm/msc01_ic.h> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 36 | #include <asm/gic.h> |
David Howells | b81947c | 2012-03-28 18:30:02 +0100 | [diff] [blame] | 37 | #include <asm/setup.h> |
Deng-Cheng Zhu | 1336113 | 2013-10-30 15:52:10 -0500 | [diff] [blame] | 38 | #include <asm/rtlx.h> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 39 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 40 | static unsigned long _msc01_biu_base; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | |
Ralf Baechle | a963dc7 | 2010-02-27 12:53:32 +0100 | [diff] [blame] | 42 | static DEFINE_RAW_SPINLOCK(mips_irq_lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | |
| 44 | static inline int mips_pcibios_iack(void) |
| 45 | { |
| 46 | int irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | |
| 48 | /* |
| 49 | * Determine highest priority pending interrupt by performing |
| 50 | * a PCI Interrupt Acknowledge cycle. |
| 51 | */ |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 52 | switch (mips_revision_sconid) { |
| 53 | case MIPS_REVISION_SCON_SOCIT: |
| 54 | case MIPS_REVISION_SCON_ROCIT: |
| 55 | case MIPS_REVISION_SCON_SOCITSC: |
| 56 | case MIPS_REVISION_SCON_SOCITSCP: |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 57 | MSC_READ(MSC01_PCI_IACK, irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | irq &= 0xff; |
| 59 | break; |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 60 | case MIPS_REVISION_SCON_GT64120: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | irq = GT_READ(GT_PCI0_IACK_OFS); |
| 62 | irq &= 0xff; |
| 63 | break; |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 64 | case MIPS_REVISION_SCON_BONITO: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 65 | /* The following will generate a PCI IACK cycle on the |
| 66 | * Bonito controller. It's a little bit kludgy, but it |
| 67 | * was the easiest way to implement it in hardware at |
| 68 | * the given time. |
| 69 | */ |
| 70 | BONITO_PCIMAP_CFG = 0x20000; |
| 71 | |
| 72 | /* Flush Bonito register block */ |
Ralf Baechle | 6be63bb | 2011-03-29 11:48:22 +0200 | [diff] [blame] | 73 | (void) BONITO_PCIMAP_CFG; |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 74 | iob(); /* sync */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | |
Chris Dearman | accfd35 | 2009-07-10 01:53:54 -0700 | [diff] [blame] | 76 | irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg); |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 77 | iob(); /* sync */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | irq &= 0xff; |
| 79 | BONITO_PCIMAP_CFG = 0; |
| 80 | break; |
| 81 | default: |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 82 | pr_emerg("Unknown system controller.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | return -1; |
| 84 | } |
| 85 | return irq; |
| 86 | } |
| 87 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 88 | static inline int get_int(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | { |
| 90 | unsigned long flags; |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 91 | int irq; |
Ralf Baechle | a963dc7 | 2010-02-27 12:53:32 +0100 | [diff] [blame] | 92 | raw_spin_lock_irqsave(&mips_irq_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 93 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 94 | irq = mips_pcibios_iack(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | |
| 96 | /* |
Ralf Baechle | 479a0e3 | 2005-08-16 15:44:06 +0000 | [diff] [blame] | 97 | * The only way we can decide if an interrupt is spurious |
| 98 | * is by checking the 8259 registers. This needs a spinlock |
| 99 | * on an SMP system, so leave it up to the generic code... |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | |
Ralf Baechle | a963dc7 | 2010-02-27 12:53:32 +0100 | [diff] [blame] | 102 | raw_spin_unlock_irqrestore(&mips_irq_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 104 | return irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | } |
| 106 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 107 | static void malta_hw0_irqdispatch(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | { |
| 109 | int irq; |
| 110 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 111 | irq = get_int(); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 112 | if (irq < 0) { |
Dmitri Vorobiev | cd80d54 | 2008-01-24 19:52:54 +0300 | [diff] [blame] | 113 | /* interrupt has already been cleared */ |
| 114 | return; |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 115 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 116 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 117 | do_IRQ(MALTA_INT_BASE + irq); |
Deng-Cheng Zhu | 1336113 | 2013-10-30 15:52:10 -0500 | [diff] [blame] | 118 | |
Deng-Cheng Zhu | 9c1f6e0 | 2014-02-28 10:23:01 -0800 | [diff] [blame] | 119 | #ifdef CONFIG_MIPS_VPE_APSP_API_MT |
Deng-Cheng Zhu | 1336113 | 2013-10-30 15:52:10 -0500 | [diff] [blame] | 120 | if (aprp_hook) |
| 121 | aprp_hook(); |
| 122 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 123 | } |
| 124 | |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame^] | 125 | static irqreturn_t i8259_handler(int irq, void *dev_id) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 126 | { |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame^] | 127 | malta_hw0_irqdispatch(); |
| 128 | return IRQ_HANDLED; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 129 | } |
| 130 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 131 | static void corehi_irqdispatch(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | { |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 133 | unsigned int intedge, intsteer, pcicmd, pcibadaddr; |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 134 | unsigned int pcimstat, intisr, inten, intpol; |
Ralf Baechle | 21a151d | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 135 | unsigned int intrcause, datalo, datahi; |
Ralf Baechle | ba38cdf | 2006-10-15 09:17:43 +0100 | [diff] [blame] | 136 | struct pt_regs *regs = get_irq_regs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 138 | pr_emerg("CoreHI interrupt, shouldn't happen, we die here!\n"); |
| 139 | pr_emerg("epc : %08lx\nStatus: %08lx\n" |
| 140 | "Cause : %08lx\nbadVaddr : %08lx\n", |
| 141 | regs->cp0_epc, regs->cp0_status, |
| 142 | regs->cp0_cause, regs->cp0_badvaddr); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 143 | |
| 144 | /* Read all the registers and then print them as there is a |
| 145 | problem with interspersed printk's upsetting the Bonito controller. |
| 146 | Do it for the others too. |
| 147 | */ |
| 148 | |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 149 | switch (mips_revision_sconid) { |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 150 | case MIPS_REVISION_SCON_SOCIT: |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 151 | case MIPS_REVISION_SCON_ROCIT: |
| 152 | case MIPS_REVISION_SCON_SOCITSC: |
| 153 | case MIPS_REVISION_SCON_SOCITSCP: |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 154 | ll_msc_irq(); |
| 155 | break; |
| 156 | case MIPS_REVISION_SCON_GT64120: |
| 157 | intrcause = GT_READ(GT_INTRCAUSE_OFS); |
| 158 | datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); |
| 159 | datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 160 | pr_emerg("GT_INTRCAUSE = %08x\n", intrcause); |
| 161 | pr_emerg("GT_CPUERR_ADDR = %02x%08x\n", |
Dmitri Vorobiev | 8216d34 | 2008-01-24 19:52:42 +0300 | [diff] [blame] | 162 | datahi, datalo); |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 163 | break; |
| 164 | case MIPS_REVISION_SCON_BONITO: |
| 165 | pcibadaddr = BONITO_PCIBADADDR; |
| 166 | pcimstat = BONITO_PCIMSTAT; |
| 167 | intisr = BONITO_INTISR; |
| 168 | inten = BONITO_INTEN; |
| 169 | intpol = BONITO_INTPOL; |
| 170 | intedge = BONITO_INTEDGE; |
| 171 | intsteer = BONITO_INTSTEER; |
| 172 | pcicmd = BONITO_PCICMD; |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 173 | pr_emerg("BONITO_INTISR = %08x\n", intisr); |
| 174 | pr_emerg("BONITO_INTEN = %08x\n", inten); |
| 175 | pr_emerg("BONITO_INTPOL = %08x\n", intpol); |
| 176 | pr_emerg("BONITO_INTEDGE = %08x\n", intedge); |
| 177 | pr_emerg("BONITO_INTSTEER = %08x\n", intsteer); |
| 178 | pr_emerg("BONITO_PCICMD = %08x\n", pcicmd); |
| 179 | pr_emerg("BONITO_PCIBADADDR = %08x\n", pcibadaddr); |
| 180 | pr_emerg("BONITO_PCIMSTAT = %08x\n", pcimstat); |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 181 | break; |
| 182 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 183 | |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 184 | die("CoreHi interrupt", regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 185 | } |
| 186 | |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame^] | 187 | static irqreturn_t corehi_handler(int irq, void *dev_id) |
| 188 | { |
| 189 | corehi_irqdispatch(); |
| 190 | return IRQ_HANDLED; |
| 191 | } |
| 192 | |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 193 | static inline int clz(unsigned long x) |
| 194 | { |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 195 | __asm__( |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 196 | " .set push \n" |
| 197 | " .set mips32 \n" |
| 198 | " clz %0, %1 \n" |
| 199 | " .set pop \n" |
| 200 | : "=r" (x) |
| 201 | : "r" (x)); |
| 202 | |
| 203 | return x; |
| 204 | } |
| 205 | |
| 206 | /* |
| 207 | * Version of ffs that only looks at bits 12..15. |
| 208 | */ |
| 209 | static inline unsigned int irq_ffs(unsigned int pending) |
| 210 | { |
| 211 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
| 212 | return -clz(pending) + 31 - CAUSEB_IP; |
| 213 | #else |
| 214 | unsigned int a0 = 7; |
| 215 | unsigned int t0; |
| 216 | |
Ralf Baechle | 0118c3c | 2006-06-05 11:54:41 +0100 | [diff] [blame] | 217 | t0 = pending & 0xf000; |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 218 | t0 = t0 < 1; |
| 219 | t0 = t0 << 2; |
| 220 | a0 = a0 - t0; |
Ralf Baechle | 0118c3c | 2006-06-05 11:54:41 +0100 | [diff] [blame] | 221 | pending = pending << t0; |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 222 | |
Ralf Baechle | 0118c3c | 2006-06-05 11:54:41 +0100 | [diff] [blame] | 223 | t0 = pending & 0xc000; |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 224 | t0 = t0 < 1; |
| 225 | t0 = t0 << 1; |
| 226 | a0 = a0 - t0; |
Ralf Baechle | 0118c3c | 2006-06-05 11:54:41 +0100 | [diff] [blame] | 227 | pending = pending << t0; |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 228 | |
Ralf Baechle | 0118c3c | 2006-06-05 11:54:41 +0100 | [diff] [blame] | 229 | t0 = pending & 0x8000; |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 230 | t0 = t0 < 1; |
Dmitri Vorobiev | ae9cef0 | 2008-01-24 19:52:52 +0300 | [diff] [blame] | 231 | /* t0 = t0 << 2; */ |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 232 | a0 = a0 - t0; |
Dmitri Vorobiev | ae9cef0 | 2008-01-24 19:52:52 +0300 | [diff] [blame] | 233 | /* pending = pending << t0; */ |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 234 | |
| 235 | return a0; |
| 236 | #endif |
| 237 | } |
| 238 | |
| 239 | /* |
| 240 | * IRQs on the Malta board look basically (barring software IRQs which we |
| 241 | * don't use at all and all external interrupt sources are combined together |
| 242 | * on hardware interrupt 0 (MIPS IRQ 2)) like: |
| 243 | * |
| 244 | * MIPS IRQ Source |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 245 | * -------- ------ |
| 246 | * 0 Software (ignored) |
| 247 | * 1 Software (ignored) |
| 248 | * 2 Combined hardware interrupt (hw0) |
| 249 | * 3 Hardware (ignored) |
| 250 | * 4 Hardware (ignored) |
| 251 | * 5 Hardware (ignored) |
| 252 | * 6 Hardware (ignored) |
| 253 | * 7 R4k timer (what we use) |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 254 | * |
| 255 | * We handle the IRQ according to _our_ priority which is: |
| 256 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 257 | * Highest ---- R4k Timer |
| 258 | * Lowest ---- Combined hardware interrupt |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 259 | * |
| 260 | * then we just return, if multiple IRQs are pending then we will just take |
| 261 | * another exception, big deal. |
| 262 | */ |
| 263 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 264 | asmlinkage void plat_irq_dispatch(void) |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 265 | { |
| 266 | unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; |
| 267 | int irq; |
| 268 | |
Ralf Baechle | e376fdf | 2012-09-17 01:23:21 +0200 | [diff] [blame] | 269 | if (unlikely(!pending)) { |
| 270 | spurious_interrupt(); |
| 271 | return; |
| 272 | } |
| 273 | |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 274 | irq = irq_ffs(pending); |
| 275 | |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame^] | 276 | /* HACK: GIC doesn't properly dispatch local interrupts yet */ |
| 277 | if (gic_present && irq == MIPSCPU_INT_GIC && gic_compare_int()) |
| 278 | do_IRQ(MIPS_GIC_IRQ_BASE); |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 279 | else |
Ralf Baechle | e376fdf | 2012-09-17 01:23:21 +0200 | [diff] [blame] | 280 | do_IRQ(MIPS_CPU_IRQ_BASE + irq); |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 281 | } |
| 282 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 283 | #ifdef CONFIG_MIPS_MT_SMP |
| 284 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 285 | #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */ |
| 286 | #define C_RESCHED C_SW0 |
| 287 | #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */ |
| 288 | #define C_CALL C_SW1 |
| 289 | static int cpu_ipi_resched_irq, cpu_ipi_call_irq; |
| 290 | |
| 291 | static void ipi_resched_dispatch(void) |
| 292 | { |
| 293 | do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); |
| 294 | } |
| 295 | |
| 296 | static void ipi_call_dispatch(void) |
| 297 | { |
| 298 | do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); |
| 299 | } |
| 300 | |
| 301 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) |
| 302 | { |
Deng-Cheng Zhu | 9c1f6e0 | 2014-02-28 10:23:01 -0800 | [diff] [blame] | 303 | #ifdef CONFIG_MIPS_VPE_APSP_API_CMP |
Deng-Cheng Zhu | 1336113 | 2013-10-30 15:52:10 -0500 | [diff] [blame] | 304 | if (aprp_hook) |
| 305 | aprp_hook(); |
| 306 | #endif |
| 307 | |
Peter Zijlstra | 184748c | 2011-04-05 17:23:39 +0200 | [diff] [blame] | 308 | scheduler_ipi(); |
| 309 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 310 | return IRQ_HANDLED; |
| 311 | } |
| 312 | |
| 313 | static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) |
| 314 | { |
| 315 | smp_call_function_interrupt(); |
| 316 | |
| 317 | return IRQ_HANDLED; |
| 318 | } |
| 319 | |
| 320 | static struct irqaction irq_resched = { |
| 321 | .handler = ipi_resched_interrupt, |
Yong Zhang | 8b5690f | 2011-11-22 14:38:03 +0000 | [diff] [blame] | 322 | .flags = IRQF_PERCPU, |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 323 | .name = "IPI_resched" |
| 324 | }; |
| 325 | |
| 326 | static struct irqaction irq_call = { |
| 327 | .handler = ipi_call_interrupt, |
Yong Zhang | 8b5690f | 2011-11-22 14:38:03 +0000 | [diff] [blame] | 328 | .flags = IRQF_PERCPU, |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 329 | .name = "IPI_call" |
| 330 | }; |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame^] | 331 | #endif /* CONFIG_MIPS_MT_SMP */ |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 332 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 333 | static struct irqaction i8259irq = { |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame^] | 334 | .handler = i8259_handler, |
Wu Zhangjin | 5a4a4ad | 2011-07-23 12:41:24 +0000 | [diff] [blame] | 335 | .name = "XT-PIC cascade", |
| 336 | .flags = IRQF_NO_THREAD, |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 337 | }; |
| 338 | |
| 339 | static struct irqaction corehi_irqaction = { |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame^] | 340 | .handler = corehi_handler, |
Wu Zhangjin | 5a4a4ad | 2011-07-23 12:41:24 +0000 | [diff] [blame] | 341 | .name = "CoreHi", |
| 342 | .flags = IRQF_NO_THREAD, |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 343 | }; |
| 344 | |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 345 | static msc_irqmap_t msc_irqmap[] __initdata = { |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 346 | {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, |
| 347 | {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, |
| 348 | }; |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 349 | static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 350 | |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 351 | static msc_irqmap_t msc_eicirqmap[] __initdata = { |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 352 | {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, |
| 353 | {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, |
| 354 | {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, |
| 355 | {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0}, |
| 356 | {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0}, |
| 357 | {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0}, |
| 358 | {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, |
| 359 | {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, |
| 360 | {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, |
| 361 | {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} |
| 362 | }; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 363 | |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 364 | static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 365 | |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 366 | void __init arch_init_ipiirq(int irq, struct irqaction *action) |
| 367 | { |
| 368 | setup_irq(irq, action); |
Thomas Gleixner | e4ec798 | 2011-03-27 15:19:28 +0200 | [diff] [blame] | 369 | irq_set_handler(irq, handle_percpu_irq); |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 370 | } |
| 371 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 372 | void __init arch_init_irq(void) |
| 373 | { |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame^] | 374 | int corehi_irq, i8259_irq; |
| 375 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 376 | init_i8259_irqs(); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 377 | |
| 378 | if (!cpu_has_veic) |
Atsushi Nemoto | 97dcb82 | 2007-01-08 02:14:29 +0900 | [diff] [blame] | 379 | mips_cpu_irq_init(); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 380 | |
Paul Burton | 237036d | 2014-01-15 10:31:54 +0000 | [diff] [blame] | 381 | if (mips_cm_present()) { |
| 382 | write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 383 | gic_present = 1; |
| 384 | } else { |
Jaidev Patwardhan | 05cf207 | 2009-07-10 01:54:25 -0700 | [diff] [blame] | 385 | if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { |
| 386 | _msc01_biu_base = (unsigned long) |
| 387 | ioremap_nocache(MSC01_BIU_REG_BASE, |
| 388 | MSC01_BIU_ADDRSPACE_SZ); |
| 389 | gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & |
| 390 | MSC01_SC_CFG_GICPRES_MSK) >> |
| 391 | MSC01_SC_CFG_GICPRES_SHF; |
| 392 | } |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 393 | } |
| 394 | if (gic_present) |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 395 | pr_debug("GIC present\n"); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 396 | |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 397 | switch (mips_revision_sconid) { |
| 398 | case MIPS_REVISION_SCON_SOCIT: |
| 399 | case MIPS_REVISION_SCON_ROCIT: |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 400 | if (cpu_has_veic) |
Dmitri Vorobiev | f807149 | 2008-01-24 19:52:47 +0300 | [diff] [blame] | 401 | init_msc_irqs(MIPS_MSC01_IC_REG_BASE, |
| 402 | MSC01E_INT_BASE, msc_eicirqmap, |
| 403 | msc_nr_eicirqs); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 404 | else |
Dmitri Vorobiev | f807149 | 2008-01-24 19:52:47 +0300 | [diff] [blame] | 405 | init_msc_irqs(MIPS_MSC01_IC_REG_BASE, |
| 406 | MSC01C_INT_BASE, msc_irqmap, |
| 407 | msc_nr_irqs); |
Chris Dearman | d725cf3 | 2007-05-08 14:05:39 +0100 | [diff] [blame] | 408 | break; |
| 409 | |
Dmitri Vorobiev | af82558 | 2008-01-24 19:52:45 +0300 | [diff] [blame] | 410 | case MIPS_REVISION_SCON_SOCITSC: |
| 411 | case MIPS_REVISION_SCON_SOCITSCP: |
Chris Dearman | d725cf3 | 2007-05-08 14:05:39 +0100 | [diff] [blame] | 412 | if (cpu_has_veic) |
Dmitri Vorobiev | f807149 | 2008-01-24 19:52:47 +0300 | [diff] [blame] | 413 | init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, |
| 414 | MSC01E_INT_BASE, msc_eicirqmap, |
| 415 | msc_nr_eicirqs); |
Chris Dearman | d725cf3 | 2007-05-08 14:05:39 +0100 | [diff] [blame] | 416 | else |
Dmitri Vorobiev | f807149 | 2008-01-24 19:52:47 +0300 | [diff] [blame] | 417 | init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, |
| 418 | MSC01C_INT_BASE, msc_irqmap, |
| 419 | msc_nr_irqs); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 420 | } |
| 421 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 422 | if (gic_present) { |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 423 | int i; |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame^] | 424 | |
| 425 | gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, MIPSCPU_INT_GIC, |
| 426 | MIPS_GIC_IRQ_BASE); |
Paul Burton | 237036d | 2014-01-15 10:31:54 +0000 | [diff] [blame] | 427 | if (!mips_cm_present()) { |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 428 | /* Enable the GIC */ |
| 429 | i = REG(_msc01_biu_base, MSC01_SC_CFG); |
| 430 | REG(_msc01_biu_base, MSC01_SC_CFG) = |
| 431 | (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); |
| 432 | pr_debug("GIC Enabled\n"); |
| 433 | } |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame^] | 434 | i8259_irq = MIPS_GIC_IRQ_BASE + GIC_INT_I8259A; |
| 435 | corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 436 | } else { |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 437 | #if defined(CONFIG_MIPS_MT_SMP) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 438 | /* set up ipi interrupts */ |
| 439 | if (cpu_has_veic) { |
| 440 | set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); |
| 441 | set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch); |
| 442 | cpu_ipi_resched_irq = MSC01E_INT_SW0; |
| 443 | cpu_ipi_call_irq = MSC01E_INT_SW1; |
| 444 | } else { |
| 445 | if (cpu_has_vint) { |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 446 | set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, |
| 447 | ipi_resched_dispatch); |
| 448 | set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, |
| 449 | ipi_call_dispatch); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 450 | } |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 451 | cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + |
| 452 | MIPS_CPU_IPI_RESCHED_IRQ; |
| 453 | cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + |
| 454 | MIPS_CPU_IPI_CALL_IRQ; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 455 | } |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 456 | arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); |
| 457 | arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 458 | #endif |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame^] | 459 | if (cpu_has_veic) { |
| 460 | set_vi_handler(MSC01E_INT_I8259A, |
| 461 | malta_hw0_irqdispatch); |
| 462 | set_vi_handler(MSC01E_INT_COREHI, |
| 463 | corehi_irqdispatch); |
| 464 | i8259_irq = MSC01E_INT_BASE + MSC01E_INT_I8259A; |
| 465 | corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI; |
| 466 | } else { |
| 467 | i8259_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_I8259A; |
| 468 | corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI; |
| 469 | } |
Chris Dearman | 7098f74 | 2009-07-10 01:54:09 -0700 | [diff] [blame] | 470 | } |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame^] | 471 | |
| 472 | setup_irq(i8259_irq, &i8259irq); |
| 473 | setup_irq(corehi_irq, &corehi_irqaction); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 474 | } |
| 475 | |
| 476 | void malta_be_init(void) |
| 477 | { |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 478 | /* Could change CM error mask register. */ |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 479 | } |
| 480 | |
| 481 | |
| 482 | static char *tr[8] = { |
| 483 | "mem", "gcr", "gic", "mmio", |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 484 | "0x04", "0x05", "0x06", "0x07" |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 485 | }; |
| 486 | |
| 487 | static char *mcmd[32] = { |
| 488 | [0x00] = "0x00", |
| 489 | [0x01] = "Legacy Write", |
| 490 | [0x02] = "Legacy Read", |
| 491 | [0x03] = "0x03", |
| 492 | [0x04] = "0x04", |
| 493 | [0x05] = "0x05", |
| 494 | [0x06] = "0x06", |
| 495 | [0x07] = "0x07", |
| 496 | [0x08] = "Coherent Read Own", |
| 497 | [0x09] = "Coherent Read Share", |
| 498 | [0x0a] = "Coherent Read Discard", |
| 499 | [0x0b] = "Coherent Ready Share Always", |
| 500 | [0x0c] = "Coherent Upgrade", |
| 501 | [0x0d] = "Coherent Writeback", |
| 502 | [0x0e] = "0x0e", |
| 503 | [0x0f] = "0x0f", |
| 504 | [0x10] = "Coherent Copyback", |
| 505 | [0x11] = "Coherent Copyback Invalidate", |
| 506 | [0x12] = "Coherent Invalidate", |
| 507 | [0x13] = "Coherent Write Invalidate", |
| 508 | [0x14] = "Coherent Completion Sync", |
| 509 | [0x15] = "0x15", |
| 510 | [0x16] = "0x16", |
| 511 | [0x17] = "0x17", |
| 512 | [0x18] = "0x18", |
| 513 | [0x19] = "0x19", |
| 514 | [0x1a] = "0x1a", |
| 515 | [0x1b] = "0x1b", |
| 516 | [0x1c] = "0x1c", |
| 517 | [0x1d] = "0x1d", |
| 518 | [0x1e] = "0x1e", |
| 519 | [0x1f] = "0x1f" |
| 520 | }; |
| 521 | |
| 522 | static char *core[8] = { |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 523 | "Invalid/OK", "Invalid/Data", |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 524 | "Shared/OK", "Shared/Data", |
| 525 | "Modified/OK", "Modified/Data", |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 526 | "Exclusive/OK", "Exclusive/Data" |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 527 | }; |
| 528 | |
| 529 | static char *causes[32] = { |
| 530 | "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR", |
| 531 | "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07", |
| 532 | "0x08", "0x09", "0x0a", "0x0b", |
| 533 | "0x0c", "0x0d", "0x0e", "0x0f", |
| 534 | "0x10", "0x11", "0x12", "0x13", |
| 535 | "0x14", "0x15", "0x16", "INTVN_WR_ERR", |
| 536 | "INTVN_RD_ERR", "0x19", "0x1a", "0x1b", |
| 537 | "0x1c", "0x1d", "0x1e", "0x1f" |
| 538 | }; |
| 539 | |
| 540 | int malta_be_handler(struct pt_regs *regs, int is_fixup) |
| 541 | { |
| 542 | /* This duplicates the handling in do_be which seems wrong */ |
| 543 | int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL; |
| 544 | |
Paul Burton | 237036d | 2014-01-15 10:31:54 +0000 | [diff] [blame] | 545 | if (mips_cm_present()) { |
| 546 | unsigned long cm_error = read_gcr_error_cause(); |
| 547 | unsigned long cm_addr = read_gcr_error_addr(); |
| 548 | unsigned long cm_other = read_gcr_error_mult(); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 549 | unsigned long cause, ocause; |
| 550 | char buf[256]; |
| 551 | |
Paul Burton | 237036d | 2014-01-15 10:31:54 +0000 | [diff] [blame] | 552 | cause = cm_error & CM_GCR_ERROR_CAUSE_ERRTYPE_MSK; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 553 | if (cause != 0) { |
Paul Burton | 237036d | 2014-01-15 10:31:54 +0000 | [diff] [blame] | 554 | cause >>= CM_GCR_ERROR_CAUSE_ERRTYPE_SHF; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 555 | if (cause < 16) { |
| 556 | unsigned long cca_bits = (cm_error >> 15) & 7; |
| 557 | unsigned long tr_bits = (cm_error >> 12) & 7; |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 558 | unsigned long cmd_bits = (cm_error >> 7) & 0x1f; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 559 | unsigned long stag_bits = (cm_error >> 3) & 15; |
| 560 | unsigned long sport_bits = (cm_error >> 0) & 7; |
| 561 | |
| 562 | snprintf(buf, sizeof(buf), |
| 563 | "CCA=%lu TR=%s MCmd=%s STag=%lu " |
| 564 | "SPort=%lu\n", |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 565 | cca_bits, tr[tr_bits], mcmd[cmd_bits], |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 566 | stag_bits, sport_bits); |
| 567 | } else { |
| 568 | /* glob state & sresp together */ |
| 569 | unsigned long c3_bits = (cm_error >> 18) & 7; |
| 570 | unsigned long c2_bits = (cm_error >> 15) & 7; |
| 571 | unsigned long c1_bits = (cm_error >> 12) & 7; |
| 572 | unsigned long c0_bits = (cm_error >> 9) & 7; |
| 573 | unsigned long sc_bit = (cm_error >> 8) & 1; |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 574 | unsigned long cmd_bits = (cm_error >> 3) & 0x1f; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 575 | unsigned long sport_bits = (cm_error >> 0) & 7; |
| 576 | snprintf(buf, sizeof(buf), |
| 577 | "C3=%s C2=%s C1=%s C0=%s SC=%s " |
| 578 | "MCmd=%s SPort=%lu\n", |
| 579 | core[c3_bits], core[c2_bits], |
| 580 | core[c1_bits], core[c0_bits], |
| 581 | sc_bit ? "True" : "False", |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 582 | mcmd[cmd_bits], sport_bits); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 583 | } |
| 584 | |
Paul Burton | 237036d | 2014-01-15 10:31:54 +0000 | [diff] [blame] | 585 | ocause = (cm_other & CM_GCR_ERROR_MULT_ERR2ND_MSK) >> |
| 586 | CM_GCR_ERROR_MULT_ERR2ND_SHF; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 587 | |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 588 | pr_err("CM_ERROR=%08lx %s <%s>\n", cm_error, |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 589 | causes[cause], buf); |
Steven J. Hill | 5792bf6 | 2014-01-01 16:35:32 +0100 | [diff] [blame] | 590 | pr_err("CM_ADDR =%08lx\n", cm_addr); |
| 591 | pr_err("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 592 | |
| 593 | /* reprime cause register */ |
Paul Burton | 237036d | 2014-01-15 10:31:54 +0000 | [diff] [blame] | 594 | write_gcr_error_cause(0); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 595 | } |
| 596 | } |
| 597 | |
| 598 | return retval; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | } |