blob: 7726dab3d08d520c4656b11a558b905b842f909b [file] [log] [blame]
Stephen Warren1bd0bd42012-10-17 16:38:21 -06001#include "tegra20.dtsi"
Thierry Reding307e28e2012-09-20 17:06:06 +02002
3/ {
4 model = "Avionic Design Tamonten SOM";
5 compatible = "ad,tamonten", "nvidia,tegra20";
6
7 memory {
8 reg = <0x00000000 0x20000000>;
9 };
10
Thierry Redinge6f09792012-11-16 16:56:50 +010011 host1x {
12 hdmi {
13 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>;
15
16 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070017 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
18 GPIO_ACTIVE_HIGH>;
Thierry Redinge6f09792012-11-16 16:56:50 +010019 };
20 };
21
Thierry Reding307e28e2012-09-20 17:06:06 +020022 pinmux {
23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
25
26 state_default: pinmux {
27 ata {
28 nvidia,pins = "ata";
29 nvidia,function = "ide";
30 };
31 atb {
32 nvidia,pins = "atb", "gma", "gme";
33 nvidia,function = "sdio4";
34 };
35 atc {
36 nvidia,pins = "atc";
37 nvidia,function = "nand";
38 };
39 atd {
40 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
41 "spia", "spib", "spic";
42 nvidia,function = "gmi";
43 };
44 cdev1 {
45 nvidia,pins = "cdev1";
46 nvidia,function = "plla_out";
47 };
48 cdev2 {
49 nvidia,pins = "cdev2";
50 nvidia,function = "pllp_out4";
51 };
52 crtp {
53 nvidia,pins = "crtp";
54 nvidia,function = "crt";
55 };
56 csus {
57 nvidia,pins = "csus";
58 nvidia,function = "vi_sensor_clk";
59 };
60 dap1 {
61 nvidia,pins = "dap1";
62 nvidia,function = "dap1";
63 };
64 dap2 {
65 nvidia,pins = "dap2";
66 nvidia,function = "dap2";
67 };
68 dap3 {
69 nvidia,pins = "dap3";
70 nvidia,function = "dap3";
71 };
72 dap4 {
73 nvidia,pins = "dap4";
74 nvidia,function = "dap4";
75 };
Thierry Reding307e28e2012-09-20 17:06:06 +020076 dta {
77 nvidia,pins = "dta", "dtd";
78 nvidia,function = "sdio2";
79 };
80 dtb {
81 nvidia,pins = "dtb", "dtc", "dte";
82 nvidia,function = "rsvd1";
83 };
84 dtf {
85 nvidia,pins = "dtf";
86 nvidia,function = "i2c3";
87 };
88 gmc {
89 nvidia,pins = "gmc";
90 nvidia,function = "uartd";
91 };
92 gpu7 {
93 nvidia,pins = "gpu7";
94 nvidia,function = "rtck";
95 };
96 gpv {
97 nvidia,pins = "gpv", "slxa", "slxk";
98 nvidia,function = "pcie";
99 };
100 hdint {
Thierry Redingec319902012-11-09 14:04:50 +0100101 nvidia,pins = "hdint";
Thierry Reding307e28e2012-09-20 17:06:06 +0200102 nvidia,function = "hdmi";
103 };
104 i2cp {
105 nvidia,pins = "i2cp";
106 nvidia,function = "i2cp";
107 };
108 irrx {
109 nvidia,pins = "irrx", "irtx";
110 nvidia,function = "uarta";
111 };
112 kbca {
113 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
114 "kbce", "kbcf";
115 nvidia,function = "kbc";
116 };
117 lcsn {
118 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
119 "ld3", "ld4", "ld5", "ld6", "ld7",
120 "ld8", "ld9", "ld10", "ld11", "ld12",
121 "ld13", "ld14", "ld15", "ld16", "ld17",
122 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
123 "lhs", "lm0", "lm1", "lpp", "lpw0",
124 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
125 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
126 "lvs";
127 nvidia,function = "displaya";
128 };
129 owc {
130 nvidia,pins = "owc", "spdi", "spdo", "uac";
131 nvidia,function = "rsvd2";
132 };
133 pmc {
134 nvidia,pins = "pmc";
135 nvidia,function = "pwr_on";
136 };
137 rm {
138 nvidia,pins = "rm";
139 nvidia,function = "i2c1";
140 };
141 sdb {
142 nvidia,pins = "sdb", "sdc", "sdd";
143 nvidia,function = "pwm";
144 };
145 sdio1 {
146 nvidia,pins = "sdio1";
147 nvidia,function = "sdio1";
148 };
149 slxc {
150 nvidia,pins = "slxc", "slxd";
151 nvidia,function = "spdif";
152 };
153 spid {
154 nvidia,pins = "spid", "spie", "spif";
155 nvidia,function = "spi1";
156 };
157 spig {
158 nvidia,pins = "spig", "spih";
159 nvidia,function = "spi2_alt";
160 };
161 uaa {
162 nvidia,pins = "uaa", "uab", "uda";
163 nvidia,function = "ulpi";
164 };
165 uad {
166 nvidia,pins = "uad";
167 nvidia,function = "irda";
168 };
169 uca {
170 nvidia,pins = "uca", "ucb";
171 nvidia,function = "uartc";
172 };
173 conf_ata {
174 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
175 "cdev1", "cdev2", "dap1", "dtb", "gma",
176 "gmb", "gmc", "gmd", "gme", "gpu7",
177 "gpv", "i2cp", "pta", "rm", "slxa",
178 "slxk", "spia", "spib", "uac";
179 nvidia,pull = <0>;
180 nvidia,tristate = <0>;
181 };
182 conf_ck32 {
183 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
184 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
185 nvidia,pull = <0>;
186 };
187 conf_csus {
188 nvidia,pins = "csus", "spid", "spif";
189 nvidia,pull = <1>;
190 nvidia,tristate = <1>;
191 };
192 conf_crtp {
193 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
194 "dtc", "dte", "dtf", "gpu", "sdio1",
195 "slxc", "slxd", "spdi", "spdo", "spig",
196 "uda";
197 nvidia,pull = <0>;
198 nvidia,tristate = <1>;
199 };
200 conf_ddc {
201 nvidia,pins = "ddc", "dta", "dtd", "kbca",
202 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
203 "sdc";
204 nvidia,pull = <2>;
205 nvidia,tristate = <0>;
206 };
207 conf_hdint {
208 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
209 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
210 "lvp0", "owc", "sdb";
211 nvidia,tristate = <1>;
212 };
213 conf_irrx {
214 nvidia,pins = "irrx", "irtx", "sdd", "spic",
215 "spie", "spih", "uaa", "uab", "uad",
216 "uca", "ucb";
217 nvidia,pull = <2>;
218 nvidia,tristate = <1>;
219 };
220 conf_lc {
221 nvidia,pins = "lc", "ls";
222 nvidia,pull = <2>;
223 };
224 conf_ld0 {
225 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
226 "ld5", "ld6", "ld7", "ld8", "ld9",
227 "ld10", "ld11", "ld12", "ld13", "ld14",
228 "ld15", "ld16", "ld17", "ldi", "lhp0",
229 "lhp1", "lhp2", "lhs", "lm0", "lpp",
230 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
231 "lvs", "pmc";
232 nvidia,tristate = <0>;
233 };
234 conf_ld17_0 {
235 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
236 "ld23_22";
237 nvidia,pull = <1>;
238 };
239 };
Thierry Redingec319902012-11-09 14:04:50 +0100240
241 state_i2cmux_ddc: pinmux_i2cmux_ddc {
242 ddc {
243 nvidia,pins = "ddc";
244 nvidia,function = "i2c2";
245 };
246 pta {
247 nvidia,pins = "pta";
248 nvidia,function = "rsvd4";
249 };
250 };
251
252 state_i2cmux_pta: pinmux_i2cmux_pta {
253 ddc {
254 nvidia,pins = "ddc";
255 nvidia,function = "rsvd4";
256 };
257 pta {
258 nvidia,pins = "pta";
259 nvidia,function = "i2c2";
260 };
261 };
262
263 state_i2cmux_idle: pinmux_i2cmux_idle {
264 ddc {
265 nvidia,pins = "ddc";
266 nvidia,function = "rsvd4";
267 };
268 pta {
269 nvidia,pins = "pta";
270 nvidia,function = "rsvd4";
271 };
272 };
Thierry Reding307e28e2012-09-20 17:06:06 +0200273 };
274
275 i2s@70002800 {
276 status = "okay";
277 };
278
279 serial@70006300 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200280 status = "okay";
281 };
282
283 i2c@7000c000 {
284 clock-frequency = <400000>;
285 status = "okay";
286 };
287
Thierry Redingec319902012-11-09 14:04:50 +0100288 i2c@7000c400 {
289 clock-frequency = <100000>;
290 status = "okay";
291 };
292
293 i2cmux {
294 compatible = "i2c-mux-pinctrl";
295 #address-cells = <1>;
296 #size-cells = <0>;
297
298 i2c-parent = <&{/i2c@7000c400}>;
299
300 pinctrl-names = "ddc", "pta", "idle";
301 pinctrl-0 = <&state_i2cmux_ddc>;
302 pinctrl-1 = <&state_i2cmux_pta>;
303 pinctrl-2 = <&state_i2cmux_idle>;
304
Thierry Redinge6f09792012-11-16 16:56:50 +0100305 hdmi_ddc: i2c@0 {
Thierry Redingec319902012-11-09 14:04:50 +0100306 reg = <0>;
307 #address-cells = <1>;
308 #size-cells = <0>;
309 };
310
311 i2c@1 {
312 reg = <1>;
313 #address-cells = <1>;
314 #size-cells = <0>;
315 };
316 };
317
Thierry Reding307e28e2012-09-20 17:06:06 +0200318 i2c@7000d000 {
319 clock-frequency = <400000>;
320 status = "okay";
321
322 pmic: tps6586x@34 {
323 compatible = "ti,tps6586x";
324 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700325 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200326
327 ti,system-power-controller;
328
329 #gpio-cells = <2>;
330 gpio-controller;
331
332 sys-supply = <&vdd_5v0_reg>;
333 vin-sm0-supply = <&sys_reg>;
334 vin-sm1-supply = <&sys_reg>;
335 vin-sm2-supply = <&sys_reg>;
336 vinldo01-supply = <&sm2_reg>;
337 vinldo23-supply = <&sm2_reg>;
338 vinldo4-supply = <&sm2_reg>;
339 vinldo678-supply = <&sm2_reg>;
340 vinldo9-supply = <&sm2_reg>;
341
342 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600343 sys_reg: sys {
Thierry Reding307e28e2012-09-20 17:06:06 +0200344 regulator-name = "vdd_sys";
345 regulator-always-on;
346 };
347
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600348 sm0 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200349 regulator-name = "vdd_sys_sm0,vdd_core";
350 regulator-min-microvolt = <1200000>;
351 regulator-max-microvolt = <1200000>;
352 regulator-always-on;
353 };
354
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600355 sm1 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200356 regulator-name = "vdd_sys_sm1,vdd_cpu";
357 regulator-min-microvolt = <1000000>;
358 regulator-max-microvolt = <1000000>;
359 regulator-always-on;
360 };
361
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600362 sm2_reg: sm2 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200363 regulator-name = "vdd_sys_sm2,vin_ldo*";
364 regulator-min-microvolt = <3700000>;
365 regulator-max-microvolt = <3700000>;
366 regulator-always-on;
367 };
368
Thierry Reding1b2d6b82013-08-09 16:49:20 +0200369 pci_clk_reg: ldo0 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200370 regulator-name = "vdd_ldo0,vddio_pex_clk";
371 regulator-min-microvolt = <3300000>;
372 regulator-max-microvolt = <3300000>;
373 };
374
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600375 ldo1 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200376 regulator-name = "vdd_ldo1,avdd_pll*";
377 regulator-min-microvolt = <1100000>;
378 regulator-max-microvolt = <1100000>;
379 regulator-always-on;
380 };
381
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600382 ldo2 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200383 regulator-name = "vdd_ldo2,vdd_rtc";
384 regulator-min-microvolt = <1200000>;
385 regulator-max-microvolt = <1200000>;
386 };
387
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600388 ldo3 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200389 regulator-name = "vdd_ldo3,avdd_usb*";
390 regulator-min-microvolt = <3300000>;
391 regulator-max-microvolt = <3300000>;
392 regulator-always-on;
393 };
394
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600395 ldo4 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200396 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
397 regulator-min-microvolt = <1800000>;
398 regulator-max-microvolt = <1800000>;
399 regulator-always-on;
400 };
401
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600402 ldo5 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200403 regulator-name = "vdd_ldo5,vcore_mmc";
404 regulator-min-microvolt = <2850000>;
405 regulator-max-microvolt = <2850000>;
406 };
407
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600408 ldo6 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200409 regulator-name = "vdd_ldo6,avdd_vdac";
410 /*
411 * According to the Tegra 2 Automotive
412 * DataSheet, a typical value for this
413 * would be 2.8V, but the PMIC only
414 * supports 2.85V.
415 */
416 regulator-min-microvolt = <2850000>;
417 regulator-max-microvolt = <2850000>;
418 };
419
Thierry Redinge6f09792012-11-16 16:56:50 +0100420 hdmi_vdd_reg: ldo7 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200421 regulator-name = "vdd_ldo7,avdd_hdmi";
422 regulator-min-microvolt = <3300000>;
423 regulator-max-microvolt = <3300000>;
424 };
425
Thierry Redinge6f09792012-11-16 16:56:50 +0100426 hdmi_pll_reg: ldo8 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200427 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
428 regulator-min-microvolt = <1800000>;
429 regulator-max-microvolt = <1800000>;
430 };
431
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600432 ldo9 {
Thierry Reding307e28e2012-09-20 17:06:06 +0200433 regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
434 /*
435 * According to the Tegra 2 Automotive
436 * DataSheet, a typical value for this
437 * would be 2.8V, but the PMIC only
438 * supports 2.85V.
439 */
440 regulator-min-microvolt = <2850000>;
441 regulator-max-microvolt = <2850000>;
442 regulator-always-on;
443 };
444
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600445 ldo_rtc {
Thierry Reding307e28e2012-09-20 17:06:06 +0200446 regulator-name = "vdd_rtc_out";
447 regulator-min-microvolt = <3300000>;
448 regulator-max-microvolt = <3300000>;
449 regulator-always-on;
450 };
451 };
452 };
Thierry Reding840a4082012-11-09 23:00:08 +0100453
454 temperature-sensor@4c {
455 compatible = "onnn,nct1008";
456 reg = <0x4c>;
457 };
Thierry Reding307e28e2012-09-20 17:06:06 +0200458 };
459
460 pmc {
461 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800462 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800463 nvidia,cpu-pwr-good-time = <5000>;
464 nvidia,cpu-pwr-off-time = <5000>;
465 nvidia,core-pwr-good-time = <3845 3845>;
466 nvidia,core-pwr-off-time = <3875>;
467 nvidia,sys-clock-req-active-high;
Thierry Reding307e28e2012-09-20 17:06:06 +0200468 };
469
Thierry Reding1b2d6b82013-08-09 16:49:20 +0200470 pcie-controller {
471 pex-clk-supply = <&pci_clk_reg>;
472 vdd-supply = <&pci_vdd_reg>;
473 };
474
Thierry Reding307e28e2012-09-20 17:06:06 +0200475 usb@c5008000 {
476 status = "okay";
477 };
478
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530479 usb-phy@c5008000 {
480 status = "okay";
481 };
482
Thierry Reding307e28e2012-09-20 17:06:06 +0200483 sdhci@c8000600 {
Stephen Warren3325f1b2013-02-12 17:25:15 -0700484 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
485 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
Thierry Reding307e28e2012-09-20 17:06:06 +0200486 bus-width = <4>;
487 status = "okay";
488 };
489
Joseph Lo7021d122013-04-03 19:31:27 +0800490 clocks {
491 compatible = "simple-bus";
492 #address-cells = <1>;
493 #size-cells = <0>;
494
495 clk32k_in: clock {
496 compatible = "fixed-clock";
497 reg=<0>;
498 #clock-cells = <0>;
499 clock-frequency = <32768>;
500 };
501 };
502
Thierry Reding307e28e2012-09-20 17:06:06 +0200503 regulators {
504 compatible = "simple-bus";
505
506 #address-cells = <1>;
507 #size-cells = <0>;
508
509 vdd_5v0_reg: regulator@0 {
510 compatible = "regulator-fixed";
511 reg = <0>;
512 regulator-name = "vdd_5v0";
513 regulator-min-microvolt = <5000000>;
514 regulator-max-microvolt = <5000000>;
515 regulator-always-on;
516 };
Thierry Reding1b2d6b82013-08-09 16:49:20 +0200517
518 pci_vdd_reg: regulator@1 {
519 compatible = "regulator-fixed";
520 reg = <1>;
521 regulator-name = "vdd_1v05";
522 regulator-min-microvolt = <1050000>;
523 regulator-max-microvolt = <1050000>;
524 gpio = <&pmic 2 0>;
525 enable-active-high;
526 };
Thierry Reding307e28e2012-09-20 17:06:06 +0200527 };
528};