blob: 661807e14e8a56f8b2c1eb304bc15543a5b05d31 [file] [log] [blame]
Ben Dooksc6184e22007-02-17 00:52:37 +01001/* linux/arch/arm/mach-s3c2410/mach-qt2410.c
2 *
3 * Copyright (C) 2006 by OpenMoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/types.h>
26#include <linux/interrupt.h>
27#include <linux/list.h>
28#include <linux/timer.h>
29#include <linux/init.h>
Ben Dooks333a42e2007-05-20 11:55:53 +010030#include <linux/sysdev.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010031#include <linux/platform_device.h>
32#include <linux/serial_core.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010033#include <linux/spi/spi.h>
34#include <linux/spi/spi_bitbang.h>
Russell Kingfced80c2008-09-06 12:10:45 +010035#include <linux/io.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010036#include <linux/mtd/mtd.h>
37#include <linux/mtd/nand.h>
38#include <linux/mtd/nand_ecc.h>
39#include <linux/mtd/partitions.h>
40
41#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
43#include <asm/mach/irq.h>
44
Russell Kinga09e64f2008-08-05 16:14:15 +010045#include <mach/hardware.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010046#include <asm/irq.h>
47#include <asm/mach-types.h>
48
Russell Kinga09e64f2008-08-05 16:14:15 +010049#include <mach/regs-gpio.h>
50#include <mach/leds-gpio.h>
Ben Dooksa2b7ba92008-10-07 22:26:09 +010051#include <plat/regs-serial.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010052#include <mach/fb.h>
Ben Dooks531b6172007-07-22 16:05:25 +010053#include <asm/plat-s3c/nand.h>
Ben Dooks06cfa552007-07-22 16:23:02 +010054#include <asm/plat-s3c24xx/udc.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010055#include <mach/spi.h>
56#include <mach/spi-gpio.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010057
Ben Dooksd5120ae2008-10-07 23:09:51 +010058#include <plat/common-smdk.h>
Ben Dooksa2b7ba92008-10-07 22:26:09 +010059#include <plat/devs.h>
60#include <plat/cpu.h>
61#include <plat/pm.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010062
63static struct map_desc qt2410_iodesc[] __initdata = {
64 { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
65};
66
67#define UCON S3C2410_UCON_DEFAULT
68#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
69#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
70
71static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
72 [0] = {
73 .hwport = 0,
74 .flags = 0,
75 .ucon = UCON,
76 .ulcon = ULCON,
77 .ufcon = UFCON,
78 },
79 [1] = {
80 .hwport = 1,
81 .flags = 0,
82 .ucon = UCON,
83 .ulcon = ULCON,
84 .ufcon = UFCON,
85 },
86 [2] = {
87 .hwport = 2,
88 .flags = 0,
89 .ucon = UCON,
90 .ulcon = ULCON,
91 .ufcon = UFCON,
92 }
93};
94
95/* LCD driver info */
96
Krzysztof Helt09fe75f2007-10-16 01:28:56 -070097static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
98 {
99 /* Configuration for 640x480 SHARP LQ080V3DG01 */
Krzysztof Heltf28ef572007-10-16 01:28:58 -0700100 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
101 S3C2410_LCDCON5_INVVLINE |
102 S3C2410_LCDCON5_INVVFRAME |
103 S3C2410_LCDCON5_PWREN |
104 S3C2410_LCDCON5_HWSWP,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700105
Krzysztof Helt1f411532007-10-16 01:28:57 -0700106 .type = S3C2410_LCDCON1_TFT,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700107 .width = 640,
108 .height = 480,
109
Krzysztof Helt69816692007-10-16 01:29:06 -0700110 .pixclock = 40000, /* HCLK/4 */
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700111 .xres = 640,
112 .yres = 480,
113 .bpp = 16,
Krzysztof Helt1f411532007-10-16 01:28:57 -0700114 .left_margin = 44,
115 .right_margin = 116,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700116 .hsync_len = 96,
Krzysztof Helt5f20f692007-10-16 01:28:59 -0700117 .upper_margin = 19,
118 .lower_margin = 11,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700119 .vsync_len = 15,
Ben Dooksc6184e22007-02-17 00:52:37 +0100120 },
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700121 {
122 /* Configuration for 480x640 toppoly TD028TTEC1 */
Krzysztof Heltf28ef572007-10-16 01:28:58 -0700123 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
124 S3C2410_LCDCON5_INVVLINE |
125 S3C2410_LCDCON5_INVVFRAME |
126 S3C2410_LCDCON5_PWREN |
127 S3C2410_LCDCON5_HWSWP,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700128
Krzysztof Helt1f411532007-10-16 01:28:57 -0700129 .type = S3C2410_LCDCON1_TFT,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700130 .width = 480,
131 .height = 640,
Krzysztof Helt69816692007-10-16 01:29:06 -0700132 .pixclock = 40000, /* HCLK/4 */
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700133 .xres = 480,
134 .yres = 640,
135 .bpp = 16,
Krzysztof Helt1f411532007-10-16 01:28:57 -0700136 .left_margin = 8,
137 .right_margin = 24,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700138 .hsync_len = 8,
Krzysztof Helt5f20f692007-10-16 01:28:59 -0700139 .upper_margin = 2,
140 .lower_margin = 4,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700141 .vsync_len = 2,
Ben Dooksc6184e22007-02-17 00:52:37 +0100142 },
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700143 {
144 /* Config for 240x320 LCD */
Krzysztof Heltf28ef572007-10-16 01:28:58 -0700145 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
146 S3C2410_LCDCON5_INVVLINE |
147 S3C2410_LCDCON5_INVVFRAME |
148 S3C2410_LCDCON5_PWREN |
149 S3C2410_LCDCON5_HWSWP,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700150
Krzysztof Helt1f411532007-10-16 01:28:57 -0700151 .type = S3C2410_LCDCON1_TFT,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700152 .width = 240,
153 .height = 320,
Krzysztof Helt69816692007-10-16 01:29:06 -0700154 .pixclock = 100000, /* HCLK/10 */
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700155 .xres = 240,
156 .yres = 320,
157 .bpp = 16,
Krzysztof Helt1f411532007-10-16 01:28:57 -0700158 .left_margin = 13,
159 .right_margin = 8,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700160 .hsync_len = 4,
Krzysztof Helt5f20f692007-10-16 01:28:59 -0700161 .upper_margin = 2,
162 .lower_margin = 7,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700163 .vsync_len = 4,
Ben Dooksc6184e22007-02-17 00:52:37 +0100164 },
165};
166
Ben Dooksc6184e22007-02-17 00:52:37 +0100167
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700168static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
169 .displays = qt2410_lcd_cfg,
170 .num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
171 .default_display = 0,
Ben Dooksc6184e22007-02-17 00:52:37 +0100172
173 .lpcsel = ((0xCE6) & ~7) | 1<<4,
Ben Dooksc6184e22007-02-17 00:52:37 +0100174};
175
176/* CS8900 */
177
178static struct resource qt2410_cs89x0_resources[] = {
179 [0] = {
180 .start = 0x19000000,
181 .end = 0x19000000 + 16,
182 .flags = IORESOURCE_MEM,
183 },
184 [1] = {
185 .start = IRQ_EINT9,
186 .end = IRQ_EINT9,
187 .flags = IORESOURCE_IRQ,
188 },
189};
190
191static struct platform_device qt2410_cs89x0 = {
192 .name = "cirrus-cs89x0",
193 .num_resources = ARRAY_SIZE(qt2410_cs89x0_resources),
194 .resource = qt2410_cs89x0_resources,
195};
196
197/* LED */
198
199static struct s3c24xx_led_platdata qt2410_pdata_led = {
200 .gpio = S3C2410_GPB0,
201 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
202 .name = "led",
203 .def_trigger = "timer",
204};
205
206static struct platform_device qt2410_led = {
207 .name = "s3c24xx_led",
208 .id = 0,
209 .dev = {
210 .platform_data = &qt2410_pdata_led,
211 },
212};
213
214/* SPI */
215
216static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
217{
218 switch (cs) {
219 case BITBANG_CS_ACTIVE:
220 s3c2410_gpio_setpin(S3C2410_GPB5, 0);
221 break;
222 case BITBANG_CS_INACTIVE:
223 s3c2410_gpio_setpin(S3C2410_GPB5, 1);
224 break;
225 }
226}
227
228static struct s3c2410_spigpio_info spi_gpio_cfg = {
229 .pin_clk = S3C2410_GPG7,
230 .pin_mosi = S3C2410_GPG6,
231 .pin_miso = S3C2410_GPG5,
232 .chip_select = &spi_gpio_cs,
233};
234
235
236static struct platform_device qt2410_spi = {
237 .name = "s3c24xx-spi-gpio",
238 .id = 1,
239 .dev = {
240 .platform_data = &spi_gpio_cfg,
241 },
242};
243
244/* Board devices */
245
246static struct platform_device *qt2410_devices[] __initdata = {
247 &s3c_device_usb,
248 &s3c_device_lcd,
249 &s3c_device_wdt,
250 &s3c_device_i2c,
251 &s3c_device_iis,
252 &s3c_device_sdi,
253 &s3c_device_usbgadget,
254 &qt2410_spi,
255 &qt2410_cs89x0,
256 &qt2410_led,
257};
258
Ben Dooksc6184e22007-02-17 00:52:37 +0100259static struct mtd_partition qt2410_nand_part[] = {
260 [0] = {
261 .name = "U-Boot",
262 .size = 0x30000,
263 .offset = 0,
264 },
265 [1] = {
266 .name = "U-Boot environment",
267 .offset = 0x30000,
268 .size = 0x4000,
269 },
270 [2] = {
271 .name = "kernel",
272 .offset = 0x34000,
273 .size = SZ_2M,
274 },
275 [3] = {
276 .name = "initrd",
277 .offset = 0x234000,
278 .size = SZ_4M,
279 },
280 [4] = {
281 .name = "jffs2",
282 .offset = 0x634000,
283 .size = 0x39cc000,
284 },
285};
286
287static struct s3c2410_nand_set qt2410_nand_sets[] = {
288 [0] = {
289 .name = "NAND",
290 .nr_chips = 1,
291 .nr_partitions = ARRAY_SIZE(qt2410_nand_part),
292 .partitions = qt2410_nand_part,
293 },
294};
295
296/* choose a set of timings which should suit most 512Mbit
297 * chips and beyond.
298 */
299
300static struct s3c2410_platform_nand qt2410_nand_info = {
301 .tacls = 20,
302 .twrph0 = 60,
303 .twrph1 = 20,
304 .nr_sets = ARRAY_SIZE(qt2410_nand_sets),
305 .sets = qt2410_nand_sets,
306};
307
308/* UDC */
309
310static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
311};
312
313static char tft_type = 's';
314
315static int __init qt2410_tft_setup(char *str)
316{
317 tft_type = str[0];
318 return 1;
319}
320
321__setup("tft=", qt2410_tft_setup);
322
323static void __init qt2410_map_io(void)
324{
325 s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
326 s3c24xx_init_clocks(12*1000*1000);
327 s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
Ben Dooksc6184e22007-02-17 00:52:37 +0100328}
329
330static void __init qt2410_machine_init(void)
331{
332 s3c_device_nand.dev.platform_data = &qt2410_nand_info;
333
334 switch (tft_type) {
335 case 'p': /* production */
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700336 qt2410_fb_info.default_display = 1;
Ben Dooksc6184e22007-02-17 00:52:37 +0100337 break;
338 case 'b': /* big */
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700339 qt2410_fb_info.default_display = 0;
Ben Dooksc6184e22007-02-17 00:52:37 +0100340 break;
341 case 's': /* small */
342 default:
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700343 qt2410_fb_info.default_display = 2;
Ben Dooksc6184e22007-02-17 00:52:37 +0100344 break;
345 }
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700346 s3c24xx_fb_set_platdata(&qt2410_fb_info);
Ben Dooksc6184e22007-02-17 00:52:37 +0100347
348 s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
349 s3c2410_gpio_setpin(S3C2410_GPB0, 1);
350
351 s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
352
353 s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
354
Ben Dooks57e51712007-04-20 11:19:16 +0100355 platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
Ben Dooksc6184e22007-02-17 00:52:37 +0100356 s3c2410_pm_init();
357}
358
359MACHINE_START(QT2410, "QT2410")
360 .phys_io = S3C2410_PA_UART,
361 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
362 .boot_params = S3C2410_SDRAM_PA + 0x100,
363 .map_io = qt2410_map_io,
364 .init_irq = s3c24xx_init_irq,
365 .init_machine = qt2410_machine_init,
366 .timer = &s3c24xx_timer,
367MACHINE_END
368
369