blob: 42f224936a8eea6c30c3da7eb361c25f049f4b0e [file] [log] [blame]
Alexander Shishkine443b332012-05-11 17:25:46 +03001/*
2 * core.c - ChipIdea USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/*
14 * Description: ChipIdea USB IP core family device controller
15 *
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
19 * - UTIL: utilities
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
24 *
25 * Compile Options
26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
29 * => case 4: Hi > Dn
30 * => case 5: Hi > Di
31 * => case 8: Hi <> Do
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
34 *
35 * Main Features
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
39 *
40 * USBTEST Report
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
43 *
44 * TODO List
45 * - OTG
46 * - Isochronous & Interrupt Traffic
47 * - Handle requests which spawns into several TDs
48 * - GET_STATUS(device) - always reports 0
49 * - Gadget API (majority of optional features)
50 * - Suspend & Remote Wakeup
51 */
52#include <linux/delay.h>
53#include <linux/device.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030054#include <linux/dma-mapping.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030055#include <linux/platform_device.h>
56#include <linux/module.h>
Richard Zhaofe6e1252012-07-07 22:56:42 +080057#include <linux/idr.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030058#include <linux/interrupt.h>
59#include <linux/io.h>
Alexander Shishkine443b332012-05-11 17:25:46 +030060#include <linux/kernel.h>
61#include <linux/slab.h>
62#include <linux/pm_runtime.h>
63#include <linux/usb/ch9.h>
64#include <linux/usb/gadget.h>
65#include <linux/usb/otg.h>
66#include <linux/usb/chipidea.h>
67
68#include "ci.h"
69#include "udc.h"
70#include "bits.h"
Alexander Shishkineb70e5a2012-05-11 17:25:54 +030071#include "host.h"
Alexander Shishkine443b332012-05-11 17:25:46 +030072#include "debug.h"
73
Alexander Shishkin5f36e232012-05-11 17:25:47 +030074/* Controller register map */
Alexander Shishkine443b332012-05-11 17:25:46 +030075static uintptr_t ci_regs_nolpm[] = {
76 [CAP_CAPLENGTH] = 0x000UL,
77 [CAP_HCCPARAMS] = 0x008UL,
78 [CAP_DCCPARAMS] = 0x024UL,
79 [CAP_TESTMODE] = 0x038UL,
80 [OP_USBCMD] = 0x000UL,
81 [OP_USBSTS] = 0x004UL,
82 [OP_USBINTR] = 0x008UL,
83 [OP_DEVICEADDR] = 0x014UL,
84 [OP_ENDPTLISTADDR] = 0x018UL,
85 [OP_PORTSC] = 0x044UL,
86 [OP_DEVLC] = 0x084UL,
Alexander Shishkin5f36e232012-05-11 17:25:47 +030087 [OP_OTGSC] = 0x064UL,
Alexander Shishkine443b332012-05-11 17:25:46 +030088 [OP_USBMODE] = 0x068UL,
89 [OP_ENDPTSETUPSTAT] = 0x06CUL,
90 [OP_ENDPTPRIME] = 0x070UL,
91 [OP_ENDPTFLUSH] = 0x074UL,
92 [OP_ENDPTSTAT] = 0x078UL,
93 [OP_ENDPTCOMPLETE] = 0x07CUL,
94 [OP_ENDPTCTRL] = 0x080UL,
95};
96
97static uintptr_t ci_regs_lpm[] = {
98 [CAP_CAPLENGTH] = 0x000UL,
99 [CAP_HCCPARAMS] = 0x008UL,
100 [CAP_DCCPARAMS] = 0x024UL,
101 [CAP_TESTMODE] = 0x0FCUL,
102 [OP_USBCMD] = 0x000UL,
103 [OP_USBSTS] = 0x004UL,
104 [OP_USBINTR] = 0x008UL,
105 [OP_DEVICEADDR] = 0x014UL,
106 [OP_ENDPTLISTADDR] = 0x018UL,
107 [OP_PORTSC] = 0x044UL,
108 [OP_DEVLC] = 0x084UL,
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300109 [OP_OTGSC] = 0x0C4UL,
Alexander Shishkine443b332012-05-11 17:25:46 +0300110 [OP_USBMODE] = 0x0C8UL,
111 [OP_ENDPTSETUPSTAT] = 0x0D8UL,
112 [OP_ENDPTPRIME] = 0x0DCUL,
113 [OP_ENDPTFLUSH] = 0x0E0UL,
114 [OP_ENDPTSTAT] = 0x0E4UL,
115 [OP_ENDPTCOMPLETE] = 0x0E8UL,
116 [OP_ENDPTCTRL] = 0x0ECUL,
117};
118
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300119static int hw_alloc_regmap(struct ci13xxx *ci, bool is_lpm)
Alexander Shishkine443b332012-05-11 17:25:46 +0300120{
121 int i;
122
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300123 kfree(ci->hw_bank.regmap);
Alexander Shishkine443b332012-05-11 17:25:46 +0300124
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300125 ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
126 GFP_KERNEL);
127 if (!ci->hw_bank.regmap)
Alexander Shishkine443b332012-05-11 17:25:46 +0300128 return -ENOMEM;
129
130 for (i = 0; i < OP_ENDPTCTRL; i++)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300131 ci->hw_bank.regmap[i] =
132 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
Alexander Shishkine443b332012-05-11 17:25:46 +0300133 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
134
135 for (; i <= OP_LAST; i++)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300136 ci->hw_bank.regmap[i] = ci->hw_bank.op +
Alexander Shishkine443b332012-05-11 17:25:46 +0300137 4 * (i - OP_ENDPTCTRL) +
138 (is_lpm
139 ? ci_regs_lpm[OP_ENDPTCTRL]
140 : ci_regs_nolpm[OP_ENDPTCTRL]);
141
142 return 0;
143}
144
145/**
146 * hw_port_test_set: writes port test mode (execute without interruption)
147 * @mode: new value
148 *
149 * This function returns an error code
150 */
151int hw_port_test_set(struct ci13xxx *ci, u8 mode)
152{
153 const u8 TEST_MODE_MAX = 7;
154
155 if (mode > TEST_MODE_MAX)
156 return -EINVAL;
157
158 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
159 return 0;
160}
161
162/**
163 * hw_port_test_get: reads port test mode value
164 *
165 * This function returns port test mode value
166 */
167u8 hw_port_test_get(struct ci13xxx *ci)
168{
169 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
170}
171
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300172static int hw_device_init(struct ci13xxx *ci, void __iomem *base)
Alexander Shishkine443b332012-05-11 17:25:46 +0300173{
174 u32 reg;
175
176 /* bank is a module variable */
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300177 ci->hw_bank.abs = base;
Alexander Shishkine443b332012-05-11 17:25:46 +0300178
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300179 ci->hw_bank.cap = ci->hw_bank.abs;
Richard Zhao77c44002012-06-29 17:48:53 +0800180 ci->hw_bank.cap += ci->platdata->capoffset;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300181 ci->hw_bank.op = ci->hw_bank.cap + ioread8(ci->hw_bank.cap);
Alexander Shishkine443b332012-05-11 17:25:46 +0300182
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300183 hw_alloc_regmap(ci, false);
184 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
Alexander Shishkine443b332012-05-11 17:25:46 +0300185 ffs_nr(HCCPARAMS_LEN);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300186 ci->hw_bank.lpm = reg;
187 hw_alloc_regmap(ci, !!reg);
188 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
189 ci->hw_bank.size += OP_LAST;
190 ci->hw_bank.size /= sizeof(u32);
Alexander Shishkine443b332012-05-11 17:25:46 +0300191
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300192 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
Alexander Shishkine443b332012-05-11 17:25:46 +0300193 ffs_nr(DCCPARAMS_DEN);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300194 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
Alexander Shishkine443b332012-05-11 17:25:46 +0300195
Richard Zhao09c94e62012-05-15 21:58:18 +0800196 if (ci->hw_ep_max > ENDPT_MAX)
Alexander Shishkine443b332012-05-11 17:25:46 +0300197 return -ENODEV;
198
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300199 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
200 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
Alexander Shishkine443b332012-05-11 17:25:46 +0300201
202 /* setup lock mode ? */
203
204 /* ENDPTSETUPSTAT is '0' by default */
205
206 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
207
208 return 0;
209}
210
211/**
212 * hw_device_reset: resets chip (execute without interruption)
213 * @ci: the controller
214 *
215 * This function returns an error code
216 */
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300217int hw_device_reset(struct ci13xxx *ci, u32 mode)
Alexander Shishkine443b332012-05-11 17:25:46 +0300218{
219 /* should flush & stop before reset */
220 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
221 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
222
223 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
224 while (hw_read(ci, OP_USBCMD, USBCMD_RST))
225 udelay(10); /* not RTOS friendly */
226
227
Richard Zhao77c44002012-06-29 17:48:53 +0800228 if (ci->platdata->notify_event)
229 ci->platdata->notify_event(ci,
Alexander Shishkine443b332012-05-11 17:25:46 +0300230 CI13XXX_CONTROLLER_RESET_EVENT);
231
Richard Zhao77c44002012-06-29 17:48:53 +0800232 if (ci->platdata->flags & CI13XXX_DISABLE_STREAMING)
Alexander Shishkin758fc982012-05-11 17:25:53 +0300233 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
Alexander Shishkine443b332012-05-11 17:25:46 +0300234
235 /* USBMODE should be configured step by step */
236 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300237 hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
Alexander Shishkine443b332012-05-11 17:25:46 +0300238 /* HW >= 2.3 */
239 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
240
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300241 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
242 pr_err("cannot enter in %s mode", ci_role(ci)->name);
Alexander Shishkine443b332012-05-11 17:25:46 +0300243 pr_err("lpm = %i", ci->hw_bank.lpm);
244 return -ENODEV;
245 }
246
247 return 0;
248}
249
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300250/**
251 * ci_otg_role - pick role based on ID pin state
252 * @ci: the controller
253 */
254static enum ci_role ci_otg_role(struct ci13xxx *ci)
255{
256 u32 sts = hw_read(ci, OP_OTGSC, ~0);
257 enum ci_role role = sts & OTGSC_ID
258 ? CI_ROLE_GADGET
259 : CI_ROLE_HOST;
260
261 return role;
262}
263
264/**
265 * ci_role_work - perform role changing based on ID pin
266 * @work: work struct
267 */
268static void ci_role_work(struct work_struct *work)
269{
270 struct ci13xxx *ci = container_of(work, struct ci13xxx, work);
271 enum ci_role role = ci_otg_role(ci);
272
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300273 if (role != ci->role) {
274 dev_dbg(ci->dev, "switching from %s to %s\n",
275 ci_role(ci)->name, ci->roles[role]->name);
276
277 ci_role_stop(ci);
278 ci_role_start(ci, role);
Richard Zhaob183c192012-09-12 14:58:11 +0300279 enable_irq(ci->irq);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300280 }
281}
282
283static ssize_t show_role(struct device *dev, struct device_attribute *attr,
284 char *buf)
285{
286 struct ci13xxx *ci = dev_get_drvdata(dev);
287
288 return sprintf(buf, "%s\n", ci_role(ci)->name);
289}
290
291static ssize_t store_role(struct device *dev, struct device_attribute *attr,
292 const char *buf, size_t count)
293{
294 struct ci13xxx *ci = dev_get_drvdata(dev);
295 enum ci_role role;
296 int ret;
297
298 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
299 if (ci->roles[role] && !strcmp(buf, ci->roles[role]->name))
300 break;
301
302 if (role == CI_ROLE_END || role == ci->role)
303 return -EINVAL;
304
305 ci_role_stop(ci);
306 ret = ci_role_start(ci, role);
307 if (ret)
308 return ret;
309
310 return count;
311}
312
313static DEVICE_ATTR(role, S_IRUSR | S_IWUSR, show_role, store_role);
314
315static irqreturn_t ci_irq(int irq, void *data)
316{
317 struct ci13xxx *ci = data;
318 irqreturn_t ret = IRQ_NONE;
Richard Zhaob183c192012-09-12 14:58:11 +0300319 u32 otgsc = 0;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300320
Richard Zhaob183c192012-09-12 14:58:11 +0300321 if (ci->is_otg)
322 otgsc = hw_read(ci, OP_OTGSC, ~0);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300323
Richard Zhaob183c192012-09-12 14:58:11 +0300324 if (ci->role != CI_ROLE_END)
325 ret = ci_role(ci)->irq(ci);
326
327 if (ci->is_otg && (otgsc & OTGSC_IDIS)) {
328 hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
329 disable_irq_nosync(ci->irq);
330 queue_work(ci->wq, &ci->work);
331 ret = IRQ_HANDLED;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300332 }
333
Richard Zhaob183c192012-09-12 14:58:11 +0300334 return ret;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300335}
336
Richard Zhaofe6e1252012-07-07 22:56:42 +0800337static DEFINE_IDA(ci_ida);
338
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800339struct platform_device *ci13xxx_add_device(struct device *dev,
340 struct resource *res, int nres,
341 struct ci13xxx_platform_data *platdata)
342{
343 struct platform_device *pdev;
Richard Zhaofe6e1252012-07-07 22:56:42 +0800344 int id, ret;
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800345
Richard Zhaofe6e1252012-07-07 22:56:42 +0800346 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
347 if (id < 0)
348 return ERR_PTR(id);
349
350 pdev = platform_device_alloc("ci_hdrc", id);
351 if (!pdev) {
352 ret = -ENOMEM;
353 goto put_id;
354 }
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800355
356 pdev->dev.parent = dev;
357 pdev->dev.dma_mask = dev->dma_mask;
358 pdev->dev.dma_parms = dev->dma_parms;
359 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
360
361 ret = platform_device_add_resources(pdev, res, nres);
362 if (ret)
363 goto err;
364
365 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
366 if (ret)
367 goto err;
368
369 ret = platform_device_add(pdev);
370 if (ret)
371 goto err;
372
373 return pdev;
374
375err:
376 platform_device_put(pdev);
Richard Zhaofe6e1252012-07-07 22:56:42 +0800377put_id:
378 ida_simple_remove(&ci_ida, id);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800379 return ERR_PTR(ret);
380}
381EXPORT_SYMBOL_GPL(ci13xxx_add_device);
382
383void ci13xxx_remove_device(struct platform_device *pdev)
384{
Lothar Waßmann98c35532012-11-22 10:11:25 +0100385 int id = pdev->id;
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800386 platform_device_unregister(pdev);
Lothar Waßmann98c35532012-11-22 10:11:25 +0100387 ida_simple_remove(&ci_ida, id);
Richard Zhaocbc6dc22012-07-07 22:56:41 +0800388}
389EXPORT_SYMBOL_GPL(ci13xxx_remove_device);
390
Bill Pemberton41ac7b32012-11-19 13:21:48 -0500391static int ci_hdrc_probe(struct platform_device *pdev)
Alexander Shishkine443b332012-05-11 17:25:46 +0300392{
393 struct device *dev = &pdev->dev;
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300394 struct ci13xxx *ci;
Alexander Shishkine443b332012-05-11 17:25:46 +0300395 struct resource *res;
396 void __iomem *base;
397 int ret;
398
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300399 if (!dev->platform_data) {
Alexander Shishkine443b332012-05-11 17:25:46 +0300400 dev_err(dev, "platform data missing\n");
401 return -ENODEV;
402 }
403
404 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
405 if (!res) {
406 dev_err(dev, "missing resource\n");
407 return -ENODEV;
408 }
409
Felipe Balbi19290812013-03-30 02:46:27 +0200410 base = devm_ioremap_resource(dev, res);
411 if (IS_ERR(base))
412 return PTR_ERR(base);
Alexander Shishkine443b332012-05-11 17:25:46 +0300413
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300414 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
415 if (!ci) {
416 dev_err(dev, "can't allocate device\n");
417 return -ENOMEM;
Alexander Shishkine443b332012-05-11 17:25:46 +0300418 }
419
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300420 ci->dev = dev;
Richard Zhao77c44002012-06-29 17:48:53 +0800421 ci->platdata = dev->platform_data;
Richard Zhaoa2c3d692012-07-07 22:56:46 +0800422 if (ci->platdata->phy)
423 ci->transceiver = ci->platdata->phy;
424 else
425 ci->global_phy = true;
Alexander Shishkine443b332012-05-11 17:25:46 +0300426
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300427 ret = hw_device_init(ci, base);
428 if (ret < 0) {
429 dev_err(dev, "can't initialize hardware\n");
430 return -ENODEV;
431 }
432
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300433 ci->hw_bank.phys = res->start;
434
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300435 ci->irq = platform_get_irq(pdev, 0);
436 if (ci->irq < 0) {
437 dev_err(dev, "missing IRQ\n");
438 return -ENODEV;
439 }
440
441 INIT_WORK(&ci->work, ci_role_work);
442 ci->wq = create_singlethread_workqueue("ci_otg");
443 if (!ci->wq) {
444 dev_err(dev, "can't create workqueue\n");
445 return -ENODEV;
446 }
447
448 /* initialize role(s) before the interrupt is requested */
Alexander Shishkineb70e5a2012-05-11 17:25:54 +0300449 ret = ci_hdrc_host_init(ci);
450 if (ret)
451 dev_info(dev, "doesn't support host\n");
452
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300453 ret = ci_hdrc_gadget_init(ci);
Alexander Shishkine443b332012-05-11 17:25:46 +0300454 if (ret)
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300455 dev_info(dev, "doesn't support gadget\n");
456
457 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
458 dev_err(dev, "no supported roles\n");
459 ret = -ENODEV;
460 goto rm_wq;
461 }
462
463 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
464 ci->is_otg = true;
Richard Zhao86ad01a2012-09-12 14:58:07 +0300465 /* ID pin needs 1ms debouce time, we delay 2ms for safe */
466 mdelay(2);
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300467 ci->role = ci_otg_role(ci);
468 } else {
469 ci->role = ci->roles[CI_ROLE_HOST]
470 ? CI_ROLE_HOST
471 : CI_ROLE_GADGET;
472 }
473
474 ret = ci_role_start(ci, ci->role);
475 if (ret) {
476 dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
477 ret = -ENODEV;
478 goto rm_wq;
479 }
480
481 platform_set_drvdata(pdev, ci);
Richard Zhao77c44002012-06-29 17:48:53 +0800482 ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300483 ci);
484 if (ret)
485 goto stop;
486
487 ret = device_create_file(dev, &dev_attr_role);
488 if (ret)
489 goto rm_attr;
490
491 if (ci->is_otg)
492 hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE);
493
494 return ret;
495
496rm_attr:
497 device_remove_file(dev, &dev_attr_role);
498stop:
499 ci_role_stop(ci);
500rm_wq:
501 flush_workqueue(ci->wq);
502 destroy_workqueue(ci->wq);
Alexander Shishkine443b332012-05-11 17:25:46 +0300503
504 return ret;
505}
506
Bill Pembertonfb4e98a2012-11-19 13:26:20 -0500507static int ci_hdrc_remove(struct platform_device *pdev)
Alexander Shishkine443b332012-05-11 17:25:46 +0300508{
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300509 struct ci13xxx *ci = platform_get_drvdata(pdev);
Alexander Shishkine443b332012-05-11 17:25:46 +0300510
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300511 flush_workqueue(ci->wq);
512 destroy_workqueue(ci->wq);
513 device_remove_file(ci->dev, &dev_attr_role);
514 free_irq(ci->irq, ci);
515 ci_role_stop(ci);
Alexander Shishkine443b332012-05-11 17:25:46 +0300516
517 return 0;
518}
519
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300520static struct platform_driver ci_hdrc_driver = {
521 .probe = ci_hdrc_probe,
Bill Pemberton76904172012-11-19 13:21:08 -0500522 .remove = ci_hdrc_remove,
Alexander Shishkine443b332012-05-11 17:25:46 +0300523 .driver = {
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300524 .name = "ci_hdrc",
Alexander Shishkine443b332012-05-11 17:25:46 +0300525 },
526};
527
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300528module_platform_driver(ci_hdrc_driver);
Alexander Shishkine443b332012-05-11 17:25:46 +0300529
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300530MODULE_ALIAS("platform:ci_hdrc");
Alexander Shishkine443b332012-05-11 17:25:46 +0300531MODULE_ALIAS("platform:ci13xxx");
532MODULE_LICENSE("GPL v2");
533MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
Alexander Shishkin5f36e232012-05-11 17:25:47 +0300534MODULE_DESCRIPTION("ChipIdea HDRC Driver");