blob: a580db29e50360f8be44403e5893764261562549 [file] [log] [blame]
Christian Pellegrine0000162009-11-02 23:07:00 +00001/*
2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 *
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 *
34 *
35 *
36 * Your platform definition file should specify something like:
37 *
38 * static struct mcp251x_platform_data mcp251x_info = {
39 * .oscillator_frequency = 8000000,
40 * .board_specific_setup = &mcp251x_setup,
Christian Pellegrine0000162009-11-02 23:07:00 +000041 * .power_enable = mcp251x_power_enable,
42 * .transceiver_enable = NULL,
43 * };
44 *
45 * static struct spi_board_info spi_board_info[] = {
46 * {
Marc Kleine-Buddef1f8c6c2010-10-18 15:00:18 +020047 * .modalias = "mcp2510",
48 * // or "mcp2515" depending on your controller
Christian Pellegrine0000162009-11-02 23:07:00 +000049 * .platform_data = &mcp251x_info,
50 * .irq = IRQ_EINT13,
51 * .max_speed_hz = 2*1000*1000,
52 * .chip_select = 2,
53 * },
54 * };
55 *
56 * Please see mcp251x.h for a description of the fields in
57 * struct mcp251x_platform_data.
58 *
59 */
60
Christian Pellegrine0000162009-11-02 23:07:00 +000061#include <linux/can/core.h>
62#include <linux/can/dev.h>
63#include <linux/can/platform/mcp251x.h>
64#include <linux/completion.h>
65#include <linux/delay.h>
66#include <linux/device.h>
67#include <linux/dma-mapping.h>
68#include <linux/freezer.h>
69#include <linux/interrupt.h>
70#include <linux/io.h>
71#include <linux/kernel.h>
72#include <linux/module.h>
73#include <linux/netdevice.h>
74#include <linux/platform_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090075#include <linux/slab.h>
Christian Pellegrine0000162009-11-02 23:07:00 +000076#include <linux/spi/spi.h>
77#include <linux/uaccess.h>
78
79/* SPI interface instruction set */
80#define INSTRUCTION_WRITE 0x02
81#define INSTRUCTION_READ 0x03
82#define INSTRUCTION_BIT_MODIFY 0x05
83#define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
84#define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
85#define INSTRUCTION_RESET 0xC0
86
87/* MPC251x registers */
88#define CANSTAT 0x0e
89#define CANCTRL 0x0f
90# define CANCTRL_REQOP_MASK 0xe0
91# define CANCTRL_REQOP_CONF 0x80
92# define CANCTRL_REQOP_LISTEN_ONLY 0x60
93# define CANCTRL_REQOP_LOOPBACK 0x40
94# define CANCTRL_REQOP_SLEEP 0x20
95# define CANCTRL_REQOP_NORMAL 0x00
96# define CANCTRL_OSM 0x08
97# define CANCTRL_ABAT 0x10
98#define TEC 0x1c
99#define REC 0x1d
100#define CNF1 0x2a
101# define CNF1_SJW_SHIFT 6
102#define CNF2 0x29
103# define CNF2_BTLMODE 0x80
104# define CNF2_SAM 0x40
105# define CNF2_PS1_SHIFT 3
106#define CNF3 0x28
107# define CNF3_SOF 0x08
108# define CNF3_WAKFIL 0x04
109# define CNF3_PHSEG2_MASK 0x07
110#define CANINTE 0x2b
111# define CANINTE_MERRE 0x80
112# define CANINTE_WAKIE 0x40
113# define CANINTE_ERRIE 0x20
114# define CANINTE_TX2IE 0x10
115# define CANINTE_TX1IE 0x08
116# define CANINTE_TX0IE 0x04
117# define CANINTE_RX1IE 0x02
118# define CANINTE_RX0IE 0x01
119#define CANINTF 0x2c
120# define CANINTF_MERRF 0x80
121# define CANINTF_WAKIF 0x40
122# define CANINTF_ERRIF 0x20
123# define CANINTF_TX2IF 0x10
124# define CANINTF_TX1IF 0x08
125# define CANINTF_TX0IF 0x04
126# define CANINTF_RX1IF 0x02
127# define CANINTF_RX0IF 0x01
Marc Kleine-Budde5601b2d2010-10-20 00:02:25 +0000128# define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
129# define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
130# define CANINTF_ERR (CANINTF_ERRIF)
Christian Pellegrine0000162009-11-02 23:07:00 +0000131#define EFLG 0x2d
132# define EFLG_EWARN 0x01
133# define EFLG_RXWAR 0x02
134# define EFLG_TXWAR 0x04
135# define EFLG_RXEP 0x08
136# define EFLG_TXEP 0x10
137# define EFLG_TXBO 0x20
138# define EFLG_RX0OVR 0x40
139# define EFLG_RX1OVR 0x80
140#define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
141# define TXBCTRL_ABTF 0x40
142# define TXBCTRL_MLOA 0x20
143# define TXBCTRL_TXERR 0x10
144# define TXBCTRL_TXREQ 0x08
145#define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
146# define SIDH_SHIFT 3
147#define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
148# define SIDL_SID_MASK 7
149# define SIDL_SID_SHIFT 5
150# define SIDL_EXIDE_SHIFT 3
151# define SIDL_EID_SHIFT 16
152# define SIDL_EID_MASK 3
153#define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
154#define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
155#define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
156# define DLC_RTR_SHIFT 6
157#define TXBCTRL_OFF 0
158#define TXBSIDH_OFF 1
159#define TXBSIDL_OFF 2
160#define TXBEID8_OFF 3
161#define TXBEID0_OFF 4
162#define TXBDLC_OFF 5
163#define TXBDAT_OFF 6
164#define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
165# define RXBCTRL_BUKT 0x04
166# define RXBCTRL_RXM0 0x20
167# define RXBCTRL_RXM1 0x40
168#define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
169# define RXBSIDH_SHIFT 3
170#define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
171# define RXBSIDL_IDE 0x08
Marc Kleine-Buddeb9958a92010-10-21 06:37:10 +0000172# define RXBSIDL_SRR 0x10
Christian Pellegrine0000162009-11-02 23:07:00 +0000173# define RXBSIDL_EID 3
174# define RXBSIDL_SHIFT 5
175#define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
176#define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
177#define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
178# define RXBDLC_LEN_MASK 0x0f
179# define RXBDLC_RTR 0x40
180#define RXBCTRL_OFF 0
181#define RXBSIDH_OFF 1
182#define RXBSIDL_OFF 2
183#define RXBEID8_OFF 3
184#define RXBEID0_OFF 4
185#define RXBDLC_OFF 5
186#define RXBDAT_OFF 6
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000187#define RXFSIDH(n) ((n) * 4)
188#define RXFSIDL(n) ((n) * 4 + 1)
189#define RXFEID8(n) ((n) * 4 + 2)
190#define RXFEID0(n) ((n) * 4 + 3)
191#define RXMSIDH(n) ((n) * 4 + 0x20)
192#define RXMSIDL(n) ((n) * 4 + 0x21)
193#define RXMEID8(n) ((n) * 4 + 0x22)
194#define RXMEID0(n) ((n) * 4 + 0x23)
Christian Pellegrine0000162009-11-02 23:07:00 +0000195
196#define GET_BYTE(val, byte) \
197 (((val) >> ((byte) * 8)) & 0xff)
198#define SET_BYTE(val, byte) \
199 (((val) & 0xff) << ((byte) * 8))
200
201/*
202 * Buffer size required for the largest SPI transfer (i.e., reading a
203 * frame)
204 */
205#define CAN_FRAME_MAX_DATA_LEN 8
206#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
207#define CAN_FRAME_MAX_BITS 128
208
209#define TX_ECHO_SKB_MAX 1
210
211#define DEVICE_NAME "mcp251x"
212
213static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
214module_param(mcp251x_enable_dma, int, S_IRUGO);
215MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
216
Marc Kleine-Budde194b9a42012-07-16 12:58:31 +0200217static const struct can_bittiming_const mcp251x_bittiming_const = {
Christian Pellegrine0000162009-11-02 23:07:00 +0000218 .name = DEVICE_NAME,
219 .tseg1_min = 3,
220 .tseg1_max = 16,
221 .tseg2_min = 2,
222 .tseg2_max = 8,
223 .sjw_max = 4,
224 .brp_min = 1,
225 .brp_max = 64,
226 .brp_inc = 1,
227};
228
Marc Kleine-Buddef1f8c6c2010-10-18 15:00:18 +0200229enum mcp251x_model {
230 CAN_MCP251X_MCP2510 = 0x2510,
231 CAN_MCP251X_MCP2515 = 0x2515,
232};
233
Christian Pellegrine0000162009-11-02 23:07:00 +0000234struct mcp251x_priv {
235 struct can_priv can;
236 struct net_device *net;
237 struct spi_device *spi;
Marc Kleine-Buddef1f8c6c2010-10-18 15:00:18 +0200238 enum mcp251x_model model;
Christian Pellegrine0000162009-11-02 23:07:00 +0000239
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000240 struct mutex mcp_lock; /* SPI device lock */
241
Christian Pellegrine0000162009-11-02 23:07:00 +0000242 u8 *spi_tx_buf;
243 u8 *spi_rx_buf;
244 dma_addr_t spi_tx_dma;
245 dma_addr_t spi_rx_dma;
246
247 struct sk_buff *tx_skb;
248 int tx_len;
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000249
Christian Pellegrine0000162009-11-02 23:07:00 +0000250 struct workqueue_struct *wq;
251 struct work_struct tx_work;
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000252 struct work_struct restart_work;
253
Christian Pellegrine0000162009-11-02 23:07:00 +0000254 int force_quit;
255 int after_suspend;
256#define AFTER_SUSPEND_UP 1
257#define AFTER_SUSPEND_DOWN 2
258#define AFTER_SUSPEND_POWER 4
259#define AFTER_SUSPEND_RESTART 8
260 int restart_tx;
261};
262
Marc Kleine-Buddebeab6752010-09-23 21:34:28 +0200263#define MCP251X_IS(_model) \
264static inline int mcp251x_is_##_model(struct spi_device *spi) \
265{ \
266 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); \
267 return priv->model == CAN_MCP251X_MCP##_model; \
268}
269
270MCP251X_IS(2510);
271MCP251X_IS(2515);
272
Christian Pellegrine0000162009-11-02 23:07:00 +0000273static void mcp251x_clean(struct net_device *net)
274{
275 struct mcp251x_priv *priv = netdev_priv(net);
276
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000277 if (priv->tx_skb || priv->tx_len)
278 net->stats.tx_errors++;
Christian Pellegrine0000162009-11-02 23:07:00 +0000279 if (priv->tx_skb)
280 dev_kfree_skb(priv->tx_skb);
281 if (priv->tx_len)
282 can_free_echo_skb(priv->net, 0);
283 priv->tx_skb = NULL;
284 priv->tx_len = 0;
285}
286
287/*
288 * Note about handling of error return of mcp251x_spi_trans: accessing
289 * registers via SPI is not really different conceptually than using
290 * normal I/O assembler instructions, although it's much more
291 * complicated from a practical POV. So it's not advisable to always
292 * check the return value of this function. Imagine that every
293 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
294 * error();", it would be a great mess (well there are some situation
295 * when exception handling C++ like could be useful after all). So we
296 * just check that transfers are OK at the beginning of our
297 * conversation with the chip and to avoid doing really nasty things
298 * (like injecting bogus packets in the network stack).
299 */
300static int mcp251x_spi_trans(struct spi_device *spi, int len)
301{
302 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
303 struct spi_transfer t = {
304 .tx_buf = priv->spi_tx_buf,
305 .rx_buf = priv->spi_rx_buf,
306 .len = len,
307 .cs_change = 0,
308 };
309 struct spi_message m;
310 int ret;
311
312 spi_message_init(&m);
313
314 if (mcp251x_enable_dma) {
315 t.tx_dma = priv->spi_tx_dma;
316 t.rx_dma = priv->spi_rx_dma;
317 m.is_dma_mapped = 1;
318 }
319
320 spi_message_add_tail(&t, &m);
321
322 ret = spi_sync(spi, &m);
323 if (ret)
324 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
325 return ret;
326}
327
328static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
329{
330 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
331 u8 val = 0;
332
Christian Pellegrine0000162009-11-02 23:07:00 +0000333 priv->spi_tx_buf[0] = INSTRUCTION_READ;
334 priv->spi_tx_buf[1] = reg;
335
336 mcp251x_spi_trans(spi, 3);
337 val = priv->spi_rx_buf[2];
338
Christian Pellegrine0000162009-11-02 23:07:00 +0000339 return val;
340}
341
Sascha Hauerf3a3ed32010-09-28 09:53:35 +0200342static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg,
343 uint8_t *v1, uint8_t *v2)
344{
345 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
346
347 priv->spi_tx_buf[0] = INSTRUCTION_READ;
348 priv->spi_tx_buf[1] = reg;
349
350 mcp251x_spi_trans(spi, 4);
351
352 *v1 = priv->spi_rx_buf[2];
353 *v2 = priv->spi_rx_buf[3];
354}
355
Christian Pellegrine0000162009-11-02 23:07:00 +0000356static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
357{
358 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
359
Christian Pellegrine0000162009-11-02 23:07:00 +0000360 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
361 priv->spi_tx_buf[1] = reg;
362 priv->spi_tx_buf[2] = val;
363
364 mcp251x_spi_trans(spi, 3);
Christian Pellegrine0000162009-11-02 23:07:00 +0000365}
366
367static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
368 u8 mask, uint8_t val)
369{
370 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
371
Christian Pellegrine0000162009-11-02 23:07:00 +0000372 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
373 priv->spi_tx_buf[1] = reg;
374 priv->spi_tx_buf[2] = mask;
375 priv->spi_tx_buf[3] = val;
376
377 mcp251x_spi_trans(spi, 4);
Christian Pellegrine0000162009-11-02 23:07:00 +0000378}
379
380static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
381 int len, int tx_buf_idx)
382{
Christian Pellegrine0000162009-11-02 23:07:00 +0000383 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
384
Marc Kleine-Buddebeab6752010-09-23 21:34:28 +0200385 if (mcp251x_is_2510(spi)) {
Christian Pellegrine0000162009-11-02 23:07:00 +0000386 int i;
387
388 for (i = 1; i < TXBDAT_OFF + len; i++)
389 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
390 buf[i]);
391 } else {
Christian Pellegrine0000162009-11-02 23:07:00 +0000392 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
393 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
Christian Pellegrine0000162009-11-02 23:07:00 +0000394 }
395}
396
397static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
398 int tx_buf_idx)
399{
400 u32 sid, eid, exide, rtr;
401 u8 buf[SPI_TRANSFER_BUF_LEN];
402
403 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
404 if (exide)
405 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
406 else
407 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
408 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
409 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
410
411 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
412 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
413 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
414 (exide << SIDL_EXIDE_SHIFT) |
415 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
416 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
417 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
418 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
419 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
420 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
421 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx), TXBCTRL_TXREQ);
422}
423
424static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
425 int buf_idx)
426{
427 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
Christian Pellegrine0000162009-11-02 23:07:00 +0000428
Marc Kleine-Buddebeab6752010-09-23 21:34:28 +0200429 if (mcp251x_is_2510(spi)) {
Christian Pellegrine0000162009-11-02 23:07:00 +0000430 int i, len;
431
432 for (i = 1; i < RXBDAT_OFF; i++)
433 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
Oliver Hartkoppc7cd6062009-12-12 04:13:21 +0000434
435 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
Christian Pellegrine0000162009-11-02 23:07:00 +0000436 for (; i < (RXBDAT_OFF + len); i++)
437 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
438 } else {
Christian Pellegrine0000162009-11-02 23:07:00 +0000439 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
440 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
441 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
Christian Pellegrine0000162009-11-02 23:07:00 +0000442 }
443}
444
445static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
446{
447 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
448 struct sk_buff *skb;
449 struct can_frame *frame;
450 u8 buf[SPI_TRANSFER_BUF_LEN];
451
452 skb = alloc_can_skb(priv->net, &frame);
453 if (!skb) {
454 dev_err(&spi->dev, "cannot allocate RX skb\n");
455 priv->net->stats.rx_dropped++;
456 return;
457 }
458
459 mcp251x_hw_rx_frame(spi, buf, buf_idx);
460 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
461 /* Extended ID format */
462 frame->can_id = CAN_EFF_FLAG;
463 frame->can_id |=
464 /* Extended ID part */
465 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
466 SET_BYTE(buf[RXBEID8_OFF], 1) |
467 SET_BYTE(buf[RXBEID0_OFF], 0) |
468 /* Standard ID part */
469 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
470 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
471 /* Remote transmission request */
472 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
473 frame->can_id |= CAN_RTR_FLAG;
474 } else {
475 /* Standard ID format */
476 frame->can_id =
477 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
478 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
Marc Kleine-Buddeb9958a92010-10-21 06:37:10 +0000479 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
480 frame->can_id |= CAN_RTR_FLAG;
Christian Pellegrine0000162009-11-02 23:07:00 +0000481 }
482 /* Data length */
Oliver Hartkoppc7cd6062009-12-12 04:13:21 +0000483 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
Christian Pellegrine0000162009-11-02 23:07:00 +0000484 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
485
486 priv->net->stats.rx_packets++;
487 priv->net->stats.rx_bytes += frame->can_dlc;
Marc Kleine-Budde57d3c7b2010-10-04 10:50:51 +0200488 netif_rx_ni(skb);
Christian Pellegrine0000162009-11-02 23:07:00 +0000489}
490
491static void mcp251x_hw_sleep(struct spi_device *spi)
492{
493 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
494}
495
Christian Pellegrine0000162009-11-02 23:07:00 +0000496static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
497 struct net_device *net)
498{
499 struct mcp251x_priv *priv = netdev_priv(net);
500 struct spi_device *spi = priv->spi;
501
502 if (priv->tx_skb || priv->tx_len) {
503 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
Christian Pellegrine0000162009-11-02 23:07:00 +0000504 return NETDEV_TX_BUSY;
505 }
506
Oliver Hartkopp3ccd4c62010-01-12 02:00:46 -0800507 if (can_dropped_invalid_skb(net, skb))
Christian Pellegrine0000162009-11-02 23:07:00 +0000508 return NETDEV_TX_OK;
Christian Pellegrine0000162009-11-02 23:07:00 +0000509
510 netif_stop_queue(net);
511 priv->tx_skb = skb;
Christian Pellegrine0000162009-11-02 23:07:00 +0000512 queue_work(priv->wq, &priv->tx_work);
513
514 return NETDEV_TX_OK;
515}
516
517static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
518{
519 struct mcp251x_priv *priv = netdev_priv(net);
520
521 switch (mode) {
522 case CAN_MODE_START:
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000523 mcp251x_clean(net);
Christian Pellegrine0000162009-11-02 23:07:00 +0000524 /* We have to delay work since SPI I/O may sleep */
525 priv->can.state = CAN_STATE_ERROR_ACTIVE;
526 priv->restart_tx = 1;
527 if (priv->can.restart_ms == 0)
528 priv->after_suspend = AFTER_SUSPEND_RESTART;
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000529 queue_work(priv->wq, &priv->restart_work);
Christian Pellegrine0000162009-11-02 23:07:00 +0000530 break;
531 default:
532 return -EOPNOTSUPP;
533 }
534
535 return 0;
536}
537
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000538static int mcp251x_set_normal_mode(struct spi_device *spi)
Christian Pellegrine0000162009-11-02 23:07:00 +0000539{
540 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
541 unsigned long timeout;
542
543 /* Enable interrupts */
544 mcp251x_write_reg(spi, CANINTE,
545 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000546 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
Christian Pellegrine0000162009-11-02 23:07:00 +0000547
548 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
549 /* Put device into loopback mode */
550 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
Christian Pellegrinad72c342010-01-14 07:08:34 +0000551 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
552 /* Put device into listen-only mode */
553 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
Christian Pellegrine0000162009-11-02 23:07:00 +0000554 } else {
555 /* Put device into normal mode */
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000556 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
Christian Pellegrine0000162009-11-02 23:07:00 +0000557
558 /* Wait for the device to enter normal mode */
559 timeout = jiffies + HZ;
560 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
561 schedule();
562 if (time_after(jiffies, timeout)) {
563 dev_err(&spi->dev, "MCP251x didn't"
564 " enter in normal mode\n");
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000565 return -EBUSY;
Christian Pellegrine0000162009-11-02 23:07:00 +0000566 }
567 }
568 }
569 priv->can.state = CAN_STATE_ERROR_ACTIVE;
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000570 return 0;
Christian Pellegrine0000162009-11-02 23:07:00 +0000571}
572
573static int mcp251x_do_set_bittiming(struct net_device *net)
574{
575 struct mcp251x_priv *priv = netdev_priv(net);
576 struct can_bittiming *bt = &priv->can.bittiming;
577 struct spi_device *spi = priv->spi;
578
579 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
580 (bt->brp - 1));
581 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
582 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
583 CNF2_SAM : 0) |
584 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
585 (bt->prop_seg - 1));
586 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
587 (bt->phase_seg2 - 1));
588 dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
589 mcp251x_read_reg(spi, CNF1),
590 mcp251x_read_reg(spi, CNF2),
591 mcp251x_read_reg(spi, CNF3));
592
593 return 0;
594}
595
596static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
597 struct spi_device *spi)
598{
Christian Pellegrin615534b2009-11-17 06:20:44 +0000599 mcp251x_do_set_bittiming(net);
Christian Pellegrine0000162009-11-02 23:07:00 +0000600
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000601 mcp251x_write_reg(spi, RXBCTRL(0),
602 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
603 mcp251x_write_reg(spi, RXBCTRL(1),
604 RXBCTRL_RXM0 | RXBCTRL_RXM1);
Christian Pellegrine0000162009-11-02 23:07:00 +0000605 return 0;
606}
607
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000608static int mcp251x_hw_reset(struct spi_device *spi)
Christian Pellegrine0000162009-11-02 23:07:00 +0000609{
610 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
611 int ret;
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000612 unsigned long timeout;
Christian Pellegrine0000162009-11-02 23:07:00 +0000613
614 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
Christian Pellegrine0000162009-11-02 23:07:00 +0000615 ret = spi_write(spi, priv->spi_tx_buf, 1);
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000616 if (ret) {
Christian Pellegrine0000162009-11-02 23:07:00 +0000617 dev_err(&spi->dev, "reset failed: ret = %d\n", ret);
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000618 return -EIO;
619 }
620
Christian Pellegrine0000162009-11-02 23:07:00 +0000621 /* Wait for reset to finish */
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000622 timeout = jiffies + HZ;
Christian Pellegrine0000162009-11-02 23:07:00 +0000623 mdelay(10);
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000624 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK)
625 != CANCTRL_REQOP_CONF) {
626 schedule();
627 if (time_after(jiffies, timeout)) {
628 dev_err(&spi->dev, "MCP251x didn't"
629 " enter in conf mode after reset\n");
630 return -EBUSY;
631 }
632 }
633 return 0;
Christian Pellegrine0000162009-11-02 23:07:00 +0000634}
635
636static int mcp251x_hw_probe(struct spi_device *spi)
637{
638 int st1, st2;
639
640 mcp251x_hw_reset(spi);
641
642 /*
643 * Please note that these are "magic values" based on after
644 * reset defaults taken from data sheet which allows us to see
645 * if we really have a chip on the bus (we avoid common all
646 * zeroes or all ones situations)
647 */
648 st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE;
649 st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17;
650
651 dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2);
652
653 /* Check for power up default values */
654 return (st1 == 0x80 && st2 == 0x07) ? 1 : 0;
655}
656
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000657static void mcp251x_open_clean(struct net_device *net)
Christian Pellegrine0000162009-11-02 23:07:00 +0000658{
659 struct mcp251x_priv *priv = netdev_priv(net);
660 struct spi_device *spi = priv->spi;
661 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
Christian Pellegrine0000162009-11-02 23:07:00 +0000662
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000663 free_irq(spi->irq, priv);
664 mcp251x_hw_sleep(spi);
Christian Pellegrine0000162009-11-02 23:07:00 +0000665 if (pdata->transceiver_enable)
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000666 pdata->transceiver_enable(0);
667 close_candev(net);
Christian Pellegrine0000162009-11-02 23:07:00 +0000668}
669
670static int mcp251x_stop(struct net_device *net)
671{
672 struct mcp251x_priv *priv = netdev_priv(net);
673 struct spi_device *spi = priv->spi;
674 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
675
676 close_candev(net);
677
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000678 priv->force_quit = 1;
679 free_irq(spi->irq, priv);
680 destroy_workqueue(priv->wq);
681 priv->wq = NULL;
682
683 mutex_lock(&priv->mcp_lock);
684
Christian Pellegrine0000162009-11-02 23:07:00 +0000685 /* Disable and clear pending interrupts */
686 mcp251x_write_reg(spi, CANINTE, 0x00);
687 mcp251x_write_reg(spi, CANINTF, 0x00);
688
Christian Pellegrine0000162009-11-02 23:07:00 +0000689 mcp251x_write_reg(spi, TXBCTRL(0), 0);
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000690 mcp251x_clean(net);
Christian Pellegrine0000162009-11-02 23:07:00 +0000691
692 mcp251x_hw_sleep(spi);
693
694 if (pdata->transceiver_enable)
695 pdata->transceiver_enable(0);
696
697 priv->can.state = CAN_STATE_STOPPED;
698
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000699 mutex_unlock(&priv->mcp_lock);
700
Christian Pellegrine0000162009-11-02 23:07:00 +0000701 return 0;
702}
703
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000704static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
705{
706 struct sk_buff *skb;
707 struct can_frame *frame;
708
709 skb = alloc_can_err_skb(net, &frame);
710 if (skb) {
Marc Kleine-Budde612eef42010-10-20 00:02:26 +0000711 frame->can_id |= can_id;
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000712 frame->data[1] = data1;
Marc Kleine-Budde57d3c7b2010-10-04 10:50:51 +0200713 netif_rx_ni(skb);
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000714 } else {
Wolfgang Grandeggeraabdfd62012-02-01 11:02:05 +0100715 netdev_err(net, "cannot allocate error skb\n");
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000716 }
717}
718
Christian Pellegrine0000162009-11-02 23:07:00 +0000719static void mcp251x_tx_work_handler(struct work_struct *ws)
720{
721 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
722 tx_work);
723 struct spi_device *spi = priv->spi;
724 struct net_device *net = priv->net;
725 struct can_frame *frame;
726
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000727 mutex_lock(&priv->mcp_lock);
Christian Pellegrine0000162009-11-02 23:07:00 +0000728 if (priv->tx_skb) {
Christian Pellegrine0000162009-11-02 23:07:00 +0000729 if (priv->can.state == CAN_STATE_BUS_OFF) {
730 mcp251x_clean(net);
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000731 } else {
732 frame = (struct can_frame *)priv->tx_skb->data;
733
734 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
735 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
736 mcp251x_hw_tx(spi, frame, 0);
737 priv->tx_len = 1 + frame->can_dlc;
738 can_put_echo_skb(priv->tx_skb, net, 0);
739 priv->tx_skb = NULL;
Christian Pellegrine0000162009-11-02 23:07:00 +0000740 }
Christian Pellegrine0000162009-11-02 23:07:00 +0000741 }
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000742 mutex_unlock(&priv->mcp_lock);
Christian Pellegrine0000162009-11-02 23:07:00 +0000743}
744
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000745static void mcp251x_restart_work_handler(struct work_struct *ws)
Christian Pellegrine0000162009-11-02 23:07:00 +0000746{
747 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000748 restart_work);
Christian Pellegrine0000162009-11-02 23:07:00 +0000749 struct spi_device *spi = priv->spi;
750 struct net_device *net = priv->net;
Christian Pellegrine0000162009-11-02 23:07:00 +0000751
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000752 mutex_lock(&priv->mcp_lock);
Christian Pellegrine0000162009-11-02 23:07:00 +0000753 if (priv->after_suspend) {
754 mdelay(10);
755 mcp251x_hw_reset(spi);
756 mcp251x_setup(net, priv, spi);
757 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
758 mcp251x_set_normal_mode(spi);
759 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
760 netif_device_attach(net);
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000761 mcp251x_clean(net);
Christian Pellegrine0000162009-11-02 23:07:00 +0000762 mcp251x_set_normal_mode(spi);
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000763 netif_wake_queue(net);
Christian Pellegrine0000162009-11-02 23:07:00 +0000764 } else {
765 mcp251x_hw_sleep(spi);
766 }
767 priv->after_suspend = 0;
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000768 priv->force_quit = 0;
Christian Pellegrine0000162009-11-02 23:07:00 +0000769 }
770
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000771 if (priv->restart_tx) {
772 priv->restart_tx = 0;
773 mcp251x_write_reg(spi, TXBCTRL(0), 0);
774 mcp251x_clean(net);
775 netif_wake_queue(net);
776 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
777 }
778 mutex_unlock(&priv->mcp_lock);
779}
Christian Pellegrine0000162009-11-02 23:07:00 +0000780
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000781static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
782{
783 struct mcp251x_priv *priv = dev_id;
784 struct spi_device *spi = priv->spi;
785 struct net_device *net = priv->net;
786
787 mutex_lock(&priv->mcp_lock);
788 while (!priv->force_quit) {
789 enum can_state new_state;
Sascha Hauerf3a3ed32010-09-28 09:53:35 +0200790 u8 intf, eflag;
Marc Kleine-Budded3cd1562010-09-28 10:18:34 +0200791 u8 clear_intf = 0;
Christian Pellegrine0000162009-11-02 23:07:00 +0000792 int can_id = 0, data1 = 0;
793
Sascha Hauerf3a3ed32010-09-28 09:53:35 +0200794 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
795
Marc Kleine-Budde5601b2d2010-10-20 00:02:25 +0000796 /* mask out flags we don't care about */
797 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
798
Marc Kleine-Budded3cd1562010-09-28 10:18:34 +0200799 /* receive buffer 0 */
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000800 if (intf & CANINTF_RX0IF) {
801 mcp251x_hw_rx(spi, 0);
Marc Kleine-Budde9c473fc2010-10-04 12:09:31 +0200802 /*
803 * Free one buffer ASAP
804 * (The MCP2515 does this automatically.)
805 */
806 if (mcp251x_is_2510(spi))
807 mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00);
Christian Pellegrine0000162009-11-02 23:07:00 +0000808 }
809
Marc Kleine-Budded3cd1562010-09-28 10:18:34 +0200810 /* receive buffer 1 */
811 if (intf & CANINTF_RX1IF) {
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000812 mcp251x_hw_rx(spi, 1);
Marc Kleine-Budde9c473fc2010-10-04 12:09:31 +0200813 /* the MCP2515 does this automatically */
814 if (mcp251x_is_2510(spi))
815 clear_intf |= CANINTF_RX1IF;
Marc Kleine-Budded3cd1562010-09-28 10:18:34 +0200816 }
Christian Pellegrine0000162009-11-02 23:07:00 +0000817
Marc Kleine-Budded3cd1562010-09-28 10:18:34 +0200818 /* any error or tx interrupt we need to clear? */
Marc Kleine-Budde5601b2d2010-10-20 00:02:25 +0000819 if (intf & (CANINTF_ERR | CANINTF_TX))
820 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
Marc Kleine-Budded3cd1562010-09-28 10:18:34 +0200821 if (clear_intf)
822 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
Christian Pellegrine0000162009-11-02 23:07:00 +0000823
Sascha Hauer7e15de32010-09-28 10:00:47 +0200824 if (eflag)
825 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000826
Christian Pellegrine0000162009-11-02 23:07:00 +0000827 /* Update can state */
828 if (eflag & EFLG_TXBO) {
829 new_state = CAN_STATE_BUS_OFF;
830 can_id |= CAN_ERR_BUSOFF;
831 } else if (eflag & EFLG_TXEP) {
832 new_state = CAN_STATE_ERROR_PASSIVE;
833 can_id |= CAN_ERR_CRTL;
834 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
835 } else if (eflag & EFLG_RXEP) {
836 new_state = CAN_STATE_ERROR_PASSIVE;
837 can_id |= CAN_ERR_CRTL;
838 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
839 } else if (eflag & EFLG_TXWAR) {
840 new_state = CAN_STATE_ERROR_WARNING;
841 can_id |= CAN_ERR_CRTL;
842 data1 |= CAN_ERR_CRTL_TX_WARNING;
843 } else if (eflag & EFLG_RXWAR) {
844 new_state = CAN_STATE_ERROR_WARNING;
845 can_id |= CAN_ERR_CRTL;
846 data1 |= CAN_ERR_CRTL_RX_WARNING;
847 } else {
848 new_state = CAN_STATE_ERROR_ACTIVE;
849 }
850
851 /* Update can state statistics */
852 switch (priv->can.state) {
853 case CAN_STATE_ERROR_ACTIVE:
854 if (new_state >= CAN_STATE_ERROR_WARNING &&
855 new_state <= CAN_STATE_BUS_OFF)
856 priv->can.can_stats.error_warning++;
857 case CAN_STATE_ERROR_WARNING: /* fallthrough */
858 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
859 new_state <= CAN_STATE_BUS_OFF)
860 priv->can.can_stats.error_passive++;
861 break;
862 default:
863 break;
864 }
865 priv->can.state = new_state;
866
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000867 if (intf & CANINTF_ERRIF) {
868 /* Handle overflow counters */
869 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
Sascha Hauer711e4d62010-09-30 09:46:00 +0200870 if (eflag & EFLG_RX0OVR) {
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000871 net->stats.rx_over_errors++;
Sascha Hauer711e4d62010-09-30 09:46:00 +0200872 net->stats.rx_errors++;
873 }
874 if (eflag & EFLG_RX1OVR) {
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000875 net->stats.rx_over_errors++;
Sascha Hauer711e4d62010-09-30 09:46:00 +0200876 net->stats.rx_errors++;
877 }
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000878 can_id |= CAN_ERR_CRTL;
879 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
Christian Pellegrine0000162009-11-02 23:07:00 +0000880 }
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000881 mcp251x_error_skb(net, can_id, data1);
Christian Pellegrine0000162009-11-02 23:07:00 +0000882 }
883
884 if (priv->can.state == CAN_STATE_BUS_OFF) {
885 if (priv->can.restart_ms == 0) {
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000886 priv->force_quit = 1;
Christian Pellegrine0000162009-11-02 23:07:00 +0000887 can_bus_off(net);
888 mcp251x_hw_sleep(spi);
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000889 break;
Christian Pellegrine0000162009-11-02 23:07:00 +0000890 }
891 }
892
893 if (intf == 0)
894 break;
895
Marc Kleine-Budde5601b2d2010-10-20 00:02:25 +0000896 if (intf & CANINTF_TX) {
Christian Pellegrine0000162009-11-02 23:07:00 +0000897 net->stats.tx_packets++;
898 net->stats.tx_bytes += priv->tx_len - 1;
899 if (priv->tx_len) {
900 can_get_echo_skb(net, 0);
901 priv->tx_len = 0;
902 }
903 netif_wake_queue(net);
904 }
905
Christian Pellegrine0000162009-11-02 23:07:00 +0000906 }
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000907 mutex_unlock(&priv->mcp_lock);
908 return IRQ_HANDLED;
909}
910
911static int mcp251x_open(struct net_device *net)
912{
913 struct mcp251x_priv *priv = netdev_priv(net);
914 struct spi_device *spi = priv->spi;
915 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
916 int ret;
917
918 ret = open_candev(net);
919 if (ret) {
920 dev_err(&spi->dev, "unable to set initial baudrate!\n");
921 return ret;
922 }
923
924 mutex_lock(&priv->mcp_lock);
925 if (pdata->transceiver_enable)
926 pdata->transceiver_enable(1);
927
928 priv->force_quit = 0;
929 priv->tx_skb = NULL;
930 priv->tx_len = 0;
931
932 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
Enric Balletbo i Serra34206f22011-04-05 07:08:41 +0000933 pdata->irq_flags ? pdata->irq_flags : IRQF_TRIGGER_FALLING,
934 DEVICE_NAME, priv);
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000935 if (ret) {
936 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
937 if (pdata->transceiver_enable)
938 pdata->transceiver_enable(0);
939 close_candev(net);
940 goto open_unlock;
941 }
942
Tejun Heo58a69cb2011-02-16 09:25:31 +0100943 priv->wq = create_freezable_workqueue("mcp251x_wq");
Christian Pellegrinbf66f372010-02-03 07:39:54 +0000944 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
945 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
946
947 ret = mcp251x_hw_reset(spi);
948 if (ret) {
949 mcp251x_open_clean(net);
950 goto open_unlock;
951 }
952 ret = mcp251x_setup(net, priv, spi);
953 if (ret) {
954 mcp251x_open_clean(net);
955 goto open_unlock;
956 }
957 ret = mcp251x_set_normal_mode(spi);
958 if (ret) {
959 mcp251x_open_clean(net);
960 goto open_unlock;
961 }
962 netif_wake_queue(net);
963
964open_unlock:
965 mutex_unlock(&priv->mcp_lock);
966 return ret;
Christian Pellegrine0000162009-11-02 23:07:00 +0000967}
968
969static const struct net_device_ops mcp251x_netdev_ops = {
970 .ndo_open = mcp251x_open,
971 .ndo_stop = mcp251x_stop,
972 .ndo_start_xmit = mcp251x_hard_start_xmit,
973};
974
975static int __devinit mcp251x_can_probe(struct spi_device *spi)
976{
977 struct net_device *net;
978 struct mcp251x_priv *priv;
979 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
980 int ret = -ENODEV;
981
982 if (!pdata)
983 /* Platform data is required for osc freq */
984 goto error_out;
985
986 /* Allocate can/net device */
987 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
988 if (!net) {
989 ret = -ENOMEM;
990 goto error_alloc;
991 }
992
993 net->netdev_ops = &mcp251x_netdev_ops;
994 net->flags |= IFF_ECHO;
995
996 priv = netdev_priv(net);
997 priv->can.bittiming_const = &mcp251x_bittiming_const;
998 priv->can.do_set_mode = mcp251x_do_set_mode;
999 priv->can.clock.freq = pdata->oscillator_frequency / 2;
Christian Pellegrinad72c342010-01-14 07:08:34 +00001000 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1001 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
Marc Kleine-Buddef1f8c6c2010-10-18 15:00:18 +02001002 priv->model = spi_get_device_id(spi)->driver_data;
Christian Pellegrine0000162009-11-02 23:07:00 +00001003 priv->net = net;
1004 dev_set_drvdata(&spi->dev, priv);
1005
1006 priv->spi = spi;
Christian Pellegrinbf66f372010-02-03 07:39:54 +00001007 mutex_init(&priv->mcp_lock);
Christian Pellegrine0000162009-11-02 23:07:00 +00001008
1009 /* If requested, allocate DMA buffers */
1010 if (mcp251x_enable_dma) {
1011 spi->dev.coherent_dma_mask = ~0;
1012
1013 /*
1014 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1015 * that much and share it between Tx and Rx DMA buffers.
1016 */
1017 priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
1018 PAGE_SIZE,
1019 &priv->spi_tx_dma,
1020 GFP_DMA);
1021
1022 if (priv->spi_tx_buf) {
Joe Perchesc2fd03a2012-06-04 12:44:18 +00001023 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2));
Christian Pellegrine0000162009-11-02 23:07:00 +00001024 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1025 (PAGE_SIZE / 2));
1026 } else {
1027 /* Fall back to non-DMA */
1028 mcp251x_enable_dma = 0;
1029 }
1030 }
1031
1032 /* Allocate non-DMA buffers */
1033 if (!mcp251x_enable_dma) {
1034 priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
1035 if (!priv->spi_tx_buf) {
1036 ret = -ENOMEM;
1037 goto error_tx_buf;
1038 }
1039 priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
Julia Lawallce739b42009-12-27 11:27:44 +00001040 if (!priv->spi_rx_buf) {
Christian Pellegrine0000162009-11-02 23:07:00 +00001041 ret = -ENOMEM;
1042 goto error_rx_buf;
1043 }
1044 }
1045
1046 if (pdata->power_enable)
1047 pdata->power_enable(1);
1048
1049 /* Call out to platform specific setup */
1050 if (pdata->board_specific_setup)
1051 pdata->board_specific_setup(spi);
1052
1053 SET_NETDEV_DEV(net, &spi->dev);
1054
Christian Pellegrine0000162009-11-02 23:07:00 +00001055 /* Configure the SPI bus */
1056 spi->mode = SPI_MODE_0;
1057 spi->bits_per_word = 8;
1058 spi_setup(spi);
1059
Christian Pellegrinbf66f372010-02-03 07:39:54 +00001060 /* Here is OK to not lock the MCP, no one knows about it yet */
Christian Pellegrine0000162009-11-02 23:07:00 +00001061 if (!mcp251x_hw_probe(spi)) {
1062 dev_info(&spi->dev, "Probe failed\n");
1063 goto error_probe;
1064 }
1065 mcp251x_hw_sleep(spi);
1066
1067 if (pdata->transceiver_enable)
1068 pdata->transceiver_enable(0);
1069
1070 ret = register_candev(net);
1071 if (!ret) {
1072 dev_info(&spi->dev, "probed\n");
1073 return ret;
1074 }
1075error_probe:
1076 if (!mcp251x_enable_dma)
1077 kfree(priv->spi_rx_buf);
1078error_rx_buf:
1079 if (!mcp251x_enable_dma)
1080 kfree(priv->spi_tx_buf);
1081error_tx_buf:
1082 free_candev(net);
1083 if (mcp251x_enable_dma)
1084 dma_free_coherent(&spi->dev, PAGE_SIZE,
1085 priv->spi_tx_buf, priv->spi_tx_dma);
1086error_alloc:
1087 if (pdata->power_enable)
1088 pdata->power_enable(0);
1089 dev_err(&spi->dev, "probe failed\n");
1090error_out:
1091 return ret;
1092}
1093
1094static int __devexit mcp251x_can_remove(struct spi_device *spi)
1095{
1096 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1097 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1098 struct net_device *net = priv->net;
1099
1100 unregister_candev(net);
1101 free_candev(net);
1102
Christian Pellegrine0000162009-11-02 23:07:00 +00001103 if (mcp251x_enable_dma) {
1104 dma_free_coherent(&spi->dev, PAGE_SIZE,
1105 priv->spi_tx_buf, priv->spi_tx_dma);
1106 } else {
1107 kfree(priv->spi_tx_buf);
1108 kfree(priv->spi_rx_buf);
1109 }
1110
1111 if (pdata->power_enable)
1112 pdata->power_enable(0);
1113
1114 return 0;
1115}
1116
1117#ifdef CONFIG_PM
1118static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state)
1119{
1120 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1121 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1122 struct net_device *net = priv->net;
1123
Christian Pellegrinbf66f372010-02-03 07:39:54 +00001124 priv->force_quit = 1;
1125 disable_irq(spi->irq);
1126 /*
1127 * Note: at this point neither IST nor workqueues are running.
1128 * open/stop cannot be called anyway so locking is not needed
1129 */
Christian Pellegrine0000162009-11-02 23:07:00 +00001130 if (netif_running(net)) {
1131 netif_device_detach(net);
1132
1133 mcp251x_hw_sleep(spi);
1134 if (pdata->transceiver_enable)
1135 pdata->transceiver_enable(0);
1136 priv->after_suspend = AFTER_SUSPEND_UP;
1137 } else {
1138 priv->after_suspend = AFTER_SUSPEND_DOWN;
1139 }
1140
1141 if (pdata->power_enable) {
1142 pdata->power_enable(0);
1143 priv->after_suspend |= AFTER_SUSPEND_POWER;
1144 }
1145
1146 return 0;
1147}
1148
1149static int mcp251x_can_resume(struct spi_device *spi)
1150{
1151 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1152 struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev);
1153
1154 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1155 pdata->power_enable(1);
Christian Pellegrinbf66f372010-02-03 07:39:54 +00001156 queue_work(priv->wq, &priv->restart_work);
Christian Pellegrine0000162009-11-02 23:07:00 +00001157 } else {
1158 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1159 if (pdata->transceiver_enable)
1160 pdata->transceiver_enable(1);
Christian Pellegrinbf66f372010-02-03 07:39:54 +00001161 queue_work(priv->wq, &priv->restart_work);
Christian Pellegrine0000162009-11-02 23:07:00 +00001162 } else {
1163 priv->after_suspend = 0;
1164 }
1165 }
Christian Pellegrinbf66f372010-02-03 07:39:54 +00001166 priv->force_quit = 0;
1167 enable_irq(spi->irq);
Christian Pellegrine0000162009-11-02 23:07:00 +00001168 return 0;
1169}
1170#else
1171#define mcp251x_can_suspend NULL
1172#define mcp251x_can_resume NULL
1173#endif
1174
Marc Kleine-Buddef1f8c6c2010-10-18 15:00:18 +02001175static const struct spi_device_id mcp251x_id_table[] = {
Marc Zyngiere4466302010-03-29 08:57:56 +00001176 { "mcp2510", CAN_MCP251X_MCP2510 },
1177 { "mcp2515", CAN_MCP251X_MCP2515 },
1178 { },
1179};
1180
1181MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1182
Christian Pellegrine0000162009-11-02 23:07:00 +00001183static struct spi_driver mcp251x_can_driver = {
1184 .driver = {
1185 .name = DEVICE_NAME,
1186 .bus = &spi_bus_type,
1187 .owner = THIS_MODULE,
1188 },
1189
Marc Zyngiere4466302010-03-29 08:57:56 +00001190 .id_table = mcp251x_id_table,
Christian Pellegrine0000162009-11-02 23:07:00 +00001191 .probe = mcp251x_can_probe,
1192 .remove = __devexit_p(mcp251x_can_remove),
1193 .suspend = mcp251x_can_suspend,
1194 .resume = mcp251x_can_resume,
1195};
1196
1197static int __init mcp251x_can_init(void)
1198{
1199 return spi_register_driver(&mcp251x_can_driver);
1200}
1201
1202static void __exit mcp251x_can_exit(void)
1203{
1204 spi_unregister_driver(&mcp251x_can_driver);
1205}
1206
1207module_init(mcp251x_can_init);
1208module_exit(mcp251x_can_exit);
1209
1210MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1211 "Christian Pellegrin <chripell@evolware.org>");
1212MODULE_DESCRIPTION("Microchip 251x CAN driver");
1213MODULE_LICENSE("GPL v2");