Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Freescale DMA ALSA SoC PCM driver |
| 3 | * |
| 4 | * Author: Timur Tabi <timur@freescale.com> |
| 5 | * |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 6 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
| 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public License |
| 9 | * version 2. This program is licensed "as is" without any warranty of any |
| 10 | * kind, whether express or implied. |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 11 | * |
| 12 | * This driver implements ASoC support for the Elo DMA controller, which is |
| 13 | * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms, |
| 14 | * the PCM driver is what handles the DMA buffer. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/dma-mapping.h> |
| 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/delay.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 23 | #include <linux/gfp.h> |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 24 | #include <linux/of_platform.h> |
| 25 | #include <linux/list.h> |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 26 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 27 | #include <sound/core.h> |
| 28 | #include <sound/pcm.h> |
| 29 | #include <sound/pcm_params.h> |
| 30 | #include <sound/soc.h> |
| 31 | |
| 32 | #include <asm/io.h> |
| 33 | |
| 34 | #include "fsl_dma.h" |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 35 | #include "fsl_ssi.h" /* For the offset of stx0 and srx0 */ |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 36 | |
| 37 | /* |
| 38 | * The formats that the DMA controller supports, which is anything |
| 39 | * that is 8, 16, or 32 bits. |
| 40 | */ |
| 41 | #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ |
| 42 | SNDRV_PCM_FMTBIT_U8 | \ |
| 43 | SNDRV_PCM_FMTBIT_S16_LE | \ |
| 44 | SNDRV_PCM_FMTBIT_S16_BE | \ |
| 45 | SNDRV_PCM_FMTBIT_U16_LE | \ |
| 46 | SNDRV_PCM_FMTBIT_U16_BE | \ |
| 47 | SNDRV_PCM_FMTBIT_S24_LE | \ |
| 48 | SNDRV_PCM_FMTBIT_S24_BE | \ |
| 49 | SNDRV_PCM_FMTBIT_U24_LE | \ |
| 50 | SNDRV_PCM_FMTBIT_U24_BE | \ |
| 51 | SNDRV_PCM_FMTBIT_S32_LE | \ |
| 52 | SNDRV_PCM_FMTBIT_S32_BE | \ |
| 53 | SNDRV_PCM_FMTBIT_U32_LE | \ |
| 54 | SNDRV_PCM_FMTBIT_U32_BE) |
| 55 | |
| 56 | #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ |
| 57 | SNDRV_PCM_RATE_CONTINUOUS) |
| 58 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 59 | struct dma_object { |
| 60 | struct list_head list; |
| 61 | struct snd_soc_platform_driver dai; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 62 | dma_addr_t ssi_stx_phys; |
| 63 | dma_addr_t ssi_srx_phys; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 64 | struct ccsr_dma_channel __iomem *channel; |
| 65 | unsigned int irq; |
| 66 | bool assigned; |
| 67 | char path[1]; |
| 68 | }; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 69 | |
| 70 | /* |
| 71 | * The number of DMA links to use. Two is the bare minimum, but if you |
| 72 | * have really small links you might need more. |
| 73 | */ |
| 74 | #define NUM_DMA_LINKS 2 |
| 75 | |
| 76 | /** fsl_dma_private: p-substream DMA data |
| 77 | * |
| 78 | * Each substream has a 1-to-1 association with a DMA channel. |
| 79 | * |
| 80 | * The link[] array is first because it needs to be aligned on a 32-byte |
| 81 | * boundary, so putting it first will ensure alignment without padding the |
| 82 | * structure. |
| 83 | * |
| 84 | * @link[]: array of link descriptors |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 85 | * @dma_channel: pointer to the DMA channel's registers |
| 86 | * @irq: IRQ for this DMA channel |
| 87 | * @substream: pointer to the substream object, needed by the ISR |
| 88 | * @ssi_sxx_phys: bus address of the STX or SRX register to use |
| 89 | * @ld_buf_phys: physical address of the LD buffer |
| 90 | * @current_link: index into link[] of the link currently being processed |
| 91 | * @dma_buf_phys: physical address of the DMA buffer |
| 92 | * @dma_buf_next: physical address of the next period to process |
| 93 | * @dma_buf_end: physical address of the byte after the end of the DMA |
| 94 | * @buffer period_size: the size of a single period |
| 95 | * @num_periods: the number of periods in the DMA buffer |
| 96 | */ |
| 97 | struct fsl_dma_private { |
| 98 | struct fsl_dma_link_descriptor link[NUM_DMA_LINKS]; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 99 | struct ccsr_dma_channel __iomem *dma_channel; |
| 100 | unsigned int irq; |
| 101 | struct snd_pcm_substream *substream; |
| 102 | dma_addr_t ssi_sxx_phys; |
| 103 | dma_addr_t ld_buf_phys; |
| 104 | unsigned int current_link; |
| 105 | dma_addr_t dma_buf_phys; |
| 106 | dma_addr_t dma_buf_next; |
| 107 | dma_addr_t dma_buf_end; |
| 108 | size_t period_size; |
| 109 | unsigned int num_periods; |
| 110 | }; |
| 111 | |
| 112 | /** |
| 113 | * fsl_dma_hardare: define characteristics of the PCM hardware. |
| 114 | * |
| 115 | * The PCM hardware is the Freescale DMA controller. This structure defines |
| 116 | * the capabilities of that hardware. |
| 117 | * |
| 118 | * Since the sampling rate and data format are not controlled by the DMA |
| 119 | * controller, we specify no limits for those values. The only exception is |
| 120 | * period_bytes_min, which is set to a reasonably low value to prevent the |
| 121 | * DMA controller from generating too many interrupts per second. |
| 122 | * |
| 123 | * Since each link descriptor has a 32-bit byte count field, we set |
| 124 | * period_bytes_max to the largest 32-bit number. We also have no maximum |
| 125 | * number of periods. |
Timur Tabi | be41e94 | 2008-07-28 17:04:39 -0500 | [diff] [blame] | 126 | * |
| 127 | * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a |
| 128 | * limitation in the SSI driver requires the sample rates for playback and |
| 129 | * capture to be the same. |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 130 | */ |
| 131 | static const struct snd_pcm_hardware fsl_dma_hardware = { |
| 132 | |
Timur Tabi | 4052ce4 | 2008-01-17 17:44:49 +0100 | [diff] [blame] | 133 | .info = SNDRV_PCM_INFO_INTERLEAVED | |
| 134 | SNDRV_PCM_INFO_MMAP | |
Timur Tabi | be41e94 | 2008-07-28 17:04:39 -0500 | [diff] [blame] | 135 | SNDRV_PCM_INFO_MMAP_VALID | |
Timur Tabi | 3a638ff | 2009-03-06 18:39:34 -0600 | [diff] [blame] | 136 | SNDRV_PCM_INFO_JOINT_DUPLEX | |
| 137 | SNDRV_PCM_INFO_PAUSE, |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 138 | .formats = FSLDMA_PCM_FORMATS, |
| 139 | .rates = FSLDMA_PCM_RATES, |
| 140 | .rate_min = 5512, |
| 141 | .rate_max = 192000, |
| 142 | .period_bytes_min = 512, /* A reasonable limit */ |
| 143 | .period_bytes_max = (u32) -1, |
| 144 | .periods_min = NUM_DMA_LINKS, |
| 145 | .periods_max = (unsigned int) -1, |
| 146 | .buffer_bytes_max = 128 * 1024, /* A reasonable limit */ |
| 147 | }; |
| 148 | |
| 149 | /** |
| 150 | * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted |
| 151 | * |
| 152 | * This function should be called by the ISR whenever the DMA controller |
| 153 | * halts data transfer. |
| 154 | */ |
| 155 | static void fsl_dma_abort_stream(struct snd_pcm_substream *substream) |
| 156 | { |
| 157 | unsigned long flags; |
| 158 | |
| 159 | snd_pcm_stream_lock_irqsave(substream, flags); |
| 160 | |
| 161 | if (snd_pcm_running(substream)) |
| 162 | snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); |
| 163 | |
| 164 | snd_pcm_stream_unlock_irqrestore(substream, flags); |
| 165 | } |
| 166 | |
| 167 | /** |
| 168 | * fsl_dma_update_pointers - update LD pointers to point to the next period |
| 169 | * |
| 170 | * As each period is completed, this function changes the the link |
| 171 | * descriptor pointers for that period to point to the next period. |
| 172 | */ |
| 173 | static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private) |
| 174 | { |
| 175 | struct fsl_dma_link_descriptor *link = |
| 176 | &dma_private->link[dma_private->current_link]; |
| 177 | |
Timur Tabi | 1a3c5a4 | 2010-08-02 12:44:36 -0500 | [diff] [blame^] | 178 | /* Update our link descriptors to point to the next period. On a 36-bit |
| 179 | * system, we also need to update the ESAD bits. We also set (keep) the |
| 180 | * snoop bits. See the comments in fsl_dma_hw_params() about snooping. |
| 181 | */ |
| 182 | if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 183 | link->source_addr = cpu_to_be32(dma_private->dma_buf_next); |
| 184 | #ifdef CONFIG_PHYS_64BIT |
| 185 | link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | |
| 186 | upper_32_bits(dma_private->dma_buf_next)); |
| 187 | #endif |
| 188 | } else { |
| 189 | link->dest_addr = cpu_to_be32(dma_private->dma_buf_next); |
| 190 | #ifdef CONFIG_PHYS_64BIT |
| 191 | link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | |
| 192 | upper_32_bits(dma_private->dma_buf_next)); |
| 193 | #endif |
| 194 | } |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 195 | |
| 196 | /* Update our variables for next time */ |
| 197 | dma_private->dma_buf_next += dma_private->period_size; |
| 198 | |
| 199 | if (dma_private->dma_buf_next >= dma_private->dma_buf_end) |
| 200 | dma_private->dma_buf_next = dma_private->dma_buf_phys; |
| 201 | |
| 202 | if (++dma_private->current_link >= NUM_DMA_LINKS) |
| 203 | dma_private->current_link = 0; |
| 204 | } |
| 205 | |
| 206 | /** |
| 207 | * fsl_dma_isr: interrupt handler for the DMA controller |
| 208 | * |
| 209 | * @irq: IRQ of the DMA channel |
| 210 | * @dev_id: pointer to the dma_private structure for this DMA channel |
| 211 | */ |
| 212 | static irqreturn_t fsl_dma_isr(int irq, void *dev_id) |
| 213 | { |
| 214 | struct fsl_dma_private *dma_private = dev_id; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 215 | struct snd_pcm_substream *substream = dma_private->substream; |
| 216 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 217 | struct device *dev = rtd->platform->dev; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 218 | struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; |
| 219 | irqreturn_t ret = IRQ_NONE; |
| 220 | u32 sr, sr2 = 0; |
| 221 | |
| 222 | /* We got an interrupt, so read the status register to see what we |
| 223 | were interrupted for. |
| 224 | */ |
| 225 | sr = in_be32(&dma_channel->sr); |
| 226 | |
| 227 | if (sr & CCSR_DMA_SR_TE) { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 228 | dev_err(dev, "dma transmit error\n"); |
| 229 | fsl_dma_abort_stream(substream); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 230 | sr2 |= CCSR_DMA_SR_TE; |
| 231 | ret = IRQ_HANDLED; |
| 232 | } |
| 233 | |
| 234 | if (sr & CCSR_DMA_SR_CH) |
| 235 | ret = IRQ_HANDLED; |
| 236 | |
| 237 | if (sr & CCSR_DMA_SR_PE) { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 238 | dev_err(dev, "dma programming error\n"); |
| 239 | fsl_dma_abort_stream(substream); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 240 | sr2 |= CCSR_DMA_SR_PE; |
| 241 | ret = IRQ_HANDLED; |
| 242 | } |
| 243 | |
| 244 | if (sr & CCSR_DMA_SR_EOLNI) { |
| 245 | sr2 |= CCSR_DMA_SR_EOLNI; |
| 246 | ret = IRQ_HANDLED; |
| 247 | } |
| 248 | |
| 249 | if (sr & CCSR_DMA_SR_CB) |
| 250 | ret = IRQ_HANDLED; |
| 251 | |
| 252 | if (sr & CCSR_DMA_SR_EOSI) { |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 253 | /* Tell ALSA we completed a period. */ |
| 254 | snd_pcm_period_elapsed(substream); |
| 255 | |
| 256 | /* |
| 257 | * Update our link descriptors to point to the next period. We |
| 258 | * only need to do this if the number of periods is not equal to |
| 259 | * the number of links. |
| 260 | */ |
| 261 | if (dma_private->num_periods != NUM_DMA_LINKS) |
| 262 | fsl_dma_update_pointers(dma_private); |
| 263 | |
| 264 | sr2 |= CCSR_DMA_SR_EOSI; |
| 265 | ret = IRQ_HANDLED; |
| 266 | } |
| 267 | |
| 268 | if (sr & CCSR_DMA_SR_EOLSI) { |
| 269 | sr2 |= CCSR_DMA_SR_EOLSI; |
| 270 | ret = IRQ_HANDLED; |
| 271 | } |
| 272 | |
| 273 | /* Clear the bits that we set */ |
| 274 | if (sr2) |
| 275 | out_be32(&dma_channel->sr, sr2); |
| 276 | |
| 277 | return ret; |
| 278 | } |
| 279 | |
| 280 | /** |
| 281 | * fsl_dma_new: initialize this PCM driver. |
| 282 | * |
| 283 | * This function is called when the codec driver calls snd_soc_new_pcms(), |
Mark Brown | 8750654 | 2008-11-18 20:50:34 +0000 | [diff] [blame] | 284 | * once for each .dai_link in the machine driver's snd_soc_card |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 285 | * structure. |
Timur Tabi | 1a3c5a4 | 2010-08-02 12:44:36 -0500 | [diff] [blame^] | 286 | * |
| 287 | * snd_dma_alloc_pages() is just a front-end to dma_alloc_coherent(), which |
| 288 | * (currently) always allocates the DMA buffer in lowmem, even if GFP_HIGHMEM |
| 289 | * is specified. Therefore, any DMA buffers we allocate will always be in low |
| 290 | * memory, but we support for 36-bit physical addresses anyway. |
| 291 | * |
| 292 | * Regardless of where the memory is actually allocated, since the device can |
| 293 | * technically DMA to any 36-bit address, we do need to set the DMA mask to 36. |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 294 | */ |
Liam Girdwood | 8cf7b2b | 2008-07-07 16:08:00 +0100 | [diff] [blame] | 295 | static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai, |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 296 | struct snd_pcm *pcm) |
| 297 | { |
Timur Tabi | 1a3c5a4 | 2010-08-02 12:44:36 -0500 | [diff] [blame^] | 298 | static u64 fsl_dma_dmamask = DMA_BIT_MASK(36); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 299 | int ret; |
| 300 | |
| 301 | if (!card->dev->dma_mask) |
| 302 | card->dev->dma_mask = &fsl_dma_dmamask; |
| 303 | |
| 304 | if (!card->dev->coherent_dma_mask) |
| 305 | card->dev->coherent_dma_mask = fsl_dma_dmamask; |
| 306 | |
Anton Vorontsov | 5c15a68 | 2009-04-04 22:33:19 +0400 | [diff] [blame] | 307 | ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 308 | fsl_dma_hardware.buffer_bytes_max, |
| 309 | &pcm->streams[0].substream->dma_buffer); |
| 310 | if (ret) { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 311 | dev_err(card->dev, "can't allocate playback dma buffer\n"); |
| 312 | return ret; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 313 | } |
| 314 | |
Anton Vorontsov | 5c15a68 | 2009-04-04 22:33:19 +0400 | [diff] [blame] | 315 | ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev, |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 316 | fsl_dma_hardware.buffer_bytes_max, |
| 317 | &pcm->streams[1].substream->dma_buffer); |
| 318 | if (ret) { |
| 319 | snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer); |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 320 | dev_err(card->dev, "can't allocate capture dma buffer\n"); |
| 321 | return ret; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 322 | } |
| 323 | |
| 324 | return 0; |
| 325 | } |
| 326 | |
| 327 | /** |
| 328 | * fsl_dma_open: open a new substream. |
| 329 | * |
| 330 | * Each substream has its own DMA buffer. |
Timur Tabi | bf9c8c9 | 2008-08-01 14:58:44 -0500 | [diff] [blame] | 331 | * |
| 332 | * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link |
| 333 | * descriptors that ping-pong from one period to the next. For example, if |
| 334 | * there are six periods and two link descriptors, this is how they look |
| 335 | * before playback starts: |
| 336 | * |
| 337 | * The last link descriptor |
| 338 | * ____________ points back to the first |
| 339 | * | | |
| 340 | * V | |
| 341 | * ___ ___ | |
| 342 | * | |->| |->| |
| 343 | * |___| |___| |
| 344 | * | | |
| 345 | * | | |
| 346 | * V V |
| 347 | * _________________________________________ |
| 348 | * | | | | | | | The DMA buffer is |
| 349 | * | | | | | | | divided into 6 parts |
| 350 | * |______|______|______|______|______|______| |
| 351 | * |
| 352 | * and here's how they look after the first period is finished playing: |
| 353 | * |
| 354 | * ____________ |
| 355 | * | | |
| 356 | * V | |
| 357 | * ___ ___ | |
| 358 | * | |->| |->| |
| 359 | * |___| |___| |
| 360 | * | | |
| 361 | * |______________ |
| 362 | * | | |
| 363 | * V V |
| 364 | * _________________________________________ |
| 365 | * | | | | | | | |
| 366 | * | | | | | | | |
| 367 | * |______|______|______|______|______|______| |
| 368 | * |
| 369 | * The first link descriptor now points to the third period. The DMA |
| 370 | * controller is currently playing the second period. When it finishes, it |
| 371 | * will jump back to the first descriptor and play the third period. |
| 372 | * |
| 373 | * There are four reasons we do this: |
| 374 | * |
| 375 | * 1. The only way to get the DMA controller to automatically restart the |
| 376 | * transfer when it gets to the end of the buffer is to use chaining |
| 377 | * mode. Basic direct mode doesn't offer that feature. |
| 378 | * 2. We need to receive an interrupt at the end of every period. The DMA |
| 379 | * controller can generate an interrupt at the end of every link transfer |
| 380 | * (aka segment). Making each period into a DMA segment will give us the |
| 381 | * interrupts we need. |
| 382 | * 3. By creating only two link descriptors, regardless of the number of |
| 383 | * periods, we do not need to reallocate the link descriptors if the |
| 384 | * number of periods changes. |
| 385 | * 4. All of the audio data is still stored in a single, contiguous DMA |
| 386 | * buffer, which is what ALSA expects. We're just dividing it into |
| 387 | * contiguous parts, and creating a link descriptor for each one. |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 388 | */ |
| 389 | static int fsl_dma_open(struct snd_pcm_substream *substream) |
| 390 | { |
| 391 | struct snd_pcm_runtime *runtime = substream->runtime; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 392 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 393 | struct device *dev = rtd->platform->dev; |
| 394 | struct dma_object *dma = |
| 395 | container_of(rtd->platform->driver, struct dma_object, dai); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 396 | struct fsl_dma_private *dma_private; |
Timur Tabi | bf9c8c9 | 2008-08-01 14:58:44 -0500 | [diff] [blame] | 397 | struct ccsr_dma_channel __iomem *dma_channel; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 398 | dma_addr_t ld_buf_phys; |
Timur Tabi | bf9c8c9 | 2008-08-01 14:58:44 -0500 | [diff] [blame] | 399 | u64 temp_link; /* Pointer to next link descriptor */ |
| 400 | u32 mr; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 401 | unsigned int channel; |
| 402 | int ret = 0; |
Timur Tabi | bf9c8c9 | 2008-08-01 14:58:44 -0500 | [diff] [blame] | 403 | unsigned int i; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 404 | |
| 405 | /* |
| 406 | * Reject any DMA buffer whose size is not a multiple of the period |
| 407 | * size. We need to make sure that the DMA buffer can be evenly divided |
| 408 | * into periods. |
| 409 | */ |
| 410 | ret = snd_pcm_hw_constraint_integer(runtime, |
| 411 | SNDRV_PCM_HW_PARAM_PERIODS); |
| 412 | if (ret < 0) { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 413 | dev_err(dev, "invalid buffer size\n"); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 414 | return ret; |
| 415 | } |
| 416 | |
| 417 | channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1; |
| 418 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 419 | if (dma->assigned) { |
| 420 | dev_err(dev, "dma channel already assigned\n"); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 421 | return -EBUSY; |
| 422 | } |
| 423 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 424 | dma_private = dma_alloc_coherent(dev, sizeof(struct fsl_dma_private), |
| 425 | &ld_buf_phys, GFP_KERNEL); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 426 | if (!dma_private) { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 427 | dev_err(dev, "can't allocate dma private data\n"); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 428 | return -ENOMEM; |
| 429 | } |
| 430 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 431 | dma_private->ssi_sxx_phys = dma->ssi_stx_phys; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 432 | else |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 433 | dma_private->ssi_sxx_phys = dma->ssi_srx_phys; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 434 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 435 | dma_private->dma_channel = dma->channel; |
| 436 | dma_private->irq = dma->irq; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 437 | dma_private->substream = substream; |
| 438 | dma_private->ld_buf_phys = ld_buf_phys; |
| 439 | dma_private->dma_buf_phys = substream->dma_buffer.addr; |
| 440 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 441 | ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private); |
| 442 | if (ret) { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 443 | dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 444 | dma_private->irq, ret); |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 445 | dma_free_coherent(dev, sizeof(struct fsl_dma_private), |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 446 | dma_private, dma_private->ld_buf_phys); |
| 447 | return ret; |
| 448 | } |
| 449 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 450 | dma->assigned = 1; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 451 | |
| 452 | snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); |
| 453 | snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); |
| 454 | runtime->private_data = dma_private; |
| 455 | |
Timur Tabi | bf9c8c9 | 2008-08-01 14:58:44 -0500 | [diff] [blame] | 456 | /* Program the fixed DMA controller parameters */ |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 457 | |
Timur Tabi | bf9c8c9 | 2008-08-01 14:58:44 -0500 | [diff] [blame] | 458 | dma_channel = dma_private->dma_channel; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 459 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 460 | temp_link = dma_private->ld_buf_phys + |
| 461 | sizeof(struct fsl_dma_link_descriptor); |
| 462 | |
| 463 | for (i = 0; i < NUM_DMA_LINKS; i++) { |
Timur Tabi | 85ef237 | 2009-02-05 17:56:02 -0600 | [diff] [blame] | 464 | dma_private->link[i].next = cpu_to_be64(temp_link); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 465 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 466 | temp_link += sizeof(struct fsl_dma_link_descriptor); |
| 467 | } |
| 468 | /* The last link descriptor points to the first */ |
| 469 | dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); |
| 470 | |
| 471 | /* Tell the DMA controller where the first link descriptor is */ |
| 472 | out_be32(&dma_channel->clndar, |
| 473 | CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); |
| 474 | out_be32(&dma_channel->eclndar, |
| 475 | CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); |
| 476 | |
| 477 | /* The manual says the BCR must be clear before enabling EMP */ |
| 478 | out_be32(&dma_channel->bcr, 0); |
| 479 | |
| 480 | /* |
| 481 | * Program the mode register for interrupts, external master control, |
| 482 | * and source/destination hold. Also clear the Channel Abort bit. |
| 483 | */ |
| 484 | mr = in_be32(&dma_channel->mr) & |
| 485 | ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); |
| 486 | |
| 487 | /* |
| 488 | * We want External Master Start and External Master Pause enabled, |
| 489 | * because the SSI is controlling the DMA controller. We want the DMA |
| 490 | * controller to be set up in advance, and then we signal only the SSI |
Timur Tabi | bf9c8c9 | 2008-08-01 14:58:44 -0500 | [diff] [blame] | 491 | * to start transferring. |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 492 | * |
| 493 | * We want End-Of-Segment Interrupts enabled, because this will generate |
| 494 | * an interrupt at the end of each segment (each link descriptor |
| 495 | * represents one segment). Each DMA segment is the same thing as an |
| 496 | * ALSA period, so this is how we get an interrupt at the end of every |
| 497 | * period. |
| 498 | * |
| 499 | * We want Error Interrupt enabled, so that we can get an error if |
| 500 | * the DMA controller is mis-programmed somehow. |
| 501 | */ |
| 502 | mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | |
| 503 | CCSR_DMA_MR_EMS_EN; |
| 504 | |
| 505 | /* For playback, we want the destination address to be held. For |
| 506 | capture, set the source address to be held. */ |
| 507 | mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? |
| 508 | CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; |
| 509 | |
| 510 | out_be32(&dma_channel->mr, mr); |
| 511 | |
| 512 | return 0; |
| 513 | } |
| 514 | |
| 515 | /** |
Timur Tabi | bf9c8c9 | 2008-08-01 14:58:44 -0500 | [diff] [blame] | 516 | * fsl_dma_hw_params: continue initializing the DMA links |
| 517 | * |
| 518 | * This function obtains hardware parameters about the opened stream and |
| 519 | * programs the DMA controller accordingly. |
| 520 | * |
Timur Tabi | 85ef237 | 2009-02-05 17:56:02 -0600 | [diff] [blame] | 521 | * One drawback of big-endian is that when copying integers of different |
| 522 | * sizes to a fixed-sized register, the address to which the integer must be |
| 523 | * copied is dependent on the size of the integer. |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 524 | * |
| 525 | * For example, if P is the address of a 32-bit register, and X is a 32-bit |
| 526 | * integer, then X should be copied to address P. However, if X is a 16-bit |
| 527 | * integer, then it should be copied to P+2. If X is an 8-bit register, |
| 528 | * then it should be copied to P+3. |
| 529 | * |
| 530 | * So for playback of 8-bit samples, the DMA controller must transfer single |
| 531 | * bytes from the DMA buffer to the last byte of the STX0 register, i.e. |
| 532 | * offset by 3 bytes. For 16-bit samples, the offset is two bytes. |
| 533 | * |
| 534 | * For 24-bit samples, the offset is 1 byte. However, the DMA controller |
| 535 | * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4, |
| 536 | * and 8 bytes at a time). So we do not support packed 24-bit samples. |
| 537 | * 24-bit data must be padded to 32 bits. |
| 538 | */ |
Timur Tabi | 85ef237 | 2009-02-05 17:56:02 -0600 | [diff] [blame] | 539 | static int fsl_dma_hw_params(struct snd_pcm_substream *substream, |
| 540 | struct snd_pcm_hw_params *hw_params) |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 541 | { |
| 542 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 543 | struct fsl_dma_private *dma_private = runtime->private_data; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 544 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 545 | struct device *dev = rtd->platform->dev; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 546 | |
Timur Tabi | 85ef237 | 2009-02-05 17:56:02 -0600 | [diff] [blame] | 547 | /* Number of bits per sample */ |
| 548 | unsigned int sample_size = |
| 549 | snd_pcm_format_physical_width(params_format(hw_params)); |
| 550 | |
| 551 | /* Number of bytes per frame */ |
| 552 | unsigned int frame_size = 2 * (sample_size / 8); |
| 553 | |
| 554 | /* Bus address of SSI STX register */ |
| 555 | dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys; |
| 556 | |
| 557 | /* Size of the DMA buffer, in bytes */ |
| 558 | size_t buffer_size = params_buffer_bytes(hw_params); |
| 559 | |
| 560 | /* Number of bytes per period */ |
| 561 | size_t period_size = params_period_bytes(hw_params); |
| 562 | |
| 563 | /* Pointer to next period */ |
| 564 | dma_addr_t temp_addr = substream->dma_buffer.addr; |
| 565 | |
| 566 | /* Pointer to DMA controller */ |
| 567 | struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; |
| 568 | |
| 569 | u32 mr; /* DMA Mode Register */ |
| 570 | |
| 571 | unsigned int i; |
| 572 | |
| 573 | /* Initialize our DMA tracking variables */ |
| 574 | dma_private->period_size = period_size; |
| 575 | dma_private->num_periods = params_periods(hw_params); |
| 576 | dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size; |
| 577 | dma_private->dma_buf_next = dma_private->dma_buf_phys + |
| 578 | (NUM_DMA_LINKS * period_size); |
| 579 | |
| 580 | if (dma_private->dma_buf_next >= dma_private->dma_buf_end) |
| 581 | /* This happens if the number of periods == NUM_DMA_LINKS */ |
| 582 | dma_private->dma_buf_next = dma_private->dma_buf_phys; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 583 | |
| 584 | mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | |
| 585 | CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK); |
| 586 | |
Timur Tabi | 85ef237 | 2009-02-05 17:56:02 -0600 | [diff] [blame] | 587 | /* Due to a quirk of the SSI's STX register, the target address |
| 588 | * for the DMA operations depends on the sample size. So we calculate |
| 589 | * that offset here. While we're at it, also tell the DMA controller |
| 590 | * how much data to transfer per sample. |
| 591 | */ |
| 592 | switch (sample_size) { |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 593 | case 8: |
| 594 | mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; |
| 595 | ssi_sxx_phys += 3; |
| 596 | break; |
| 597 | case 16: |
| 598 | mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; |
| 599 | ssi_sxx_phys += 2; |
| 600 | break; |
| 601 | case 32: |
| 602 | mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; |
| 603 | break; |
| 604 | default: |
Timur Tabi | 85ef237 | 2009-02-05 17:56:02 -0600 | [diff] [blame] | 605 | /* We should never get here */ |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 606 | dev_err(dev, "unsupported sample size %u\n", sample_size); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 607 | return -EINVAL; |
| 608 | } |
| 609 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 610 | /* |
| 611 | * BWC should always be a multiple of the frame size. BWC determines |
| 612 | * how many bytes are sent/received before the DMA controller checks the |
| 613 | * SSI to see if it needs to stop. For playback, the transmit FIFO can |
| 614 | * hold three frames, so we want to send two frames at a time. For |
| 615 | * capture, the receive FIFO is triggered when it contains one frame, so |
| 616 | * we want to receive one frame at a time. |
| 617 | */ |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 618 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 619 | mr |= CCSR_DMA_MR_BWC(2 * frame_size); |
| 620 | else |
| 621 | mr |= CCSR_DMA_MR_BWC(frame_size); |
| 622 | |
| 623 | out_be32(&dma_channel->mr, mr); |
| 624 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 625 | for (i = 0; i < NUM_DMA_LINKS; i++) { |
| 626 | struct fsl_dma_link_descriptor *link = &dma_private->link[i]; |
| 627 | |
Timur Tabi | 85ef237 | 2009-02-05 17:56:02 -0600 | [diff] [blame] | 628 | link->count = cpu_to_be32(period_size); |
| 629 | |
Timur Tabi | 1a3c5a4 | 2010-08-02 12:44:36 -0500 | [diff] [blame^] | 630 | /* The snoop bit tells the DMA controller whether it should tell |
Timur Tabi | 85ef237 | 2009-02-05 17:56:02 -0600 | [diff] [blame] | 631 | * the ECM to snoop during a read or write to an address. For |
| 632 | * audio, we use DMA to transfer data between memory and an I/O |
| 633 | * device (the SSI's STX0 or SRX0 register). Snooping is only |
| 634 | * needed if there is a cache, so we need to snoop memory |
| 635 | * addresses only. For playback, that means we snoop the source |
| 636 | * but not the destination. For capture, we snoop the |
| 637 | * destination but not the source. |
| 638 | * |
| 639 | * Note that failing to snoop properly is unlikely to cause |
| 640 | * cache incoherency if the period size is larger than the |
| 641 | * size of L1 cache. This is because filling in one period will |
| 642 | * flush out the data for the previous period. So if you |
| 643 | * increased period_bytes_min to a large enough size, you might |
| 644 | * get more performance by not snooping, and you'll still be |
Timur Tabi | 1a3c5a4 | 2010-08-02 12:44:36 -0500 | [diff] [blame^] | 645 | * okay. You'll need to update fsl_dma_update_pointers() also. |
Timur Tabi | 85ef237 | 2009-02-05 17:56:02 -0600 | [diff] [blame] | 646 | */ |
| 647 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 648 | link->source_addr = cpu_to_be32(temp_addr); |
Timur Tabi | 1a3c5a4 | 2010-08-02 12:44:36 -0500 | [diff] [blame^] | 649 | link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | |
| 650 | upper_32_bits(temp_addr)); |
Timur Tabi | 85ef237 | 2009-02-05 17:56:02 -0600 | [diff] [blame] | 651 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 652 | link->dest_addr = cpu_to_be32(ssi_sxx_phys); |
Timur Tabi | 1a3c5a4 | 2010-08-02 12:44:36 -0500 | [diff] [blame^] | 653 | link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | |
| 654 | upper_32_bits(ssi_sxx_phys)); |
Timur Tabi | 85ef237 | 2009-02-05 17:56:02 -0600 | [diff] [blame] | 655 | } else { |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 656 | link->source_addr = cpu_to_be32(ssi_sxx_phys); |
Timur Tabi | 1a3c5a4 | 2010-08-02 12:44:36 -0500 | [diff] [blame^] | 657 | link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP | |
| 658 | upper_32_bits(ssi_sxx_phys)); |
Timur Tabi | 85ef237 | 2009-02-05 17:56:02 -0600 | [diff] [blame] | 659 | |
| 660 | link->dest_addr = cpu_to_be32(temp_addr); |
Timur Tabi | 1a3c5a4 | 2010-08-02 12:44:36 -0500 | [diff] [blame^] | 661 | link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP | |
| 662 | upper_32_bits(temp_addr)); |
Timur Tabi | 85ef237 | 2009-02-05 17:56:02 -0600 | [diff] [blame] | 663 | } |
| 664 | |
| 665 | temp_addr += period_size; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 666 | } |
| 667 | |
| 668 | return 0; |
| 669 | } |
| 670 | |
| 671 | /** |
| 672 | * fsl_dma_pointer: determine the current position of the DMA transfer |
| 673 | * |
| 674 | * This function is called by ALSA when ALSA wants to know where in the |
| 675 | * stream buffer the hardware currently is. |
| 676 | * |
| 677 | * For playback, the SAR register contains the physical address of the most |
| 678 | * recent DMA transfer. For capture, the value is in the DAR register. |
| 679 | * |
| 680 | * The base address of the buffer is stored in the source_addr field of the |
| 681 | * first link descriptor. |
| 682 | */ |
| 683 | static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream) |
| 684 | { |
| 685 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 686 | struct fsl_dma_private *dma_private = runtime->private_data; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 687 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 688 | struct device *dev = rtd->platform->dev; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 689 | struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; |
| 690 | dma_addr_t position; |
| 691 | snd_pcm_uframes_t frames; |
| 692 | |
Timur Tabi | 1a3c5a4 | 2010-08-02 12:44:36 -0500 | [diff] [blame^] | 693 | /* Obtain the current DMA pointer, but don't read the ESAD bits if we |
| 694 | * only have 32-bit DMA addresses. This function is typically called |
| 695 | * in interrupt context, so we need to optimize it. |
| 696 | */ |
| 697 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 698 | position = in_be32(&dma_channel->sar); |
Timur Tabi | 1a3c5a4 | 2010-08-02 12:44:36 -0500 | [diff] [blame^] | 699 | #ifdef CONFIG_PHYS_64BIT |
| 700 | position |= (u64)(in_be32(&dma_channel->satr) & |
| 701 | CCSR_DMA_ATR_ESAD_MASK) << 32; |
| 702 | #endif |
| 703 | } else { |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 704 | position = in_be32(&dma_channel->dar); |
Timur Tabi | 1a3c5a4 | 2010-08-02 12:44:36 -0500 | [diff] [blame^] | 705 | #ifdef CONFIG_PHYS_64BIT |
| 706 | position |= (u64)(in_be32(&dma_channel->datr) & |
| 707 | CCSR_DMA_ATR_ESAD_MASK) << 32; |
| 708 | #endif |
| 709 | } |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 710 | |
Timur Tabi | a4d11fe | 2009-03-25 18:20:37 -0500 | [diff] [blame] | 711 | /* |
| 712 | * When capture is started, the SSI immediately starts to fill its FIFO. |
| 713 | * This means that the DMA controller is not started until the FIFO is |
| 714 | * full. However, ALSA calls this function before that happens, when |
| 715 | * MR.DAR is still zero. In this case, just return zero to indicate |
| 716 | * that nothing has been received yet. |
| 717 | */ |
| 718 | if (!position) |
| 719 | return 0; |
| 720 | |
| 721 | if ((position < dma_private->dma_buf_phys) || |
| 722 | (position > dma_private->dma_buf_end)) { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 723 | dev_err(dev, "dma pointer is out of range, halting stream\n"); |
Timur Tabi | a4d11fe | 2009-03-25 18:20:37 -0500 | [diff] [blame] | 724 | return SNDRV_PCM_POS_XRUN; |
| 725 | } |
| 726 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 727 | frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys); |
| 728 | |
| 729 | /* |
| 730 | * If the current address is just past the end of the buffer, wrap it |
| 731 | * around. |
| 732 | */ |
| 733 | if (frames == runtime->buffer_size) |
| 734 | frames = 0; |
| 735 | |
| 736 | return frames; |
| 737 | } |
| 738 | |
| 739 | /** |
| 740 | * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params() |
| 741 | * |
| 742 | * Release the resources allocated in fsl_dma_hw_params() and de-program the |
| 743 | * registers. |
| 744 | * |
| 745 | * This function can be called multiple times. |
| 746 | */ |
| 747 | static int fsl_dma_hw_free(struct snd_pcm_substream *substream) |
| 748 | { |
| 749 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 750 | struct fsl_dma_private *dma_private = runtime->private_data; |
| 751 | |
| 752 | if (dma_private) { |
| 753 | struct ccsr_dma_channel __iomem *dma_channel; |
| 754 | |
| 755 | dma_channel = dma_private->dma_channel; |
| 756 | |
| 757 | /* Stop the DMA */ |
| 758 | out_be32(&dma_channel->mr, CCSR_DMA_MR_CA); |
| 759 | out_be32(&dma_channel->mr, 0); |
| 760 | |
| 761 | /* Reset all the other registers */ |
| 762 | out_be32(&dma_channel->sr, -1); |
| 763 | out_be32(&dma_channel->clndar, 0); |
| 764 | out_be32(&dma_channel->eclndar, 0); |
| 765 | out_be32(&dma_channel->satr, 0); |
| 766 | out_be32(&dma_channel->sar, 0); |
| 767 | out_be32(&dma_channel->datr, 0); |
| 768 | out_be32(&dma_channel->dar, 0); |
| 769 | out_be32(&dma_channel->bcr, 0); |
| 770 | out_be32(&dma_channel->nlndar, 0); |
| 771 | out_be32(&dma_channel->enlndar, 0); |
| 772 | } |
| 773 | |
| 774 | return 0; |
| 775 | } |
| 776 | |
| 777 | /** |
| 778 | * fsl_dma_close: close the stream. |
| 779 | */ |
| 780 | static int fsl_dma_close(struct snd_pcm_substream *substream) |
| 781 | { |
| 782 | struct snd_pcm_runtime *runtime = substream->runtime; |
| 783 | struct fsl_dma_private *dma_private = runtime->private_data; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 784 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 785 | struct device *dev = rtd->platform->dev; |
| 786 | struct dma_object *dma = |
| 787 | container_of(rtd->platform->driver, struct dma_object, dai); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 788 | |
| 789 | if (dma_private) { |
| 790 | if (dma_private->irq) |
| 791 | free_irq(dma_private->irq, dma_private); |
| 792 | |
| 793 | if (dma_private->ld_buf_phys) { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 794 | dma_unmap_single(dev, dma_private->ld_buf_phys, |
| 795 | sizeof(dma_private->link), |
| 796 | DMA_TO_DEVICE); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 797 | } |
| 798 | |
| 799 | /* Deallocate the fsl_dma_private structure */ |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 800 | dma_free_coherent(dev, sizeof(struct fsl_dma_private), |
| 801 | dma_private, dma_private->ld_buf_phys); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 802 | substream->runtime->private_data = NULL; |
| 803 | } |
| 804 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 805 | dma->assigned = 0; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 806 | |
| 807 | return 0; |
| 808 | } |
| 809 | |
| 810 | /* |
| 811 | * Remove this PCM driver. |
| 812 | */ |
| 813 | static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm) |
| 814 | { |
| 815 | struct snd_pcm_substream *substream; |
| 816 | unsigned int i; |
| 817 | |
| 818 | for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { |
| 819 | substream = pcm->streams[i].substream; |
| 820 | if (substream) { |
| 821 | snd_dma_free_pages(&substream->dma_buffer); |
| 822 | substream->dma_buffer.area = NULL; |
| 823 | substream->dma_buffer.addr = 0; |
| 824 | } |
| 825 | } |
| 826 | } |
| 827 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 828 | /* List of DMA nodes that we've probed */ |
| 829 | static LIST_HEAD(dma_list); |
| 830 | |
| 831 | /** |
| 832 | * find_ssi_node -- returns the SSI node that points to his DMA channel node |
| 833 | * |
| 834 | * Although this DMA driver attempts to operate independently of the other |
| 835 | * devices, it still needs to determine some information about the SSI device |
| 836 | * that it's working with. Unfortunately, the device tree does not contain |
| 837 | * a pointer from the DMA channel node to the SSI node -- the pointer goes the |
| 838 | * other way. So we need to scan the device tree for SSI nodes until we find |
| 839 | * the one that points to the given DMA channel node. It's ugly, but at least |
| 840 | * it's contained in this one function. |
| 841 | */ |
| 842 | static struct device_node *find_ssi_node(struct device_node *dma_channel_np) |
| 843 | { |
| 844 | struct device_node *ssi_np, *np; |
| 845 | |
| 846 | for_each_compatible_node(ssi_np, NULL, "fsl,mpc8610-ssi") { |
| 847 | /* Check each DMA phandle to see if it points to us. We |
| 848 | * assume that device_node pointers are a valid comparison. |
| 849 | */ |
| 850 | np = of_parse_phandle(ssi_np, "fsl,playback-dma", 0); |
| 851 | if (np == dma_channel_np) |
| 852 | return ssi_np; |
| 853 | |
| 854 | np = of_parse_phandle(ssi_np, "fsl,capture-dma", 0); |
| 855 | if (np == dma_channel_np) |
| 856 | return ssi_np; |
| 857 | } |
| 858 | |
| 859 | return NULL; |
| 860 | } |
| 861 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 862 | static struct snd_pcm_ops fsl_dma_ops = { |
| 863 | .open = fsl_dma_open, |
| 864 | .close = fsl_dma_close, |
| 865 | .ioctl = snd_pcm_lib_ioctl, |
| 866 | .hw_params = fsl_dma_hw_params, |
| 867 | .hw_free = fsl_dma_hw_free, |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 868 | .pointer = fsl_dma_pointer, |
| 869 | }; |
| 870 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 871 | static int __devinit fsl_soc_dma_probe(struct of_device *of_dev, |
| 872 | const struct of_device_id *match) |
| 873 | { |
| 874 | struct dma_object *dma; |
| 875 | struct device_node *np = of_dev->dev.of_node; |
| 876 | struct device_node *ssi_np; |
| 877 | struct resource res; |
| 878 | int ret; |
| 879 | |
| 880 | /* Find the SSI node that points to us. */ |
| 881 | ssi_np = find_ssi_node(np); |
| 882 | if (!ssi_np) { |
| 883 | dev_err(&of_dev->dev, "cannot find parent SSI node\n"); |
| 884 | return -ENODEV; |
| 885 | } |
| 886 | |
| 887 | ret = of_address_to_resource(ssi_np, 0, &res); |
| 888 | of_node_put(ssi_np); |
| 889 | if (ret) { |
| 890 | dev_err(&of_dev->dev, "could not determine device resources\n"); |
| 891 | return ret; |
| 892 | } |
| 893 | |
| 894 | dma = kzalloc(sizeof(*dma) + strlen(np->full_name), GFP_KERNEL); |
| 895 | if (!dma) { |
| 896 | dev_err(&of_dev->dev, "could not allocate dma object\n"); |
| 897 | return -ENOMEM; |
| 898 | } |
| 899 | |
| 900 | strcpy(dma->path, np->full_name); |
| 901 | dma->dai.ops = &fsl_dma_ops; |
| 902 | dma->dai.pcm_new = fsl_dma_new; |
| 903 | dma->dai.pcm_free = fsl_dma_free_dma_buffers; |
| 904 | |
| 905 | /* Store the SSI-specific information that we need */ |
| 906 | dma->ssi_stx_phys = res.start + offsetof(struct ccsr_ssi, stx0); |
| 907 | dma->ssi_srx_phys = res.start + offsetof(struct ccsr_ssi, srx0); |
| 908 | |
| 909 | ret = snd_soc_register_platform(&of_dev->dev, &dma->dai); |
| 910 | if (ret) { |
| 911 | dev_err(&of_dev->dev, "could not register platform\n"); |
| 912 | kfree(dma); |
| 913 | return ret; |
| 914 | } |
| 915 | |
| 916 | dma->channel = of_iomap(np, 0); |
| 917 | dma->irq = irq_of_parse_and_map(np, 0); |
| 918 | list_add(&dma->list, &dma_list); |
| 919 | |
| 920 | return 0; |
| 921 | } |
| 922 | |
| 923 | static int __devexit fsl_soc_dma_remove(struct of_device *of_dev) |
| 924 | { |
| 925 | struct list_head *n, *ptr; |
| 926 | struct dma_object *dma; |
| 927 | |
| 928 | list_for_each_safe(ptr, n, &dma_list) { |
| 929 | dma = list_entry(ptr, struct dma_object, list); |
| 930 | list_del_init(ptr); |
| 931 | |
| 932 | snd_soc_unregister_platform(&of_dev->dev); |
| 933 | iounmap(dma->channel); |
| 934 | irq_dispose_mapping(dma->irq); |
| 935 | kfree(dma); |
| 936 | } |
| 937 | |
| 938 | return 0; |
| 939 | } |
| 940 | |
| 941 | static const struct of_device_id fsl_soc_dma_ids[] = { |
| 942 | { .compatible = "fsl,ssi-dma-channel", }, |
| 943 | {} |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 944 | }; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 945 | MODULE_DEVICE_TABLE(of, fsl_soc_dma_ids); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 946 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 947 | static struct of_platform_driver fsl_soc_dma_driver = { |
| 948 | .driver = { |
| 949 | .name = "fsl-pcm-audio", |
| 950 | .owner = THIS_MODULE, |
| 951 | .of_match_table = fsl_soc_dma_ids, |
| 952 | }, |
| 953 | .probe = fsl_soc_dma_probe, |
| 954 | .remove = __devexit_p(fsl_soc_dma_remove), |
| 955 | }; |
| 956 | |
| 957 | static int __init fsl_soc_dma_init(void) |
| 958 | { |
| 959 | pr_info("Freescale Elo DMA ASoC PCM Driver\n"); |
| 960 | |
| 961 | return of_register_platform_driver(&fsl_soc_dma_driver); |
| 962 | } |
| 963 | |
| 964 | static void __exit fsl_soc_dma_exit(void) |
| 965 | { |
| 966 | of_unregister_platform_driver(&fsl_soc_dma_driver); |
| 967 | } |
| 968 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 969 | module_init(fsl_soc_dma_init); |
| 970 | module_exit(fsl_soc_dma_exit); |
Mark Brown | 958e792 | 2008-12-03 19:58:17 +0000 | [diff] [blame] | 971 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 972 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 973 | MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM Driver"); |
| 974 | MODULE_LICENSE("GPL v2"); |