Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 1 | /* |
| 2 | * hdmi.c |
| 3 | * |
| 4 | * HDMI interface DSS driver setting for TI's OMAP4 family of processor. |
| 5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ |
| 6 | * Authors: Yong Zhi |
| 7 | * Mythri pk <mythripk@ti.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License version 2 as published by |
| 11 | * the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 16 | * more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License along with |
| 19 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 20 | */ |
| 21 | |
| 22 | #define DSS_SUBSYS_NAME "HDMI" |
| 23 | |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/io.h> |
| 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/mutex.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/string.h> |
Tomi Valkeinen | 24e6289 | 2011-05-23 11:51:18 +0300 | [diff] [blame] | 32 | #include <linux/platform_device.h> |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 33 | #include <linux/pm_runtime.h> |
| 34 | #include <linux/clk.h> |
Tomi Valkeinen | a0b38cc | 2011-05-11 14:05:07 +0300 | [diff] [blame] | 35 | #include <video/omapdss.h> |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 36 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
| 37 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) |
| 38 | #include <sound/soc.h> |
| 39 | #include <sound/pcm_params.h> |
Mythri P K | 7334167 | 2011-09-08 19:06:24 +0530 | [diff] [blame] | 40 | #include "ti_hdmi_4xxx_ip.h" |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 41 | #endif |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 42 | |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 43 | #include "ti_hdmi.h" |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 44 | #include "dss.h" |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 45 | #include "dss_features.h" |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 46 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 47 | #define HDMI_WP 0x0 |
| 48 | #define HDMI_CORE_SYS 0x400 |
| 49 | #define HDMI_CORE_AV 0x900 |
| 50 | #define HDMI_PLLCTRL 0x200 |
| 51 | #define HDMI_PHY 0x300 |
| 52 | |
Mythri P K | 7c1f1ec | 2011-09-08 19:06:22 +0530 | [diff] [blame] | 53 | /* HDMI EDID Length move this */ |
| 54 | #define HDMI_EDID_MAX_LENGTH 256 |
| 55 | #define EDID_TIMING_DESCRIPTOR_SIZE 0x12 |
| 56 | #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 |
| 57 | #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 |
| 58 | #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 |
| 59 | #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 |
| 60 | |
| 61 | #define OMAP_HDMI_TIMINGS_NB 34 |
| 62 | |
Tomi Valkeinen | b44e458 | 2011-08-22 13:16:24 +0300 | [diff] [blame] | 63 | #define HDMI_DEFAULT_REGN 16 |
Tomi Valkeinen | 8d88767a | 2011-08-22 13:02:52 +0300 | [diff] [blame] | 64 | #define HDMI_DEFAULT_REGM2 1 |
| 65 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 66 | static struct { |
| 67 | struct mutex lock; |
| 68 | struct omap_display_platform_data *pdata; |
| 69 | struct platform_device *pdev; |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 70 | struct hdmi_ip_data ip_data; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 71 | int code; |
| 72 | int mode; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 73 | |
| 74 | struct clk *sys_clk; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 75 | } hdmi; |
| 76 | |
| 77 | /* |
| 78 | * Logic for the below structure : |
| 79 | * user enters the CEA or VESA timings by specifying the HDMI/DVI code. |
| 80 | * There is a correspondence between CEA/VESA timing and code, please |
| 81 | * refer to section 6.3 in HDMI 1.3 specification for timing code. |
| 82 | * |
| 83 | * In the below structure, cea_vesa_timings corresponds to all OMAP4 |
| 84 | * supported CEA and VESA timing values.code_cea corresponds to the CEA |
| 85 | * code, It is used to get the timing from cea_vesa_timing array.Similarly |
| 86 | * with code_vesa. Code_index is used for back mapping, that is once EDID |
| 87 | * is read from the TV, EDID is parsed to find the timing values and then |
| 88 | * map it to corresponding CEA or VESA index. |
| 89 | */ |
| 90 | |
| 91 | static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = { |
| 92 | { {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0}, |
| 93 | { {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1}, |
| 94 | { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}, |
| 95 | { {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0}, |
| 96 | { {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0}, |
| 97 | { {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0}, |
| 98 | { {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0}, |
| 99 | { {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1}, |
| 100 | { {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1}, |
| 101 | { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1}, |
| 102 | { {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0}, |
| 103 | { {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0}, |
| 104 | { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1}, |
| 105 | { {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0}, |
| 106 | { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1}, |
| 107 | /* VESA From Here */ |
| 108 | { {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0}, |
| 109 | { {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1}, |
| 110 | { {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1}, |
| 111 | { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0}, |
| 112 | { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0}, |
| 113 | { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1}, |
| 114 | { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1}, |
| 115 | { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1}, |
| 116 | { {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0}, |
| 117 | { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0}, |
| 118 | { {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0}, |
| 119 | { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0}, |
| 120 | { {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1}, |
| 121 | { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1}, |
| 122 | { {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1}, |
| 123 | { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1}, |
| 124 | { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1}, |
| 125 | { {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1}, |
| 126 | { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1} |
| 127 | }; |
| 128 | |
| 129 | /* |
| 130 | * This is a static mapping array which maps the timing values |
| 131 | * with corresponding CEA / VESA code |
| 132 | */ |
| 133 | static const int code_index[OMAP_HDMI_TIMINGS_NB] = { |
| 134 | 1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32, |
| 135 | /* <--15 CEA 17--> vesa*/ |
| 136 | 4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A, |
| 137 | 0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B |
| 138 | }; |
| 139 | |
| 140 | /* |
| 141 | * This is reverse static mapping which maps the CEA / VESA code |
| 142 | * to the corresponding timing values |
| 143 | */ |
| 144 | static const int code_cea[39] = { |
| 145 | -1, 0, 3, 3, 2, 8, 5, 5, -1, -1, |
| 146 | -1, -1, -1, -1, -1, -1, 9, 10, 10, 1, |
| 147 | 7, 6, 6, -1, -1, -1, -1, -1, -1, 11, |
| 148 | 11, 12, 14, -1, -1, 13, 13, 4, 4 |
| 149 | }; |
| 150 | |
| 151 | static const int code_vesa[85] = { |
| 152 | -1, -1, -1, -1, 15, -1, -1, -1, -1, 16, |
| 153 | -1, -1, -1, -1, 17, -1, 23, -1, -1, -1, |
| 154 | -1, -1, 29, 18, -1, -1, -1, 32, 19, -1, |
| 155 | -1, -1, 21, -1, -1, 22, -1, -1, -1, 20, |
| 156 | -1, 30, 24, -1, -1, -1, -1, 25, -1, -1, |
| 157 | -1, -1, -1, -1, -1, -1, -1, 31, 26, -1, |
| 158 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 159 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 160 | -1, 27, 28, -1, 33}; |
| 161 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 162 | static int hdmi_runtime_get(void) |
| 163 | { |
| 164 | int r; |
| 165 | |
| 166 | DSSDBG("hdmi_runtime_get\n"); |
| 167 | |
| 168 | r = pm_runtime_get_sync(&hdmi.pdev->dev); |
| 169 | WARN_ON(r < 0); |
| 170 | return r < 0 ? r : 0; |
| 171 | } |
| 172 | |
| 173 | static void hdmi_runtime_put(void) |
| 174 | { |
| 175 | int r; |
| 176 | |
| 177 | DSSDBG("hdmi_runtime_put\n"); |
| 178 | |
Tomi Valkeinen | 0eaf9f5 | 2012-01-23 13:23:08 +0200 | [diff] [blame] | 179 | r = pm_runtime_put_sync(&hdmi.pdev->dev); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 180 | WARN_ON(r < 0); |
| 181 | } |
| 182 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 183 | int hdmi_init_display(struct omap_dss_device *dssdev) |
| 184 | { |
| 185 | DSSDBG("init_display\n"); |
| 186 | |
Mythri P K | 60634a2 | 2011-09-08 19:06:26 +0530 | [diff] [blame] | 187 | dss_init_hdmi_ip_ops(&hdmi.ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 188 | return 0; |
| 189 | } |
| 190 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 191 | static int get_timings_index(void) |
| 192 | { |
| 193 | int code; |
| 194 | |
| 195 | if (hdmi.mode == 0) |
| 196 | code = code_vesa[hdmi.code]; |
| 197 | else |
| 198 | code = code_cea[hdmi.code]; |
| 199 | |
| 200 | if (code == -1) { |
| 201 | /* HDMI code 4 corresponds to 640 * 480 VGA */ |
| 202 | hdmi.code = 4; |
| 203 | /* DVI mode 1 corresponds to HDMI 0 to DVI */ |
| 204 | hdmi.mode = HDMI_DVI; |
| 205 | |
| 206 | code = code_vesa[hdmi.code]; |
| 207 | } |
| 208 | return code; |
| 209 | } |
| 210 | |
| 211 | static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) |
| 212 | { |
| 213 | int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0; |
| 214 | int timing_vsync = 0, timing_hsync = 0; |
Mythri P K | 38863b7 | 2011-09-08 19:06:20 +0530 | [diff] [blame] | 215 | struct hdmi_video_timings temp; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 216 | struct hdmi_cm cm = {-1}; |
| 217 | DSSDBG("hdmi_get_code\n"); |
| 218 | |
| 219 | for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) { |
| 220 | temp = cea_vesa_timings[i].timings; |
| 221 | if ((temp.pixel_clock == timing->pixel_clock) && |
| 222 | (temp.x_res == timing->x_res) && |
| 223 | (temp.y_res == timing->y_res)) { |
| 224 | |
| 225 | temp_hsync = temp.hfp + temp.hsw + temp.hbp; |
| 226 | timing_hsync = timing->hfp + timing->hsw + timing->hbp; |
| 227 | temp_vsync = temp.vfp + temp.vsw + temp.vbp; |
| 228 | timing_vsync = timing->vfp + timing->vsw + timing->vbp; |
| 229 | |
| 230 | DSSDBG("temp_hsync = %d , temp_vsync = %d" |
| 231 | "timing_hsync = %d, timing_vsync = %d\n", |
| 232 | temp_hsync, temp_hsync, |
| 233 | timing_hsync, timing_vsync); |
| 234 | |
| 235 | if ((temp_hsync == timing_hsync) && |
| 236 | (temp_vsync == timing_vsync)) { |
| 237 | code = i; |
| 238 | cm.code = code_index[i]; |
| 239 | if (code < 14) |
| 240 | cm.mode = HDMI_HDMI; |
| 241 | else |
| 242 | cm.mode = HDMI_DVI; |
| 243 | DSSDBG("Hdmi_code = %d mode = %d\n", |
| 244 | cm.code, cm.mode); |
| 245 | break; |
| 246 | } |
| 247 | } |
| 248 | } |
| 249 | |
| 250 | return cm; |
| 251 | } |
| 252 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 253 | static void update_hdmi_timings(struct hdmi_config *cfg, |
| 254 | struct omap_video_timings *timings, int code) |
| 255 | { |
| 256 | cfg->timings.timings.x_res = timings->x_res; |
| 257 | cfg->timings.timings.y_res = timings->y_res; |
| 258 | cfg->timings.timings.hbp = timings->hbp; |
| 259 | cfg->timings.timings.hfp = timings->hfp; |
| 260 | cfg->timings.timings.hsw = timings->hsw; |
| 261 | cfg->timings.timings.vbp = timings->vbp; |
| 262 | cfg->timings.timings.vfp = timings->vfp; |
| 263 | cfg->timings.timings.vsw = timings->vsw; |
| 264 | cfg->timings.timings.pixel_clock = timings->pixel_clock; |
| 265 | cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol; |
| 266 | cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol; |
| 267 | } |
| 268 | |
Archit Taneja | c3dc6a7 | 2011-09-13 18:28:41 +0530 | [diff] [blame] | 269 | unsigned long hdmi_get_pixel_clock(void) |
| 270 | { |
| 271 | /* HDMI Pixel Clock in Mhz */ |
Tomi Valkeinen | ef319c6 | 2011-10-20 13:36:59 +0300 | [diff] [blame] | 272 | return hdmi.ip_data.cfg.timings.timings.pixel_clock * 1000; |
Archit Taneja | c3dc6a7 | 2011-09-13 18:28:41 +0530 | [diff] [blame] | 273 | } |
| 274 | |
Archit Taneja | 6cb07b2 | 2011-04-12 13:52:25 +0530 | [diff] [blame] | 275 | static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, |
| 276 | struct hdmi_pll_info *pi) |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 277 | { |
Archit Taneja | 6cb07b2 | 2011-04-12 13:52:25 +0530 | [diff] [blame] | 278 | unsigned long clkin, refclk; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 279 | u32 mf; |
| 280 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 281 | clkin = clk_get_rate(hdmi.sys_clk) / 10000; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 282 | /* |
| 283 | * Input clock is predivided by N + 1 |
| 284 | * out put of which is reference clk |
| 285 | */ |
Tomi Valkeinen | 8d88767a | 2011-08-22 13:02:52 +0300 | [diff] [blame] | 286 | if (dssdev->clocks.hdmi.regn == 0) |
| 287 | pi->regn = HDMI_DEFAULT_REGN; |
| 288 | else |
| 289 | pi->regn = dssdev->clocks.hdmi.regn; |
| 290 | |
Tomi Valkeinen | b44e458 | 2011-08-22 13:16:24 +0300 | [diff] [blame] | 291 | refclk = clkin / pi->regn; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 292 | |
| 293 | /* |
| 294 | * multiplier is pixel_clk/ref_clk |
| 295 | * Multiplying by 100 to avoid fractional part removal |
| 296 | */ |
Archit Taneja | 6cb07b2 | 2011-04-12 13:52:25 +0530 | [diff] [blame] | 297 | pi->regm = (phy * 100 / (refclk)) / 100; |
Tomi Valkeinen | 8d88767a | 2011-08-22 13:02:52 +0300 | [diff] [blame] | 298 | |
| 299 | if (dssdev->clocks.hdmi.regm2 == 0) |
| 300 | pi->regm2 = HDMI_DEFAULT_REGM2; |
| 301 | else |
| 302 | pi->regm2 = dssdev->clocks.hdmi.regm2; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 303 | |
| 304 | /* |
| 305 | * fractional multiplier is remainder of the difference between |
| 306 | * multiplier and actual phy(required pixel clock thus should be |
| 307 | * multiplied by 2^18(262144) divided by the reference clock |
| 308 | */ |
| 309 | mf = (phy - pi->regm * refclk) * 262144; |
Archit Taneja | 6cb07b2 | 2011-04-12 13:52:25 +0530 | [diff] [blame] | 310 | pi->regmf = mf / (refclk); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 311 | |
| 312 | /* |
| 313 | * Dcofreq should be set to 1 if required pixel clock |
| 314 | * is greater than 1000MHz |
| 315 | */ |
| 316 | pi->dcofreq = phy > 1000 * 100; |
Tomi Valkeinen | b44e458 | 2011-08-22 13:16:24 +0300 | [diff] [blame] | 317 | pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 318 | |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 319 | /* Set the reference clock to sysclk reference */ |
| 320 | pi->refsel = HDMI_REFSEL_SYSCLK; |
| 321 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 322 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); |
| 323 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); |
| 324 | } |
| 325 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 326 | static int hdmi_power_on(struct omap_dss_device *dssdev) |
| 327 | { |
| 328 | int r, code = 0; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 329 | struct omap_video_timings *p; |
Archit Taneja | 6cb07b2 | 2011-04-12 13:52:25 +0530 | [diff] [blame] | 330 | unsigned long phy; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 331 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 332 | r = hdmi_runtime_get(); |
| 333 | if (r) |
| 334 | return r; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 335 | |
Tomi Valkeinen | 7797c6d | 2011-11-04 10:22:46 +0200 | [diff] [blame] | 336 | dss_mgr_disable(dssdev->manager); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 337 | |
| 338 | p = &dssdev->panel.timings; |
| 339 | |
| 340 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", |
| 341 | dssdev->panel.timings.x_res, |
| 342 | dssdev->panel.timings.y_res); |
| 343 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 344 | code = get_timings_index(); |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 345 | update_hdmi_timings(&hdmi.ip_data.cfg, p, code); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 346 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 347 | phy = p->pixel_clock; |
| 348 | |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 349 | hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 350 | |
Mythri P K | 60634a2 | 2011-09-08 19:06:26 +0530 | [diff] [blame] | 351 | hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 352 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 353 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ |
Mythri P K | 60634a2 | 2011-09-08 19:06:26 +0530 | [diff] [blame] | 354 | r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 355 | if (r) { |
| 356 | DSSDBG("Failed to lock PLL\n"); |
| 357 | goto err; |
| 358 | } |
| 359 | |
Mythri P K | 60634a2 | 2011-09-08 19:06:26 +0530 | [diff] [blame] | 360 | r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 361 | if (r) { |
| 362 | DSSDBG("Failed to start PHY\n"); |
| 363 | goto err; |
| 364 | } |
| 365 | |
Mythri P K | 7b27da5 | 2011-09-08 19:06:19 +0530 | [diff] [blame] | 366 | hdmi.ip_data.cfg.cm.mode = hdmi.mode; |
| 367 | hdmi.ip_data.cfg.cm.code = hdmi.code; |
Mythri P K | 60634a2 | 2011-09-08 19:06:26 +0530 | [diff] [blame] | 368 | hdmi.ip_data.ops->video_configure(&hdmi.ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 369 | |
| 370 | /* Make selection of HDMI in DSS */ |
| 371 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); |
| 372 | |
| 373 | /* Select the dispc clock source as PRCM clock, to ensure that it is not |
| 374 | * DSI PLL source as the clock selected by DSI PLL might not be |
| 375 | * sufficient for the resolution selected / that can be changed |
| 376 | * dynamically by user. This can be moved to single location , say |
| 377 | * Boardfile. |
| 378 | */ |
Archit Taneja | 6cb07b2 | 2011-04-12 13:52:25 +0530 | [diff] [blame] | 379 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 380 | |
| 381 | /* bypass TV gamma table */ |
| 382 | dispc_enable_gamma_table(0); |
| 383 | |
| 384 | /* tv size */ |
| 385 | dispc_set_digit_size(dssdev->panel.timings.x_res, |
| 386 | dssdev->panel.timings.y_res); |
| 387 | |
Mythri P K | 60634a2 | 2011-09-08 19:06:26 +0530 | [diff] [blame] | 388 | hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 1); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 389 | |
Tomi Valkeinen | 33ca237 | 2011-11-21 13:42:58 +0200 | [diff] [blame] | 390 | r = dss_mgr_enable(dssdev->manager); |
| 391 | if (r) |
| 392 | goto err_mgr_enable; |
Tomi Valkeinen | 3870c90 | 2011-08-31 14:47:11 +0300 | [diff] [blame] | 393 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 394 | return 0; |
Tomi Valkeinen | 33ca237 | 2011-11-21 13:42:58 +0200 | [diff] [blame] | 395 | |
| 396 | err_mgr_enable: |
| 397 | hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0); |
| 398 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); |
| 399 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 400 | err: |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 401 | hdmi_runtime_put(); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 402 | return -EIO; |
| 403 | } |
| 404 | |
| 405 | static void hdmi_power_off(struct omap_dss_device *dssdev) |
| 406 | { |
Tomi Valkeinen | 7797c6d | 2011-11-04 10:22:46 +0200 | [diff] [blame] | 407 | dss_mgr_disable(dssdev->manager); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 408 | |
Mythri P K | 60634a2 | 2011-09-08 19:06:26 +0530 | [diff] [blame] | 409 | hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0); |
| 410 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); |
| 411 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 412 | hdmi_runtime_put(); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 413 | } |
| 414 | |
| 415 | int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, |
| 416 | struct omap_video_timings *timings) |
| 417 | { |
| 418 | struct hdmi_cm cm; |
| 419 | |
| 420 | cm = hdmi_get_code(timings); |
| 421 | if (cm.code == -1) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 422 | return -EINVAL; |
| 423 | } |
| 424 | |
| 425 | return 0; |
| 426 | |
| 427 | } |
| 428 | |
| 429 | void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev) |
| 430 | { |
| 431 | struct hdmi_cm cm; |
| 432 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 433 | cm = hdmi_get_code(&dssdev->panel.timings); |
| 434 | hdmi.code = cm.code; |
| 435 | hdmi.mode = cm.mode; |
Tomi Valkeinen | fa70dc5 | 2011-08-22 14:57:33 +0300 | [diff] [blame] | 436 | |
| 437 | if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { |
| 438 | int r; |
| 439 | |
| 440 | hdmi_power_off(dssdev); |
| 441 | |
| 442 | r = hdmi_power_on(dssdev); |
| 443 | if (r) |
| 444 | DSSERR("failed to power on device\n"); |
| 445 | } |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 446 | } |
| 447 | |
Mythri P K | 162874d | 2011-09-22 13:37:45 +0530 | [diff] [blame] | 448 | void hdmi_dump_regs(struct seq_file *s) |
| 449 | { |
| 450 | mutex_lock(&hdmi.lock); |
| 451 | |
| 452 | if (hdmi_runtime_get()) |
| 453 | return; |
| 454 | |
| 455 | hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s); |
| 456 | hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s); |
| 457 | hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s); |
| 458 | hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s); |
| 459 | |
| 460 | hdmi_runtime_put(); |
| 461 | mutex_unlock(&hdmi.lock); |
| 462 | } |
| 463 | |
Tomi Valkeinen | 4702456 | 2011-08-25 17:12:56 +0300 | [diff] [blame] | 464 | int omapdss_hdmi_read_edid(u8 *buf, int len) |
| 465 | { |
| 466 | int r; |
| 467 | |
| 468 | mutex_lock(&hdmi.lock); |
| 469 | |
| 470 | r = hdmi_runtime_get(); |
| 471 | BUG_ON(r); |
| 472 | |
| 473 | r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len); |
| 474 | |
| 475 | hdmi_runtime_put(); |
| 476 | mutex_unlock(&hdmi.lock); |
| 477 | |
| 478 | return r; |
| 479 | } |
| 480 | |
Tomi Valkeinen | 759593f | 2011-08-29 18:10:20 +0300 | [diff] [blame] | 481 | bool omapdss_hdmi_detect(void) |
| 482 | { |
| 483 | int r; |
| 484 | |
| 485 | mutex_lock(&hdmi.lock); |
| 486 | |
| 487 | r = hdmi_runtime_get(); |
| 488 | BUG_ON(r); |
| 489 | |
| 490 | r = hdmi.ip_data.ops->detect(&hdmi.ip_data); |
| 491 | |
| 492 | hdmi_runtime_put(); |
| 493 | mutex_unlock(&hdmi.lock); |
| 494 | |
| 495 | return r == 1; |
| 496 | } |
| 497 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 498 | int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev) |
| 499 | { |
Tomi Valkeinen | c49d005 | 2012-01-17 11:09:57 +0200 | [diff] [blame] | 500 | struct omap_dss_hdmi_data *priv = dssdev->data; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 501 | int r = 0; |
| 502 | |
| 503 | DSSDBG("ENTER hdmi_display_enable\n"); |
| 504 | |
| 505 | mutex_lock(&hdmi.lock); |
| 506 | |
Tomi Valkeinen | 05e1d60 | 2011-06-23 16:38:21 +0300 | [diff] [blame] | 507 | if (dssdev->manager == NULL) { |
| 508 | DSSERR("failed to enable display: no manager\n"); |
| 509 | r = -ENODEV; |
| 510 | goto err0; |
| 511 | } |
| 512 | |
Tomi Valkeinen | c49d005 | 2012-01-17 11:09:57 +0200 | [diff] [blame] | 513 | hdmi.ip_data.hpd_gpio = priv->hpd_gpio; |
| 514 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 515 | r = omap_dss_start_device(dssdev); |
| 516 | if (r) { |
| 517 | DSSERR("failed to start device\n"); |
| 518 | goto err0; |
| 519 | } |
| 520 | |
| 521 | if (dssdev->platform_enable) { |
| 522 | r = dssdev->platform_enable(dssdev); |
| 523 | if (r) { |
| 524 | DSSERR("failed to enable GPIO's\n"); |
| 525 | goto err1; |
| 526 | } |
| 527 | } |
| 528 | |
| 529 | r = hdmi_power_on(dssdev); |
| 530 | if (r) { |
| 531 | DSSERR("failed to power on device\n"); |
| 532 | goto err2; |
| 533 | } |
| 534 | |
| 535 | mutex_unlock(&hdmi.lock); |
| 536 | return 0; |
| 537 | |
| 538 | err2: |
| 539 | if (dssdev->platform_disable) |
| 540 | dssdev->platform_disable(dssdev); |
| 541 | err1: |
| 542 | omap_dss_stop_device(dssdev); |
| 543 | err0: |
| 544 | mutex_unlock(&hdmi.lock); |
| 545 | return r; |
| 546 | } |
| 547 | |
| 548 | void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev) |
| 549 | { |
| 550 | DSSDBG("Enter hdmi_display_disable\n"); |
| 551 | |
| 552 | mutex_lock(&hdmi.lock); |
| 553 | |
| 554 | hdmi_power_off(dssdev); |
| 555 | |
| 556 | if (dssdev->platform_disable) |
| 557 | dssdev->platform_disable(dssdev); |
| 558 | |
| 559 | omap_dss_stop_device(dssdev); |
| 560 | |
| 561 | mutex_unlock(&hdmi.lock); |
| 562 | } |
| 563 | |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 564 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
| 565 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 566 | |
Ricardo Neri | edefcda | 2011-11-27 16:18:01 -0600 | [diff] [blame] | 567 | static int hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, |
| 568 | struct snd_soc_dai *dai) |
| 569 | { |
| 570 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 571 | struct snd_soc_codec *codec = rtd->codec; |
| 572 | struct platform_device *pdev = to_platform_device(codec->dev); |
| 573 | struct hdmi_ip_data *ip_data = snd_soc_codec_get_drvdata(codec); |
| 574 | int err = 0; |
| 575 | |
| 576 | if (!(ip_data->ops) && !(ip_data->ops->audio_enable)) { |
| 577 | dev_err(&pdev->dev, "Cannot enable/disable audio\n"); |
| 578 | return -ENODEV; |
| 579 | } |
| 580 | |
| 581 | switch (cmd) { |
| 582 | case SNDRV_PCM_TRIGGER_START: |
| 583 | case SNDRV_PCM_TRIGGER_RESUME: |
| 584 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 585 | ip_data->ops->audio_enable(ip_data, true); |
| 586 | break; |
| 587 | case SNDRV_PCM_TRIGGER_STOP: |
| 588 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 589 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 590 | ip_data->ops->audio_enable(ip_data, false); |
| 591 | break; |
| 592 | default: |
| 593 | err = -EINVAL; |
| 594 | } |
| 595 | return err; |
| 596 | } |
| 597 | |
Ricardo Neri | 284cb31 | 2011-11-22 20:50:50 -0600 | [diff] [blame] | 598 | static int hdmi_audio_hw_params(struct snd_pcm_substream *substream, |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 599 | struct snd_pcm_hw_params *params, |
| 600 | struct snd_soc_dai *dai) |
| 601 | { |
Ricardo Neri | 284cb31 | 2011-11-22 20:50:50 -0600 | [diff] [blame] | 602 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 603 | struct snd_soc_codec *codec = rtd->codec; |
| 604 | struct hdmi_ip_data *ip_data = snd_soc_codec_get_drvdata(codec); |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 605 | struct hdmi_audio_format audio_format; |
| 606 | struct hdmi_audio_dma audio_dma; |
| 607 | struct hdmi_core_audio_config core_cfg; |
| 608 | struct hdmi_core_infoframe_audio aud_if_cfg; |
| 609 | int err, n, cts; |
| 610 | enum hdmi_core_audio_sample_freq sample_freq; |
| 611 | |
| 612 | switch (params_format(params)) { |
| 613 | case SNDRV_PCM_FORMAT_S16_LE: |
| 614 | core_cfg.i2s_cfg.word_max_length = |
| 615 | HDMI_AUDIO_I2S_MAX_WORD_20BITS; |
| 616 | core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS; |
| 617 | core_cfg.i2s_cfg.in_length_bits = |
| 618 | HDMI_AUDIO_I2S_INPUT_LENGTH_16; |
| 619 | core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT; |
| 620 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; |
| 621 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; |
| 622 | audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; |
| 623 | audio_dma.transfer_size = 0x10; |
| 624 | break; |
| 625 | case SNDRV_PCM_FORMAT_S24_LE: |
| 626 | core_cfg.i2s_cfg.word_max_length = |
| 627 | HDMI_AUDIO_I2S_MAX_WORD_24BITS; |
| 628 | core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS; |
| 629 | core_cfg.i2s_cfg.in_length_bits = |
| 630 | HDMI_AUDIO_I2S_INPUT_LENGTH_24; |
| 631 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE; |
| 632 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS; |
| 633 | audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT; |
| 634 | core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT; |
| 635 | audio_dma.transfer_size = 0x20; |
| 636 | break; |
| 637 | default: |
| 638 | return -EINVAL; |
| 639 | } |
| 640 | |
| 641 | switch (params_rate(params)) { |
| 642 | case 32000: |
| 643 | sample_freq = HDMI_AUDIO_FS_32000; |
| 644 | break; |
| 645 | case 44100: |
| 646 | sample_freq = HDMI_AUDIO_FS_44100; |
| 647 | break; |
| 648 | case 48000: |
| 649 | sample_freq = HDMI_AUDIO_FS_48000; |
| 650 | break; |
| 651 | default: |
| 652 | return -EINVAL; |
| 653 | } |
| 654 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 655 | err = hdmi_config_audio_acr(ip_data, params_rate(params), &n, &cts); |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 656 | if (err < 0) |
| 657 | return err; |
| 658 | |
| 659 | /* Audio wrapper config */ |
| 660 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; |
| 661 | audio_format.active_chnnls_msk = 0x03; |
| 662 | audio_format.type = HDMI_AUDIO_TYPE_LPCM; |
| 663 | audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; |
| 664 | /* Disable start/stop signals of IEC 60958 blocks */ |
| 665 | audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF; |
| 666 | |
| 667 | audio_dma.block_size = 0xC0; |
| 668 | audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; |
| 669 | audio_dma.fifo_threshold = 0x20; /* in number of samples */ |
| 670 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 671 | hdmi_wp_audio_config_dma(ip_data, &audio_dma); |
| 672 | hdmi_wp_audio_config_format(ip_data, &audio_format); |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 673 | |
| 674 | /* |
| 675 | * I2S config |
| 676 | */ |
| 677 | core_cfg.i2s_cfg.en_high_bitrate_aud = false; |
| 678 | /* Only used with high bitrate audio */ |
| 679 | core_cfg.i2s_cfg.cbit_order = false; |
| 680 | /* Serial data and word select should change on sck rising edge */ |
| 681 | core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING; |
| 682 | core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM; |
| 683 | /* Set I2S word select polarity */ |
| 684 | core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT; |
| 685 | core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST; |
| 686 | /* Set serial data to word select shift. See Phillips spec. */ |
| 687 | core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT; |
| 688 | /* Enable one of the four available serial data channels */ |
| 689 | core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN; |
| 690 | |
| 691 | /* Core audio config */ |
| 692 | core_cfg.freq_sample = sample_freq; |
| 693 | core_cfg.n = n; |
| 694 | core_cfg.cts = cts; |
| 695 | if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) { |
| 696 | core_cfg.aud_par_busclk = 0; |
| 697 | core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW; |
| 698 | core_cfg.use_mclk = false; |
| 699 | } else { |
| 700 | core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8); |
| 701 | core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW; |
| 702 | core_cfg.use_mclk = true; |
| 703 | core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS; |
| 704 | } |
| 705 | core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH; |
| 706 | core_cfg.en_spdif = false; |
| 707 | /* Use sample frequency from channel status word */ |
| 708 | core_cfg.fs_override = true; |
| 709 | /* Enable ACR packets */ |
| 710 | core_cfg.en_acr_pkt = true; |
| 711 | /* Disable direct streaming digital audio */ |
| 712 | core_cfg.en_dsd_audio = false; |
| 713 | /* Use parallel audio interface */ |
| 714 | core_cfg.en_parallel_aud_input = true; |
| 715 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 716 | hdmi_core_audio_config(ip_data, &core_cfg); |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 717 | |
| 718 | /* |
| 719 | * Configure packet |
| 720 | * info frame audio see doc CEA861-D page 74 |
| 721 | */ |
| 722 | aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM; |
| 723 | aud_if_cfg.db1_channel_count = 2; |
| 724 | aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM; |
| 725 | aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM; |
| 726 | aud_if_cfg.db4_channel_alloc = 0x00; |
| 727 | aud_if_cfg.db5_downmix_inh = false; |
| 728 | aud_if_cfg.db5_lsv = 0; |
| 729 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 730 | hdmi_core_audio_infoframe_config(ip_data, &aud_if_cfg); |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 731 | return 0; |
| 732 | } |
| 733 | |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 734 | static int hdmi_audio_startup(struct snd_pcm_substream *substream, |
| 735 | struct snd_soc_dai *dai) |
| 736 | { |
| 737 | if (!hdmi.mode) { |
| 738 | pr_err("Current video settings do not support audio.\n"); |
| 739 | return -EIO; |
| 740 | } |
| 741 | return 0; |
| 742 | } |
| 743 | |
Ricardo Neri | b17ce11 | 2011-11-22 20:09:41 -0600 | [diff] [blame] | 744 | static int hdmi_audio_codec_probe(struct snd_soc_codec *codec) |
| 745 | { |
| 746 | struct hdmi_ip_data *priv = &hdmi.ip_data; |
| 747 | |
| 748 | snd_soc_codec_set_drvdata(codec, priv); |
| 749 | return 0; |
| 750 | } |
| 751 | |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 752 | static struct snd_soc_codec_driver hdmi_audio_codec_drv = { |
Ricardo Neri | b17ce11 | 2011-11-22 20:09:41 -0600 | [diff] [blame] | 753 | .probe = hdmi_audio_codec_probe, |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 754 | }; |
| 755 | |
| 756 | static struct snd_soc_dai_ops hdmi_audio_codec_ops = { |
| 757 | .hw_params = hdmi_audio_hw_params, |
| 758 | .trigger = hdmi_audio_trigger, |
| 759 | .startup = hdmi_audio_startup, |
| 760 | }; |
| 761 | |
| 762 | static struct snd_soc_dai_driver hdmi_codec_dai_drv = { |
| 763 | .name = "hdmi-audio-codec", |
| 764 | .playback = { |
| 765 | .channels_min = 2, |
| 766 | .channels_max = 2, |
| 767 | .rates = SNDRV_PCM_RATE_32000 | |
| 768 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, |
| 769 | .formats = SNDRV_PCM_FMTBIT_S16_LE | |
| 770 | SNDRV_PCM_FMTBIT_S24_LE, |
| 771 | }, |
| 772 | .ops = &hdmi_audio_codec_ops, |
| 773 | }; |
Ricardo Neri | 82335c4 | 2011-04-05 16:05:18 -0500 | [diff] [blame] | 774 | #endif |
| 775 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 776 | static int hdmi_get_clocks(struct platform_device *pdev) |
| 777 | { |
| 778 | struct clk *clk; |
| 779 | |
| 780 | clk = clk_get(&pdev->dev, "sys_clk"); |
| 781 | if (IS_ERR(clk)) { |
| 782 | DSSERR("can't get sys_clk\n"); |
| 783 | return PTR_ERR(clk); |
| 784 | } |
| 785 | |
| 786 | hdmi.sys_clk = clk; |
| 787 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 788 | return 0; |
| 789 | } |
| 790 | |
| 791 | static void hdmi_put_clocks(void) |
| 792 | { |
| 793 | if (hdmi.sys_clk) |
| 794 | clk_put(hdmi.sys_clk); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 795 | } |
| 796 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 797 | /* HDMI HW IP initialisation */ |
| 798 | static int omapdss_hdmihw_probe(struct platform_device *pdev) |
| 799 | { |
| 800 | struct resource *hdmi_mem; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 801 | int r; |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 802 | |
| 803 | hdmi.pdata = pdev->dev.platform_data; |
| 804 | hdmi.pdev = pdev; |
| 805 | |
| 806 | mutex_init(&hdmi.lock); |
| 807 | |
| 808 | hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0); |
| 809 | if (!hdmi_mem) { |
| 810 | DSSERR("can't get IORESOURCE_MEM HDMI\n"); |
| 811 | return -EINVAL; |
| 812 | } |
| 813 | |
| 814 | /* Base address taken from platform */ |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 815 | hdmi.ip_data.base_wp = ioremap(hdmi_mem->start, |
| 816 | resource_size(hdmi_mem)); |
| 817 | if (!hdmi.ip_data.base_wp) { |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 818 | DSSERR("can't ioremap WP\n"); |
| 819 | return -ENOMEM; |
| 820 | } |
| 821 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 822 | r = hdmi_get_clocks(pdev); |
| 823 | if (r) { |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 824 | iounmap(hdmi.ip_data.base_wp); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 825 | return r; |
| 826 | } |
| 827 | |
| 828 | pm_runtime_enable(&pdev->dev); |
| 829 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 830 | hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS; |
| 831 | hdmi.ip_data.core_av_offset = HDMI_CORE_AV; |
| 832 | hdmi.ip_data.pll_offset = HDMI_PLLCTRL; |
| 833 | hdmi.ip_data.phy_offset = HDMI_PHY; |
| 834 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 835 | hdmi_panel_init(); |
| 836 | |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 837 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
| 838 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) |
| 839 | |
| 840 | /* Register ASoC codec DAI */ |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 841 | r = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv, |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 842 | &hdmi_codec_dai_drv, 1); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 843 | if (r) { |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 844 | DSSERR("can't register ASoC HDMI audio codec\n"); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 845 | return r; |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 846 | } |
| 847 | #endif |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 848 | return 0; |
| 849 | } |
| 850 | |
| 851 | static int omapdss_hdmihw_remove(struct platform_device *pdev) |
| 852 | { |
| 853 | hdmi_panel_exit(); |
| 854 | |
Ricardo Neri | ad44cc3 | 2011-05-18 22:31:56 -0500 | [diff] [blame] | 855 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
| 856 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) |
| 857 | snd_soc_unregister_codec(&pdev->dev); |
| 858 | #endif |
| 859 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 860 | pm_runtime_disable(&pdev->dev); |
| 861 | |
| 862 | hdmi_put_clocks(); |
| 863 | |
Mythri P K | 95a8aeb | 2011-09-08 19:06:18 +0530 | [diff] [blame] | 864 | iounmap(hdmi.ip_data.base_wp); |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 865 | |
| 866 | return 0; |
| 867 | } |
| 868 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 869 | static int hdmi_runtime_suspend(struct device *dev) |
| 870 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 871 | clk_disable(hdmi.sys_clk); |
| 872 | |
| 873 | dispc_runtime_put(); |
| 874 | dss_runtime_put(); |
| 875 | |
| 876 | return 0; |
| 877 | } |
| 878 | |
| 879 | static int hdmi_runtime_resume(struct device *dev) |
| 880 | { |
| 881 | int r; |
| 882 | |
| 883 | r = dss_runtime_get(); |
| 884 | if (r < 0) |
| 885 | goto err_get_dss; |
| 886 | |
| 887 | r = dispc_runtime_get(); |
| 888 | if (r < 0) |
| 889 | goto err_get_dispc; |
| 890 | |
| 891 | |
| 892 | clk_enable(hdmi.sys_clk); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 893 | |
| 894 | return 0; |
| 895 | |
| 896 | err_get_dispc: |
| 897 | dss_runtime_put(); |
| 898 | err_get_dss: |
| 899 | return r; |
| 900 | } |
| 901 | |
| 902 | static const struct dev_pm_ops hdmi_pm_ops = { |
| 903 | .runtime_suspend = hdmi_runtime_suspend, |
| 904 | .runtime_resume = hdmi_runtime_resume, |
| 905 | }; |
| 906 | |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 907 | static struct platform_driver omapdss_hdmihw_driver = { |
| 908 | .probe = omapdss_hdmihw_probe, |
| 909 | .remove = omapdss_hdmihw_remove, |
| 910 | .driver = { |
| 911 | .name = "omapdss_hdmi", |
| 912 | .owner = THIS_MODULE, |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 913 | .pm = &hdmi_pm_ops, |
Mythri P K | c3198a5 | 2011-03-12 12:04:27 +0530 | [diff] [blame] | 914 | }, |
| 915 | }; |
| 916 | |
| 917 | int hdmi_init_platform_driver(void) |
| 918 | { |
| 919 | return platform_driver_register(&omapdss_hdmihw_driver); |
| 920 | } |
| 921 | |
| 922 | void hdmi_uninit_platform_driver(void) |
| 923 | { |
| 924 | return platform_driver_unregister(&omapdss_hdmihw_driver); |
| 925 | } |