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Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001/*
2 * TI DaVinci DM365 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -040015#include <linux/init.h>
16#include <linux/clk.h>
17#include <linux/serial_8250.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
Sandeep Paulraja3e13e82010-02-01 09:51:31 -050020#include <linux/spi/spi.h>
Matt Porter3ad7a422013-03-06 11:15:31 -050021#include <linux/platform_data/edma.h>
Philip Avinash9cc15152013-08-18 10:49:00 +053022#include <linux/platform_data/gpio-davinci.h>
23#include <linux/platform_data/keyscan-davinci.h>
24#include <linux/platform_data/spi-davinci.h>
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -040025
26#include <asm/mach/map.h>
27
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -040028#include <mach/cputype.h>
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -040029#include <mach/psc.h>
30#include <mach/mux.h>
31#include <mach/irqs.h>
32#include <mach/time.h>
33#include <mach/serial.h>
34#include <mach/common.h>
35
Manjunath Hadli39c6d2d2011-12-21 19:13:35 +053036#include "davinci.h"
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -040037#include "clock.h"
38#include "mux.h"
Hebbar, Gururaja896f66b2012-08-27 18:56:41 +053039#include "asp.h"
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -040040
41#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
Manjunath Hadli719f56f2011-12-15 17:41:51 +053042#define DM365_RTC_BASE 0x01c69000
Lad, Prabhakar120c6602013-03-19 07:34:36 -030043#define DM365_KEYSCAN_BASE 0x01c69400
44#define DM365_OSD_BASE 0x01c71c00
45#define DM365_VENC_BASE 0x01c71e00
Manjunath Hadli719f56f2011-12-15 17:41:51 +053046#define DAVINCI_DM365_VC_BASE 0x01d0c000
47#define DAVINCI_DMA_VC_TX 2
48#define DAVINCI_DMA_VC_RX 3
Manjunath Hadli719f56f2011-12-15 17:41:51 +053049#define DM365_EMAC_BASE 0x01d07000
50#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
51#define DM365_EMAC_CNTRL_OFFSET 0x0000
52#define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
53#define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
54#define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
55
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -040056static struct pll_data pll1_data = {
57 .num = 1,
58 .phys_base = DAVINCI_PLL1_BASE,
59 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
60};
61
62static struct pll_data pll2_data = {
63 .num = 2,
64 .phys_base = DAVINCI_PLL2_BASE,
65 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
66};
67
68static struct clk ref_clk = {
69 .name = "ref_clk",
70 .rate = DM365_REF_FREQ,
71};
72
73static struct clk pll1_clk = {
74 .name = "pll1",
75 .parent = &ref_clk,
76 .flags = CLK_PLL,
77 .pll_data = &pll1_data,
78};
79
80static struct clk pll1_aux_clk = {
81 .name = "pll1_aux_clk",
82 .parent = &pll1_clk,
83 .flags = CLK_PLL | PRE_PLL,
84};
85
86static struct clk pll1_sysclkbp = {
87 .name = "pll1_sysclkbp",
88 .parent = &pll1_clk,
89 .flags = CLK_PLL | PRE_PLL,
90 .div_reg = BPDIV
91};
92
93static struct clk clkout0_clk = {
94 .name = "clkout0",
95 .parent = &pll1_clk,
96 .flags = CLK_PLL | PRE_PLL,
97};
98
99static struct clk pll1_sysclk1 = {
100 .name = "pll1_sysclk1",
101 .parent = &pll1_clk,
102 .flags = CLK_PLL,
103 .div_reg = PLLDIV1,
104};
105
106static struct clk pll1_sysclk2 = {
107 .name = "pll1_sysclk2",
108 .parent = &pll1_clk,
109 .flags = CLK_PLL,
110 .div_reg = PLLDIV2,
111};
112
113static struct clk pll1_sysclk3 = {
114 .name = "pll1_sysclk3",
115 .parent = &pll1_clk,
116 .flags = CLK_PLL,
117 .div_reg = PLLDIV3,
118};
119
120static struct clk pll1_sysclk4 = {
121 .name = "pll1_sysclk4",
122 .parent = &pll1_clk,
123 .flags = CLK_PLL,
124 .div_reg = PLLDIV4,
125};
126
127static struct clk pll1_sysclk5 = {
128 .name = "pll1_sysclk5",
129 .parent = &pll1_clk,
130 .flags = CLK_PLL,
131 .div_reg = PLLDIV5,
132};
133
134static struct clk pll1_sysclk6 = {
135 .name = "pll1_sysclk6",
136 .parent = &pll1_clk,
137 .flags = CLK_PLL,
138 .div_reg = PLLDIV6,
139};
140
141static struct clk pll1_sysclk7 = {
142 .name = "pll1_sysclk7",
143 .parent = &pll1_clk,
144 .flags = CLK_PLL,
145 .div_reg = PLLDIV7,
146};
147
148static struct clk pll1_sysclk8 = {
149 .name = "pll1_sysclk8",
150 .parent = &pll1_clk,
151 .flags = CLK_PLL,
152 .div_reg = PLLDIV8,
153};
154
155static struct clk pll1_sysclk9 = {
156 .name = "pll1_sysclk9",
157 .parent = &pll1_clk,
158 .flags = CLK_PLL,
159 .div_reg = PLLDIV9,
160};
161
162static struct clk pll2_clk = {
163 .name = "pll2",
164 .parent = &ref_clk,
165 .flags = CLK_PLL,
166 .pll_data = &pll2_data,
167};
168
169static struct clk pll2_aux_clk = {
170 .name = "pll2_aux_clk",
171 .parent = &pll2_clk,
172 .flags = CLK_PLL | PRE_PLL,
173};
174
175static struct clk clkout1_clk = {
176 .name = "clkout1",
177 .parent = &pll2_clk,
178 .flags = CLK_PLL | PRE_PLL,
179};
180
181static struct clk pll2_sysclk1 = {
182 .name = "pll2_sysclk1",
183 .parent = &pll2_clk,
184 .flags = CLK_PLL,
185 .div_reg = PLLDIV1,
186};
187
188static struct clk pll2_sysclk2 = {
189 .name = "pll2_sysclk2",
190 .parent = &pll2_clk,
191 .flags = CLK_PLL,
192 .div_reg = PLLDIV2,
193};
194
195static struct clk pll2_sysclk3 = {
196 .name = "pll2_sysclk3",
197 .parent = &pll2_clk,
198 .flags = CLK_PLL,
199 .div_reg = PLLDIV3,
200};
201
202static struct clk pll2_sysclk4 = {
203 .name = "pll2_sysclk4",
204 .parent = &pll2_clk,
205 .flags = CLK_PLL,
206 .div_reg = PLLDIV4,
207};
208
209static struct clk pll2_sysclk5 = {
210 .name = "pll2_sysclk5",
211 .parent = &pll2_clk,
212 .flags = CLK_PLL,
213 .div_reg = PLLDIV5,
214};
215
216static struct clk pll2_sysclk6 = {
217 .name = "pll2_sysclk6",
218 .parent = &pll2_clk,
219 .flags = CLK_PLL,
220 .div_reg = PLLDIV6,
221};
222
223static struct clk pll2_sysclk7 = {
224 .name = "pll2_sysclk7",
225 .parent = &pll2_clk,
226 .flags = CLK_PLL,
227 .div_reg = PLLDIV7,
228};
229
230static struct clk pll2_sysclk8 = {
231 .name = "pll2_sysclk8",
232 .parent = &pll2_clk,
233 .flags = CLK_PLL,
234 .div_reg = PLLDIV8,
235};
236
237static struct clk pll2_sysclk9 = {
238 .name = "pll2_sysclk9",
239 .parent = &pll2_clk,
240 .flags = CLK_PLL,
241 .div_reg = PLLDIV9,
242};
243
244static struct clk vpss_dac_clk = {
245 .name = "vpss_dac",
246 .parent = &pll1_sysclk3,
247 .lpsc = DM365_LPSC_DAC_CLK,
248};
249
250static struct clk vpss_master_clk = {
251 .name = "vpss_master",
252 .parent = &pll1_sysclk5,
253 .lpsc = DM365_LPSC_VPSSMSTR,
254 .flags = CLK_PSC,
255};
256
Lad, Prabhakar9a3e89b2013-03-22 04:53:12 -0300257static struct clk vpss_slave_clk = {
258 .name = "vpss_slave",
259 .parent = &pll1_sysclk5,
260 .lpsc = DAVINCI_LPSC_VPSSSLV,
261};
262
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400263static struct clk arm_clk = {
264 .name = "arm_clk",
265 .parent = &pll2_sysclk2,
266 .lpsc = DAVINCI_LPSC_ARM,
267 .flags = ALWAYS_ENABLED,
268};
269
270static struct clk uart0_clk = {
271 .name = "uart0",
272 .parent = &pll1_aux_clk,
273 .lpsc = DAVINCI_LPSC_UART0,
274};
275
276static struct clk uart1_clk = {
277 .name = "uart1",
278 .parent = &pll1_sysclk4,
279 .lpsc = DAVINCI_LPSC_UART1,
280};
281
282static struct clk i2c_clk = {
283 .name = "i2c",
284 .parent = &pll1_aux_clk,
285 .lpsc = DAVINCI_LPSC_I2C,
286};
287
288static struct clk mmcsd0_clk = {
289 .name = "mmcsd0",
290 .parent = &pll1_sysclk8,
291 .lpsc = DAVINCI_LPSC_MMC_SD,
292};
293
294static struct clk mmcsd1_clk = {
295 .name = "mmcsd1",
296 .parent = &pll1_sysclk4,
297 .lpsc = DM365_LPSC_MMC_SD1,
298};
299
300static struct clk spi0_clk = {
301 .name = "spi0",
302 .parent = &pll1_sysclk4,
303 .lpsc = DAVINCI_LPSC_SPI,
304};
305
306static struct clk spi1_clk = {
307 .name = "spi1",
308 .parent = &pll1_sysclk4,
309 .lpsc = DM365_LPSC_SPI1,
310};
311
312static struct clk spi2_clk = {
313 .name = "spi2",
314 .parent = &pll1_sysclk4,
315 .lpsc = DM365_LPSC_SPI2,
316};
317
318static struct clk spi3_clk = {
319 .name = "spi3",
320 .parent = &pll1_sysclk4,
321 .lpsc = DM365_LPSC_SPI3,
322};
323
324static struct clk spi4_clk = {
325 .name = "spi4",
326 .parent = &pll1_aux_clk,
327 .lpsc = DM365_LPSC_SPI4,
328};
329
330static struct clk gpio_clk = {
331 .name = "gpio",
332 .parent = &pll1_sysclk4,
333 .lpsc = DAVINCI_LPSC_GPIO,
334};
335
336static struct clk aemif_clk = {
337 .name = "aemif",
338 .parent = &pll1_sysclk4,
339 .lpsc = DAVINCI_LPSC_AEMIF,
340};
341
342static struct clk pwm0_clk = {
343 .name = "pwm0",
344 .parent = &pll1_aux_clk,
345 .lpsc = DAVINCI_LPSC_PWM0,
346};
347
348static struct clk pwm1_clk = {
349 .name = "pwm1",
350 .parent = &pll1_aux_clk,
351 .lpsc = DAVINCI_LPSC_PWM1,
352};
353
354static struct clk pwm2_clk = {
355 .name = "pwm2",
356 .parent = &pll1_aux_clk,
357 .lpsc = DAVINCI_LPSC_PWM2,
358};
359
360static struct clk pwm3_clk = {
361 .name = "pwm3",
362 .parent = &ref_clk,
363 .lpsc = DM365_LPSC_PWM3,
364};
365
366static struct clk timer0_clk = {
367 .name = "timer0",
368 .parent = &pll1_aux_clk,
369 .lpsc = DAVINCI_LPSC_TIMER0,
370};
371
372static struct clk timer1_clk = {
373 .name = "timer1",
374 .parent = &pll1_aux_clk,
375 .lpsc = DAVINCI_LPSC_TIMER1,
376};
377
378static struct clk timer2_clk = {
379 .name = "timer2",
380 .parent = &pll1_aux_clk,
381 .lpsc = DAVINCI_LPSC_TIMER2,
382 .usecount = 1,
383};
384
385static struct clk timer3_clk = {
386 .name = "timer3",
387 .parent = &pll1_aux_clk,
388 .lpsc = DM365_LPSC_TIMER3,
389};
390
391static struct clk usb_clk = {
392 .name = "usb",
Sandeep Paulrajed160672009-08-27 16:39:43 -0400393 .parent = &pll1_aux_clk,
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400394 .lpsc = DAVINCI_LPSC_USB,
395};
396
397static struct clk emac_clk = {
398 .name = "emac",
399 .parent = &pll1_sysclk4,
400 .lpsc = DM365_LPSC_EMAC,
401};
402
403static struct clk voicecodec_clk = {
404 .name = "voice_codec",
405 .parent = &pll2_sysclk4,
406 .lpsc = DM365_LPSC_VOICE_CODEC,
407};
408
409static struct clk asp0_clk = {
410 .name = "asp0",
411 .parent = &pll1_sysclk4,
412 .lpsc = DM365_LPSC_McBSP1,
413};
414
415static struct clk rto_clk = {
416 .name = "rto",
417 .parent = &pll1_sysclk4,
418 .lpsc = DM365_LPSC_RTO,
419};
420
421static struct clk mjcp_clk = {
422 .name = "mjcp",
423 .parent = &pll1_sysclk3,
424 .lpsc = DM365_LPSC_MJCP,
425};
426
Kevin Hilman08aca082010-01-11 08:22:23 -0800427static struct clk_lookup dm365_clks[] = {
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400428 CLK(NULL, "ref", &ref_clk),
429 CLK(NULL, "pll1", &pll1_clk),
430 CLK(NULL, "pll1_aux", &pll1_aux_clk),
431 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
432 CLK(NULL, "clkout0", &clkout0_clk),
433 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
434 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
435 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
436 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
437 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
438 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
439 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
440 CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
441 CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
442 CLK(NULL, "pll2", &pll2_clk),
443 CLK(NULL, "pll2_aux", &pll2_aux_clk),
444 CLK(NULL, "clkout1", &clkout1_clk),
445 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
446 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
447 CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
448 CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
449 CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
450 CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
451 CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
452 CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
453 CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
454 CLK(NULL, "vpss_dac", &vpss_dac_clk),
Lad, Prabhakar9a3e89b2013-03-22 04:53:12 -0300455 CLK("vpss", "master", &vpss_master_clk),
456 CLK("vpss", "slave", &vpss_slave_clk),
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400457 CLK(NULL, "arm", &arm_clk),
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +0530458 CLK("serial8250.0", NULL, &uart0_clk),
459 CLK("serial8250.1", NULL, &uart1_clk),
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400460 CLK("i2c_davinci.1", NULL, &i2c_clk),
Manjunathappa, Prakashd7ca4c72013-03-28 18:41:59 +0530461 CLK("da830-mmc.0", NULL, &mmcsd0_clk),
462 CLK("da830-mmc.1", NULL, &mmcsd1_clk),
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400463 CLK("spi_davinci.0", NULL, &spi0_clk),
464 CLK("spi_davinci.1", NULL, &spi1_clk),
465 CLK("spi_davinci.2", NULL, &spi2_clk),
466 CLK("spi_davinci.3", NULL, &spi3_clk),
467 CLK("spi_davinci.4", NULL, &spi4_clk),
468 CLK(NULL, "gpio", &gpio_clk),
469 CLK(NULL, "aemif", &aemif_clk),
470 CLK(NULL, "pwm0", &pwm0_clk),
471 CLK(NULL, "pwm1", &pwm1_clk),
472 CLK(NULL, "pwm2", &pwm2_clk),
473 CLK(NULL, "pwm3", &pwm3_clk),
474 CLK(NULL, "timer0", &timer0_clk),
475 CLK(NULL, "timer1", &timer1_clk),
Ivan Khoronzhuk84374812013-11-27 15:31:53 +0200476 CLK("davinci-wdt", NULL, &timer2_clk),
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400477 CLK(NULL, "timer3", &timer3_clk),
478 CLK(NULL, "usb", &usb_clk),
479 CLK("davinci_emac.1", NULL, &emac_clk),
Lad, Prabhakar46c18332013-08-15 11:31:33 +0530480 CLK("davinci_mdio.0", "fck", &emac_clk),
Miguel Aguilare89861e2010-01-21 11:41:51 -0600481 CLK("davinci_voicecodec", NULL, &voicecodec_clk),
Chris Paulson-Ellisbedad0c2010-11-16 12:27:09 +0000482 CLK("davinci-mcbsp", NULL, &asp0_clk),
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400483 CLK(NULL, "rto", &rto_clk),
484 CLK(NULL, "mjcp", &mjcp_clk),
485 CLK(NULL, NULL, NULL),
486};
487
488/*----------------------------------------------------------------------*/
489
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400490#define INTMUX 0x18
491#define EVTMUX 0x1c
492
493
494static const struct mux_config dm365_pins[] = {
495#ifdef CONFIG_DAVINCI_MUX
496MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
497
498MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
499MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
500MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
501MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
502MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
503MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
504
505MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
506MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
507
Thomas Koeller77352272010-05-11 17:06:49 +0200508MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
509MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400510MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
511MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
512MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
513MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
Thomas Koeller77352272010-05-11 17:06:49 +0200514MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
515MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400516
517MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
518MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
519MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
520MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
521MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
522MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
523
524MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
525MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
526MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
527MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
528MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
529
530MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
531MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
532MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
533MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
534MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
535MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
536
537MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
538MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
539MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
540MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
541MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
542MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
543MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
544MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
545MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
546MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
547MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
548MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
549MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
550MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
551MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
552MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
553MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
Sandeep Paulraj9f513152009-06-20 12:11:09 -0400554
Miguel Aguilar990c09d2009-10-13 13:57:07 -0600555MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
Sandeep Paulraj9f513152009-06-20 12:11:09 -0400556
Sandeep Paulrajaf5dbae2009-06-24 12:22:28 -0400557MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
558MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
559MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
560MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
561MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
562MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
563MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
564MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
565MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
566MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
567MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
568MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
569
570MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
571MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
572MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
573MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
574MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
575
576MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
577MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
578MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
579MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
580MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
581
582MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
583MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
584MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
585MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
586MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
587
588MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
589MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
590MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
591MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
592MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
593
Thomas Koeller0efe2b72010-05-11 17:06:48 +0200594MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
595MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
596MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
597
Sandeep Paulrajaf5dbae2009-06-24 12:22:28 -0400598MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
Thomas Koeller2168e762010-05-11 17:06:47 +0200599MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
600MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
601MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
Sandeep Paulrajaf5dbae2009-06-24 12:22:28 -0400602MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
603MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
Thomas Koellerce100662010-04-08 17:01:56 +0200604MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
Sandeep Paulrajaf5dbae2009-06-24 12:22:28 -0400605
606MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
607MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
608MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
609MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
610MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
611MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
612MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
613MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
Sandeep Paulraj866d2862009-08-03 13:58:24 -0400614MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
615MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
Sandeep Paulrajaf5dbae2009-06-24 12:22:28 -0400616
Sandeep Paulraj9f513152009-06-20 12:11:09 -0400617INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
618INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
619INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
620INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
621INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
622INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
623INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
624INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
625INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
626INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
Sandeep Paulraj0c30e0d2009-08-18 11:08:27 -0400627INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
628INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
629INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
630INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
631INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
632INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
633INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
634INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
Miguel Aguilare9ab3212009-09-02 15:33:29 -0600635
636EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
637EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
Miguel Aguilare89861e2010-01-21 11:41:51 -0600638EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
639EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400640#endif
641};
642
Sandeep Paulraja3e13e82010-02-01 09:51:31 -0500643static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
644
645static struct davinci_spi_platform_data dm365_spi0_pdata = {
646 .version = SPI_VERSION_1,
647 .num_chipselect = 2,
Michael Williamson2e3e2a52011-02-08 07:59:55 -0500648 .dma_event_q = EVENTQ_3,
Franklin S Cooper Jr1b0838b2015-08-12 08:26:19 -0500649 .prescaler_limit = 1,
Sandeep Paulraja3e13e82010-02-01 09:51:31 -0500650};
651
652static struct resource dm365_spi0_resources[] = {
653 {
654 .start = 0x01c66000,
655 .end = 0x01c667ff,
656 .flags = IORESOURCE_MEM,
657 },
658 {
659 .start = IRQ_DM365_SPIINT0_0,
660 .flags = IORESOURCE_IRQ,
661 },
662 {
663 .start = 17,
664 .flags = IORESOURCE_DMA,
665 },
666 {
667 .start = 16,
668 .flags = IORESOURCE_DMA,
669 },
Sandeep Paulraja3e13e82010-02-01 09:51:31 -0500670};
671
672static struct platform_device dm365_spi0_device = {
673 .name = "spi_davinci",
674 .id = 0,
675 .dev = {
676 .dma_mask = &dm365_spi0_dma_mask,
677 .coherent_dma_mask = DMA_BIT_MASK(32),
678 .platform_data = &dm365_spi0_pdata,
679 },
680 .num_resources = ARRAY_SIZE(dm365_spi0_resources),
681 .resource = dm365_spi0_resources,
682};
683
684void __init dm365_init_spi0(unsigned chipselect_mask,
Uwe Kleine-Königd65566e2012-03-30 22:13:53 +0200685 const struct spi_board_info *info, unsigned len)
Sandeep Paulraja3e13e82010-02-01 09:51:31 -0500686{
687 davinci_cfg_reg(DM365_SPI0_SCLK);
688 davinci_cfg_reg(DM365_SPI0_SDI);
689 davinci_cfg_reg(DM365_SPI0_SDO);
690
691 /* not all slaves will be wired up */
692 if (chipselect_mask & BIT(0))
693 davinci_cfg_reg(DM365_SPI0_SDENA0);
694 if (chipselect_mask & BIT(1))
695 davinci_cfg_reg(DM365_SPI0_SDENA1);
696
697 spi_register_board_info(info, len);
698
699 platform_device_register(&dm365_spi0_device);
700}
701
Philip Avinash9cc15152013-08-18 10:49:00 +0530702static struct resource dm365_gpio_resources[] = {
703 { /* registers */
704 .start = DAVINCI_GPIO_BASE,
705 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
706 .flags = IORESOURCE_MEM,
707 },
708 { /* interrupt */
709 .start = IRQ_DM365_GPIO0,
710 .end = IRQ_DM365_GPIO7,
711 .flags = IORESOURCE_IRQ,
712 },
713};
714
715static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
716 .ngpio = 104,
Philip Avinash9cc15152013-08-18 10:49:00 +0530717 .gpio_unbanked = 8,
718};
719
720int __init dm365_gpio_register(void)
721{
722 return davinci_gpio_register(dm365_gpio_resources,
Lad, Prabhakare462f1f2013-11-08 12:15:56 +0530723 ARRAY_SIZE(dm365_gpio_resources),
Philip Avinash9cc15152013-08-18 10:49:00 +0530724 &dm365_gpio_platform_data);
725}
726
Sandeep Paulraj8ed0a9d2009-06-20 12:23:39 -0400727static struct emac_platform_data dm365_emac_pdata = {
728 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
729 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
730 .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
Sandeep Paulraj8ed0a9d2009-06-20 12:23:39 -0400731 .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
732 .version = EMAC_VERSION_2,
733};
734
735static struct resource dm365_emac_resources[] = {
736 {
737 .start = DM365_EMAC_BASE,
Cyril Chemparathyd22960c2010-09-15 10:11:22 -0400738 .end = DM365_EMAC_BASE + SZ_16K - 1,
Sandeep Paulraj8ed0a9d2009-06-20 12:23:39 -0400739 .flags = IORESOURCE_MEM,
740 },
741 {
742 .start = IRQ_DM365_EMAC_RXTHRESH,
743 .end = IRQ_DM365_EMAC_RXTHRESH,
744 .flags = IORESOURCE_IRQ,
745 },
746 {
747 .start = IRQ_DM365_EMAC_RXPULSE,
748 .end = IRQ_DM365_EMAC_RXPULSE,
749 .flags = IORESOURCE_IRQ,
750 },
751 {
752 .start = IRQ_DM365_EMAC_TXPULSE,
753 .end = IRQ_DM365_EMAC_TXPULSE,
754 .flags = IORESOURCE_IRQ,
755 },
756 {
757 .start = IRQ_DM365_EMAC_MISCPULSE,
758 .end = IRQ_DM365_EMAC_MISCPULSE,
759 .flags = IORESOURCE_IRQ,
760 },
761};
762
763static struct platform_device dm365_emac_device = {
764 .name = "davinci_emac",
765 .id = 1,
766 .dev = {
767 .platform_data = &dm365_emac_pdata,
768 },
769 .num_resources = ARRAY_SIZE(dm365_emac_resources),
770 .resource = dm365_emac_resources,
771};
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400772
Cyril Chemparathyd22960c2010-09-15 10:11:22 -0400773static struct resource dm365_mdio_resources[] = {
774 {
775 .start = DM365_EMAC_MDIO_BASE,
776 .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
777 .flags = IORESOURCE_MEM,
778 },
779};
780
781static struct platform_device dm365_mdio_device = {
782 .name = "davinci_mdio",
783 .id = 0,
784 .num_resources = ARRAY_SIZE(dm365_mdio_resources),
785 .resource = dm365_mdio_resources,
786};
787
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400788static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
789 [IRQ_VDINT0] = 2,
790 [IRQ_VDINT1] = 6,
791 [IRQ_VDINT2] = 6,
792 [IRQ_HISTINT] = 6,
793 [IRQ_H3AINT] = 6,
794 [IRQ_PRVUINT] = 6,
795 [IRQ_RSZINT] = 6,
796 [IRQ_DM365_INSFINT] = 7,
797 [IRQ_VENCINT] = 6,
798 [IRQ_ASQINT] = 6,
799 [IRQ_IMXINT] = 6,
800 [IRQ_DM365_IMCOPINT] = 4,
801 [IRQ_USBINT] = 4,
802 [IRQ_DM365_RTOINT] = 7,
803 [IRQ_DM365_TINT5] = 7,
804 [IRQ_DM365_TINT6] = 5,
805 [IRQ_CCINT0] = 5,
806 [IRQ_CCERRINT] = 5,
807 [IRQ_TCERRINT0] = 5,
808 [IRQ_TCERRINT] = 7,
809 [IRQ_PSCIN] = 4,
810 [IRQ_DM365_SPINT2_1] = 7,
811 [IRQ_DM365_TINT7] = 7,
812 [IRQ_DM365_SDIOINT0] = 7,
813 [IRQ_MBXINT] = 7,
814 [IRQ_MBRINT] = 7,
815 [IRQ_MMCINT] = 7,
816 [IRQ_DM365_MMCINT1] = 7,
817 [IRQ_DM365_PWMINT3] = 7,
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400818 [IRQ_AEMIFINT] = 2,
819 [IRQ_DM365_SDIOINT1] = 2,
820 [IRQ_TINT0_TINT12] = 7,
821 [IRQ_TINT0_TINT34] = 7,
822 [IRQ_TINT1_TINT12] = 7,
823 [IRQ_TINT1_TINT34] = 7,
824 [IRQ_PWMINT0] = 7,
825 [IRQ_PWMINT1] = 3,
826 [IRQ_PWMINT2] = 3,
827 [IRQ_I2C] = 3,
828 [IRQ_UARTINT0] = 3,
829 [IRQ_UARTINT1] = 3,
Miguel Aguilar99381b42009-11-05 08:52:05 -0600830 [IRQ_DM365_RTCINT] = 3,
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400831 [IRQ_DM365_SPIINT0_0] = 3,
832 [IRQ_DM365_SPIINT3_0] = 3,
833 [IRQ_DM365_GPIO0] = 3,
834 [IRQ_DM365_GPIO1] = 7,
835 [IRQ_DM365_GPIO2] = 4,
836 [IRQ_DM365_GPIO3] = 4,
837 [IRQ_DM365_GPIO4] = 7,
838 [IRQ_DM365_GPIO5] = 7,
839 [IRQ_DM365_GPIO6] = 7,
840 [IRQ_DM365_GPIO7] = 7,
841 [IRQ_DM365_EMAC_RXTHRESH] = 7,
842 [IRQ_DM365_EMAC_RXPULSE] = 7,
843 [IRQ_DM365_EMAC_TXPULSE] = 7,
844 [IRQ_DM365_EMAC_MISCPULSE] = 7,
845 [IRQ_DM365_GPIO12] = 7,
846 [IRQ_DM365_GPIO13] = 7,
847 [IRQ_DM365_GPIO14] = 7,
848 [IRQ_DM365_GPIO15] = 7,
849 [IRQ_DM365_KEYINT] = 7,
850 [IRQ_DM365_TCERRINT2] = 7,
851 [IRQ_DM365_TCERRINT3] = 7,
852 [IRQ_DM365_EMUINT] = 7,
853};
854
Sandeep Paulraj15061b52009-06-20 13:15:39 -0400855/* Four Transfer Controllers on DM365 */
Matt Porter6cba4352013-06-20 16:06:38 -0500856static s8
Sandeep Paulraj15061b52009-06-20 13:15:39 -0400857dm365_queue_priority_mapping[][2] = {
858 /* {event queue no, Priority} */
859 {0, 7},
860 {1, 7},
861 {2, 7},
862 {3, 0},
863 {-1, -1},
864};
865
Sekhar Noribc3ac9f2010-06-29 11:35:12 +0530866static struct edma_soc_info edma_cc0_info = {
Sekhar Noribc3ac9f2010-06-29 11:35:12 +0530867 .queue_priority_mapping = dm365_queue_priority_mapping,
868 .default_queue = EVENTQ_3,
869};
870
871static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = {
872 &edma_cc0_info,
Sandeep Paulraj15061b52009-06-20 13:15:39 -0400873};
874
875static struct resource edma_resources[] = {
876 {
877 .name = "edma_cc0",
878 .start = 0x01c00000,
879 .end = 0x01c00000 + SZ_64K - 1,
880 .flags = IORESOURCE_MEM,
881 },
882 {
883 .name = "edma_tc0",
884 .start = 0x01c10000,
885 .end = 0x01c10000 + SZ_1K - 1,
886 .flags = IORESOURCE_MEM,
887 },
888 {
889 .name = "edma_tc1",
890 .start = 0x01c10400,
891 .end = 0x01c10400 + SZ_1K - 1,
892 .flags = IORESOURCE_MEM,
893 },
894 {
895 .name = "edma_tc2",
896 .start = 0x01c10800,
897 .end = 0x01c10800 + SZ_1K - 1,
898 .flags = IORESOURCE_MEM,
899 },
900 {
901 .name = "edma_tc3",
902 .start = 0x01c10c00,
903 .end = 0x01c10c00 + SZ_1K - 1,
904 .flags = IORESOURCE_MEM,
905 },
906 {
907 .name = "edma0",
908 .start = IRQ_CCINT0,
909 .flags = IORESOURCE_IRQ,
910 },
911 {
912 .name = "edma0_err",
913 .start = IRQ_CCERRINT,
914 .flags = IORESOURCE_IRQ,
915 },
916 /* not using TC*_ERR */
917};
918
919static struct platform_device dm365_edma_device = {
920 .name = "edma",
921 .id = 0,
922 .dev.platform_data = dm365_edma_info,
923 .num_resources = ARRAY_SIZE(edma_resources),
924 .resource = edma_resources,
925};
926
Miguel Aguilare9ab3212009-09-02 15:33:29 -0600927static struct resource dm365_asp_resources[] = {
928 {
Peter Ujfalusiee880db2013-11-13 16:48:17 +0200929 .name = "mpu",
Miguel Aguilare9ab3212009-09-02 15:33:29 -0600930 .start = DAVINCI_DM365_ASP0_BASE,
931 .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
932 .flags = IORESOURCE_MEM,
933 },
934 {
935 .start = DAVINCI_DMA_ASP0_TX,
936 .end = DAVINCI_DMA_ASP0_TX,
937 .flags = IORESOURCE_DMA,
938 },
939 {
940 .start = DAVINCI_DMA_ASP0_RX,
941 .end = DAVINCI_DMA_ASP0_RX,
942 .flags = IORESOURCE_DMA,
943 },
944};
945
946static struct platform_device dm365_asp_device = {
Chris Paulson-Ellisbedad0c2010-11-16 12:27:09 +0000947 .name = "davinci-mcbsp",
948 .id = -1,
Miguel Aguilare9ab3212009-09-02 15:33:29 -0600949 .num_resources = ARRAY_SIZE(dm365_asp_resources),
950 .resource = dm365_asp_resources,
951};
952
Miguel Aguilare89861e2010-01-21 11:41:51 -0600953static struct resource dm365_vc_resources[] = {
954 {
955 .start = DAVINCI_DM365_VC_BASE,
956 .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
957 .flags = IORESOURCE_MEM,
958 },
959 {
960 .start = DAVINCI_DMA_VC_TX,
961 .end = DAVINCI_DMA_VC_TX,
962 .flags = IORESOURCE_DMA,
963 },
964 {
965 .start = DAVINCI_DMA_VC_RX,
966 .end = DAVINCI_DMA_VC_RX,
967 .flags = IORESOURCE_DMA,
968 },
969};
970
971static struct platform_device dm365_vc_device = {
972 .name = "davinci_voicecodec",
973 .id = -1,
974 .num_resources = ARRAY_SIZE(dm365_vc_resources),
975 .resource = dm365_vc_resources,
976};
977
Miguel Aguilar99381b42009-11-05 08:52:05 -0600978static struct resource dm365_rtc_resources[] = {
979 {
980 .start = DM365_RTC_BASE,
981 .end = DM365_RTC_BASE + SZ_1K - 1,
982 .flags = IORESOURCE_MEM,
983 },
984 {
985 .start = IRQ_DM365_RTCINT,
986 .flags = IORESOURCE_IRQ,
987 },
988};
989
990static struct platform_device dm365_rtc_device = {
991 .name = "rtc_davinci",
992 .id = 0,
993 .num_resources = ARRAY_SIZE(dm365_rtc_resources),
994 .resource = dm365_rtc_resources,
995};
996
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -0400997static struct map_desc dm365_io_desc[] = {
998 {
999 .virtual = IO_VIRT,
1000 .pfn = __phys_to_pfn(IO_PHYS),
1001 .length = IO_SIZE,
1002 .type = MT_DEVICE
1003 },
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001004};
1005
Miguel Aguilar990c09d2009-10-13 13:57:07 -06001006static struct resource dm365_ks_resources[] = {
1007 {
1008 /* registers */
1009 .start = DM365_KEYSCAN_BASE,
1010 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
1011 .flags = IORESOURCE_MEM,
1012 },
1013 {
1014 /* interrupt */
1015 .start = IRQ_DM365_KEYINT,
1016 .end = IRQ_DM365_KEYINT,
1017 .flags = IORESOURCE_IRQ,
1018 },
1019};
1020
1021static struct platform_device dm365_ks_device = {
1022 .name = "davinci_keyscan",
1023 .id = 0,
1024 .num_resources = ARRAY_SIZE(dm365_ks_resources),
1025 .resource = dm365_ks_resources,
1026};
1027
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001028/* Contents of JTAG ID register used to identify exact cpu type */
1029static struct davinci_id dm365_ids[] = {
1030 {
1031 .variant = 0x0,
1032 .part_no = 0xb83e,
1033 .manufacturer = 0x017,
1034 .cpu_id = DAVINCI_CPU_ID_DM365,
Sandeep Paulrajcc36e972009-08-07 13:19:45 -04001035 .name = "dm365_rev1.1",
1036 },
1037 {
1038 .variant = 0x8,
1039 .part_no = 0xb83e,
1040 .manufacturer = 0x017,
1041 .cpu_id = DAVINCI_CPU_ID_DM365,
1042 .name = "dm365_rev1.2",
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001043 },
1044};
1045
Cyril Chemparathye4c822c2010-05-07 17:06:36 -04001046static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001047
Kevin Hilman28552c22010-02-25 15:36:38 -08001048static struct davinci_timer_info dm365_timer_info = {
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001049 .timers = davinci_timer_instance,
1050 .clockevent_id = T0_BOT,
1051 .clocksource_id = T0_TOP,
1052};
1053
Thomas Koellera2767b42010-06-22 14:08:12 +02001054#define DM365_UART1_BASE (IO_PHYS + 0x106000)
1055
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +05301056static struct plat_serial8250_port dm365_serial0_platform_data[] = {
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001057 {
1058 .mapbase = DAVINCI_UART0_BASE,
1059 .irq = IRQ_UARTINT0,
1060 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1061 UPF_IOREMAP,
1062 .iotype = UPIO_MEM,
1063 .regshift = 2,
1064 },
1065 {
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +05301066 .flags = 0,
1067 }
1068};
1069static struct plat_serial8250_port dm365_serial1_platform_data[] = {
1070 {
Thomas Koellera2767b42010-06-22 14:08:12 +02001071 .mapbase = DM365_UART1_BASE,
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001072 .irq = IRQ_UARTINT1,
1073 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1074 UPF_IOREMAP,
1075 .iotype = UPIO_MEM,
1076 .regshift = 2,
1077 },
1078 {
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +05301079 .flags = 0,
1080 }
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001081};
1082
Manjunathappa, Prakashfcf71572013-06-19 14:45:42 +05301083struct platform_device dm365_serial_device[] = {
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +05301084 {
1085 .name = "serial8250",
1086 .id = PLAT8250_DEV_PLATFORM,
1087 .dev = {
1088 .platform_data = dm365_serial0_platform_data,
1089 }
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001090 },
Manjunathappa, Prakash19955c32013-06-19 14:45:38 +05301091 {
1092 .name = "serial8250",
1093 .id = PLAT8250_DEV_PLATFORM1,
1094 .dev = {
1095 .platform_data = dm365_serial1_platform_data,
1096 }
1097 },
1098 {
1099 }
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001100};
1101
1102static struct davinci_soc_info davinci_soc_info_dm365 = {
1103 .io_desc = dm365_io_desc,
1104 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
Cyril Chemparathy3347db82010-05-07 17:06:34 -04001105 .jtag_id_reg = 0x01c40028,
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001106 .ids = dm365_ids,
1107 .ids_num = ARRAY_SIZE(dm365_ids),
1108 .cpu_clks = dm365_clks,
1109 .psc_bases = dm365_psc_bases,
1110 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
Cyril Chemparathy779b0d52010-05-07 17:06:38 -04001111 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001112 .pinmux_pins = dm365_pins,
1113 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
Cyril Chemparathybd808942010-05-07 17:06:37 -04001114 .intc_base = DAVINCI_ARM_INTC_BASE,
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001115 .intc_type = DAVINCI_INTC_TYPE_AINTC,
1116 .intc_irq_prios = dm365_default_priorities,
1117 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
1118 .timer_info = &dm365_timer_info,
Sandeep Paulraj8ed0a9d2009-06-20 12:23:39 -04001119 .emac_pdata = &dm365_emac_pdata,
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001120 .sram_dma = 0x00010000,
1121 .sram_len = SZ_32K,
1122};
1123
Miguel Aguilare9ab3212009-09-02 15:33:29 -06001124void __init dm365_init_asp(struct snd_platform_data *pdata)
1125{
1126 davinci_cfg_reg(DM365_MCBSP0_BDX);
1127 davinci_cfg_reg(DM365_MCBSP0_X);
1128 davinci_cfg_reg(DM365_MCBSP0_BFSX);
1129 davinci_cfg_reg(DM365_MCBSP0_BDR);
1130 davinci_cfg_reg(DM365_MCBSP0_R);
1131 davinci_cfg_reg(DM365_MCBSP0_BFSR);
1132 davinci_cfg_reg(DM365_EVT2_ASP_TX);
1133 davinci_cfg_reg(DM365_EVT3_ASP_RX);
1134 dm365_asp_device.dev.platform_data = pdata;
1135 platform_device_register(&dm365_asp_device);
1136}
1137
Miguel Aguilare89861e2010-01-21 11:41:51 -06001138void __init dm365_init_vc(struct snd_platform_data *pdata)
1139{
1140 davinci_cfg_reg(DM365_EVT2_VC_TX);
1141 davinci_cfg_reg(DM365_EVT3_VC_RX);
1142 dm365_vc_device.dev.platform_data = pdata;
1143 platform_device_register(&dm365_vc_device);
1144}
1145
Miguel Aguilar990c09d2009-10-13 13:57:07 -06001146void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
1147{
Miguel Aguilar990c09d2009-10-13 13:57:07 -06001148 dm365_ks_device.dev.platform_data = pdata;
1149 platform_device_register(&dm365_ks_device);
1150}
1151
Miguel Aguilar99381b42009-11-05 08:52:05 -06001152void __init dm365_init_rtc(void)
1153{
1154 davinci_cfg_reg(DM365_INT_PRTCSS);
1155 platform_device_register(&dm365_rtc_device);
1156}
1157
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001158void __init dm365_init(void)
1159{
1160 davinci_common_init(&davinci_soc_info_dm365);
Manjunath Hadli5cfb19a2011-12-21 19:13:36 +05301161 davinci_map_sysmod();
Sandeep Paulrajfb8fcb82009-06-11 09:41:05 -04001162}
Sandeep Paulraj8ed0a9d2009-06-20 12:23:39 -04001163
Murali Karicherif2a4c592010-02-01 17:38:53 -05001164static struct resource dm365_vpss_resources[] = {
1165 {
1166 /* VPSS ISP5 Base address */
1167 .name = "isp5",
1168 .start = 0x01c70000,
1169 .end = 0x01c70000 + 0xff,
1170 .flags = IORESOURCE_MEM,
1171 },
1172 {
1173 /* VPSS CLK Base address */
1174 .name = "vpss",
1175 .start = 0x01c70200,
1176 .end = 0x01c70200 + 0xff,
1177 .flags = IORESOURCE_MEM,
1178 },
1179};
1180
1181static struct platform_device dm365_vpss_device = {
1182 .name = "vpss",
1183 .id = -1,
1184 .dev.platform_data = "dm365_vpss",
1185 .num_resources = ARRAY_SIZE(dm365_vpss_resources),
1186 .resource = dm365_vpss_resources,
1187};
1188
1189static struct resource vpfe_resources[] = {
1190 {
1191 .start = IRQ_VDINT0,
1192 .end = IRQ_VDINT0,
1193 .flags = IORESOURCE_IRQ,
1194 },
1195 {
1196 .start = IRQ_VDINT1,
1197 .end = IRQ_VDINT1,
1198 .flags = IORESOURCE_IRQ,
1199 },
1200};
1201
1202static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
1203static struct platform_device vpfe_capture_dev = {
1204 .name = CAPTURE_DRV_NAME,
1205 .id = -1,
1206 .num_resources = ARRAY_SIZE(vpfe_resources),
1207 .resource = vpfe_resources,
1208 .dev = {
1209 .dma_mask = &vpfe_capture_dma_mask,
1210 .coherent_dma_mask = DMA_BIT_MASK(32),
1211 },
1212};
1213
1214static void dm365_isif_setup_pinmux(void)
1215{
1216 davinci_cfg_reg(DM365_VIN_CAM_WEN);
1217 davinci_cfg_reg(DM365_VIN_CAM_VD);
1218 davinci_cfg_reg(DM365_VIN_CAM_HD);
1219 davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
1220 davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
1221}
1222
1223static struct resource isif_resource[] = {
1224 /* ISIF Base address */
1225 {
1226 .start = 0x01c71000,
1227 .end = 0x01c71000 + 0x1ff,
1228 .flags = IORESOURCE_MEM,
1229 },
1230 /* ISIF Linearization table 0 */
1231 {
1232 .start = 0x1C7C000,
1233 .end = 0x1C7C000 + 0x2ff,
1234 .flags = IORESOURCE_MEM,
1235 },
1236 /* ISIF Linearization table 1 */
1237 {
1238 .start = 0x1C7C400,
1239 .end = 0x1C7C400 + 0x2ff,
1240 .flags = IORESOURCE_MEM,
1241 },
1242};
1243static struct platform_device dm365_isif_dev = {
1244 .name = "isif",
1245 .id = -1,
1246 .num_resources = ARRAY_SIZE(isif_resource),
1247 .resource = isif_resource,
1248 .dev = {
1249 .dma_mask = &vpfe_capture_dma_mask,
1250 .coherent_dma_mask = DMA_BIT_MASK(32),
1251 .platform_data = dm365_isif_setup_pinmux,
1252 },
1253};
1254
Lad, Prabhakar120c6602013-03-19 07:34:36 -03001255static struct resource dm365_osd_resources[] = {
1256 {
1257 .start = DM365_OSD_BASE,
1258 .end = DM365_OSD_BASE + 0xff,
1259 .flags = IORESOURCE_MEM,
1260 },
1261};
1262
1263static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
1264
1265static struct platform_device dm365_osd_dev = {
1266 .name = DM365_VPBE_OSD_SUBDEV_NAME,
1267 .id = -1,
1268 .num_resources = ARRAY_SIZE(dm365_osd_resources),
1269 .resource = dm365_osd_resources,
1270 .dev = {
1271 .dma_mask = &dm365_video_dma_mask,
1272 .coherent_dma_mask = DMA_BIT_MASK(32),
1273 },
1274};
1275
1276static struct resource dm365_venc_resources[] = {
1277 {
1278 .start = IRQ_VENCINT,
1279 .end = IRQ_VENCINT,
1280 .flags = IORESOURCE_IRQ,
1281 },
1282 /* venc registers io space */
1283 {
1284 .start = DM365_VENC_BASE,
1285 .end = DM365_VENC_BASE + 0x177,
1286 .flags = IORESOURCE_MEM,
1287 },
1288 /* vdaccfg registers io space */
1289 {
1290 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
1291 .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
1292 .flags = IORESOURCE_MEM,
1293 },
1294};
1295
1296static struct resource dm365_v4l2_disp_resources[] = {
1297 {
1298 .start = IRQ_VENCINT,
1299 .end = IRQ_VENCINT,
1300 .flags = IORESOURCE_IRQ,
1301 },
1302 /* venc registers io space */
1303 {
1304 .start = DM365_VENC_BASE,
1305 .end = DM365_VENC_BASE + 0x177,
1306 .flags = IORESOURCE_MEM,
1307 },
1308};
1309
Boris BREZILLON27ffaeb2014-11-10 14:28:31 -03001310static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
Lad, Prabhakar120c6602013-03-19 07:34:36 -03001311{
1312 switch (if_type) {
Boris BREZILLON27ffaeb2014-11-10 14:28:31 -03001313 case MEDIA_BUS_FMT_SGRBG8_1X8:
Lad, Prabhakar120c6602013-03-19 07:34:36 -03001314 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1315 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1316 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1317 break;
Boris BREZILLON27ffaeb2014-11-10 14:28:31 -03001318 case MEDIA_BUS_FMT_YUYV10_1X20:
Lad, Prabhakar120c6602013-03-19 07:34:36 -03001319 if (field)
1320 davinci_cfg_reg(DM365_VOUT_FIELD);
1321 else
1322 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1323 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1324 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1325 break;
1326 default:
1327 return -EINVAL;
1328 }
1329
1330 return 0;
1331}
1332
1333static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
1334 unsigned int pclock)
1335{
1336 void __iomem *vpss_clkctl_reg;
1337 u32 val;
1338
1339 vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
1340
1341 switch (type) {
1342 case VPBE_ENC_STD:
1343 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1344 break;
1345 case VPBE_ENC_DV_TIMINGS:
1346 if (pclock <= 27000000) {
1347 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1348 } else {
1349 /* set sysclk4 to output 74.25 MHz from pll1 */
1350 val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
1351 VPSS_VENCCLKEN_ENABLE;
1352 }
1353 break;
1354 default:
1355 return -EINVAL;
1356 }
1357 writel(val, vpss_clkctl_reg);
1358
1359 return 0;
1360}
1361
1362static struct platform_device dm365_vpbe_display = {
1363 .name = "vpbe-v4l2",
1364 .id = -1,
1365 .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources),
1366 .resource = dm365_v4l2_disp_resources,
1367 .dev = {
1368 .dma_mask = &dm365_video_dma_mask,
1369 .coherent_dma_mask = DMA_BIT_MASK(32),
1370 },
1371};
1372
Sekhar Nori9c559702013-07-12 15:19:03 +05301373static struct venc_platform_data dm365_venc_pdata = {
Lad, Prabhakar120c6602013-03-19 07:34:36 -03001374 .setup_pinmux = dm365_vpbe_setup_pinmux,
1375 .setup_clock = dm365_venc_setup_clock,
1376};
1377
1378static struct platform_device dm365_venc_dev = {
1379 .name = DM365_VPBE_VENC_SUBDEV_NAME,
1380 .id = -1,
1381 .num_resources = ARRAY_SIZE(dm365_venc_resources),
1382 .resource = dm365_venc_resources,
1383 .dev = {
1384 .dma_mask = &dm365_video_dma_mask,
1385 .coherent_dma_mask = DMA_BIT_MASK(32),
1386 .platform_data = (void *)&dm365_venc_pdata,
1387 },
1388};
1389
1390static struct platform_device dm365_vpbe_dev = {
1391 .name = "vpbe_controller",
1392 .id = -1,
1393 .dev = {
1394 .dma_mask = &dm365_video_dma_mask,
1395 .coherent_dma_mask = DMA_BIT_MASK(32),
1396 },
1397};
1398
1399int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1400 struct vpbe_config *vpbe_cfg)
1401{
1402 if (vpfe_cfg || vpbe_cfg)
1403 platform_device_register(&dm365_vpss_device);
1404
1405 if (vpfe_cfg) {
1406 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1407 platform_device_register(&dm365_isif_dev);
1408 platform_device_register(&vpfe_capture_dev);
1409 }
1410 if (vpbe_cfg) {
1411 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1412 platform_device_register(&dm365_osd_dev);
1413 platform_device_register(&dm365_venc_dev);
1414 platform_device_register(&dm365_vpbe_dev);
1415 platform_device_register(&dm365_vpbe_display);
1416 }
1417
1418 return 0;
1419}
1420
Sandeep Paulraj8ed0a9d2009-06-20 12:23:39 -04001421static int __init dm365_init_devices(void)
1422{
Sekhar Nori12330902014-02-26 10:29:43 +05301423 int ret = 0;
1424
Sandeep Paulraj8ed0a9d2009-06-20 12:23:39 -04001425 if (!cpu_is_davinci_dm365())
1426 return 0;
1427
Sandeep Paulraj15061b52009-06-20 13:15:39 -04001428 davinci_cfg_reg(DM365_INT_EDMA_CC);
1429 platform_device_register(&dm365_edma_device);
Cyril Chemparathyd22960c2010-09-15 10:11:22 -04001430
1431 platform_device_register(&dm365_mdio_device);
Sandeep Paulraj8ed0a9d2009-06-20 12:23:39 -04001432 platform_device_register(&dm365_emac_device);
Cyril Chemparathyd22960c2010-09-15 10:11:22 -04001433
Sekhar Nori12330902014-02-26 10:29:43 +05301434 ret = davinci_init_wdt();
1435 if (ret)
1436 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1437
1438 return ret;
Sandeep Paulraj8ed0a9d2009-06-20 12:23:39 -04001439}
1440postcore_initcall(dm365_init_devices);