Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 34 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 35 | #include <linux/pci.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 36 | |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 37 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
| 38 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 39 | static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); |
| 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
| 41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 42 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
| 43 | int write); |
| 44 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 45 | uint64_t offset, |
| 46 | uint64_t size); |
| 47 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 48 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 49 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
| 50 | unsigned alignment); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 51 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 52 | static int i915_gem_evict_something(struct drm_device *dev, int min_size); |
| 53 | static int i915_gem_evict_from_list(struct drm_device *dev, |
| 54 | struct list_head *head); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 55 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 56 | struct drm_i915_gem_pwrite *args, |
| 57 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 58 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 59 | static LIST_HEAD(shrink_list); |
| 60 | static DEFINE_SPINLOCK(shrink_list_lock); |
| 61 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 62 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
| 63 | unsigned long end) |
| 64 | { |
| 65 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 66 | |
| 67 | if (start >= end || |
| 68 | (start & (PAGE_SIZE - 1)) != 0 || |
| 69 | (end & (PAGE_SIZE - 1)) != 0) { |
| 70 | return -EINVAL; |
| 71 | } |
| 72 | |
| 73 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
| 74 | end - start); |
| 75 | |
| 76 | dev->gtt_total = (uint32_t) (end - start); |
| 77 | |
| 78 | return 0; |
| 79 | } |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 80 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 81 | int |
| 82 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 83 | struct drm_file *file_priv) |
| 84 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 85 | struct drm_i915_gem_init *args = data; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 86 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 87 | |
| 88 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 89 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 90 | mutex_unlock(&dev->struct_mutex); |
| 91 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 92 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 93 | } |
| 94 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 95 | int |
| 96 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 97 | struct drm_file *file_priv) |
| 98 | { |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 99 | struct drm_i915_gem_get_aperture *args = data; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 100 | |
| 101 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 102 | return -ENODEV; |
| 103 | |
| 104 | args->aper_size = dev->gtt_total; |
Keith Packard | 2678d9d | 2008-11-20 22:54:54 -0800 | [diff] [blame] | 105 | args->aper_available_size = (args->aper_size - |
| 106 | atomic_read(&dev->pin_memory)); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 107 | |
| 108 | return 0; |
| 109 | } |
| 110 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 111 | |
| 112 | /** |
| 113 | * Creates a new mm object and returns a handle to it. |
| 114 | */ |
| 115 | int |
| 116 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 117 | struct drm_file *file_priv) |
| 118 | { |
| 119 | struct drm_i915_gem_create *args = data; |
| 120 | struct drm_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 121 | int ret; |
| 122 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 123 | |
| 124 | args->size = roundup(args->size, PAGE_SIZE); |
| 125 | |
| 126 | /* Allocate the new object */ |
| 127 | obj = drm_gem_object_alloc(dev, args->size); |
| 128 | if (obj == NULL) |
| 129 | return -ENOMEM; |
| 130 | |
| 131 | ret = drm_gem_handle_create(file_priv, obj, &handle); |
| 132 | mutex_lock(&dev->struct_mutex); |
| 133 | drm_gem_object_handle_unreference(obj); |
| 134 | mutex_unlock(&dev->struct_mutex); |
| 135 | |
| 136 | if (ret) |
| 137 | return ret; |
| 138 | |
| 139 | args->handle = handle; |
| 140 | |
| 141 | return 0; |
| 142 | } |
| 143 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 144 | static inline int |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 145 | fast_shmem_read(struct page **pages, |
| 146 | loff_t page_base, int page_offset, |
| 147 | char __user *data, |
| 148 | int length) |
| 149 | { |
| 150 | char __iomem *vaddr; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 151 | int unwritten; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 152 | |
| 153 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); |
| 154 | if (vaddr == NULL) |
| 155 | return -ENOMEM; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 156 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 157 | kunmap_atomic(vaddr, KM_USER0); |
| 158 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 159 | if (unwritten) |
| 160 | return -EFAULT; |
| 161 | |
| 162 | return 0; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 163 | } |
| 164 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 165 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
| 166 | { |
| 167 | drm_i915_private_t *dev_priv = obj->dev->dev_private; |
| 168 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 169 | |
| 170 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 171 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 172 | } |
| 173 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 174 | static inline int |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 175 | slow_shmem_copy(struct page *dst_page, |
| 176 | int dst_offset, |
| 177 | struct page *src_page, |
| 178 | int src_offset, |
| 179 | int length) |
| 180 | { |
| 181 | char *dst_vaddr, *src_vaddr; |
| 182 | |
| 183 | dst_vaddr = kmap_atomic(dst_page, KM_USER0); |
| 184 | if (dst_vaddr == NULL) |
| 185 | return -ENOMEM; |
| 186 | |
| 187 | src_vaddr = kmap_atomic(src_page, KM_USER1); |
| 188 | if (src_vaddr == NULL) { |
| 189 | kunmap_atomic(dst_vaddr, KM_USER0); |
| 190 | return -ENOMEM; |
| 191 | } |
| 192 | |
| 193 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
| 194 | |
| 195 | kunmap_atomic(src_vaddr, KM_USER1); |
| 196 | kunmap_atomic(dst_vaddr, KM_USER0); |
| 197 | |
| 198 | return 0; |
| 199 | } |
| 200 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 201 | static inline int |
| 202 | slow_shmem_bit17_copy(struct page *gpu_page, |
| 203 | int gpu_offset, |
| 204 | struct page *cpu_page, |
| 205 | int cpu_offset, |
| 206 | int length, |
| 207 | int is_read) |
| 208 | { |
| 209 | char *gpu_vaddr, *cpu_vaddr; |
| 210 | |
| 211 | /* Use the unswizzled path if this page isn't affected. */ |
| 212 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
| 213 | if (is_read) |
| 214 | return slow_shmem_copy(cpu_page, cpu_offset, |
| 215 | gpu_page, gpu_offset, length); |
| 216 | else |
| 217 | return slow_shmem_copy(gpu_page, gpu_offset, |
| 218 | cpu_page, cpu_offset, length); |
| 219 | } |
| 220 | |
| 221 | gpu_vaddr = kmap_atomic(gpu_page, KM_USER0); |
| 222 | if (gpu_vaddr == NULL) |
| 223 | return -ENOMEM; |
| 224 | |
| 225 | cpu_vaddr = kmap_atomic(cpu_page, KM_USER1); |
| 226 | if (cpu_vaddr == NULL) { |
| 227 | kunmap_atomic(gpu_vaddr, KM_USER0); |
| 228 | return -ENOMEM; |
| 229 | } |
| 230 | |
| 231 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
| 232 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
| 233 | */ |
| 234 | while (length > 0) { |
| 235 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 236 | int this_length = min(cacheline_end - gpu_offset, length); |
| 237 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 238 | |
| 239 | if (is_read) { |
| 240 | memcpy(cpu_vaddr + cpu_offset, |
| 241 | gpu_vaddr + swizzled_gpu_offset, |
| 242 | this_length); |
| 243 | } else { |
| 244 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
| 245 | cpu_vaddr + cpu_offset, |
| 246 | this_length); |
| 247 | } |
| 248 | cpu_offset += this_length; |
| 249 | gpu_offset += this_length; |
| 250 | length -= this_length; |
| 251 | } |
| 252 | |
| 253 | kunmap_atomic(cpu_vaddr, KM_USER1); |
| 254 | kunmap_atomic(gpu_vaddr, KM_USER0); |
| 255 | |
| 256 | return 0; |
| 257 | } |
| 258 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 259 | /** |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 260 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
| 261 | * from the backing pages of the object to the user's address space. On a |
| 262 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
| 263 | */ |
| 264 | static int |
| 265 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 266 | struct drm_i915_gem_pread *args, |
| 267 | struct drm_file *file_priv) |
| 268 | { |
| 269 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 270 | ssize_t remain; |
| 271 | loff_t offset, page_base; |
| 272 | char __user *user_data; |
| 273 | int page_offset, page_length; |
| 274 | int ret; |
| 275 | |
| 276 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 277 | remain = args->size; |
| 278 | |
| 279 | mutex_lock(&dev->struct_mutex); |
| 280 | |
| 281 | ret = i915_gem_object_get_pages(obj); |
| 282 | if (ret != 0) |
| 283 | goto fail_unlock; |
| 284 | |
| 285 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, |
| 286 | args->size); |
| 287 | if (ret != 0) |
| 288 | goto fail_put_pages; |
| 289 | |
| 290 | obj_priv = obj->driver_private; |
| 291 | offset = args->offset; |
| 292 | |
| 293 | while (remain > 0) { |
| 294 | /* Operation in this page |
| 295 | * |
| 296 | * page_base = page offset within aperture |
| 297 | * page_offset = offset within page |
| 298 | * page_length = bytes to copy for this page |
| 299 | */ |
| 300 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 301 | page_offset = offset & (PAGE_SIZE-1); |
| 302 | page_length = remain; |
| 303 | if ((page_offset + remain) > PAGE_SIZE) |
| 304 | page_length = PAGE_SIZE - page_offset; |
| 305 | |
| 306 | ret = fast_shmem_read(obj_priv->pages, |
| 307 | page_base, page_offset, |
| 308 | user_data, page_length); |
| 309 | if (ret) |
| 310 | goto fail_put_pages; |
| 311 | |
| 312 | remain -= page_length; |
| 313 | user_data += page_length; |
| 314 | offset += page_length; |
| 315 | } |
| 316 | |
| 317 | fail_put_pages: |
| 318 | i915_gem_object_put_pages(obj); |
| 319 | fail_unlock: |
| 320 | mutex_unlock(&dev->struct_mutex); |
| 321 | |
| 322 | return ret; |
| 323 | } |
| 324 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 325 | static inline gfp_t |
| 326 | i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj) |
| 327 | { |
| 328 | return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping); |
| 329 | } |
| 330 | |
| 331 | static inline void |
| 332 | i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp) |
| 333 | { |
| 334 | mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp); |
| 335 | } |
| 336 | |
| 337 | static int |
| 338 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) |
| 339 | { |
| 340 | int ret; |
| 341 | |
| 342 | ret = i915_gem_object_get_pages(obj); |
| 343 | |
| 344 | /* If we've insufficient memory to map in the pages, attempt |
| 345 | * to make some space by throwing out some old buffers. |
| 346 | */ |
| 347 | if (ret == -ENOMEM) { |
| 348 | struct drm_device *dev = obj->dev; |
| 349 | gfp_t gfp; |
| 350 | |
| 351 | ret = i915_gem_evict_something(dev, obj->size); |
| 352 | if (ret) |
| 353 | return ret; |
| 354 | |
| 355 | gfp = i915_gem_object_get_page_gfp_mask(obj); |
| 356 | i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY); |
| 357 | ret = i915_gem_object_get_pages(obj); |
| 358 | i915_gem_object_set_page_gfp_mask (obj, gfp); |
| 359 | } |
| 360 | |
| 361 | return ret; |
| 362 | } |
| 363 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 364 | /** |
| 365 | * This is the fallback shmem pread path, which allocates temporary storage |
| 366 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
| 367 | * can copy out of the object's backing pages while holding the struct mutex |
| 368 | * and not take page faults. |
| 369 | */ |
| 370 | static int |
| 371 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 372 | struct drm_i915_gem_pread *args, |
| 373 | struct drm_file *file_priv) |
| 374 | { |
| 375 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 376 | struct mm_struct *mm = current->mm; |
| 377 | struct page **user_pages; |
| 378 | ssize_t remain; |
| 379 | loff_t offset, pinned_pages, i; |
| 380 | loff_t first_data_page, last_data_page, num_pages; |
| 381 | int shmem_page_index, shmem_page_offset; |
| 382 | int data_page_index, data_page_offset; |
| 383 | int page_length; |
| 384 | int ret; |
| 385 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 386 | int do_bit17_swizzling; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 387 | |
| 388 | remain = args->size; |
| 389 | |
| 390 | /* Pin the user pages containing the data. We can't fault while |
| 391 | * holding the struct mutex, yet we want to hold it while |
| 392 | * dereferencing the user data. |
| 393 | */ |
| 394 | first_data_page = data_ptr / PAGE_SIZE; |
| 395 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 396 | num_pages = last_data_page - first_data_page + 1; |
| 397 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 398 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 399 | if (user_pages == NULL) |
| 400 | return -ENOMEM; |
| 401 | |
| 402 | down_read(&mm->mmap_sem); |
| 403 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
Eric Anholt | e5e9ecd | 2009-04-07 16:01:22 -0700 | [diff] [blame] | 404 | num_pages, 1, 0, user_pages, NULL); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 405 | up_read(&mm->mmap_sem); |
| 406 | if (pinned_pages < num_pages) { |
| 407 | ret = -EFAULT; |
| 408 | goto fail_put_user_pages; |
| 409 | } |
| 410 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 411 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 412 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 413 | mutex_lock(&dev->struct_mutex); |
| 414 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 415 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 416 | if (ret) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 417 | goto fail_unlock; |
| 418 | |
| 419 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, |
| 420 | args->size); |
| 421 | if (ret != 0) |
| 422 | goto fail_put_pages; |
| 423 | |
| 424 | obj_priv = obj->driver_private; |
| 425 | offset = args->offset; |
| 426 | |
| 427 | while (remain > 0) { |
| 428 | /* Operation in this page |
| 429 | * |
| 430 | * shmem_page_index = page number within shmem file |
| 431 | * shmem_page_offset = offset within page in shmem file |
| 432 | * data_page_index = page number in get_user_pages return |
| 433 | * data_page_offset = offset with data_page_index page. |
| 434 | * page_length = bytes to copy for this page |
| 435 | */ |
| 436 | shmem_page_index = offset / PAGE_SIZE; |
| 437 | shmem_page_offset = offset & ~PAGE_MASK; |
| 438 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 439 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 440 | |
| 441 | page_length = remain; |
| 442 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 443 | page_length = PAGE_SIZE - shmem_page_offset; |
| 444 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 445 | page_length = PAGE_SIZE - data_page_offset; |
| 446 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 447 | if (do_bit17_swizzling) { |
| 448 | ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
| 449 | shmem_page_offset, |
| 450 | user_pages[data_page_index], |
| 451 | data_page_offset, |
| 452 | page_length, |
| 453 | 1); |
| 454 | } else { |
| 455 | ret = slow_shmem_copy(user_pages[data_page_index], |
| 456 | data_page_offset, |
| 457 | obj_priv->pages[shmem_page_index], |
| 458 | shmem_page_offset, |
| 459 | page_length); |
| 460 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 461 | if (ret) |
| 462 | goto fail_put_pages; |
| 463 | |
| 464 | remain -= page_length; |
| 465 | data_ptr += page_length; |
| 466 | offset += page_length; |
| 467 | } |
| 468 | |
| 469 | fail_put_pages: |
| 470 | i915_gem_object_put_pages(obj); |
| 471 | fail_unlock: |
| 472 | mutex_unlock(&dev->struct_mutex); |
| 473 | fail_put_user_pages: |
| 474 | for (i = 0; i < pinned_pages; i++) { |
| 475 | SetPageDirty(user_pages[i]); |
| 476 | page_cache_release(user_pages[i]); |
| 477 | } |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 478 | drm_free_large(user_pages); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 479 | |
| 480 | return ret; |
| 481 | } |
| 482 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 483 | /** |
| 484 | * Reads data from the object referenced by handle. |
| 485 | * |
| 486 | * On error, the contents of *data are undefined. |
| 487 | */ |
| 488 | int |
| 489 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 490 | struct drm_file *file_priv) |
| 491 | { |
| 492 | struct drm_i915_gem_pread *args = data; |
| 493 | struct drm_gem_object *obj; |
| 494 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 495 | int ret; |
| 496 | |
| 497 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 498 | if (obj == NULL) |
| 499 | return -EBADF; |
| 500 | obj_priv = obj->driver_private; |
| 501 | |
| 502 | /* Bounds check source. |
| 503 | * |
| 504 | * XXX: This could use review for overflow issues... |
| 505 | */ |
| 506 | if (args->offset > obj->size || args->size > obj->size || |
| 507 | args->offset + args->size > obj->size) { |
| 508 | drm_gem_object_unreference(obj); |
| 509 | return -EINVAL; |
| 510 | } |
| 511 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 512 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 513 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 514 | } else { |
| 515 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
| 516 | if (ret != 0) |
| 517 | ret = i915_gem_shmem_pread_slow(dev, obj, args, |
| 518 | file_priv); |
| 519 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 520 | |
| 521 | drm_gem_object_unreference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 522 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 523 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 524 | } |
| 525 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 526 | /* This is the fast write path which cannot handle |
| 527 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 528 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 529 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 530 | static inline int |
| 531 | fast_user_write(struct io_mapping *mapping, |
| 532 | loff_t page_base, int page_offset, |
| 533 | char __user *user_data, |
| 534 | int length) |
| 535 | { |
| 536 | char *vaddr_atomic; |
| 537 | unsigned long unwritten; |
| 538 | |
| 539 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
| 540 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 541 | user_data, length); |
| 542 | io_mapping_unmap_atomic(vaddr_atomic); |
| 543 | if (unwritten) |
| 544 | return -EFAULT; |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 545 | return 0; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 546 | } |
| 547 | |
| 548 | /* Here's the write path which can sleep for |
| 549 | * page faults |
| 550 | */ |
| 551 | |
| 552 | static inline int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 553 | slow_kernel_write(struct io_mapping *mapping, |
| 554 | loff_t gtt_base, int gtt_offset, |
| 555 | struct page *user_page, int user_offset, |
| 556 | int length) |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 557 | { |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 558 | char *src_vaddr, *dst_vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 559 | unsigned long unwritten; |
| 560 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 561 | dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base); |
| 562 | src_vaddr = kmap_atomic(user_page, KM_USER1); |
| 563 | unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset, |
| 564 | src_vaddr + user_offset, |
| 565 | length); |
| 566 | kunmap_atomic(src_vaddr, KM_USER1); |
| 567 | io_mapping_unmap_atomic(dst_vaddr); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 568 | if (unwritten) |
| 569 | return -EFAULT; |
| 570 | return 0; |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 571 | } |
| 572 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 573 | static inline int |
| 574 | fast_shmem_write(struct page **pages, |
| 575 | loff_t page_base, int page_offset, |
| 576 | char __user *data, |
| 577 | int length) |
| 578 | { |
| 579 | char __iomem *vaddr; |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 580 | unsigned long unwritten; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 581 | |
| 582 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); |
| 583 | if (vaddr == NULL) |
| 584 | return -ENOMEM; |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 585 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 586 | kunmap_atomic(vaddr, KM_USER0); |
| 587 | |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 588 | if (unwritten) |
| 589 | return -EFAULT; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 590 | return 0; |
| 591 | } |
| 592 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 593 | /** |
| 594 | * This is the fast pwrite path, where we copy the data directly from the |
| 595 | * user into the GTT, uncached. |
| 596 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 597 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 598 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 599 | struct drm_i915_gem_pwrite *args, |
| 600 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 601 | { |
| 602 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 603 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 604 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 605 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 606 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 607 | int page_offset, page_length; |
| 608 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 609 | |
| 610 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 611 | remain = args->size; |
| 612 | if (!access_ok(VERIFY_READ, user_data, remain)) |
| 613 | return -EFAULT; |
| 614 | |
| 615 | |
| 616 | mutex_lock(&dev->struct_mutex); |
| 617 | ret = i915_gem_object_pin(obj, 0); |
| 618 | if (ret) { |
| 619 | mutex_unlock(&dev->struct_mutex); |
| 620 | return ret; |
| 621 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 622 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 623 | if (ret) |
| 624 | goto fail; |
| 625 | |
| 626 | obj_priv = obj->driver_private; |
| 627 | offset = obj_priv->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 628 | |
| 629 | while (remain > 0) { |
| 630 | /* Operation in this page |
| 631 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 632 | * page_base = page offset within aperture |
| 633 | * page_offset = offset within page |
| 634 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 635 | */ |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 636 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 637 | page_offset = offset & (PAGE_SIZE-1); |
| 638 | page_length = remain; |
| 639 | if ((page_offset + remain) > PAGE_SIZE) |
| 640 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 641 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 642 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, |
| 643 | page_offset, user_data, page_length); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 644 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 645 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 646 | * source page isn't available. Return the error and we'll |
| 647 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 648 | */ |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 649 | if (ret) |
| 650 | goto fail; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 651 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 652 | remain -= page_length; |
| 653 | user_data += page_length; |
| 654 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 655 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 656 | |
| 657 | fail: |
| 658 | i915_gem_object_unpin(obj); |
| 659 | mutex_unlock(&dev->struct_mutex); |
| 660 | |
| 661 | return ret; |
| 662 | } |
| 663 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 664 | /** |
| 665 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin |
| 666 | * the memory and maps it using kmap_atomic for copying. |
| 667 | * |
| 668 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU |
| 669 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). |
| 670 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 671 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 672 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 673 | struct drm_i915_gem_pwrite *args, |
| 674 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 675 | { |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 676 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 677 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 678 | ssize_t remain; |
| 679 | loff_t gtt_page_base, offset; |
| 680 | loff_t first_data_page, last_data_page, num_pages; |
| 681 | loff_t pinned_pages, i; |
| 682 | struct page **user_pages; |
| 683 | struct mm_struct *mm = current->mm; |
| 684 | int gtt_page_offset, data_page_offset, data_page_index, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 685 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 686 | uint64_t data_ptr = args->data_ptr; |
| 687 | |
| 688 | remain = args->size; |
| 689 | |
| 690 | /* Pin the user pages containing the data. We can't fault while |
| 691 | * holding the struct mutex, and all of the pwrite implementations |
| 692 | * want to hold it while dereferencing the user data. |
| 693 | */ |
| 694 | first_data_page = data_ptr / PAGE_SIZE; |
| 695 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 696 | num_pages = last_data_page - first_data_page + 1; |
| 697 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 698 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 699 | if (user_pages == NULL) |
| 700 | return -ENOMEM; |
| 701 | |
| 702 | down_read(&mm->mmap_sem); |
| 703 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 704 | num_pages, 0, 0, user_pages, NULL); |
| 705 | up_read(&mm->mmap_sem); |
| 706 | if (pinned_pages < num_pages) { |
| 707 | ret = -EFAULT; |
| 708 | goto out_unpin_pages; |
| 709 | } |
| 710 | |
| 711 | mutex_lock(&dev->struct_mutex); |
| 712 | ret = i915_gem_object_pin(obj, 0); |
| 713 | if (ret) |
| 714 | goto out_unlock; |
| 715 | |
| 716 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 717 | if (ret) |
| 718 | goto out_unpin_object; |
| 719 | |
| 720 | obj_priv = obj->driver_private; |
| 721 | offset = obj_priv->gtt_offset + args->offset; |
| 722 | |
| 723 | while (remain > 0) { |
| 724 | /* Operation in this page |
| 725 | * |
| 726 | * gtt_page_base = page offset within aperture |
| 727 | * gtt_page_offset = offset within page in aperture |
| 728 | * data_page_index = page number in get_user_pages return |
| 729 | * data_page_offset = offset with data_page_index page. |
| 730 | * page_length = bytes to copy for this page |
| 731 | */ |
| 732 | gtt_page_base = offset & PAGE_MASK; |
| 733 | gtt_page_offset = offset & ~PAGE_MASK; |
| 734 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 735 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 736 | |
| 737 | page_length = remain; |
| 738 | if ((gtt_page_offset + page_length) > PAGE_SIZE) |
| 739 | page_length = PAGE_SIZE - gtt_page_offset; |
| 740 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 741 | page_length = PAGE_SIZE - data_page_offset; |
| 742 | |
| 743 | ret = slow_kernel_write(dev_priv->mm.gtt_mapping, |
| 744 | gtt_page_base, gtt_page_offset, |
| 745 | user_pages[data_page_index], |
| 746 | data_page_offset, |
| 747 | page_length); |
| 748 | |
| 749 | /* If we get a fault while copying data, then (presumably) our |
| 750 | * source page isn't available. Return the error and we'll |
| 751 | * retry in the slow path. |
| 752 | */ |
| 753 | if (ret) |
| 754 | goto out_unpin_object; |
| 755 | |
| 756 | remain -= page_length; |
| 757 | offset += page_length; |
| 758 | data_ptr += page_length; |
| 759 | } |
| 760 | |
| 761 | out_unpin_object: |
| 762 | i915_gem_object_unpin(obj); |
| 763 | out_unlock: |
| 764 | mutex_unlock(&dev->struct_mutex); |
| 765 | out_unpin_pages: |
| 766 | for (i = 0; i < pinned_pages; i++) |
| 767 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 768 | drm_free_large(user_pages); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 769 | |
| 770 | return ret; |
| 771 | } |
| 772 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 773 | /** |
| 774 | * This is the fast shmem pwrite path, which attempts to directly |
| 775 | * copy_from_user into the kmapped pages backing the object. |
| 776 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 777 | static int |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 778 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 779 | struct drm_i915_gem_pwrite *args, |
| 780 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 781 | { |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 782 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 783 | ssize_t remain; |
| 784 | loff_t offset, page_base; |
| 785 | char __user *user_data; |
| 786 | int page_offset, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 787 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 788 | |
| 789 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 790 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 791 | |
| 792 | mutex_lock(&dev->struct_mutex); |
| 793 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 794 | ret = i915_gem_object_get_pages(obj); |
| 795 | if (ret != 0) |
| 796 | goto fail_unlock; |
| 797 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 798 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 799 | if (ret != 0) |
| 800 | goto fail_put_pages; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 801 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 802 | obj_priv = obj->driver_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 803 | offset = args->offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 804 | obj_priv->dirty = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 805 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 806 | while (remain > 0) { |
| 807 | /* Operation in this page |
| 808 | * |
| 809 | * page_base = page offset within aperture |
| 810 | * page_offset = offset within page |
| 811 | * page_length = bytes to copy for this page |
| 812 | */ |
| 813 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 814 | page_offset = offset & (PAGE_SIZE-1); |
| 815 | page_length = remain; |
| 816 | if ((page_offset + remain) > PAGE_SIZE) |
| 817 | page_length = PAGE_SIZE - page_offset; |
| 818 | |
| 819 | ret = fast_shmem_write(obj_priv->pages, |
| 820 | page_base, page_offset, |
| 821 | user_data, page_length); |
| 822 | if (ret) |
| 823 | goto fail_put_pages; |
| 824 | |
| 825 | remain -= page_length; |
| 826 | user_data += page_length; |
| 827 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 828 | } |
| 829 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 830 | fail_put_pages: |
| 831 | i915_gem_object_put_pages(obj); |
| 832 | fail_unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 833 | mutex_unlock(&dev->struct_mutex); |
| 834 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 835 | return ret; |
| 836 | } |
| 837 | |
| 838 | /** |
| 839 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin |
| 840 | * the memory and maps it using kmap_atomic for copying. |
| 841 | * |
| 842 | * This avoids taking mmap_sem for faulting on the user's address while the |
| 843 | * struct_mutex is held. |
| 844 | */ |
| 845 | static int |
| 846 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 847 | struct drm_i915_gem_pwrite *args, |
| 848 | struct drm_file *file_priv) |
| 849 | { |
| 850 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 851 | struct mm_struct *mm = current->mm; |
| 852 | struct page **user_pages; |
| 853 | ssize_t remain; |
| 854 | loff_t offset, pinned_pages, i; |
| 855 | loff_t first_data_page, last_data_page, num_pages; |
| 856 | int shmem_page_index, shmem_page_offset; |
| 857 | int data_page_index, data_page_offset; |
| 858 | int page_length; |
| 859 | int ret; |
| 860 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 861 | int do_bit17_swizzling; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 862 | |
| 863 | remain = args->size; |
| 864 | |
| 865 | /* Pin the user pages containing the data. We can't fault while |
| 866 | * holding the struct mutex, and all of the pwrite implementations |
| 867 | * want to hold it while dereferencing the user data. |
| 868 | */ |
| 869 | first_data_page = data_ptr / PAGE_SIZE; |
| 870 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 871 | num_pages = last_data_page - first_data_page + 1; |
| 872 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 873 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 874 | if (user_pages == NULL) |
| 875 | return -ENOMEM; |
| 876 | |
| 877 | down_read(&mm->mmap_sem); |
| 878 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 879 | num_pages, 0, 0, user_pages, NULL); |
| 880 | up_read(&mm->mmap_sem); |
| 881 | if (pinned_pages < num_pages) { |
| 882 | ret = -EFAULT; |
| 883 | goto fail_put_user_pages; |
| 884 | } |
| 885 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 886 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 887 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 888 | mutex_lock(&dev->struct_mutex); |
| 889 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 890 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 891 | if (ret) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 892 | goto fail_unlock; |
| 893 | |
| 894 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 895 | if (ret != 0) |
| 896 | goto fail_put_pages; |
| 897 | |
| 898 | obj_priv = obj->driver_private; |
| 899 | offset = args->offset; |
| 900 | obj_priv->dirty = 1; |
| 901 | |
| 902 | while (remain > 0) { |
| 903 | /* Operation in this page |
| 904 | * |
| 905 | * shmem_page_index = page number within shmem file |
| 906 | * shmem_page_offset = offset within page in shmem file |
| 907 | * data_page_index = page number in get_user_pages return |
| 908 | * data_page_offset = offset with data_page_index page. |
| 909 | * page_length = bytes to copy for this page |
| 910 | */ |
| 911 | shmem_page_index = offset / PAGE_SIZE; |
| 912 | shmem_page_offset = offset & ~PAGE_MASK; |
| 913 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 914 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 915 | |
| 916 | page_length = remain; |
| 917 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 918 | page_length = PAGE_SIZE - shmem_page_offset; |
| 919 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 920 | page_length = PAGE_SIZE - data_page_offset; |
| 921 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 922 | if (do_bit17_swizzling) { |
| 923 | ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
| 924 | shmem_page_offset, |
| 925 | user_pages[data_page_index], |
| 926 | data_page_offset, |
| 927 | page_length, |
| 928 | 0); |
| 929 | } else { |
| 930 | ret = slow_shmem_copy(obj_priv->pages[shmem_page_index], |
| 931 | shmem_page_offset, |
| 932 | user_pages[data_page_index], |
| 933 | data_page_offset, |
| 934 | page_length); |
| 935 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 936 | if (ret) |
| 937 | goto fail_put_pages; |
| 938 | |
| 939 | remain -= page_length; |
| 940 | data_ptr += page_length; |
| 941 | offset += page_length; |
| 942 | } |
| 943 | |
| 944 | fail_put_pages: |
| 945 | i915_gem_object_put_pages(obj); |
| 946 | fail_unlock: |
| 947 | mutex_unlock(&dev->struct_mutex); |
| 948 | fail_put_user_pages: |
| 949 | for (i = 0; i < pinned_pages; i++) |
| 950 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 951 | drm_free_large(user_pages); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 952 | |
| 953 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 954 | } |
| 955 | |
| 956 | /** |
| 957 | * Writes data to the object referenced by handle. |
| 958 | * |
| 959 | * On error, the contents of the buffer that were to be modified are undefined. |
| 960 | */ |
| 961 | int |
| 962 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 963 | struct drm_file *file_priv) |
| 964 | { |
| 965 | struct drm_i915_gem_pwrite *args = data; |
| 966 | struct drm_gem_object *obj; |
| 967 | struct drm_i915_gem_object *obj_priv; |
| 968 | int ret = 0; |
| 969 | |
| 970 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 971 | if (obj == NULL) |
| 972 | return -EBADF; |
| 973 | obj_priv = obj->driver_private; |
| 974 | |
| 975 | /* Bounds check destination. |
| 976 | * |
| 977 | * XXX: This could use review for overflow issues... |
| 978 | */ |
| 979 | if (args->offset > obj->size || args->size > obj->size || |
| 980 | args->offset + args->size > obj->size) { |
| 981 | drm_gem_object_unreference(obj); |
| 982 | return -EINVAL; |
| 983 | } |
| 984 | |
| 985 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 986 | * it would end up going through the fenced access, and we'll get |
| 987 | * different detiling behavior between reading and writing. |
| 988 | * pread/pwrite currently are reading and writing from the CPU |
| 989 | * perspective, requiring manual detiling by the client. |
| 990 | */ |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 991 | if (obj_priv->phys_obj) |
| 992 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); |
| 993 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 994 | dev->gtt_total != 0) { |
| 995 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); |
| 996 | if (ret == -EFAULT) { |
| 997 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, |
| 998 | file_priv); |
| 999 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1000 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
| 1001 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1002 | } else { |
| 1003 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); |
| 1004 | if (ret == -EFAULT) { |
| 1005 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, |
| 1006 | file_priv); |
| 1007 | } |
| 1008 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1009 | |
| 1010 | #if WATCH_PWRITE |
| 1011 | if (ret) |
| 1012 | DRM_INFO("pwrite failed %d\n", ret); |
| 1013 | #endif |
| 1014 | |
| 1015 | drm_gem_object_unreference(obj); |
| 1016 | |
| 1017 | return ret; |
| 1018 | } |
| 1019 | |
| 1020 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1021 | * Called when user space prepares to use an object with the CPU, either |
| 1022 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1023 | */ |
| 1024 | int |
| 1025 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1026 | struct drm_file *file_priv) |
| 1027 | { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1028 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1029 | struct drm_i915_gem_set_domain *args = data; |
| 1030 | struct drm_gem_object *obj; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1031 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1032 | uint32_t read_domains = args->read_domains; |
| 1033 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1034 | int ret; |
| 1035 | |
| 1036 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1037 | return -ENODEV; |
| 1038 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1039 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1040 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1041 | return -EINVAL; |
| 1042 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1043 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1044 | return -EINVAL; |
| 1045 | |
| 1046 | /* Having something in the write domain implies it's in the read |
| 1047 | * domain, and only that read domain. Enforce that in the request. |
| 1048 | */ |
| 1049 | if (write_domain != 0 && read_domains != write_domain) |
| 1050 | return -EINVAL; |
| 1051 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1052 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1053 | if (obj == NULL) |
| 1054 | return -EBADF; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1055 | obj_priv = obj->driver_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1056 | |
| 1057 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1058 | |
| 1059 | intel_mark_busy(dev, obj); |
| 1060 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1061 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 1062 | DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1063 | obj, obj->size, read_domains, write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1064 | #endif |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1065 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1066 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1067 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1068 | /* Update the LRU on the fence for the CPU access that's |
| 1069 | * about to occur. |
| 1070 | */ |
| 1071 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
| 1072 | list_move_tail(&obj_priv->fence_list, |
| 1073 | &dev_priv->mm.fence_list); |
| 1074 | } |
| 1075 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1076 | /* Silently promote "you're not bound, there was nothing to do" |
| 1077 | * to success, since the client was just asking us to |
| 1078 | * make sure everything was done. |
| 1079 | */ |
| 1080 | if (ret == -EINVAL) |
| 1081 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1082 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1083 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1084 | } |
| 1085 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1086 | drm_gem_object_unreference(obj); |
| 1087 | mutex_unlock(&dev->struct_mutex); |
| 1088 | return ret; |
| 1089 | } |
| 1090 | |
| 1091 | /** |
| 1092 | * Called when user space has done writes to this buffer |
| 1093 | */ |
| 1094 | int |
| 1095 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1096 | struct drm_file *file_priv) |
| 1097 | { |
| 1098 | struct drm_i915_gem_sw_finish *args = data; |
| 1099 | struct drm_gem_object *obj; |
| 1100 | struct drm_i915_gem_object *obj_priv; |
| 1101 | int ret = 0; |
| 1102 | |
| 1103 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1104 | return -ENODEV; |
| 1105 | |
| 1106 | mutex_lock(&dev->struct_mutex); |
| 1107 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1108 | if (obj == NULL) { |
| 1109 | mutex_unlock(&dev->struct_mutex); |
| 1110 | return -EBADF; |
| 1111 | } |
| 1112 | |
| 1113 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 1114 | DRM_INFO("%s: sw_finish %d (%p %zd)\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1115 | __func__, args->handle, obj, obj->size); |
| 1116 | #endif |
| 1117 | obj_priv = obj->driver_private; |
| 1118 | |
| 1119 | /* Pinned buffers may be scanout, so flush the cache */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1120 | if (obj_priv->pin_count) |
| 1121 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1122 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1123 | drm_gem_object_unreference(obj); |
| 1124 | mutex_unlock(&dev->struct_mutex); |
| 1125 | return ret; |
| 1126 | } |
| 1127 | |
| 1128 | /** |
| 1129 | * Maps the contents of an object, returning the address it is mapped |
| 1130 | * into. |
| 1131 | * |
| 1132 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1133 | * imply a ref on the object itself. |
| 1134 | */ |
| 1135 | int |
| 1136 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1137 | struct drm_file *file_priv) |
| 1138 | { |
| 1139 | struct drm_i915_gem_mmap *args = data; |
| 1140 | struct drm_gem_object *obj; |
| 1141 | loff_t offset; |
| 1142 | unsigned long addr; |
| 1143 | |
| 1144 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1145 | return -ENODEV; |
| 1146 | |
| 1147 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1148 | if (obj == NULL) |
| 1149 | return -EBADF; |
| 1150 | |
| 1151 | offset = args->offset; |
| 1152 | |
| 1153 | down_write(¤t->mm->mmap_sem); |
| 1154 | addr = do_mmap(obj->filp, 0, args->size, |
| 1155 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1156 | args->offset); |
| 1157 | up_write(¤t->mm->mmap_sem); |
| 1158 | mutex_lock(&dev->struct_mutex); |
| 1159 | drm_gem_object_unreference(obj); |
| 1160 | mutex_unlock(&dev->struct_mutex); |
| 1161 | if (IS_ERR((void *)addr)) |
| 1162 | return addr; |
| 1163 | |
| 1164 | args->addr_ptr = (uint64_t) addr; |
| 1165 | |
| 1166 | return 0; |
| 1167 | } |
| 1168 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1169 | /** |
| 1170 | * i915_gem_fault - fault a page into the GTT |
| 1171 | * vma: VMA in question |
| 1172 | * vmf: fault info |
| 1173 | * |
| 1174 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1175 | * from userspace. The fault handler takes care of binding the object to |
| 1176 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1177 | * only if needed based on whether the old reg is still valid or the object |
| 1178 | * is tiled) and inserting a new PTE into the faulting process. |
| 1179 | * |
| 1180 | * Note that the faulting process may involve evicting existing objects |
| 1181 | * from the GTT and/or fence registers to make room. So performance may |
| 1182 | * suffer if the GTT working set is large or there are few fence registers |
| 1183 | * left. |
| 1184 | */ |
| 1185 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1186 | { |
| 1187 | struct drm_gem_object *obj = vma->vm_private_data; |
| 1188 | struct drm_device *dev = obj->dev; |
| 1189 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1190 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1191 | pgoff_t page_offset; |
| 1192 | unsigned long pfn; |
| 1193 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1194 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1195 | |
| 1196 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1197 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1198 | PAGE_SHIFT; |
| 1199 | |
| 1200 | /* Now bind it into the GTT if needed */ |
| 1201 | mutex_lock(&dev->struct_mutex); |
| 1202 | if (!obj_priv->gtt_space) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1203 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1204 | if (ret) { |
| 1205 | mutex_unlock(&dev->struct_mutex); |
| 1206 | return VM_FAULT_SIGBUS; |
| 1207 | } |
Chris Wilson | 4960aac | 2009-09-14 16:50:25 +0100 | [diff] [blame] | 1208 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
Kristian Høgsberg | 07f4f3e | 2009-05-27 14:37:28 -0400 | [diff] [blame] | 1209 | |
| 1210 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1211 | if (ret) { |
| 1212 | mutex_unlock(&dev->struct_mutex); |
| 1213 | return VM_FAULT_SIGBUS; |
| 1214 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1215 | } |
| 1216 | |
| 1217 | /* Need a new fence register? */ |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1218 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 1219 | ret = i915_gem_object_get_fence_reg(obj); |
Chris Wilson | 7d8d58b | 2009-02-04 14:15:10 +0000 | [diff] [blame] | 1220 | if (ret) { |
| 1221 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1222 | return VM_FAULT_SIGBUS; |
Chris Wilson | 7d8d58b | 2009-02-04 14:15:10 +0000 | [diff] [blame] | 1223 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1224 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1225 | |
| 1226 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
| 1227 | page_offset; |
| 1228 | |
| 1229 | /* Finally, remap it using the new GTT offset */ |
| 1230 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
| 1231 | |
| 1232 | mutex_unlock(&dev->struct_mutex); |
| 1233 | |
| 1234 | switch (ret) { |
| 1235 | case -ENOMEM: |
| 1236 | case -EAGAIN: |
| 1237 | return VM_FAULT_OOM; |
| 1238 | case -EFAULT: |
Jesse Barnes | 959b887 | 2009-03-20 14:16:33 -0700 | [diff] [blame] | 1239 | case -EINVAL: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1240 | return VM_FAULT_SIGBUS; |
| 1241 | default: |
| 1242 | return VM_FAULT_NOPAGE; |
| 1243 | } |
| 1244 | } |
| 1245 | |
| 1246 | /** |
| 1247 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 1248 | * @obj: obj in question |
| 1249 | * |
| 1250 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 1251 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 1252 | * up the object based on the offset and sets up the various memory mapping |
| 1253 | * structures. |
| 1254 | * |
| 1255 | * This routine allocates and attaches a fake offset for @obj. |
| 1256 | */ |
| 1257 | static int |
| 1258 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) |
| 1259 | { |
| 1260 | struct drm_device *dev = obj->dev; |
| 1261 | struct drm_gem_mm *mm = dev->mm_private; |
| 1262 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1263 | struct drm_map_list *list; |
Benjamin Herrenschmidt | f77d390 | 2009-02-02 16:55:46 +1100 | [diff] [blame] | 1264 | struct drm_local_map *map; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1265 | int ret = 0; |
| 1266 | |
| 1267 | /* Set the object up for mmap'ing */ |
| 1268 | list = &obj->map_list; |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1269 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1270 | if (!list->map) |
| 1271 | return -ENOMEM; |
| 1272 | |
| 1273 | map = list->map; |
| 1274 | map->type = _DRM_GEM; |
| 1275 | map->size = obj->size; |
| 1276 | map->handle = obj; |
| 1277 | |
| 1278 | /* Get a DRM GEM mmap offset allocated... */ |
| 1279 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
| 1280 | obj->size / PAGE_SIZE, 0, 0); |
| 1281 | if (!list->file_offset_node) { |
| 1282 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); |
| 1283 | ret = -ENOMEM; |
| 1284 | goto out_free_list; |
| 1285 | } |
| 1286 | |
| 1287 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
| 1288 | obj->size / PAGE_SIZE, 0); |
| 1289 | if (!list->file_offset_node) { |
| 1290 | ret = -ENOMEM; |
| 1291 | goto out_free_list; |
| 1292 | } |
| 1293 | |
| 1294 | list->hash.key = list->file_offset_node->start; |
| 1295 | if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) { |
| 1296 | DRM_ERROR("failed to add to map hash\n"); |
| 1297 | goto out_free_mm; |
| 1298 | } |
| 1299 | |
| 1300 | /* By now we should be all set, any drm_mmap request on the offset |
| 1301 | * below will get to our mmap & fault handler */ |
| 1302 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; |
| 1303 | |
| 1304 | return 0; |
| 1305 | |
| 1306 | out_free_mm: |
| 1307 | drm_mm_put_block(list->file_offset_node); |
| 1308 | out_free_list: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1309 | kfree(list->map); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1310 | |
| 1311 | return ret; |
| 1312 | } |
| 1313 | |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1314 | /** |
| 1315 | * i915_gem_release_mmap - remove physical page mappings |
| 1316 | * @obj: obj in question |
| 1317 | * |
| 1318 | * Preserve the reservation of the mmaping with the DRM core code, but |
| 1319 | * relinquish ownership of the pages back to the system. |
| 1320 | * |
| 1321 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1322 | * object through the GTT and then lose the fence register due to |
| 1323 | * resource pressure. Similarly if the object has been moved out of the |
| 1324 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1325 | * mapping will then trigger a page fault on the next user access, allowing |
| 1326 | * fixup by i915_gem_fault(). |
| 1327 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1328 | void |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1329 | i915_gem_release_mmap(struct drm_gem_object *obj) |
| 1330 | { |
| 1331 | struct drm_device *dev = obj->dev; |
| 1332 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1333 | |
| 1334 | if (dev->dev_mapping) |
| 1335 | unmap_mapping_range(dev->dev_mapping, |
| 1336 | obj_priv->mmap_offset, obj->size, 1); |
| 1337 | } |
| 1338 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1339 | static void |
| 1340 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) |
| 1341 | { |
| 1342 | struct drm_device *dev = obj->dev; |
| 1343 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1344 | struct drm_gem_mm *mm = dev->mm_private; |
| 1345 | struct drm_map_list *list; |
| 1346 | |
| 1347 | list = &obj->map_list; |
| 1348 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
| 1349 | |
| 1350 | if (list->file_offset_node) { |
| 1351 | drm_mm_put_block(list->file_offset_node); |
| 1352 | list->file_offset_node = NULL; |
| 1353 | } |
| 1354 | |
| 1355 | if (list->map) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1356 | kfree(list->map); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1357 | list->map = NULL; |
| 1358 | } |
| 1359 | |
| 1360 | obj_priv->mmap_offset = 0; |
| 1361 | } |
| 1362 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1363 | /** |
| 1364 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1365 | * @obj: object to check |
| 1366 | * |
| 1367 | * Return the required GTT alignment for an object, taking into account |
| 1368 | * potential fence register mapping if needed. |
| 1369 | */ |
| 1370 | static uint32_t |
| 1371 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) |
| 1372 | { |
| 1373 | struct drm_device *dev = obj->dev; |
| 1374 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1375 | int start, i; |
| 1376 | |
| 1377 | /* |
| 1378 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1379 | * if a fence register is needed for the object. |
| 1380 | */ |
| 1381 | if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE) |
| 1382 | return 4096; |
| 1383 | |
| 1384 | /* |
| 1385 | * Previous chips need to be aligned to the size of the smallest |
| 1386 | * fence register that can contain the object. |
| 1387 | */ |
| 1388 | if (IS_I9XX(dev)) |
| 1389 | start = 1024*1024; |
| 1390 | else |
| 1391 | start = 512*1024; |
| 1392 | |
| 1393 | for (i = start; i < obj->size; i <<= 1) |
| 1394 | ; |
| 1395 | |
| 1396 | return i; |
| 1397 | } |
| 1398 | |
| 1399 | /** |
| 1400 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1401 | * @dev: DRM device |
| 1402 | * @data: GTT mapping ioctl data |
| 1403 | * @file_priv: GEM object info |
| 1404 | * |
| 1405 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1406 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1407 | * up so we can get faults in the handler above. |
| 1408 | * |
| 1409 | * The fault handler will take care of binding the object into the GTT |
| 1410 | * (since it may have been evicted to make room for something), allocating |
| 1411 | * a fence register, and mapping the appropriate aperture address into |
| 1412 | * userspace. |
| 1413 | */ |
| 1414 | int |
| 1415 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1416 | struct drm_file *file_priv) |
| 1417 | { |
| 1418 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1419 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1420 | struct drm_gem_object *obj; |
| 1421 | struct drm_i915_gem_object *obj_priv; |
| 1422 | int ret; |
| 1423 | |
| 1424 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1425 | return -ENODEV; |
| 1426 | |
| 1427 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1428 | if (obj == NULL) |
| 1429 | return -EBADF; |
| 1430 | |
| 1431 | mutex_lock(&dev->struct_mutex); |
| 1432 | |
| 1433 | obj_priv = obj->driver_private; |
| 1434 | |
| 1435 | if (!obj_priv->mmap_offset) { |
| 1436 | ret = i915_gem_create_mmap_offset(obj); |
Chris Wilson | 13af106 | 2009-02-11 14:26:31 +0000 | [diff] [blame] | 1437 | if (ret) { |
| 1438 | drm_gem_object_unreference(obj); |
| 1439 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1440 | return ret; |
Chris Wilson | 13af106 | 2009-02-11 14:26:31 +0000 | [diff] [blame] | 1441 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1442 | } |
| 1443 | |
| 1444 | args->offset = obj_priv->mmap_offset; |
| 1445 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1446 | /* |
| 1447 | * Pull it into the GTT so that we have a page list (makes the |
| 1448 | * initial fault faster and any subsequent flushing possible). |
| 1449 | */ |
| 1450 | if (!obj_priv->agp_mem) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1451 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1452 | if (ret) { |
| 1453 | drm_gem_object_unreference(obj); |
| 1454 | mutex_unlock(&dev->struct_mutex); |
| 1455 | return ret; |
| 1456 | } |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 1457 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1458 | } |
| 1459 | |
| 1460 | drm_gem_object_unreference(obj); |
| 1461 | mutex_unlock(&dev->struct_mutex); |
| 1462 | |
| 1463 | return 0; |
| 1464 | } |
| 1465 | |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 1466 | void |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1467 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1468 | { |
| 1469 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1470 | int page_count = obj->size / PAGE_SIZE; |
| 1471 | int i; |
| 1472 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1473 | BUG_ON(obj_priv->pages_refcount == 0); |
| 1474 | |
| 1475 | if (--obj_priv->pages_refcount != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1476 | return; |
| 1477 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1478 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1479 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1480 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1481 | if (obj_priv->madv == I915_MADV_DONTNEED) |
| 1482 | obj_priv->dirty = 0; |
| 1483 | |
| 1484 | for (i = 0; i < page_count; i++) { |
| 1485 | if (obj_priv->pages[i] == NULL) |
| 1486 | break; |
| 1487 | |
| 1488 | if (obj_priv->dirty) |
| 1489 | set_page_dirty(obj_priv->pages[i]); |
| 1490 | |
| 1491 | if (obj_priv->madv == I915_MADV_WILLNEED) |
| 1492 | mark_page_accessed(obj_priv->pages[i]); |
| 1493 | |
| 1494 | page_cache_release(obj_priv->pages[i]); |
| 1495 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1496 | obj_priv->dirty = 0; |
| 1497 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 1498 | drm_free_large(obj_priv->pages); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1499 | obj_priv->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1500 | } |
| 1501 | |
| 1502 | static void |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1503 | i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1504 | { |
| 1505 | struct drm_device *dev = obj->dev; |
| 1506 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1507 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1508 | |
| 1509 | /* Add a reference if we're newly entering the active list. */ |
| 1510 | if (!obj_priv->active) { |
| 1511 | drm_gem_object_reference(obj); |
| 1512 | obj_priv->active = 1; |
| 1513 | } |
| 1514 | /* Move from whatever list we were on to the tail of execution. */ |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1515 | spin_lock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1516 | list_move_tail(&obj_priv->list, |
| 1517 | &dev_priv->mm.active_list); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1518 | spin_unlock(&dev_priv->mm.active_list_lock); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1519 | obj_priv->last_rendering_seqno = seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1520 | } |
| 1521 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1522 | static void |
| 1523 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) |
| 1524 | { |
| 1525 | struct drm_device *dev = obj->dev; |
| 1526 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1527 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1528 | |
| 1529 | BUG_ON(!obj_priv->active); |
| 1530 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); |
| 1531 | obj_priv->last_rendering_seqno = 0; |
| 1532 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1533 | |
| 1534 | static void |
| 1535 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) |
| 1536 | { |
| 1537 | struct drm_device *dev = obj->dev; |
| 1538 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1539 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1540 | |
| 1541 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 1542 | if (obj_priv->pin_count != 0) |
| 1543 | list_del_init(&obj_priv->list); |
| 1544 | else |
| 1545 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
| 1546 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1547 | obj_priv->last_rendering_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1548 | if (obj_priv->active) { |
| 1549 | obj_priv->active = 0; |
| 1550 | drm_gem_object_unreference(obj); |
| 1551 | } |
| 1552 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 1553 | } |
| 1554 | |
| 1555 | /** |
| 1556 | * Creates a new sequence number, emitting a write of it to the status page |
| 1557 | * plus an interrupt, which will trigger i915_user_interrupt_handler. |
| 1558 | * |
| 1559 | * Must be called with struct_lock held. |
| 1560 | * |
| 1561 | * Returned sequence numbers are nonzero on success. |
| 1562 | */ |
| 1563 | static uint32_t |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1564 | i915_add_request(struct drm_device *dev, struct drm_file *file_priv, |
| 1565 | uint32_t flush_domains) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1566 | { |
| 1567 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1568 | struct drm_i915_file_private *i915_file_priv = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1569 | struct drm_i915_gem_request *request; |
| 1570 | uint32_t seqno; |
| 1571 | int was_empty; |
| 1572 | RING_LOCALS; |
| 1573 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1574 | if (file_priv != NULL) |
| 1575 | i915_file_priv = file_priv->driver_priv; |
| 1576 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1577 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1578 | if (request == NULL) |
| 1579 | return 0; |
| 1580 | |
| 1581 | /* Grab the seqno we're going to make this request be, and bump the |
| 1582 | * next (skipping 0 so it can be the reserved no-seqno value). |
| 1583 | */ |
| 1584 | seqno = dev_priv->mm.next_gem_seqno; |
| 1585 | dev_priv->mm.next_gem_seqno++; |
| 1586 | if (dev_priv->mm.next_gem_seqno == 0) |
| 1587 | dev_priv->mm.next_gem_seqno++; |
| 1588 | |
| 1589 | BEGIN_LP_RING(4); |
| 1590 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 1591 | OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 1592 | OUT_RING(seqno); |
| 1593 | |
| 1594 | OUT_RING(MI_USER_INTERRUPT); |
| 1595 | ADVANCE_LP_RING(); |
| 1596 | |
| 1597 | DRM_DEBUG("%d\n", seqno); |
| 1598 | |
| 1599 | request->seqno = seqno; |
| 1600 | request->emitted_jiffies = jiffies; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1601 | was_empty = list_empty(&dev_priv->mm.request_list); |
| 1602 | list_add_tail(&request->list, &dev_priv->mm.request_list); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1603 | if (i915_file_priv) { |
| 1604 | list_add_tail(&request->client_list, |
| 1605 | &i915_file_priv->mm.request_list); |
| 1606 | } else { |
| 1607 | INIT_LIST_HEAD(&request->client_list); |
| 1608 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1609 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1610 | /* Associate any objects on the flushing list matching the write |
| 1611 | * domain we're flushing with our flush. |
| 1612 | */ |
| 1613 | if (flush_domains != 0) { |
| 1614 | struct drm_i915_gem_object *obj_priv, *next; |
| 1615 | |
| 1616 | list_for_each_entry_safe(obj_priv, next, |
| 1617 | &dev_priv->mm.flushing_list, list) { |
| 1618 | struct drm_gem_object *obj = obj_priv->obj; |
| 1619 | |
| 1620 | if ((obj->write_domain & flush_domains) == |
| 1621 | obj->write_domain) { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 1622 | uint32_t old_write_domain = obj->write_domain; |
| 1623 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1624 | obj->write_domain = 0; |
| 1625 | i915_gem_object_move_to_active(obj, seqno); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 1626 | |
| 1627 | trace_i915_gem_object_change_domain(obj, |
| 1628 | obj->read_domains, |
| 1629 | old_write_domain); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1630 | } |
| 1631 | } |
| 1632 | |
| 1633 | } |
| 1634 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1635 | if (!dev_priv->mm.suspended) { |
| 1636 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); |
| 1637 | if (was_empty) |
| 1638 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1639 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1640 | return seqno; |
| 1641 | } |
| 1642 | |
| 1643 | /** |
| 1644 | * Command execution barrier |
| 1645 | * |
| 1646 | * Ensures that all commands in the ring are finished |
| 1647 | * before signalling the CPU |
| 1648 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 1649 | static uint32_t |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1650 | i915_retire_commands(struct drm_device *dev) |
| 1651 | { |
| 1652 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1653 | uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
| 1654 | uint32_t flush_domains = 0; |
| 1655 | RING_LOCALS; |
| 1656 | |
| 1657 | /* The sampler always gets flushed on i965 (sigh) */ |
| 1658 | if (IS_I965G(dev)) |
| 1659 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
| 1660 | BEGIN_LP_RING(2); |
| 1661 | OUT_RING(cmd); |
| 1662 | OUT_RING(0); /* noop */ |
| 1663 | ADVANCE_LP_RING(); |
| 1664 | return flush_domains; |
| 1665 | } |
| 1666 | |
| 1667 | /** |
| 1668 | * Moves buffers associated only with the given active seqno from the active |
| 1669 | * to inactive list, potentially freeing them. |
| 1670 | */ |
| 1671 | static void |
| 1672 | i915_gem_retire_request(struct drm_device *dev, |
| 1673 | struct drm_i915_gem_request *request) |
| 1674 | { |
| 1675 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1676 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 1677 | trace_i915_gem_request_retire(dev, request->seqno); |
| 1678 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1679 | /* Move any buffers on the active list that are no longer referenced |
| 1680 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1681 | */ |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1682 | spin_lock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1683 | while (!list_empty(&dev_priv->mm.active_list)) { |
| 1684 | struct drm_gem_object *obj; |
| 1685 | struct drm_i915_gem_object *obj_priv; |
| 1686 | |
| 1687 | obj_priv = list_first_entry(&dev_priv->mm.active_list, |
| 1688 | struct drm_i915_gem_object, |
| 1689 | list); |
| 1690 | obj = obj_priv->obj; |
| 1691 | |
| 1692 | /* If the seqno being retired doesn't match the oldest in the |
| 1693 | * list, then the oldest in the list must still be newer than |
| 1694 | * this seqno. |
| 1695 | */ |
| 1696 | if (obj_priv->last_rendering_seqno != request->seqno) |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1697 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1698 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1699 | #if WATCH_LRU |
| 1700 | DRM_INFO("%s: retire %d moves to inactive list %p\n", |
| 1701 | __func__, request->seqno, obj); |
| 1702 | #endif |
| 1703 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1704 | if (obj->write_domain != 0) |
| 1705 | i915_gem_object_move_to_flushing(obj); |
Shaohua Li | 68c8434 | 2009-04-08 10:58:23 +0800 | [diff] [blame] | 1706 | else { |
| 1707 | /* Take a reference on the object so it won't be |
| 1708 | * freed while the spinlock is held. The list |
| 1709 | * protection for this spinlock is safe when breaking |
| 1710 | * the lock like this since the next thing we do |
| 1711 | * is just get the head of the list again. |
| 1712 | */ |
| 1713 | drm_gem_object_reference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1714 | i915_gem_object_move_to_inactive(obj); |
Shaohua Li | 68c8434 | 2009-04-08 10:58:23 +0800 | [diff] [blame] | 1715 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 1716 | drm_gem_object_unreference(obj); |
| 1717 | spin_lock(&dev_priv->mm.active_list_lock); |
| 1718 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1719 | } |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1720 | out: |
| 1721 | spin_unlock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1722 | } |
| 1723 | |
| 1724 | /** |
| 1725 | * Returns true if seq1 is later than seq2. |
| 1726 | */ |
Ben Gamari | 22be172 | 2009-09-14 17:48:43 -0400 | [diff] [blame] | 1727 | bool |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1728 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
| 1729 | { |
| 1730 | return (int32_t)(seq1 - seq2) >= 0; |
| 1731 | } |
| 1732 | |
| 1733 | uint32_t |
| 1734 | i915_get_gem_seqno(struct drm_device *dev) |
| 1735 | { |
| 1736 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1737 | |
| 1738 | return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX); |
| 1739 | } |
| 1740 | |
| 1741 | /** |
| 1742 | * This function clears the request list as sequence numbers are passed. |
| 1743 | */ |
| 1744 | void |
| 1745 | i915_gem_retire_requests(struct drm_device *dev) |
| 1746 | { |
| 1747 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1748 | uint32_t seqno; |
| 1749 | |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1750 | if (!dev_priv->hw_status_page) |
| 1751 | return; |
| 1752 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1753 | seqno = i915_get_gem_seqno(dev); |
| 1754 | |
| 1755 | while (!list_empty(&dev_priv->mm.request_list)) { |
| 1756 | struct drm_i915_gem_request *request; |
| 1757 | uint32_t retiring_seqno; |
| 1758 | |
| 1759 | request = list_first_entry(&dev_priv->mm.request_list, |
| 1760 | struct drm_i915_gem_request, |
| 1761 | list); |
| 1762 | retiring_seqno = request->seqno; |
| 1763 | |
| 1764 | if (i915_seqno_passed(seqno, retiring_seqno) || |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1765 | atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1766 | i915_gem_retire_request(dev, request); |
| 1767 | |
| 1768 | list_del(&request->list); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1769 | list_del(&request->client_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1770 | kfree(request); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1771 | } else |
| 1772 | break; |
| 1773 | } |
| 1774 | } |
| 1775 | |
| 1776 | void |
| 1777 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1778 | { |
| 1779 | drm_i915_private_t *dev_priv; |
| 1780 | struct drm_device *dev; |
| 1781 | |
| 1782 | dev_priv = container_of(work, drm_i915_private_t, |
| 1783 | mm.retire_work.work); |
| 1784 | dev = dev_priv->dev; |
| 1785 | |
| 1786 | mutex_lock(&dev->struct_mutex); |
| 1787 | i915_gem_retire_requests(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 1788 | if (!dev_priv->mm.suspended && |
| 1789 | !list_empty(&dev_priv->mm.request_list)) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1790 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1791 | mutex_unlock(&dev->struct_mutex); |
| 1792 | } |
| 1793 | |
| 1794 | /** |
| 1795 | * Waits for a sequence number to be signaled, and cleans up the |
| 1796 | * request and object lists appropriately for that event. |
| 1797 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 1798 | static int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1799 | i915_wait_request(struct drm_device *dev, uint32_t seqno) |
| 1800 | { |
| 1801 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1802 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1803 | int ret = 0; |
| 1804 | |
| 1805 | BUG_ON(seqno == 0); |
| 1806 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1807 | if (atomic_read(&dev_priv->mm.wedged)) |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 1808 | return -EIO; |
| 1809 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1810 | if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) { |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1811 | if (IS_IGDNG(dev)) |
| 1812 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 1813 | else |
| 1814 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1815 | if (!ier) { |
| 1816 | DRM_ERROR("something (likely vbetool) disabled " |
| 1817 | "interrupts, re-enabling\n"); |
| 1818 | i915_driver_irq_preinstall(dev); |
| 1819 | i915_driver_irq_postinstall(dev); |
| 1820 | } |
| 1821 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 1822 | trace_i915_gem_request_wait_begin(dev, seqno); |
| 1823 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1824 | dev_priv->mm.waiting_gem_seqno = seqno; |
| 1825 | i915_user_irq_get(dev); |
| 1826 | ret = wait_event_interruptible(dev_priv->irq_queue, |
| 1827 | i915_seqno_passed(i915_get_gem_seqno(dev), |
| 1828 | seqno) || |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1829 | atomic_read(&dev_priv->mm.wedged)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1830 | i915_user_irq_put(dev); |
| 1831 | dev_priv->mm.waiting_gem_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 1832 | |
| 1833 | trace_i915_gem_request_wait_end(dev, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1834 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1835 | if (atomic_read(&dev_priv->mm.wedged)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1836 | ret = -EIO; |
| 1837 | |
| 1838 | if (ret && ret != -ERESTARTSYS) |
| 1839 | DRM_ERROR("%s returns %d (awaiting %d at %d)\n", |
| 1840 | __func__, ret, seqno, i915_get_gem_seqno(dev)); |
| 1841 | |
| 1842 | /* Directly dispatch request retiring. While we have the work queue |
| 1843 | * to handle this, the waiter on a request often wants an associated |
| 1844 | * buffer to have made it to the inactive list, and we would need |
| 1845 | * a separate wait queue to handle that. |
| 1846 | */ |
| 1847 | if (ret == 0) |
| 1848 | i915_gem_retire_requests(dev); |
| 1849 | |
| 1850 | return ret; |
| 1851 | } |
| 1852 | |
| 1853 | static void |
| 1854 | i915_gem_flush(struct drm_device *dev, |
| 1855 | uint32_t invalidate_domains, |
| 1856 | uint32_t flush_domains) |
| 1857 | { |
| 1858 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1859 | uint32_t cmd; |
| 1860 | RING_LOCALS; |
| 1861 | |
| 1862 | #if WATCH_EXEC |
| 1863 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, |
| 1864 | invalidate_domains, flush_domains); |
| 1865 | #endif |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 1866 | trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno, |
| 1867 | invalidate_domains, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1868 | |
| 1869 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
| 1870 | drm_agp_chipset_flush(dev); |
| 1871 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1872 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1873 | /* |
| 1874 | * read/write caches: |
| 1875 | * |
| 1876 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 1877 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 1878 | * also flushed at 2d versus 3d pipeline switches. |
| 1879 | * |
| 1880 | * read-only caches: |
| 1881 | * |
| 1882 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 1883 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 1884 | * |
| 1885 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 1886 | * |
| 1887 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 1888 | * invalidated when MI_EXE_FLUSH is set. |
| 1889 | * |
| 1890 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 1891 | * invalidated with every MI_FLUSH. |
| 1892 | * |
| 1893 | * TLBs: |
| 1894 | * |
| 1895 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 1896 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 1897 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 1898 | * are flushed at any MI_FLUSH. |
| 1899 | */ |
| 1900 | |
| 1901 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
| 1902 | if ((invalidate_domains|flush_domains) & |
| 1903 | I915_GEM_DOMAIN_RENDER) |
| 1904 | cmd &= ~MI_NO_WRITE_FLUSH; |
| 1905 | if (!IS_I965G(dev)) { |
| 1906 | /* |
| 1907 | * On the 965, the sampler cache always gets flushed |
| 1908 | * and this bit is reserved. |
| 1909 | */ |
| 1910 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 1911 | cmd |= MI_READ_FLUSH; |
| 1912 | } |
| 1913 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 1914 | cmd |= MI_EXE_FLUSH; |
| 1915 | |
| 1916 | #if WATCH_EXEC |
| 1917 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); |
| 1918 | #endif |
| 1919 | BEGIN_LP_RING(2); |
| 1920 | OUT_RING(cmd); |
| 1921 | OUT_RING(0); /* noop */ |
| 1922 | ADVANCE_LP_RING(); |
| 1923 | } |
| 1924 | } |
| 1925 | |
| 1926 | /** |
| 1927 | * Ensures that all rendering to the object has completed and the object is |
| 1928 | * safe to unbind from the GTT or access from the CPU. |
| 1929 | */ |
| 1930 | static int |
| 1931 | i915_gem_object_wait_rendering(struct drm_gem_object *obj) |
| 1932 | { |
| 1933 | struct drm_device *dev = obj->dev; |
| 1934 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1935 | int ret; |
| 1936 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1937 | /* This function only exists to support waiting for existing rendering, |
| 1938 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1939 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1940 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1941 | |
| 1942 | /* If there is rendering queued on the buffer being evicted, wait for |
| 1943 | * it. |
| 1944 | */ |
| 1945 | if (obj_priv->active) { |
| 1946 | #if WATCH_BUF |
| 1947 | DRM_INFO("%s: object %p wait for seqno %08x\n", |
| 1948 | __func__, obj, obj_priv->last_rendering_seqno); |
| 1949 | #endif |
| 1950 | ret = i915_wait_request(dev, obj_priv->last_rendering_seqno); |
| 1951 | if (ret != 0) |
| 1952 | return ret; |
| 1953 | } |
| 1954 | |
| 1955 | return 0; |
| 1956 | } |
| 1957 | |
| 1958 | /** |
| 1959 | * Unbinds an object from the GTT aperture. |
| 1960 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1961 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1962 | i915_gem_object_unbind(struct drm_gem_object *obj) |
| 1963 | { |
| 1964 | struct drm_device *dev = obj->dev; |
| 1965 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1966 | int ret = 0; |
| 1967 | |
| 1968 | #if WATCH_BUF |
| 1969 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); |
| 1970 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); |
| 1971 | #endif |
| 1972 | if (obj_priv->gtt_space == NULL) |
| 1973 | return 0; |
| 1974 | |
| 1975 | if (obj_priv->pin_count != 0) { |
| 1976 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 1977 | return -EINVAL; |
| 1978 | } |
| 1979 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 1980 | /* blow away mappings if mapped through GTT */ |
| 1981 | i915_gem_release_mmap(obj); |
| 1982 | |
| 1983 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) |
| 1984 | i915_gem_clear_fence_reg(obj); |
| 1985 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1986 | /* Move the object to the CPU domain to ensure that |
| 1987 | * any possible CPU writes while it's not in the GTT |
| 1988 | * are flushed when we go to remap it. This will |
| 1989 | * also ensure that all pending GPU writes are finished |
| 1990 | * before we unbind. |
| 1991 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1992 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1993 | if (ret) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1994 | if (ret != -ERESTARTSYS) |
| 1995 | DRM_ERROR("set_domain failed: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1996 | return ret; |
| 1997 | } |
| 1998 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 1999 | BUG_ON(obj_priv->active); |
| 2000 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2001 | if (obj_priv->agp_mem != NULL) { |
| 2002 | drm_unbind_agp(obj_priv->agp_mem); |
| 2003 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); |
| 2004 | obj_priv->agp_mem = NULL; |
| 2005 | } |
| 2006 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2007 | i915_gem_object_put_pages(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2008 | |
| 2009 | if (obj_priv->gtt_space) { |
| 2010 | atomic_dec(&dev->gtt_count); |
| 2011 | atomic_sub(obj->size, &dev->gtt_memory); |
| 2012 | |
| 2013 | drm_mm_put_block(obj_priv->gtt_space); |
| 2014 | obj_priv->gtt_space = NULL; |
| 2015 | } |
| 2016 | |
| 2017 | /* Remove ourselves from the LRU list if present. */ |
| 2018 | if (!list_empty(&obj_priv->list)) |
| 2019 | list_del_init(&obj_priv->list); |
| 2020 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2021 | trace_i915_gem_object_unbind(obj); |
| 2022 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2023 | return 0; |
| 2024 | } |
| 2025 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2026 | static inline int |
| 2027 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) |
| 2028 | { |
| 2029 | return !obj_priv->dirty || obj_priv->madv == I915_MADV_DONTNEED; |
| 2030 | } |
| 2031 | |
| 2032 | static struct drm_gem_object * |
| 2033 | i915_gem_find_inactive_object(struct drm_device *dev, int min_size) |
| 2034 | { |
| 2035 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2036 | struct drm_i915_gem_object *obj_priv; |
| 2037 | struct drm_gem_object *best = NULL; |
| 2038 | struct drm_gem_object *first = NULL; |
| 2039 | |
| 2040 | /* Try to find the smallest clean object */ |
| 2041 | list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) { |
| 2042 | struct drm_gem_object *obj = obj_priv->obj; |
| 2043 | if (obj->size >= min_size) { |
| 2044 | if (i915_gem_object_is_purgeable(obj_priv) && |
| 2045 | (!best || obj->size < best->size)) { |
| 2046 | best = obj; |
| 2047 | if (best->size == min_size) |
| 2048 | return best; |
| 2049 | } |
| 2050 | if (!first) |
| 2051 | first = obj; |
| 2052 | } |
| 2053 | } |
| 2054 | |
| 2055 | return best ? best : first; |
| 2056 | } |
| 2057 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2058 | static int |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2059 | i915_gem_evict_everything(struct drm_device *dev) |
| 2060 | { |
| 2061 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2062 | uint32_t seqno; |
| 2063 | int ret; |
| 2064 | bool lists_empty; |
| 2065 | |
| 2066 | DRM_INFO("GTT full, evicting everything: " |
| 2067 | "%d objects [%d pinned], " |
| 2068 | "%d object bytes [%d pinned], " |
| 2069 | "%d/%d gtt bytes\n", |
| 2070 | atomic_read(&dev->object_count), |
| 2071 | atomic_read(&dev->pin_count), |
| 2072 | atomic_read(&dev->object_memory), |
| 2073 | atomic_read(&dev->pin_memory), |
| 2074 | atomic_read(&dev->gtt_memory), |
| 2075 | dev->gtt_total); |
| 2076 | |
| 2077 | spin_lock(&dev_priv->mm.active_list_lock); |
| 2078 | lists_empty = (list_empty(&dev_priv->mm.inactive_list) && |
| 2079 | list_empty(&dev_priv->mm.flushing_list) && |
| 2080 | list_empty(&dev_priv->mm.active_list)); |
| 2081 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 2082 | |
| 2083 | if (lists_empty) { |
| 2084 | DRM_ERROR("GTT full, but lists empty!\n"); |
| 2085 | return -ENOSPC; |
| 2086 | } |
| 2087 | |
| 2088 | /* Flush everything (on to the inactive lists) and evict */ |
| 2089 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 2090 | seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS); |
| 2091 | if (seqno == 0) |
| 2092 | return -ENOMEM; |
| 2093 | |
| 2094 | ret = i915_wait_request(dev, seqno); |
| 2095 | if (ret) |
| 2096 | return ret; |
| 2097 | |
| 2098 | ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list); |
| 2099 | if (ret) |
| 2100 | return ret; |
| 2101 | |
| 2102 | spin_lock(&dev_priv->mm.active_list_lock); |
| 2103 | lists_empty = (list_empty(&dev_priv->mm.inactive_list) && |
| 2104 | list_empty(&dev_priv->mm.flushing_list) && |
| 2105 | list_empty(&dev_priv->mm.active_list)); |
| 2106 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 2107 | BUG_ON(!lists_empty); |
| 2108 | |
| 2109 | return 0; |
| 2110 | } |
| 2111 | |
| 2112 | static int |
| 2113 | i915_gem_evict_something(struct drm_device *dev, int min_size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2114 | { |
| 2115 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2116 | struct drm_gem_object *obj; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2117 | int have_waited = 0; |
| 2118 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2119 | |
| 2120 | for (;;) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2121 | i915_gem_retire_requests(dev); |
| 2122 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2123 | /* If there's an inactive buffer available now, grab it |
| 2124 | * and be done. |
| 2125 | */ |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2126 | obj = i915_gem_find_inactive_object(dev, min_size); |
| 2127 | if (obj) { |
| 2128 | struct drm_i915_gem_object *obj_priv; |
| 2129 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2130 | #if WATCH_LRU |
| 2131 | DRM_INFO("%s: evicting %p\n", __func__, obj); |
| 2132 | #endif |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2133 | obj_priv = obj->driver_private; |
| 2134 | BUG_ON(obj_priv->pin_count != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2135 | BUG_ON(obj_priv->active); |
| 2136 | |
| 2137 | /* Wait on the rendering and unbind the buffer. */ |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2138 | return i915_gem_object_unbind(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2139 | } |
| 2140 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2141 | if (have_waited) |
| 2142 | return 0; |
| 2143 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2144 | /* If we didn't get anything, but the ring is still processing |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2145 | * things, wait for the next to finish and hopefully leave us |
| 2146 | * a buffer to evict. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2147 | */ |
| 2148 | if (!list_empty(&dev_priv->mm.request_list)) { |
| 2149 | struct drm_i915_gem_request *request; |
| 2150 | |
| 2151 | request = list_first_entry(&dev_priv->mm.request_list, |
| 2152 | struct drm_i915_gem_request, |
| 2153 | list); |
| 2154 | |
| 2155 | ret = i915_wait_request(dev, request->seqno); |
| 2156 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2157 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2158 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2159 | have_waited = 1; |
| 2160 | continue; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2161 | } |
| 2162 | |
| 2163 | /* If we didn't have anything on the request list but there |
| 2164 | * are buffers awaiting a flush, emit one and try again. |
| 2165 | * When we wait on it, those buffers waiting for that flush |
| 2166 | * will get moved to inactive. |
| 2167 | */ |
| 2168 | if (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2169 | struct drm_i915_gem_object *obj_priv; |
| 2170 | uint32_t seqno; |
| 2171 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2172 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, |
| 2173 | struct drm_i915_gem_object, |
| 2174 | list); |
| 2175 | obj = obj_priv->obj; |
| 2176 | |
| 2177 | i915_gem_flush(dev, |
| 2178 | obj->write_domain, |
| 2179 | obj->write_domain); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2180 | seqno = i915_add_request(dev, NULL, obj->write_domain); |
| 2181 | if (seqno == 0) |
| 2182 | return -ENOMEM; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2183 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2184 | ret = i915_wait_request(dev, seqno); |
| 2185 | if (ret) |
| 2186 | return ret; |
| 2187 | |
| 2188 | have_waited = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2189 | continue; |
| 2190 | } |
| 2191 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2192 | /* If we didn't do any of the above, there's no single buffer |
| 2193 | * large enough to swap out for the new one, so just evict |
| 2194 | * everything and start again. (This should be rare.) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2195 | */ |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2196 | if (!list_empty (&dev_priv->mm.inactive_list)) { |
| 2197 | DRM_INFO("GTT full, evicting inactive buffers\n"); |
| 2198 | return i915_gem_evict_from_list(dev, |
| 2199 | &dev_priv->mm.inactive_list); |
| 2200 | } else |
| 2201 | return i915_gem_evict_everything(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2202 | } |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 2203 | } |
| 2204 | |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 2205 | int |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2206 | i915_gem_object_get_pages(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2207 | { |
| 2208 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2209 | int page_count, i; |
| 2210 | struct address_space *mapping; |
| 2211 | struct inode *inode; |
| 2212 | struct page *page; |
| 2213 | int ret; |
| 2214 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2215 | if (obj_priv->pages_refcount++ != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2216 | return 0; |
| 2217 | |
| 2218 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2219 | * at this point until we release them. |
| 2220 | */ |
| 2221 | page_count = obj->size / PAGE_SIZE; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2222 | BUG_ON(obj_priv->pages != NULL); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 2223 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2224 | if (obj_priv->pages == NULL) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2225 | DRM_ERROR("Failed to allocate page list\n"); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2226 | obj_priv->pages_refcount--; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2227 | return -ENOMEM; |
| 2228 | } |
| 2229 | |
| 2230 | inode = obj->filp->f_path.dentry->d_inode; |
| 2231 | mapping = inode->i_mapping; |
| 2232 | for (i = 0; i < page_count; i++) { |
| 2233 | page = read_mapping_page(mapping, i, NULL); |
| 2234 | if (IS_ERR(page)) { |
| 2235 | ret = PTR_ERR(page); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2236 | i915_gem_object_put_pages(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2237 | return ret; |
| 2238 | } |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2239 | obj_priv->pages[i] = page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2240 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2241 | |
| 2242 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 2243 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2244 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2245 | return 0; |
| 2246 | } |
| 2247 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2248 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2249 | { |
| 2250 | struct drm_gem_object *obj = reg->obj; |
| 2251 | struct drm_device *dev = obj->dev; |
| 2252 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2253 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2254 | int regnum = obj_priv->fence_reg; |
| 2255 | uint64_t val; |
| 2256 | |
| 2257 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2258 | 0xfffff000) << 32; |
| 2259 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2260 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2261 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2262 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2263 | val |= I965_FENCE_REG_VALID; |
| 2264 | |
| 2265 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); |
| 2266 | } |
| 2267 | |
| 2268 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2269 | { |
| 2270 | struct drm_gem_object *obj = reg->obj; |
| 2271 | struct drm_device *dev = obj->dev; |
| 2272 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2273 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2274 | int regnum = obj_priv->fence_reg; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2275 | int tile_width; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2276 | uint32_t fence_reg, val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2277 | uint32_t pitch_val; |
| 2278 | |
| 2279 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2280 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Linus Torvalds | f06da26 | 2009-02-09 08:57:29 -0800 | [diff] [blame] | 2281 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2282 | __func__, obj_priv->gtt_offset, obj->size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2283 | return; |
| 2284 | } |
| 2285 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2286 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2287 | HAS_128_BYTE_Y_TILING(dev)) |
| 2288 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2289 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2290 | tile_width = 512; |
| 2291 | |
| 2292 | /* Note: pitch better be a power of two tile widths */ |
| 2293 | pitch_val = obj_priv->stride / tile_width; |
| 2294 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2295 | |
| 2296 | val = obj_priv->gtt_offset; |
| 2297 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2298 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2299 | val |= I915_FENCE_SIZE_BITS(obj->size); |
| 2300 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2301 | val |= I830_FENCE_REG_VALID; |
| 2302 | |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2303 | if (regnum < 8) |
| 2304 | fence_reg = FENCE_REG_830_0 + (regnum * 4); |
| 2305 | else |
| 2306 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); |
| 2307 | I915_WRITE(fence_reg, val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2308 | } |
| 2309 | |
| 2310 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2311 | { |
| 2312 | struct drm_gem_object *obj = reg->obj; |
| 2313 | struct drm_device *dev = obj->dev; |
| 2314 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2315 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2316 | int regnum = obj_priv->fence_reg; |
| 2317 | uint32_t val; |
| 2318 | uint32_t pitch_val; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2319 | uint32_t fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2320 | |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2321 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2322 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2323 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2324 | __func__, obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2325 | return; |
| 2326 | } |
| 2327 | |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2328 | pitch_val = obj_priv->stride / 128; |
| 2329 | pitch_val = ffs(pitch_val) - 1; |
| 2330 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2331 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2332 | val = obj_priv->gtt_offset; |
| 2333 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2334 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2335 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
| 2336 | WARN_ON(fence_size_bits & ~0x00000f00); |
| 2337 | val |= fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2338 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2339 | val |= I830_FENCE_REG_VALID; |
| 2340 | |
| 2341 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2342 | } |
| 2343 | |
| 2344 | /** |
| 2345 | * i915_gem_object_get_fence_reg - set up a fence reg for an object |
| 2346 | * @obj: object to map through a fence reg |
| 2347 | * |
| 2348 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2349 | * to them without having to worry about swizzling if the object is tiled. |
| 2350 | * |
| 2351 | * This function walks the fence regs looking for a free one for @obj, |
| 2352 | * stealing one if it can't find any. |
| 2353 | * |
| 2354 | * It then sets up the reg based on the object's properties: address, pitch |
| 2355 | * and tiling format. |
| 2356 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2357 | int |
| 2358 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2359 | { |
| 2360 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2361 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2362 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2363 | struct drm_i915_fence_reg *reg = NULL; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2364 | struct drm_i915_gem_object *old_obj_priv = NULL; |
| 2365 | int i, ret, avail; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2366 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2367 | /* Just update our place in the LRU if our fence is getting used. */ |
| 2368 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
| 2369 | list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list); |
| 2370 | return 0; |
| 2371 | } |
| 2372 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2373 | switch (obj_priv->tiling_mode) { |
| 2374 | case I915_TILING_NONE: |
| 2375 | WARN(1, "allocating a fence for non-tiled object?\n"); |
| 2376 | break; |
| 2377 | case I915_TILING_X: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2378 | if (!obj_priv->stride) |
| 2379 | return -EINVAL; |
| 2380 | WARN((obj_priv->stride & (512 - 1)), |
| 2381 | "object 0x%08x is X tiled but has non-512B pitch\n", |
| 2382 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2383 | break; |
| 2384 | case I915_TILING_Y: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2385 | if (!obj_priv->stride) |
| 2386 | return -EINVAL; |
| 2387 | WARN((obj_priv->stride & (128 - 1)), |
| 2388 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
| 2389 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2390 | break; |
| 2391 | } |
| 2392 | |
| 2393 | /* First try to find a free reg */ |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2394 | avail = 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2395 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2396 | reg = &dev_priv->fence_regs[i]; |
| 2397 | if (!reg->obj) |
| 2398 | break; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2399 | |
| 2400 | old_obj_priv = reg->obj->driver_private; |
| 2401 | if (!old_obj_priv->pin_count) |
| 2402 | avail++; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2403 | } |
| 2404 | |
| 2405 | /* None available, try to steal one or wait for a user to finish */ |
| 2406 | if (i == dev_priv->num_fence_regs) { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2407 | struct drm_gem_object *old_obj = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2408 | |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2409 | if (avail == 0) |
Chris Wilson | 2939e1f | 2009-06-06 09:46:03 +0100 | [diff] [blame] | 2410 | return -ENOSPC; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2411 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2412 | list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list, |
| 2413 | fence_list) { |
| 2414 | old_obj = old_obj_priv->obj; |
Chris Wilson | d7619c4 | 2009-02-11 14:26:47 +0000 | [diff] [blame] | 2415 | |
| 2416 | if (old_obj_priv->pin_count) |
| 2417 | continue; |
| 2418 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2419 | /* Take a reference, as otherwise the wait_rendering |
| 2420 | * below may cause the object to get freed out from |
| 2421 | * under us. |
| 2422 | */ |
| 2423 | drm_gem_object_reference(old_obj); |
| 2424 | |
Chris Wilson | d7619c4 | 2009-02-11 14:26:47 +0000 | [diff] [blame] | 2425 | /* i915 uses fences for GPU access to tiled buffers */ |
| 2426 | if (IS_I965G(dev) || !old_obj_priv->active) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2427 | break; |
Chris Wilson | d7619c4 | 2009-02-11 14:26:47 +0000 | [diff] [blame] | 2428 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2429 | /* This brings the object to the head of the LRU if it |
| 2430 | * had been written to. The only way this should |
| 2431 | * result in us waiting longer than the expected |
| 2432 | * optimal amount of time is if there was a |
| 2433 | * fence-using buffer later that was read-only. |
| 2434 | */ |
| 2435 | i915_gem_object_flush_gpu_write_domain(old_obj); |
| 2436 | ret = i915_gem_object_wait_rendering(old_obj); |
Chris Wilson | 58c2fb6 | 2009-09-01 12:02:39 +0100 | [diff] [blame] | 2437 | if (ret != 0) { |
| 2438 | drm_gem_object_unreference(old_obj); |
Chris Wilson | d7619c4 | 2009-02-11 14:26:47 +0000 | [diff] [blame] | 2439 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2440 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2441 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2442 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2443 | } |
| 2444 | |
| 2445 | /* |
| 2446 | * Zap this virtual mapping so we can set up a fence again |
| 2447 | * for this object next time we need it. |
| 2448 | */ |
Chris Wilson | 58c2fb6 | 2009-09-01 12:02:39 +0100 | [diff] [blame] | 2449 | i915_gem_release_mmap(old_obj); |
| 2450 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2451 | i = old_obj_priv->fence_reg; |
Chris Wilson | 58c2fb6 | 2009-09-01 12:02:39 +0100 | [diff] [blame] | 2452 | reg = &dev_priv->fence_regs[i]; |
| 2453 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2454 | old_obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2455 | list_del_init(&old_obj_priv->fence_list); |
Chris Wilson | 58c2fb6 | 2009-09-01 12:02:39 +0100 | [diff] [blame] | 2456 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2457 | drm_gem_object_unreference(old_obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2458 | } |
| 2459 | |
| 2460 | obj_priv->fence_reg = i; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2461 | list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list); |
| 2462 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2463 | reg->obj = obj; |
| 2464 | |
| 2465 | if (IS_I965G(dev)) |
| 2466 | i965_write_fence_reg(reg); |
| 2467 | else if (IS_I9XX(dev)) |
| 2468 | i915_write_fence_reg(reg); |
| 2469 | else |
| 2470 | i830_write_fence_reg(reg); |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2471 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2472 | trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode); |
| 2473 | |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2474 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2475 | } |
| 2476 | |
| 2477 | /** |
| 2478 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2479 | * @obj: object to clear |
| 2480 | * |
| 2481 | * Zeroes out the fence register itself and clears out the associated |
| 2482 | * data structures in dev_priv and obj_priv. |
| 2483 | */ |
| 2484 | static void |
| 2485 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) |
| 2486 | { |
| 2487 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2488 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2489 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2490 | |
| 2491 | if (IS_I965G(dev)) |
| 2492 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2493 | else { |
| 2494 | uint32_t fence_reg; |
| 2495 | |
| 2496 | if (obj_priv->fence_reg < 8) |
| 2497 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; |
| 2498 | else |
| 2499 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - |
| 2500 | 8) * 4; |
| 2501 | |
| 2502 | I915_WRITE(fence_reg, 0); |
| 2503 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2504 | |
| 2505 | dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL; |
| 2506 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2507 | list_del_init(&obj_priv->fence_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2508 | } |
| 2509 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2510 | /** |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2511 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access |
| 2512 | * to the buffer to finish, and then resets the fence register. |
| 2513 | * @obj: tiled object holding a fence register. |
| 2514 | * |
| 2515 | * Zeroes out the fence register itself and clears out the associated |
| 2516 | * data structures in dev_priv and obj_priv. |
| 2517 | */ |
| 2518 | int |
| 2519 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj) |
| 2520 | { |
| 2521 | struct drm_device *dev = obj->dev; |
| 2522 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2523 | |
| 2524 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) |
| 2525 | return 0; |
| 2526 | |
| 2527 | /* On the i915, GPU access to tiled buffers is via a fence, |
| 2528 | * therefore we must wait for any outstanding access to complete |
| 2529 | * before clearing the fence. |
| 2530 | */ |
| 2531 | if (!IS_I965G(dev)) { |
| 2532 | int ret; |
| 2533 | |
| 2534 | i915_gem_object_flush_gpu_write_domain(obj); |
| 2535 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2536 | ret = i915_gem_object_wait_rendering(obj); |
| 2537 | if (ret != 0) |
| 2538 | return ret; |
| 2539 | } |
| 2540 | |
| 2541 | i915_gem_clear_fence_reg (obj); |
| 2542 | |
| 2543 | return 0; |
| 2544 | } |
| 2545 | |
| 2546 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2547 | * Finds free space in the GTT aperture and binds the object there. |
| 2548 | */ |
| 2549 | static int |
| 2550 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) |
| 2551 | { |
| 2552 | struct drm_device *dev = obj->dev; |
| 2553 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2554 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2555 | struct drm_mm_node *free_space; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2556 | bool retry_alloc = false; |
| 2557 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2558 | |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 2559 | if (dev_priv->mm.suspended) |
| 2560 | return -EBUSY; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2561 | |
| 2562 | if (obj_priv->madv == I915_MADV_DONTNEED) { |
| 2563 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2564 | return -EINVAL; |
| 2565 | } |
| 2566 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2567 | if (alignment == 0) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2568 | alignment = i915_gem_get_gtt_alignment(obj); |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2569 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2570 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2571 | return -EINVAL; |
| 2572 | } |
| 2573 | |
| 2574 | search_free: |
| 2575 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
| 2576 | obj->size, alignment, 0); |
| 2577 | if (free_space != NULL) { |
| 2578 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, |
| 2579 | alignment); |
| 2580 | if (obj_priv->gtt_space != NULL) { |
| 2581 | obj_priv->gtt_space->private = obj; |
| 2582 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
| 2583 | } |
| 2584 | } |
| 2585 | if (obj_priv->gtt_space == NULL) { |
| 2586 | /* If the gtt is empty and we're still having trouble |
| 2587 | * fitting our object in, we're out of memory. |
| 2588 | */ |
| 2589 | #if WATCH_LRU |
| 2590 | DRM_INFO("%s: GTT full, evicting something\n", __func__); |
| 2591 | #endif |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2592 | ret = i915_gem_evict_something(dev, obj->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2593 | if (ret != 0) { |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 2594 | if (ret != -ERESTARTSYS) |
| 2595 | DRM_ERROR("Failed to evict a buffer %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2596 | return ret; |
| 2597 | } |
| 2598 | goto search_free; |
| 2599 | } |
| 2600 | |
| 2601 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 2602 | DRM_INFO("Binding object of size %zd at 0x%08x\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2603 | obj->size, obj_priv->gtt_offset); |
| 2604 | #endif |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2605 | if (retry_alloc) { |
| 2606 | i915_gem_object_set_page_gfp_mask (obj, |
| 2607 | i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY); |
| 2608 | } |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2609 | ret = i915_gem_object_get_pages(obj); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2610 | if (retry_alloc) { |
| 2611 | i915_gem_object_set_page_gfp_mask (obj, |
| 2612 | i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY); |
| 2613 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2614 | if (ret) { |
| 2615 | drm_mm_put_block(obj_priv->gtt_space); |
| 2616 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2617 | |
| 2618 | if (ret == -ENOMEM) { |
| 2619 | /* first try to clear up some space from the GTT */ |
| 2620 | ret = i915_gem_evict_something(dev, obj->size); |
| 2621 | if (ret) { |
| 2622 | if (ret != -ERESTARTSYS) |
| 2623 | DRM_ERROR("Failed to allocate space for backing pages %d\n", ret); |
| 2624 | |
| 2625 | /* now try to shrink everyone else */ |
| 2626 | if (! retry_alloc) { |
| 2627 | retry_alloc = true; |
| 2628 | goto search_free; |
| 2629 | } |
| 2630 | |
| 2631 | return ret; |
| 2632 | } |
| 2633 | |
| 2634 | goto search_free; |
| 2635 | } |
| 2636 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2637 | return ret; |
| 2638 | } |
| 2639 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2640 | /* Create an AGP memory structure pointing at our pages, and bind it |
| 2641 | * into the GTT. |
| 2642 | */ |
| 2643 | obj_priv->agp_mem = drm_agp_bind_pages(dev, |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2644 | obj_priv->pages, |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2645 | obj->size >> PAGE_SHIFT, |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 2646 | obj_priv->gtt_offset, |
| 2647 | obj_priv->agp_type); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2648 | if (obj_priv->agp_mem == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2649 | i915_gem_object_put_pages(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2650 | drm_mm_put_block(obj_priv->gtt_space); |
| 2651 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2652 | |
| 2653 | ret = i915_gem_evict_something(dev, obj->size); |
| 2654 | if (ret) { |
| 2655 | if (ret != -ERESTARTSYS) |
| 2656 | DRM_ERROR("Failed to allocate space to bind AGP: %d\n", ret); |
| 2657 | return ret; |
| 2658 | } |
| 2659 | |
| 2660 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2661 | } |
| 2662 | atomic_inc(&dev->gtt_count); |
| 2663 | atomic_add(obj->size, &dev->gtt_memory); |
| 2664 | |
| 2665 | /* Assert that the object is not currently in any GPU domain. As it |
| 2666 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2667 | * a GPU cache |
| 2668 | */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 2669 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
| 2670 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2671 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2672 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
| 2673 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2674 | return 0; |
| 2675 | } |
| 2676 | |
| 2677 | void |
| 2678 | i915_gem_clflush_object(struct drm_gem_object *obj) |
| 2679 | { |
| 2680 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2681 | |
| 2682 | /* If we don't have a page list set up, then we're not pinned |
| 2683 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2684 | * again at bind time. |
| 2685 | */ |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2686 | if (obj_priv->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2687 | return; |
| 2688 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2689 | trace_i915_gem_object_clflush(obj); |
| 2690 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2691 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2692 | } |
| 2693 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2694 | /** Flushes any GPU write domain for the object if it's dirty. */ |
| 2695 | static void |
| 2696 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) |
| 2697 | { |
| 2698 | struct drm_device *dev = obj->dev; |
| 2699 | uint32_t seqno; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2700 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2701 | |
| 2702 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
| 2703 | return; |
| 2704 | |
| 2705 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2706 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2707 | i915_gem_flush(dev, 0, obj->write_domain); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2708 | seqno = i915_add_request(dev, NULL, obj->write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2709 | obj->write_domain = 0; |
| 2710 | i915_gem_object_move_to_active(obj, seqno); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2711 | |
| 2712 | trace_i915_gem_object_change_domain(obj, |
| 2713 | obj->read_domains, |
| 2714 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2715 | } |
| 2716 | |
| 2717 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2718 | static void |
| 2719 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) |
| 2720 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2721 | uint32_t old_write_domain; |
| 2722 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2723 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
| 2724 | return; |
| 2725 | |
| 2726 | /* No actual flushing is required for the GTT write domain. Writes |
| 2727 | * to it immediately go to main memory as far as we know, so there's |
| 2728 | * no chipset flush. It also doesn't land in render cache. |
| 2729 | */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2730 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2731 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2732 | |
| 2733 | trace_i915_gem_object_change_domain(obj, |
| 2734 | obj->read_domains, |
| 2735 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2736 | } |
| 2737 | |
| 2738 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2739 | static void |
| 2740 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) |
| 2741 | { |
| 2742 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2743 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2744 | |
| 2745 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) |
| 2746 | return; |
| 2747 | |
| 2748 | i915_gem_clflush_object(obj); |
| 2749 | drm_agp_chipset_flush(dev); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2750 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2751 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2752 | |
| 2753 | trace_i915_gem_object_change_domain(obj, |
| 2754 | obj->read_domains, |
| 2755 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2756 | } |
| 2757 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2758 | /** |
| 2759 | * Moves a single object to the GTT read, and possibly write domain. |
| 2760 | * |
| 2761 | * This function returns when the move is complete, including waiting on |
| 2762 | * flushes to occur. |
| 2763 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2764 | int |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2765 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
| 2766 | { |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2767 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2768 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2769 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2770 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2771 | /* Not valid to be called on unbound objects. */ |
| 2772 | if (obj_priv->gtt_space == NULL) |
| 2773 | return -EINVAL; |
| 2774 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2775 | i915_gem_object_flush_gpu_write_domain(obj); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2776 | /* Wait on any GPU rendering and flushing to occur. */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2777 | ret = i915_gem_object_wait_rendering(obj); |
| 2778 | if (ret != 0) |
| 2779 | return ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2780 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2781 | old_write_domain = obj->write_domain; |
| 2782 | old_read_domains = obj->read_domains; |
| 2783 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2784 | /* If we're writing through the GTT domain, then CPU and GPU caches |
| 2785 | * will need to be invalidated at next use. |
| 2786 | */ |
| 2787 | if (write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2788 | obj->read_domains &= I915_GEM_DOMAIN_GTT; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2789 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2790 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2791 | |
| 2792 | /* It should now be out of any other write domains, and we can update |
| 2793 | * the domain values for our changes. |
| 2794 | */ |
| 2795 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2796 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2797 | if (write) { |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2798 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2799 | obj_priv->dirty = 1; |
| 2800 | } |
| 2801 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2802 | trace_i915_gem_object_change_domain(obj, |
| 2803 | old_read_domains, |
| 2804 | old_write_domain); |
| 2805 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2806 | return 0; |
| 2807 | } |
| 2808 | |
| 2809 | /** |
| 2810 | * Moves a single object to the CPU read, and possibly write domain. |
| 2811 | * |
| 2812 | * This function returns when the move is complete, including waiting on |
| 2813 | * flushes to occur. |
| 2814 | */ |
| 2815 | static int |
| 2816 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) |
| 2817 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2818 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2819 | int ret; |
| 2820 | |
| 2821 | i915_gem_object_flush_gpu_write_domain(obj); |
| 2822 | /* Wait on any GPU rendering and flushing to occur. */ |
| 2823 | ret = i915_gem_object_wait_rendering(obj); |
| 2824 | if (ret != 0) |
| 2825 | return ret; |
| 2826 | |
| 2827 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2828 | |
| 2829 | /* If we have a partially-valid cache of the object in the CPU, |
| 2830 | * finish invalidating it and free the per-page flags. |
| 2831 | */ |
| 2832 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 2833 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2834 | old_write_domain = obj->write_domain; |
| 2835 | old_read_domains = obj->read_domains; |
| 2836 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2837 | /* Flush the CPU cache if it's still invalid. */ |
| 2838 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
| 2839 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2840 | |
| 2841 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 2842 | } |
| 2843 | |
| 2844 | /* It should now be out of any other write domains, and we can update |
| 2845 | * the domain values for our changes. |
| 2846 | */ |
| 2847 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 2848 | |
| 2849 | /* If we're writing through the CPU, then the GPU read domains will |
| 2850 | * need to be invalidated at next use. |
| 2851 | */ |
| 2852 | if (write) { |
| 2853 | obj->read_domains &= I915_GEM_DOMAIN_CPU; |
| 2854 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 2855 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2856 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2857 | trace_i915_gem_object_change_domain(obj, |
| 2858 | old_read_domains, |
| 2859 | old_write_domain); |
| 2860 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2861 | return 0; |
| 2862 | } |
| 2863 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2864 | /* |
| 2865 | * Set the next domain for the specified object. This |
| 2866 | * may not actually perform the necessary flushing/invaliding though, |
| 2867 | * as that may want to be batched with other set_domain operations |
| 2868 | * |
| 2869 | * This is (we hope) the only really tricky part of gem. The goal |
| 2870 | * is fairly simple -- track which caches hold bits of the object |
| 2871 | * and make sure they remain coherent. A few concrete examples may |
| 2872 | * help to explain how it works. For shorthand, we use the notation |
| 2873 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 2874 | * a pair of read and write domain masks. |
| 2875 | * |
| 2876 | * Case 1: the batch buffer |
| 2877 | * |
| 2878 | * 1. Allocated |
| 2879 | * 2. Written by CPU |
| 2880 | * 3. Mapped to GTT |
| 2881 | * 4. Read by GPU |
| 2882 | * 5. Unmapped from GTT |
| 2883 | * 6. Freed |
| 2884 | * |
| 2885 | * Let's take these a step at a time |
| 2886 | * |
| 2887 | * 1. Allocated |
| 2888 | * Pages allocated from the kernel may still have |
| 2889 | * cache contents, so we set them to (CPU, CPU) always. |
| 2890 | * 2. Written by CPU (using pwrite) |
| 2891 | * The pwrite function calls set_domain (CPU, CPU) and |
| 2892 | * this function does nothing (as nothing changes) |
| 2893 | * 3. Mapped by GTT |
| 2894 | * This function asserts that the object is not |
| 2895 | * currently in any GPU-based read or write domains |
| 2896 | * 4. Read by GPU |
| 2897 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 2898 | * As write_domain is zero, this function adds in the |
| 2899 | * current read domains (CPU+COMMAND, 0). |
| 2900 | * flush_domains is set to CPU. |
| 2901 | * invalidate_domains is set to COMMAND |
| 2902 | * clflush is run to get data out of the CPU caches |
| 2903 | * then i915_dev_set_domain calls i915_gem_flush to |
| 2904 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 2905 | * 5. Unmapped from GTT |
| 2906 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 2907 | * flush_domains and invalidate_domains end up both zero |
| 2908 | * so no flushing/invalidating happens |
| 2909 | * 6. Freed |
| 2910 | * yay, done |
| 2911 | * |
| 2912 | * Case 2: The shared render buffer |
| 2913 | * |
| 2914 | * 1. Allocated |
| 2915 | * 2. Mapped to GTT |
| 2916 | * 3. Read/written by GPU |
| 2917 | * 4. set_domain to (CPU,CPU) |
| 2918 | * 5. Read/written by CPU |
| 2919 | * 6. Read/written by GPU |
| 2920 | * |
| 2921 | * 1. Allocated |
| 2922 | * Same as last example, (CPU, CPU) |
| 2923 | * 2. Mapped to GTT |
| 2924 | * Nothing changes (assertions find that it is not in the GPU) |
| 2925 | * 3. Read/written by GPU |
| 2926 | * execbuffer calls set_domain (RENDER, RENDER) |
| 2927 | * flush_domains gets CPU |
| 2928 | * invalidate_domains gets GPU |
| 2929 | * clflush (obj) |
| 2930 | * MI_FLUSH and drm_agp_chipset_flush |
| 2931 | * 4. set_domain (CPU, CPU) |
| 2932 | * flush_domains gets GPU |
| 2933 | * invalidate_domains gets CPU |
| 2934 | * wait_rendering (obj) to make sure all drawing is complete. |
| 2935 | * This will include an MI_FLUSH to get the data from GPU |
| 2936 | * to memory |
| 2937 | * clflush (obj) to invalidate the CPU cache |
| 2938 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 2939 | * 5. Read/written by CPU |
| 2940 | * cache lines are loaded and dirtied |
| 2941 | * 6. Read written by GPU |
| 2942 | * Same as last GPU access |
| 2943 | * |
| 2944 | * Case 3: The constant buffer |
| 2945 | * |
| 2946 | * 1. Allocated |
| 2947 | * 2. Written by CPU |
| 2948 | * 3. Read by GPU |
| 2949 | * 4. Updated (written) by CPU again |
| 2950 | * 5. Read by GPU |
| 2951 | * |
| 2952 | * 1. Allocated |
| 2953 | * (CPU, CPU) |
| 2954 | * 2. Written by CPU |
| 2955 | * (CPU, CPU) |
| 2956 | * 3. Read by GPU |
| 2957 | * (CPU+RENDER, 0) |
| 2958 | * flush_domains = CPU |
| 2959 | * invalidate_domains = RENDER |
| 2960 | * clflush (obj) |
| 2961 | * MI_FLUSH |
| 2962 | * drm_agp_chipset_flush |
| 2963 | * 4. Updated (written) by CPU again |
| 2964 | * (CPU, CPU) |
| 2965 | * flush_domains = 0 (no previous write domain) |
| 2966 | * invalidate_domains = 0 (no new read domains) |
| 2967 | * 5. Read by GPU |
| 2968 | * (CPU+RENDER, 0) |
| 2969 | * flush_domains = CPU |
| 2970 | * invalidate_domains = RENDER |
| 2971 | * clflush (obj) |
| 2972 | * MI_FLUSH |
| 2973 | * drm_agp_chipset_flush |
| 2974 | */ |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 2975 | static void |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 2976 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2977 | { |
| 2978 | struct drm_device *dev = obj->dev; |
| 2979 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2980 | uint32_t invalidate_domains = 0; |
| 2981 | uint32_t flush_domains = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 2982 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2983 | |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 2984 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
| 2985 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2986 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 2987 | intel_mark_busy(dev, obj); |
| 2988 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2989 | #if WATCH_BUF |
| 2990 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", |
| 2991 | __func__, obj, |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 2992 | obj->read_domains, obj->pending_read_domains, |
| 2993 | obj->write_domain, obj->pending_write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2994 | #endif |
| 2995 | /* |
| 2996 | * If the object isn't moving to a new write domain, |
| 2997 | * let the object stay in multiple read domains |
| 2998 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 2999 | if (obj->pending_write_domain == 0) |
| 3000 | obj->pending_read_domains |= obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3001 | else |
| 3002 | obj_priv->dirty = 1; |
| 3003 | |
| 3004 | /* |
| 3005 | * Flush the current write domain if |
| 3006 | * the new read domains don't match. Invalidate |
| 3007 | * any read domains which differ from the old |
| 3008 | * write domain |
| 3009 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3010 | if (obj->write_domain && |
| 3011 | obj->write_domain != obj->pending_read_domains) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3012 | flush_domains |= obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3013 | invalidate_domains |= |
| 3014 | obj->pending_read_domains & ~obj->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3015 | } |
| 3016 | /* |
| 3017 | * Invalidate any read caches which may have |
| 3018 | * stale data. That is, any new read domains. |
| 3019 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3020 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3021 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { |
| 3022 | #if WATCH_BUF |
| 3023 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", |
| 3024 | __func__, flush_domains, invalidate_domains); |
| 3025 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3026 | i915_gem_clflush_object(obj); |
| 3027 | } |
| 3028 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 3029 | old_read_domains = obj->read_domains; |
| 3030 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3031 | /* The actual obj->write_domain will be updated with |
| 3032 | * pending_write_domain after we emit the accumulated flush for all |
| 3033 | * of our domain changes in execbuffers (which clears objects' |
| 3034 | * write_domains). So if we have a current write domain that we |
| 3035 | * aren't changing, set pending_write_domain to that. |
| 3036 | */ |
| 3037 | if (flush_domains == 0 && obj->pending_write_domain == 0) |
| 3038 | obj->pending_write_domain = obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3039 | obj->read_domains = obj->pending_read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3040 | |
| 3041 | dev->invalidate_domains |= invalidate_domains; |
| 3042 | dev->flush_domains |= flush_domains; |
| 3043 | #if WATCH_BUF |
| 3044 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", |
| 3045 | __func__, |
| 3046 | obj->read_domains, obj->write_domain, |
| 3047 | dev->invalidate_domains, dev->flush_domains); |
| 3048 | #endif |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 3049 | |
| 3050 | trace_i915_gem_object_change_domain(obj, |
| 3051 | old_read_domains, |
| 3052 | obj->write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3053 | } |
| 3054 | |
| 3055 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3056 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3057 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3058 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 3059 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 3060 | */ |
| 3061 | static void |
| 3062 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) |
| 3063 | { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3064 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 3065 | |
| 3066 | if (!obj_priv->page_cpu_valid) |
| 3067 | return; |
| 3068 | |
| 3069 | /* If we're partially in the CPU read domain, finish moving it in. |
| 3070 | */ |
| 3071 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3072 | int i; |
| 3073 | |
| 3074 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { |
| 3075 | if (obj_priv->page_cpu_valid[i]) |
| 3076 | continue; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3077 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3078 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3079 | } |
| 3080 | |
| 3081 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 3082 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 3083 | */ |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3084 | kfree(obj_priv->page_cpu_valid); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3085 | obj_priv->page_cpu_valid = NULL; |
| 3086 | } |
| 3087 | |
| 3088 | /** |
| 3089 | * Set the CPU read domain on a range of the object. |
| 3090 | * |
| 3091 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 3092 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 3093 | * pages have been flushed, and will be respected by |
| 3094 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 3095 | * of the whole object. |
| 3096 | * |
| 3097 | * This function returns when the move is complete, including waiting on |
| 3098 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3099 | */ |
| 3100 | static int |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3101 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 3102 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3103 | { |
| 3104 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 3105 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3106 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3107 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3108 | if (offset == 0 && size == obj->size) |
| 3109 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 3110 | |
| 3111 | i915_gem_object_flush_gpu_write_domain(obj); |
| 3112 | /* Wait on any GPU rendering and flushing to occur. */ |
| 3113 | ret = i915_gem_object_wait_rendering(obj); |
| 3114 | if (ret != 0) |
| 3115 | return ret; |
| 3116 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3117 | |
| 3118 | /* If we're already fully in the CPU read domain, we're done. */ |
| 3119 | if (obj_priv->page_cpu_valid == NULL && |
| 3120 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3121 | return 0; |
| 3122 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3123 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 3124 | * newly adding I915_GEM_DOMAIN_CPU |
| 3125 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3126 | if (obj_priv->page_cpu_valid == NULL) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3127 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
| 3128 | GFP_KERNEL); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3129 | if (obj_priv->page_cpu_valid == NULL) |
| 3130 | return -ENOMEM; |
| 3131 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 3132 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3133 | |
| 3134 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 3135 | * perspective. |
| 3136 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3137 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 3138 | i++) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3139 | if (obj_priv->page_cpu_valid[i]) |
| 3140 | continue; |
| 3141 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3142 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3143 | |
| 3144 | obj_priv->page_cpu_valid[i] = 1; |
| 3145 | } |
| 3146 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3147 | /* It should now be out of any other write domains, and we can update |
| 3148 | * the domain values for our changes. |
| 3149 | */ |
| 3150 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 3151 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 3152 | old_read_domains = obj->read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3153 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 3154 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 3155 | trace_i915_gem_object_change_domain(obj, |
| 3156 | old_read_domains, |
| 3157 | obj->write_domain); |
| 3158 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3159 | return 0; |
| 3160 | } |
| 3161 | |
| 3162 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3163 | * Pin an object to the GTT and evaluate the relocations landing in it. |
| 3164 | */ |
| 3165 | static int |
| 3166 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, |
| 3167 | struct drm_file *file_priv, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3168 | struct drm_i915_gem_exec_object *entry, |
| 3169 | struct drm_i915_gem_relocation_entry *relocs) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3170 | { |
| 3171 | struct drm_device *dev = obj->dev; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3172 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3173 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 3174 | int i, ret; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3175 | void __iomem *reloc_page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3176 | |
| 3177 | /* Choose the GTT offset for our buffer and put it there. */ |
| 3178 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); |
| 3179 | if (ret) |
| 3180 | return ret; |
| 3181 | |
| 3182 | entry->offset = obj_priv->gtt_offset; |
| 3183 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3184 | /* Apply the relocations, using the GTT aperture to avoid cache |
| 3185 | * flushing requirements. |
| 3186 | */ |
| 3187 | for (i = 0; i < entry->relocation_count; i++) { |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3188 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3189 | struct drm_gem_object *target_obj; |
| 3190 | struct drm_i915_gem_object *target_obj_priv; |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 3191 | uint32_t reloc_val, reloc_offset; |
| 3192 | uint32_t __iomem *reloc_entry; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3193 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3194 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3195 | reloc->target_handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3196 | if (target_obj == NULL) { |
| 3197 | i915_gem_object_unpin(obj); |
| 3198 | return -EBADF; |
| 3199 | } |
| 3200 | target_obj_priv = target_obj->driver_private; |
| 3201 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3202 | #if WATCH_RELOC |
| 3203 | DRM_INFO("%s: obj %p offset %08x target %d " |
| 3204 | "read %08x write %08x gtt %08x " |
| 3205 | "presumed %08x delta %08x\n", |
| 3206 | __func__, |
| 3207 | obj, |
| 3208 | (int) reloc->offset, |
| 3209 | (int) reloc->target_handle, |
| 3210 | (int) reloc->read_domains, |
| 3211 | (int) reloc->write_domain, |
| 3212 | (int) target_obj_priv->gtt_offset, |
| 3213 | (int) reloc->presumed_offset, |
| 3214 | reloc->delta); |
| 3215 | #endif |
| 3216 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3217 | /* The target buffer should have appeared before us in the |
| 3218 | * exec_object list, so it should have a GTT space bound by now. |
| 3219 | */ |
| 3220 | if (target_obj_priv->gtt_space == NULL) { |
| 3221 | DRM_ERROR("No GTT space found for object %d\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3222 | reloc->target_handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3223 | drm_gem_object_unreference(target_obj); |
| 3224 | i915_gem_object_unpin(obj); |
| 3225 | return -EINVAL; |
| 3226 | } |
| 3227 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3228 | /* Validate that the target is in a valid r/w GPU domain */ |
| 3229 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
| 3230 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3231 | DRM_ERROR("reloc with read/write CPU domains: " |
| 3232 | "obj %p target %d offset %d " |
| 3233 | "read %08x write %08x", |
| 3234 | obj, reloc->target_handle, |
| 3235 | (int) reloc->offset, |
| 3236 | reloc->read_domains, |
| 3237 | reloc->write_domain); |
| 3238 | drm_gem_object_unreference(target_obj); |
| 3239 | i915_gem_object_unpin(obj); |
| 3240 | return -EINVAL; |
| 3241 | } |
| 3242 | if (reloc->write_domain && target_obj->pending_write_domain && |
| 3243 | reloc->write_domain != target_obj->pending_write_domain) { |
| 3244 | DRM_ERROR("Write domain conflict: " |
| 3245 | "obj %p target %d offset %d " |
| 3246 | "new %08x old %08x\n", |
| 3247 | obj, reloc->target_handle, |
| 3248 | (int) reloc->offset, |
| 3249 | reloc->write_domain, |
| 3250 | target_obj->pending_write_domain); |
| 3251 | drm_gem_object_unreference(target_obj); |
| 3252 | i915_gem_object_unpin(obj); |
| 3253 | return -EINVAL; |
| 3254 | } |
| 3255 | |
| 3256 | target_obj->pending_read_domains |= reloc->read_domains; |
| 3257 | target_obj->pending_write_domain |= reloc->write_domain; |
| 3258 | |
| 3259 | /* If the relocation already has the right value in it, no |
| 3260 | * more work needs to be done. |
| 3261 | */ |
| 3262 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
| 3263 | drm_gem_object_unreference(target_obj); |
| 3264 | continue; |
| 3265 | } |
| 3266 | |
| 3267 | /* Check that the relocation address is valid... */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3268 | if (reloc->offset > obj->size - 4) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3269 | DRM_ERROR("Relocation beyond object bounds: " |
| 3270 | "obj %p target %d offset %d size %d.\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3271 | obj, reloc->target_handle, |
| 3272 | (int) reloc->offset, (int) obj->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3273 | drm_gem_object_unreference(target_obj); |
| 3274 | i915_gem_object_unpin(obj); |
| 3275 | return -EINVAL; |
| 3276 | } |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3277 | if (reloc->offset & 3) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3278 | DRM_ERROR("Relocation not 4-byte aligned: " |
| 3279 | "obj %p target %d offset %d.\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3280 | obj, reloc->target_handle, |
| 3281 | (int) reloc->offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3282 | drm_gem_object_unreference(target_obj); |
| 3283 | i915_gem_object_unpin(obj); |
| 3284 | return -EINVAL; |
| 3285 | } |
| 3286 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3287 | /* and points to somewhere within the target object. */ |
Chris Wilson | cd0b9fb | 2009-09-15 23:23:18 +0100 | [diff] [blame] | 3288 | if (reloc->delta >= target_obj->size) { |
| 3289 | DRM_ERROR("Relocation beyond target object bounds: " |
| 3290 | "obj %p target %d delta %d size %d.\n", |
| 3291 | obj, reloc->target_handle, |
| 3292 | (int) reloc->delta, (int) target_obj->size); |
| 3293 | drm_gem_object_unreference(target_obj); |
| 3294 | i915_gem_object_unpin(obj); |
| 3295 | return -EINVAL; |
| 3296 | } |
| 3297 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3298 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 3299 | if (ret != 0) { |
| 3300 | drm_gem_object_unreference(target_obj); |
| 3301 | i915_gem_object_unpin(obj); |
| 3302 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3303 | } |
| 3304 | |
| 3305 | /* Map the page containing the relocation we're going to |
| 3306 | * perform. |
| 3307 | */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3308 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3309 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
| 3310 | (reloc_offset & |
| 3311 | ~(PAGE_SIZE - 1))); |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 3312 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3313 | (reloc_offset & (PAGE_SIZE - 1))); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3314 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3315 | |
| 3316 | #if WATCH_BUF |
| 3317 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3318 | obj, (unsigned int) reloc->offset, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3319 | readl(reloc_entry), reloc_val); |
| 3320 | #endif |
| 3321 | writel(reloc_val, reloc_entry); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3322 | io_mapping_unmap_atomic(reloc_page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3323 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3324 | /* The updated presumed offset for this entry will be |
| 3325 | * copied back out to the user. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3326 | */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3327 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3328 | |
| 3329 | drm_gem_object_unreference(target_obj); |
| 3330 | } |
| 3331 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3332 | #if WATCH_BUF |
| 3333 | if (0) |
| 3334 | i915_gem_dump_object(obj, 128, __func__, ~0); |
| 3335 | #endif |
| 3336 | return 0; |
| 3337 | } |
| 3338 | |
| 3339 | /** Dispatch a batchbuffer to the ring |
| 3340 | */ |
| 3341 | static int |
| 3342 | i915_dispatch_gem_execbuffer(struct drm_device *dev, |
| 3343 | struct drm_i915_gem_execbuffer *exec, |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3344 | struct drm_clip_rect *cliprects, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3345 | uint64_t exec_offset) |
| 3346 | { |
| 3347 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3348 | int nbox = exec->num_cliprects; |
| 3349 | int i = 0, count; |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3350 | uint32_t exec_start, exec_len; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3351 | RING_LOCALS; |
| 3352 | |
| 3353 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3354 | exec_len = (uint32_t) exec->batch_len; |
| 3355 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 3356 | trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno); |
| 3357 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3358 | count = nbox ? nbox : 1; |
| 3359 | |
| 3360 | for (i = 0; i < count; i++) { |
| 3361 | if (i < nbox) { |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3362 | int ret = i915_emit_box(dev, cliprects, i, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3363 | exec->DR1, exec->DR4); |
| 3364 | if (ret) |
| 3365 | return ret; |
| 3366 | } |
| 3367 | |
| 3368 | if (IS_I830(dev) || IS_845G(dev)) { |
| 3369 | BEGIN_LP_RING(4); |
| 3370 | OUT_RING(MI_BATCH_BUFFER); |
| 3371 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); |
| 3372 | OUT_RING(exec_start + exec_len - 4); |
| 3373 | OUT_RING(0); |
| 3374 | ADVANCE_LP_RING(); |
| 3375 | } else { |
| 3376 | BEGIN_LP_RING(2); |
| 3377 | if (IS_I965G(dev)) { |
| 3378 | OUT_RING(MI_BATCH_BUFFER_START | |
| 3379 | (2 << 6) | |
| 3380 | MI_BATCH_NON_SECURE_I965); |
| 3381 | OUT_RING(exec_start); |
| 3382 | } else { |
| 3383 | OUT_RING(MI_BATCH_BUFFER_START | |
| 3384 | (2 << 6)); |
| 3385 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); |
| 3386 | } |
| 3387 | ADVANCE_LP_RING(); |
| 3388 | } |
| 3389 | } |
| 3390 | |
| 3391 | /* XXX breadcrumb */ |
| 3392 | return 0; |
| 3393 | } |
| 3394 | |
| 3395 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3396 | * emitted over 20 msec ago. |
| 3397 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3398 | * Note that if we were to use the current jiffies each time around the loop, |
| 3399 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3400 | * render a frame was over 20ms. |
| 3401 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3402 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3403 | * relatively low latency when blocking on a particular request to finish. |
| 3404 | */ |
| 3405 | static int |
| 3406 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) |
| 3407 | { |
| 3408 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; |
| 3409 | int ret = 0; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3410 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3411 | |
| 3412 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3413 | while (!list_empty(&i915_file_priv->mm.request_list)) { |
| 3414 | struct drm_i915_gem_request *request; |
| 3415 | |
| 3416 | request = list_first_entry(&i915_file_priv->mm.request_list, |
| 3417 | struct drm_i915_gem_request, |
| 3418 | client_list); |
| 3419 | |
| 3420 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3421 | break; |
| 3422 | |
| 3423 | ret = i915_wait_request(dev, request->seqno); |
| 3424 | if (ret != 0) |
| 3425 | break; |
| 3426 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3427 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3428 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3429 | return ret; |
| 3430 | } |
| 3431 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3432 | static int |
| 3433 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list, |
| 3434 | uint32_t buffer_count, |
| 3435 | struct drm_i915_gem_relocation_entry **relocs) |
| 3436 | { |
| 3437 | uint32_t reloc_count = 0, reloc_index = 0, i; |
| 3438 | int ret; |
| 3439 | |
| 3440 | *relocs = NULL; |
| 3441 | for (i = 0; i < buffer_count; i++) { |
| 3442 | if (reloc_count + exec_list[i].relocation_count < reloc_count) |
| 3443 | return -EINVAL; |
| 3444 | reloc_count += exec_list[i].relocation_count; |
| 3445 | } |
| 3446 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3447 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3448 | if (*relocs == NULL) |
| 3449 | return -ENOMEM; |
| 3450 | |
| 3451 | for (i = 0; i < buffer_count; i++) { |
| 3452 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
| 3453 | |
| 3454 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; |
| 3455 | |
| 3456 | ret = copy_from_user(&(*relocs)[reloc_index], |
| 3457 | user_relocs, |
| 3458 | exec_list[i].relocation_count * |
| 3459 | sizeof(**relocs)); |
| 3460 | if (ret != 0) { |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3461 | drm_free_large(*relocs); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3462 | *relocs = NULL; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3463 | return -EFAULT; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3464 | } |
| 3465 | |
| 3466 | reloc_index += exec_list[i].relocation_count; |
| 3467 | } |
| 3468 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3469 | return 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3470 | } |
| 3471 | |
| 3472 | static int |
| 3473 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list, |
| 3474 | uint32_t buffer_count, |
| 3475 | struct drm_i915_gem_relocation_entry *relocs) |
| 3476 | { |
| 3477 | uint32_t reloc_count = 0, i; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3478 | int ret = 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3479 | |
| 3480 | for (i = 0; i < buffer_count; i++) { |
| 3481 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3482 | int unwritten; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3483 | |
| 3484 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; |
| 3485 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3486 | unwritten = copy_to_user(user_relocs, |
| 3487 | &relocs[reloc_count], |
| 3488 | exec_list[i].relocation_count * |
| 3489 | sizeof(*relocs)); |
| 3490 | |
| 3491 | if (unwritten) { |
| 3492 | ret = -EFAULT; |
| 3493 | goto err; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3494 | } |
| 3495 | |
| 3496 | reloc_count += exec_list[i].relocation_count; |
| 3497 | } |
| 3498 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3499 | err: |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3500 | drm_free_large(relocs); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3501 | |
| 3502 | return ret; |
| 3503 | } |
| 3504 | |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3505 | static int |
| 3506 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec, |
| 3507 | uint64_t exec_offset) |
| 3508 | { |
| 3509 | uint32_t exec_start, exec_len; |
| 3510 | |
| 3511 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3512 | exec_len = (uint32_t) exec->batch_len; |
| 3513 | |
| 3514 | if ((exec_start | exec_len) & 0x7) |
| 3515 | return -EINVAL; |
| 3516 | |
| 3517 | if (!exec_start) |
| 3518 | return -EINVAL; |
| 3519 | |
| 3520 | return 0; |
| 3521 | } |
| 3522 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3523 | int |
| 3524 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 3525 | struct drm_file *file_priv) |
| 3526 | { |
| 3527 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3528 | struct drm_i915_gem_execbuffer *args = data; |
| 3529 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 3530 | struct drm_gem_object **object_list = NULL; |
| 3531 | struct drm_gem_object *batch_obj; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3532 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3533 | struct drm_clip_rect *cliprects = NULL; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3534 | struct drm_i915_gem_relocation_entry *relocs; |
| 3535 | int ret, ret2, i, pinned = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3536 | uint64_t exec_offset; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3537 | uint32_t seqno, flush_domains, reloc_index; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3538 | int pin_tries; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3539 | |
| 3540 | #if WATCH_EXEC |
| 3541 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3542 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3543 | #endif |
| 3544 | |
Eric Anholt | 4f481ed | 2008-09-10 14:22:49 -0700 | [diff] [blame] | 3545 | if (args->buffer_count < 1) { |
| 3546 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3547 | return -EINVAL; |
| 3548 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3549 | /* Copy in the exec list from userland */ |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3550 | exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count); |
| 3551 | object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3552 | if (exec_list == NULL || object_list == NULL) { |
| 3553 | DRM_ERROR("Failed to allocate exec or object list " |
| 3554 | "for %d buffers\n", |
| 3555 | args->buffer_count); |
| 3556 | ret = -ENOMEM; |
| 3557 | goto pre_mutex_err; |
| 3558 | } |
| 3559 | ret = copy_from_user(exec_list, |
| 3560 | (struct drm_i915_relocation_entry __user *) |
| 3561 | (uintptr_t) args->buffers_ptr, |
| 3562 | sizeof(*exec_list) * args->buffer_count); |
| 3563 | if (ret != 0) { |
| 3564 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 3565 | args->buffer_count, ret); |
| 3566 | goto pre_mutex_err; |
| 3567 | } |
| 3568 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3569 | if (args->num_cliprects != 0) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3570 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
| 3571 | GFP_KERNEL); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3572 | if (cliprects == NULL) |
| 3573 | goto pre_mutex_err; |
| 3574 | |
| 3575 | ret = copy_from_user(cliprects, |
| 3576 | (struct drm_clip_rect __user *) |
| 3577 | (uintptr_t) args->cliprects_ptr, |
| 3578 | sizeof(*cliprects) * args->num_cliprects); |
| 3579 | if (ret != 0) { |
| 3580 | DRM_ERROR("copy %d cliprects failed: %d\n", |
| 3581 | args->num_cliprects, ret); |
| 3582 | goto pre_mutex_err; |
| 3583 | } |
| 3584 | } |
| 3585 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3586 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
| 3587 | &relocs); |
| 3588 | if (ret != 0) |
| 3589 | goto pre_mutex_err; |
| 3590 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3591 | mutex_lock(&dev->struct_mutex); |
| 3592 | |
| 3593 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3594 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3595 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3596 | DRM_ERROR("Execbuf while wedged\n"); |
| 3597 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3598 | ret = -EIO; |
| 3599 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3600 | } |
| 3601 | |
| 3602 | if (dev_priv->mm.suspended) { |
| 3603 | DRM_ERROR("Execbuf while VT-switched.\n"); |
| 3604 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3605 | ret = -EBUSY; |
| 3606 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3607 | } |
| 3608 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3609 | /* Look up object handles */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3610 | for (i = 0; i < args->buffer_count; i++) { |
| 3611 | object_list[i] = drm_gem_object_lookup(dev, file_priv, |
| 3612 | exec_list[i].handle); |
| 3613 | if (object_list[i] == NULL) { |
| 3614 | DRM_ERROR("Invalid object handle %d at index %d\n", |
| 3615 | exec_list[i].handle, i); |
| 3616 | ret = -EBADF; |
| 3617 | goto err; |
| 3618 | } |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3619 | |
| 3620 | obj_priv = object_list[i]->driver_private; |
| 3621 | if (obj_priv->in_execbuffer) { |
| 3622 | DRM_ERROR("Object %p appears more than once in object list\n", |
| 3623 | object_list[i]); |
| 3624 | ret = -EBADF; |
| 3625 | goto err; |
| 3626 | } |
| 3627 | obj_priv->in_execbuffer = true; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3628 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3629 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3630 | /* Pin and relocate */ |
| 3631 | for (pin_tries = 0; ; pin_tries++) { |
| 3632 | ret = 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3633 | reloc_index = 0; |
| 3634 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3635 | for (i = 0; i < args->buffer_count; i++) { |
| 3636 | object_list[i]->pending_read_domains = 0; |
| 3637 | object_list[i]->pending_write_domain = 0; |
| 3638 | ret = i915_gem_object_pin_and_relocate(object_list[i], |
| 3639 | file_priv, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3640 | &exec_list[i], |
| 3641 | &relocs[reloc_index]); |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3642 | if (ret) |
| 3643 | break; |
| 3644 | pinned = i + 1; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3645 | reloc_index += exec_list[i].relocation_count; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3646 | } |
| 3647 | /* success */ |
| 3648 | if (ret == 0) |
| 3649 | break; |
| 3650 | |
| 3651 | /* error other than GTT full, or we've already tried again */ |
Chris Wilson | 2939e1f | 2009-06-06 09:46:03 +0100 | [diff] [blame] | 3652 | if (ret != -ENOSPC || pin_tries >= 1) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3653 | if (ret != -ERESTARTSYS) { |
| 3654 | unsigned long long total_size = 0; |
| 3655 | for (i = 0; i < args->buffer_count; i++) |
| 3656 | total_size += object_list[i]->size; |
| 3657 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n", |
| 3658 | pinned+1, args->buffer_count, |
| 3659 | total_size, ret); |
| 3660 | DRM_ERROR("%d objects [%d pinned], " |
| 3661 | "%d object bytes [%d pinned], " |
| 3662 | "%d/%d gtt bytes\n", |
| 3663 | atomic_read(&dev->object_count), |
| 3664 | atomic_read(&dev->pin_count), |
| 3665 | atomic_read(&dev->object_memory), |
| 3666 | atomic_read(&dev->pin_memory), |
| 3667 | atomic_read(&dev->gtt_memory), |
| 3668 | dev->gtt_total); |
| 3669 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3670 | goto err; |
| 3671 | } |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3672 | |
| 3673 | /* unpin all of our buffers */ |
| 3674 | for (i = 0; i < pinned; i++) |
| 3675 | i915_gem_object_unpin(object_list[i]); |
Eric Anholt | b117763 | 2008-12-10 10:09:41 -0800 | [diff] [blame] | 3676 | pinned = 0; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3677 | |
| 3678 | /* evict everyone we can from the aperture */ |
| 3679 | ret = i915_gem_evict_everything(dev); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3680 | if (ret && ret != -ENOSPC) |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3681 | goto err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3682 | } |
| 3683 | |
| 3684 | /* Set the pending read domains for the batch buffer to COMMAND */ |
| 3685 | batch_obj = object_list[args->buffer_count-1]; |
Chris Wilson | 5f26a2c | 2009-06-06 09:45:58 +0100 | [diff] [blame] | 3686 | if (batch_obj->pending_write_domain) { |
| 3687 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); |
| 3688 | ret = -EINVAL; |
| 3689 | goto err; |
| 3690 | } |
| 3691 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3692 | |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3693 | /* Sanity check the batch buffer, prior to moving objects */ |
| 3694 | exec_offset = exec_list[args->buffer_count - 1].offset; |
| 3695 | ret = i915_gem_check_execbuffer (args, exec_offset); |
| 3696 | if (ret != 0) { |
| 3697 | DRM_ERROR("execbuf with invalid offset/length\n"); |
| 3698 | goto err; |
| 3699 | } |
| 3700 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3701 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3702 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3703 | /* Zero the global flush/invalidate flags. These |
| 3704 | * will be modified as new domains are computed |
| 3705 | * for each object |
| 3706 | */ |
| 3707 | dev->invalidate_domains = 0; |
| 3708 | dev->flush_domains = 0; |
| 3709 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3710 | for (i = 0; i < args->buffer_count; i++) { |
| 3711 | struct drm_gem_object *obj = object_list[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3712 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3713 | /* Compute new gpu domains and update invalidate/flush */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3714 | i915_gem_object_set_to_gpu_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3715 | } |
| 3716 | |
| 3717 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3718 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3719 | if (dev->invalidate_domains | dev->flush_domains) { |
| 3720 | #if WATCH_EXEC |
| 3721 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", |
| 3722 | __func__, |
| 3723 | dev->invalidate_domains, |
| 3724 | dev->flush_domains); |
| 3725 | #endif |
| 3726 | i915_gem_flush(dev, |
| 3727 | dev->invalidate_domains, |
| 3728 | dev->flush_domains); |
| 3729 | if (dev->flush_domains) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3730 | (void)i915_add_request(dev, file_priv, |
| 3731 | dev->flush_domains); |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3732 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3733 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3734 | for (i = 0; i < args->buffer_count; i++) { |
| 3735 | struct drm_gem_object *obj = object_list[i]; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 3736 | uint32_t old_write_domain = obj->write_domain; |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3737 | |
| 3738 | obj->write_domain = obj->pending_write_domain; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 3739 | trace_i915_gem_object_change_domain(obj, |
| 3740 | obj->read_domains, |
| 3741 | old_write_domain); |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3742 | } |
| 3743 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3744 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3745 | |
| 3746 | #if WATCH_COHERENCY |
| 3747 | for (i = 0; i < args->buffer_count; i++) { |
| 3748 | i915_gem_object_check_coherency(object_list[i], |
| 3749 | exec_list[i].handle); |
| 3750 | } |
| 3751 | #endif |
| 3752 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3753 | #if WATCH_EXEC |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 3754 | i915_gem_dump_object(batch_obj, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3755 | args->batch_len, |
| 3756 | __func__, |
| 3757 | ~0); |
| 3758 | #endif |
| 3759 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3760 | /* Exec the batchbuffer */ |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3761 | ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3762 | if (ret) { |
| 3763 | DRM_ERROR("dispatch failed %d\n", ret); |
| 3764 | goto err; |
| 3765 | } |
| 3766 | |
| 3767 | /* |
| 3768 | * Ensure that the commands in the batch buffer are |
| 3769 | * finished before the interrupt fires |
| 3770 | */ |
| 3771 | flush_domains = i915_retire_commands(dev); |
| 3772 | |
| 3773 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3774 | |
| 3775 | /* |
| 3776 | * Get a seqno representing the execution of the current buffer, |
| 3777 | * which we can wait on. We would like to mitigate these interrupts, |
| 3778 | * likely by only creating seqnos occasionally (so that we have |
| 3779 | * *some* interrupts representing completion of buffers that we can |
| 3780 | * wait on when trying to clear up gtt space). |
| 3781 | */ |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3782 | seqno = i915_add_request(dev, file_priv, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3783 | BUG_ON(seqno == 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3784 | for (i = 0; i < args->buffer_count; i++) { |
| 3785 | struct drm_gem_object *obj = object_list[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3786 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 3787 | i915_gem_object_move_to_active(obj, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3788 | #if WATCH_LRU |
| 3789 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); |
| 3790 | #endif |
| 3791 | } |
| 3792 | #if WATCH_LRU |
| 3793 | i915_dump_lru(dev, __func__); |
| 3794 | #endif |
| 3795 | |
| 3796 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3797 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3798 | err: |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3799 | for (i = 0; i < pinned; i++) |
| 3800 | i915_gem_object_unpin(object_list[i]); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3801 | |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3802 | for (i = 0; i < args->buffer_count; i++) { |
| 3803 | if (object_list[i]) { |
| 3804 | obj_priv = object_list[i]->driver_private; |
| 3805 | obj_priv->in_execbuffer = false; |
| 3806 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3807 | drm_gem_object_unreference(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3808 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3809 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3810 | mutex_unlock(&dev->struct_mutex); |
| 3811 | |
Roland Dreier | a35f2e2 | 2009-02-06 17:48:09 -0800 | [diff] [blame] | 3812 | if (!ret) { |
| 3813 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 3814 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 3815 | (uintptr_t) args->buffers_ptr, |
| 3816 | exec_list, |
| 3817 | sizeof(*exec_list) * args->buffer_count); |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3818 | if (ret) { |
| 3819 | ret = -EFAULT; |
Roland Dreier | a35f2e2 | 2009-02-06 17:48:09 -0800 | [diff] [blame] | 3820 | DRM_ERROR("failed to copy %d exec entries " |
| 3821 | "back to user (%d)\n", |
| 3822 | args->buffer_count, ret); |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3823 | } |
Roland Dreier | a35f2e2 | 2009-02-06 17:48:09 -0800 | [diff] [blame] | 3824 | } |
| 3825 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3826 | /* Copy the updated relocations out regardless of current error |
| 3827 | * state. Failure to update the relocs would mean that the next |
| 3828 | * time userland calls execbuf, it would do so with presumed offset |
| 3829 | * state that didn't match the actual object state. |
| 3830 | */ |
| 3831 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, |
| 3832 | relocs); |
| 3833 | if (ret2 != 0) { |
| 3834 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); |
| 3835 | |
| 3836 | if (ret == 0) |
| 3837 | ret = ret2; |
| 3838 | } |
| 3839 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3840 | pre_mutex_err: |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3841 | drm_free_large(object_list); |
| 3842 | drm_free_large(exec_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3843 | kfree(cliprects); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3844 | |
| 3845 | return ret; |
| 3846 | } |
| 3847 | |
| 3848 | int |
| 3849 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) |
| 3850 | { |
| 3851 | struct drm_device *dev = obj->dev; |
| 3852 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 3853 | int ret; |
| 3854 | |
| 3855 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3856 | if (obj_priv->gtt_space == NULL) { |
| 3857 | ret = i915_gem_object_bind_to_gtt(obj, alignment); |
| 3858 | if (ret != 0) { |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3859 | if (ret != -EBUSY && ret != -ERESTARTSYS) |
Kyle McMartin | 0fce81e | 2009-02-28 15:01:16 -0500 | [diff] [blame] | 3860 | DRM_ERROR("Failure to bind: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3861 | return ret; |
| 3862 | } |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3863 | } |
| 3864 | /* |
| 3865 | * Pre-965 chips need a fence register set up in order to |
| 3866 | * properly handle tiled surfaces. |
| 3867 | */ |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3868 | if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 3869 | ret = i915_gem_object_get_fence_reg(obj); |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3870 | if (ret != 0) { |
| 3871 | if (ret != -EBUSY && ret != -ERESTARTSYS) |
| 3872 | DRM_ERROR("Failure to install fence: %d\n", |
| 3873 | ret); |
| 3874 | return ret; |
| 3875 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3876 | } |
| 3877 | obj_priv->pin_count++; |
| 3878 | |
| 3879 | /* If the object is not active and not pending a flush, |
| 3880 | * remove it from the inactive list |
| 3881 | */ |
| 3882 | if (obj_priv->pin_count == 1) { |
| 3883 | atomic_inc(&dev->pin_count); |
| 3884 | atomic_add(obj->size, &dev->pin_memory); |
| 3885 | if (!obj_priv->active && |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 3886 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 && |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3887 | !list_empty(&obj_priv->list)) |
| 3888 | list_del_init(&obj_priv->list); |
| 3889 | } |
| 3890 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3891 | |
| 3892 | return 0; |
| 3893 | } |
| 3894 | |
| 3895 | void |
| 3896 | i915_gem_object_unpin(struct drm_gem_object *obj) |
| 3897 | { |
| 3898 | struct drm_device *dev = obj->dev; |
| 3899 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3900 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 3901 | |
| 3902 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3903 | obj_priv->pin_count--; |
| 3904 | BUG_ON(obj_priv->pin_count < 0); |
| 3905 | BUG_ON(obj_priv->gtt_space == NULL); |
| 3906 | |
| 3907 | /* If the object is no longer pinned, and is |
| 3908 | * neither active nor being flushed, then stick it on |
| 3909 | * the inactive list |
| 3910 | */ |
| 3911 | if (obj_priv->pin_count == 0) { |
| 3912 | if (!obj_priv->active && |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 3913 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3914 | list_move_tail(&obj_priv->list, |
| 3915 | &dev_priv->mm.inactive_list); |
| 3916 | atomic_dec(&dev->pin_count); |
| 3917 | atomic_sub(obj->size, &dev->pin_memory); |
| 3918 | } |
| 3919 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3920 | } |
| 3921 | |
| 3922 | int |
| 3923 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 3924 | struct drm_file *file_priv) |
| 3925 | { |
| 3926 | struct drm_i915_gem_pin *args = data; |
| 3927 | struct drm_gem_object *obj; |
| 3928 | struct drm_i915_gem_object *obj_priv; |
| 3929 | int ret; |
| 3930 | |
| 3931 | mutex_lock(&dev->struct_mutex); |
| 3932 | |
| 3933 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 3934 | if (obj == NULL) { |
| 3935 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", |
| 3936 | args->handle); |
| 3937 | mutex_unlock(&dev->struct_mutex); |
| 3938 | return -EBADF; |
| 3939 | } |
| 3940 | obj_priv = obj->driver_private; |
| 3941 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3942 | if (obj_priv->madv == I915_MADV_DONTNEED) { |
| 3943 | DRM_ERROR("Attempting to pin a I915_MADV_DONTNEED buffer\n"); |
| 3944 | drm_gem_object_unreference(obj); |
| 3945 | mutex_unlock(&dev->struct_mutex); |
| 3946 | return -EINVAL; |
| 3947 | } |
| 3948 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3949 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
| 3950 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 3951 | args->handle); |
Chris Wilson | 96dec61 | 2009-02-08 19:08:04 +0000 | [diff] [blame] | 3952 | drm_gem_object_unreference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3953 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3954 | return -EINVAL; |
| 3955 | } |
| 3956 | |
| 3957 | obj_priv->user_pin_count++; |
| 3958 | obj_priv->pin_filp = file_priv; |
| 3959 | if (obj_priv->user_pin_count == 1) { |
| 3960 | ret = i915_gem_object_pin(obj, args->alignment); |
| 3961 | if (ret != 0) { |
| 3962 | drm_gem_object_unreference(obj); |
| 3963 | mutex_unlock(&dev->struct_mutex); |
| 3964 | return ret; |
| 3965 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3966 | } |
| 3967 | |
| 3968 | /* XXX - flush the CPU caches for pinned objects |
| 3969 | * as the X server doesn't manage domains yet |
| 3970 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3971 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3972 | args->offset = obj_priv->gtt_offset; |
| 3973 | drm_gem_object_unreference(obj); |
| 3974 | mutex_unlock(&dev->struct_mutex); |
| 3975 | |
| 3976 | return 0; |
| 3977 | } |
| 3978 | |
| 3979 | int |
| 3980 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 3981 | struct drm_file *file_priv) |
| 3982 | { |
| 3983 | struct drm_i915_gem_pin *args = data; |
| 3984 | struct drm_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3985 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3986 | |
| 3987 | mutex_lock(&dev->struct_mutex); |
| 3988 | |
| 3989 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 3990 | if (obj == NULL) { |
| 3991 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", |
| 3992 | args->handle); |
| 3993 | mutex_unlock(&dev->struct_mutex); |
| 3994 | return -EBADF; |
| 3995 | } |
| 3996 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3997 | obj_priv = obj->driver_private; |
| 3998 | if (obj_priv->pin_filp != file_priv) { |
| 3999 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 4000 | args->handle); |
| 4001 | drm_gem_object_unreference(obj); |
| 4002 | mutex_unlock(&dev->struct_mutex); |
| 4003 | return -EINVAL; |
| 4004 | } |
| 4005 | obj_priv->user_pin_count--; |
| 4006 | if (obj_priv->user_pin_count == 0) { |
| 4007 | obj_priv->pin_filp = NULL; |
| 4008 | i915_gem_object_unpin(obj); |
| 4009 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4010 | |
| 4011 | drm_gem_object_unreference(obj); |
| 4012 | mutex_unlock(&dev->struct_mutex); |
| 4013 | return 0; |
| 4014 | } |
| 4015 | |
| 4016 | int |
| 4017 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 4018 | struct drm_file *file_priv) |
| 4019 | { |
| 4020 | struct drm_i915_gem_busy *args = data; |
| 4021 | struct drm_gem_object *obj; |
| 4022 | struct drm_i915_gem_object *obj_priv; |
| 4023 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4024 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4025 | if (obj == NULL) { |
| 4026 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", |
| 4027 | args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4028 | return -EBADF; |
| 4029 | } |
| 4030 | |
Chris Wilson | b1ce786 | 2009-06-06 09:46:00 +0100 | [diff] [blame] | 4031 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | f21289b | 2009-02-18 09:44:56 -0800 | [diff] [blame] | 4032 | /* Update the active list for the hardware's current position. |
| 4033 | * Otherwise this only updates on a delayed timer or when irqs are |
| 4034 | * actually unmasked, and our working set ends up being larger than |
| 4035 | * required. |
| 4036 | */ |
| 4037 | i915_gem_retire_requests(dev); |
| 4038 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4039 | obj_priv = obj->driver_private; |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4040 | /* Don't count being on the flushing list against the object being |
| 4041 | * done. Otherwise, a buffer left on the flushing list but not getting |
| 4042 | * flushed (because nobody's flushing that domain) won't ever return |
| 4043 | * unbusy and get reused by libdrm's bo cache. The other expected |
| 4044 | * consumer of this interface, OpenGL's occlusion queries, also specs |
| 4045 | * that the objects get unbusy "eventually" without any interference. |
| 4046 | */ |
| 4047 | args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4048 | |
| 4049 | drm_gem_object_unreference(obj); |
| 4050 | mutex_unlock(&dev->struct_mutex); |
| 4051 | return 0; |
| 4052 | } |
| 4053 | |
| 4054 | int |
| 4055 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4056 | struct drm_file *file_priv) |
| 4057 | { |
| 4058 | return i915_gem_ring_throttle(dev, file_priv); |
| 4059 | } |
| 4060 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4061 | int |
| 4062 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4063 | struct drm_file *file_priv) |
| 4064 | { |
| 4065 | struct drm_i915_gem_madvise *args = data; |
| 4066 | struct drm_gem_object *obj; |
| 4067 | struct drm_i915_gem_object *obj_priv; |
| 4068 | |
| 4069 | switch (args->madv) { |
| 4070 | case I915_MADV_DONTNEED: |
| 4071 | case I915_MADV_WILLNEED: |
| 4072 | break; |
| 4073 | default: |
| 4074 | return -EINVAL; |
| 4075 | } |
| 4076 | |
| 4077 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4078 | if (obj == NULL) { |
| 4079 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", |
| 4080 | args->handle); |
| 4081 | return -EBADF; |
| 4082 | } |
| 4083 | |
| 4084 | mutex_lock(&dev->struct_mutex); |
| 4085 | obj_priv = obj->driver_private; |
| 4086 | |
| 4087 | if (obj_priv->pin_count) { |
| 4088 | drm_gem_object_unreference(obj); |
| 4089 | mutex_unlock(&dev->struct_mutex); |
| 4090 | |
| 4091 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); |
| 4092 | return -EINVAL; |
| 4093 | } |
| 4094 | |
| 4095 | obj_priv->madv = args->madv; |
| 4096 | args->retained = obj_priv->gtt_space != NULL; |
| 4097 | |
| 4098 | drm_gem_object_unreference(obj); |
| 4099 | mutex_unlock(&dev->struct_mutex); |
| 4100 | |
| 4101 | return 0; |
| 4102 | } |
| 4103 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4104 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 4105 | { |
| 4106 | struct drm_i915_gem_object *obj_priv; |
| 4107 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4108 | obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4109 | if (obj_priv == NULL) |
| 4110 | return -ENOMEM; |
| 4111 | |
| 4112 | /* |
| 4113 | * We've just allocated pages from the kernel, |
| 4114 | * so they've just been written by the CPU with |
| 4115 | * zeros. They'll need to be clflushed before we |
| 4116 | * use them with the GPU. |
| 4117 | */ |
| 4118 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 4119 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
| 4120 | |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 4121 | obj_priv->agp_type = AGP_USER_MEMORY; |
| 4122 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4123 | obj->driver_private = obj_priv; |
| 4124 | obj_priv->obj = obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4125 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4126 | INIT_LIST_HEAD(&obj_priv->list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4127 | INIT_LIST_HEAD(&obj_priv->fence_list); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4128 | obj_priv->madv = I915_MADV_WILLNEED; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4129 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 4130 | trace_i915_gem_object_create(obj); |
| 4131 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4132 | return 0; |
| 4133 | } |
| 4134 | |
| 4135 | void i915_gem_free_object(struct drm_gem_object *obj) |
| 4136 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4137 | struct drm_device *dev = obj->dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4138 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 4139 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 4140 | trace_i915_gem_object_destroy(obj); |
| 4141 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4142 | while (obj_priv->pin_count > 0) |
| 4143 | i915_gem_object_unpin(obj); |
| 4144 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4145 | if (obj_priv->phys_obj) |
| 4146 | i915_gem_detach_phys_object(dev, obj); |
| 4147 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4148 | i915_gem_object_unbind(obj); |
| 4149 | |
Chris Wilson | 7e61615 | 2009-09-10 08:53:04 +0100 | [diff] [blame] | 4150 | if (obj_priv->mmap_offset) |
| 4151 | i915_gem_free_mmap_offset(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4152 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4153 | kfree(obj_priv->page_cpu_valid); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 4154 | kfree(obj_priv->bit_17); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4155 | kfree(obj->driver_private); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4156 | } |
| 4157 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4158 | /** Unbinds all objects that are on the given buffer list. */ |
| 4159 | static int |
| 4160 | i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head) |
| 4161 | { |
| 4162 | struct drm_gem_object *obj; |
| 4163 | struct drm_i915_gem_object *obj_priv; |
| 4164 | int ret; |
| 4165 | |
| 4166 | while (!list_empty(head)) { |
| 4167 | obj_priv = list_first_entry(head, |
| 4168 | struct drm_i915_gem_object, |
| 4169 | list); |
| 4170 | obj = obj_priv->obj; |
| 4171 | |
| 4172 | if (obj_priv->pin_count != 0) { |
| 4173 | DRM_ERROR("Pinned object in unbind list\n"); |
| 4174 | mutex_unlock(&dev->struct_mutex); |
| 4175 | return -EINVAL; |
| 4176 | } |
| 4177 | |
| 4178 | ret = i915_gem_object_unbind(obj); |
| 4179 | if (ret != 0) { |
| 4180 | DRM_ERROR("Error unbinding object in LeaveVT: %d\n", |
| 4181 | ret); |
| 4182 | mutex_unlock(&dev->struct_mutex); |
| 4183 | return ret; |
| 4184 | } |
| 4185 | } |
| 4186 | |
| 4187 | |
| 4188 | return 0; |
| 4189 | } |
| 4190 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4191 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4192 | i915_gem_idle(struct drm_device *dev) |
| 4193 | { |
| 4194 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4195 | uint32_t seqno, cur_seqno, last_seqno; |
| 4196 | int stuck, ret; |
| 4197 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4198 | mutex_lock(&dev->struct_mutex); |
| 4199 | |
| 4200 | if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) { |
| 4201 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4202 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4203 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4204 | |
| 4205 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4206 | * We need to replace this with a semaphore, or something. |
| 4207 | */ |
| 4208 | dev_priv->mm.suspended = 1; |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 4209 | del_timer(&dev_priv->hangcheck_timer); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4210 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4211 | /* Cancel the retire work handler, wait for it to finish if running |
| 4212 | */ |
| 4213 | mutex_unlock(&dev->struct_mutex); |
| 4214 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4215 | mutex_lock(&dev->struct_mutex); |
| 4216 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4217 | i915_kernel_lost_context(dev); |
| 4218 | |
| 4219 | /* Flush the GPU along with all non-CPU write domains |
| 4220 | */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 4221 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 4222 | seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4223 | |
| 4224 | if (seqno == 0) { |
| 4225 | mutex_unlock(&dev->struct_mutex); |
| 4226 | return -ENOMEM; |
| 4227 | } |
| 4228 | |
| 4229 | dev_priv->mm.waiting_gem_seqno = seqno; |
| 4230 | last_seqno = 0; |
| 4231 | stuck = 0; |
| 4232 | for (;;) { |
| 4233 | cur_seqno = i915_get_gem_seqno(dev); |
| 4234 | if (i915_seqno_passed(cur_seqno, seqno)) |
| 4235 | break; |
| 4236 | if (last_seqno == cur_seqno) { |
| 4237 | if (stuck++ > 100) { |
| 4238 | DRM_ERROR("hardware wedged\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4239 | atomic_set(&dev_priv->mm.wedged, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4240 | DRM_WAKEUP(&dev_priv->irq_queue); |
| 4241 | break; |
| 4242 | } |
| 4243 | } |
| 4244 | msleep(10); |
| 4245 | last_seqno = cur_seqno; |
| 4246 | } |
| 4247 | dev_priv->mm.waiting_gem_seqno = 0; |
| 4248 | |
| 4249 | i915_gem_retire_requests(dev); |
| 4250 | |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4251 | spin_lock(&dev_priv->mm.active_list_lock); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4252 | if (!atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4253 | /* Active and flushing should now be empty as we've |
| 4254 | * waited for a sequence higher than any pending execbuffer |
| 4255 | */ |
| 4256 | WARN_ON(!list_empty(&dev_priv->mm.active_list)); |
| 4257 | WARN_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 4258 | /* Request should now be empty as we've also waited |
| 4259 | * for the last request in the list |
| 4260 | */ |
| 4261 | WARN_ON(!list_empty(&dev_priv->mm.request_list)); |
| 4262 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4263 | |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4264 | /* Empty the active and flushing lists to inactive. If there's |
| 4265 | * anything left at this point, it means that we're wedged and |
| 4266 | * nothing good's going to happen by leaving them there. So strip |
| 4267 | * the GPU domains and just stuff them onto inactive. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4268 | */ |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4269 | while (!list_empty(&dev_priv->mm.active_list)) { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 4270 | struct drm_gem_object *obj; |
| 4271 | uint32_t old_write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4272 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 4273 | obj = list_first_entry(&dev_priv->mm.active_list, |
| 4274 | struct drm_i915_gem_object, |
| 4275 | list)->obj; |
| 4276 | old_write_domain = obj->write_domain; |
| 4277 | obj->write_domain &= ~I915_GEM_GPU_DOMAINS; |
| 4278 | i915_gem_object_move_to_inactive(obj); |
| 4279 | |
| 4280 | trace_i915_gem_object_change_domain(obj, |
| 4281 | obj->read_domains, |
| 4282 | old_write_domain); |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4283 | } |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4284 | spin_unlock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4285 | |
| 4286 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 4287 | struct drm_gem_object *obj; |
| 4288 | uint32_t old_write_domain; |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4289 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame^] | 4290 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
| 4291 | struct drm_i915_gem_object, |
| 4292 | list)->obj; |
| 4293 | old_write_domain = obj->write_domain; |
| 4294 | obj->write_domain &= ~I915_GEM_GPU_DOMAINS; |
| 4295 | i915_gem_object_move_to_inactive(obj); |
| 4296 | |
| 4297 | trace_i915_gem_object_change_domain(obj, |
| 4298 | obj->read_domains, |
| 4299 | old_write_domain); |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4300 | } |
| 4301 | |
| 4302 | |
| 4303 | /* Move all inactive buffers out of the GTT. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4304 | ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list); |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4305 | WARN_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4306 | if (ret) { |
| 4307 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4308 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4309 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4310 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4311 | i915_gem_cleanup_ringbuffer(dev); |
| 4312 | mutex_unlock(&dev->struct_mutex); |
| 4313 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4314 | return 0; |
| 4315 | } |
| 4316 | |
| 4317 | static int |
| 4318 | i915_gem_init_hws(struct drm_device *dev) |
| 4319 | { |
| 4320 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4321 | struct drm_gem_object *obj; |
| 4322 | struct drm_i915_gem_object *obj_priv; |
| 4323 | int ret; |
| 4324 | |
| 4325 | /* If we need a physical address for the status page, it's already |
| 4326 | * initialized at driver load time. |
| 4327 | */ |
| 4328 | if (!I915_NEED_GFX_HWS(dev)) |
| 4329 | return 0; |
| 4330 | |
| 4331 | obj = drm_gem_object_alloc(dev, 4096); |
| 4332 | if (obj == NULL) { |
| 4333 | DRM_ERROR("Failed to allocate status page\n"); |
| 4334 | return -ENOMEM; |
| 4335 | } |
| 4336 | obj_priv = obj->driver_private; |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 4337 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4338 | |
| 4339 | ret = i915_gem_object_pin(obj, 4096); |
| 4340 | if (ret != 0) { |
| 4341 | drm_gem_object_unreference(obj); |
| 4342 | return ret; |
| 4343 | } |
| 4344 | |
| 4345 | dev_priv->status_gfx_addr = obj_priv->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4346 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4347 | dev_priv->hw_status_page = kmap(obj_priv->pages[0]); |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 4348 | if (dev_priv->hw_status_page == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4349 | DRM_ERROR("Failed to map status page.\n"); |
| 4350 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
Chris Wilson | 3eb2ee7 | 2009-02-11 14:26:34 +0000 | [diff] [blame] | 4351 | i915_gem_object_unpin(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4352 | drm_gem_object_unreference(obj); |
| 4353 | return -EINVAL; |
| 4354 | } |
| 4355 | dev_priv->hws_obj = obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4356 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); |
| 4357 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 4358 | I915_READ(HWS_PGA); /* posting read */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4359 | DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr); |
| 4360 | |
| 4361 | return 0; |
| 4362 | } |
| 4363 | |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4364 | static void |
| 4365 | i915_gem_cleanup_hws(struct drm_device *dev) |
| 4366 | { |
| 4367 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | bab2d1f | 2009-02-20 17:52:20 +0000 | [diff] [blame] | 4368 | struct drm_gem_object *obj; |
| 4369 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4370 | |
| 4371 | if (dev_priv->hws_obj == NULL) |
| 4372 | return; |
| 4373 | |
Chris Wilson | bab2d1f | 2009-02-20 17:52:20 +0000 | [diff] [blame] | 4374 | obj = dev_priv->hws_obj; |
| 4375 | obj_priv = obj->driver_private; |
| 4376 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4377 | kunmap(obj_priv->pages[0]); |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4378 | i915_gem_object_unpin(obj); |
| 4379 | drm_gem_object_unreference(obj); |
| 4380 | dev_priv->hws_obj = NULL; |
Chris Wilson | bab2d1f | 2009-02-20 17:52:20 +0000 | [diff] [blame] | 4381 | |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4382 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
| 4383 | dev_priv->hw_status_page = NULL; |
| 4384 | |
| 4385 | /* Write high address into HWS_PGA when disabling. */ |
| 4386 | I915_WRITE(HWS_PGA, 0x1ffff000); |
| 4387 | } |
| 4388 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4389 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4390 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 4391 | { |
| 4392 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4393 | struct drm_gem_object *obj; |
| 4394 | struct drm_i915_gem_object *obj_priv; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4395 | drm_i915_ring_buffer_t *ring = &dev_priv->ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4396 | int ret; |
Keith Packard | 50aa253d | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 4397 | u32 head; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4398 | |
| 4399 | ret = i915_gem_init_hws(dev); |
| 4400 | if (ret != 0) |
| 4401 | return ret; |
| 4402 | |
| 4403 | obj = drm_gem_object_alloc(dev, 128 * 1024); |
| 4404 | if (obj == NULL) { |
| 4405 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4406 | i915_gem_cleanup_hws(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4407 | return -ENOMEM; |
| 4408 | } |
| 4409 | obj_priv = obj->driver_private; |
| 4410 | |
| 4411 | ret = i915_gem_object_pin(obj, 4096); |
| 4412 | if (ret != 0) { |
| 4413 | drm_gem_object_unreference(obj); |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4414 | i915_gem_cleanup_hws(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4415 | return ret; |
| 4416 | } |
| 4417 | |
| 4418 | /* Set up the kernel mapping for the ring. */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4419 | ring->Size = obj->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4420 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4421 | ring->map.offset = dev->agp->base + obj_priv->gtt_offset; |
| 4422 | ring->map.size = obj->size; |
| 4423 | ring->map.type = 0; |
| 4424 | ring->map.flags = 0; |
| 4425 | ring->map.mtrr = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4426 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4427 | drm_core_ioremap_wc(&ring->map, dev); |
| 4428 | if (ring->map.handle == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4429 | DRM_ERROR("Failed to map ringbuffer.\n"); |
| 4430 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); |
Chris Wilson | 47ed185 | 2009-02-11 14:26:33 +0000 | [diff] [blame] | 4431 | i915_gem_object_unpin(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4432 | drm_gem_object_unreference(obj); |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4433 | i915_gem_cleanup_hws(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4434 | return -EINVAL; |
| 4435 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4436 | ring->ring_obj = obj; |
| 4437 | ring->virtual_start = ring->map.handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4438 | |
| 4439 | /* Stop the ring if it's running. */ |
| 4440 | I915_WRITE(PRB0_CTL, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4441 | I915_WRITE(PRB0_TAIL, 0); |
Keith Packard | 50aa253d | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 4442 | I915_WRITE(PRB0_HEAD, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4443 | |
| 4444 | /* Initialize the ring. */ |
| 4445 | I915_WRITE(PRB0_START, obj_priv->gtt_offset); |
Keith Packard | 50aa253d | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 4446 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
| 4447 | |
| 4448 | /* G45 ring initialization fails to reset head to zero */ |
| 4449 | if (head != 0) { |
| 4450 | DRM_ERROR("Ring head not reset to zero " |
| 4451 | "ctl %08x head %08x tail %08x start %08x\n", |
| 4452 | I915_READ(PRB0_CTL), |
| 4453 | I915_READ(PRB0_HEAD), |
| 4454 | I915_READ(PRB0_TAIL), |
| 4455 | I915_READ(PRB0_START)); |
| 4456 | I915_WRITE(PRB0_HEAD, 0); |
| 4457 | |
| 4458 | DRM_ERROR("Ring head forced to zero " |
| 4459 | "ctl %08x head %08x tail %08x start %08x\n", |
| 4460 | I915_READ(PRB0_CTL), |
| 4461 | I915_READ(PRB0_HEAD), |
| 4462 | I915_READ(PRB0_TAIL), |
| 4463 | I915_READ(PRB0_START)); |
| 4464 | } |
| 4465 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4466 | I915_WRITE(PRB0_CTL, |
| 4467 | ((obj->size - 4096) & RING_NR_PAGES) | |
| 4468 | RING_NO_REPORT | |
| 4469 | RING_VALID); |
| 4470 | |
Keith Packard | 50aa253d | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 4471 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
| 4472 | |
| 4473 | /* If the head is still not zero, the ring is dead */ |
| 4474 | if (head != 0) { |
| 4475 | DRM_ERROR("Ring initialization failed " |
| 4476 | "ctl %08x head %08x tail %08x start %08x\n", |
| 4477 | I915_READ(PRB0_CTL), |
| 4478 | I915_READ(PRB0_HEAD), |
| 4479 | I915_READ(PRB0_TAIL), |
| 4480 | I915_READ(PRB0_START)); |
| 4481 | return -EIO; |
| 4482 | } |
| 4483 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4484 | /* Update our cache of the ring state */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4485 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4486 | i915_kernel_lost_context(dev); |
| 4487 | else { |
| 4488 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
| 4489 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; |
| 4490 | ring->space = ring->head - (ring->tail + 8); |
| 4491 | if (ring->space < 0) |
| 4492 | ring->space += ring->Size; |
| 4493 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4494 | |
| 4495 | return 0; |
| 4496 | } |
| 4497 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4498 | void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4499 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4500 | { |
| 4501 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4502 | |
| 4503 | if (dev_priv->ring.ring_obj == NULL) |
| 4504 | return; |
| 4505 | |
| 4506 | drm_core_ioremapfree(&dev_priv->ring.map, dev); |
| 4507 | |
| 4508 | i915_gem_object_unpin(dev_priv->ring.ring_obj); |
| 4509 | drm_gem_object_unreference(dev_priv->ring.ring_obj); |
| 4510 | dev_priv->ring.ring_obj = NULL; |
| 4511 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); |
| 4512 | |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4513 | i915_gem_cleanup_hws(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4514 | } |
| 4515 | |
| 4516 | int |
| 4517 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4518 | struct drm_file *file_priv) |
| 4519 | { |
| 4520 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4521 | int ret; |
| 4522 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4523 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4524 | return 0; |
| 4525 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4526 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4527 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4528 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4529 | } |
| 4530 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4531 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4532 | dev_priv->mm.suspended = 0; |
| 4533 | |
| 4534 | ret = i915_gem_init_ringbuffer(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4535 | if (ret != 0) { |
| 4536 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4537 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4538 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4539 | |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4540 | spin_lock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4541 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4542 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 4543 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4544 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 4545 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
| 4546 | BUG_ON(!list_empty(&dev_priv->mm.request_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4547 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4548 | |
| 4549 | drm_irq_install(dev); |
| 4550 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4551 | return 0; |
| 4552 | } |
| 4553 | |
| 4554 | int |
| 4555 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4556 | struct drm_file *file_priv) |
| 4557 | { |
| 4558 | int ret; |
| 4559 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4560 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4561 | return 0; |
| 4562 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4563 | ret = i915_gem_idle(dev); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4564 | drm_irq_uninstall(dev); |
| 4565 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4566 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4567 | } |
| 4568 | |
| 4569 | void |
| 4570 | i915_gem_lastclose(struct drm_device *dev) |
| 4571 | { |
| 4572 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4573 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4574 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4575 | return; |
| 4576 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4577 | ret = i915_gem_idle(dev); |
| 4578 | if (ret) |
| 4579 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4580 | } |
| 4581 | |
| 4582 | void |
| 4583 | i915_gem_load(struct drm_device *dev) |
| 4584 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4585 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4586 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4587 | |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4588 | spin_lock_init(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4589 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
| 4590 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 4591 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
| 4592 | INIT_LIST_HEAD(&dev_priv->mm.request_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4593 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4594 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4595 | i915_gem_retire_work_handler); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4596 | dev_priv->mm.next_gem_seqno = 1; |
| 4597 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4598 | spin_lock(&shrink_list_lock); |
| 4599 | list_add(&dev_priv->mm.shrink_list, &shrink_list); |
| 4600 | spin_unlock(&shrink_list_lock); |
| 4601 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4602 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
| 4603 | dev_priv->fence_reg_start = 3; |
| 4604 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 4605 | if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4606 | dev_priv->num_fence_regs = 16; |
| 4607 | else |
| 4608 | dev_priv->num_fence_regs = 8; |
| 4609 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4610 | /* Initialize fence registers to zero */ |
| 4611 | if (IS_I965G(dev)) { |
| 4612 | for (i = 0; i < 16; i++) |
| 4613 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); |
| 4614 | } else { |
| 4615 | for (i = 0; i < 8; i++) |
| 4616 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); |
| 4617 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 4618 | for (i = 0; i < 8; i++) |
| 4619 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); |
| 4620 | } |
| 4621 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4622 | i915_gem_detect_bit_6_swizzle(dev); |
| 4623 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4624 | |
| 4625 | /* |
| 4626 | * Create a physically contiguous memory object for this object |
| 4627 | * e.g. for cursor + overlay regs |
| 4628 | */ |
| 4629 | int i915_gem_init_phys_object(struct drm_device *dev, |
| 4630 | int id, int size) |
| 4631 | { |
| 4632 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4633 | struct drm_i915_gem_phys_object *phys_obj; |
| 4634 | int ret; |
| 4635 | |
| 4636 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4637 | return 0; |
| 4638 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4639 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4640 | if (!phys_obj) |
| 4641 | return -ENOMEM; |
| 4642 | |
| 4643 | phys_obj->id = id; |
| 4644 | |
| 4645 | phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff); |
| 4646 | if (!phys_obj->handle) { |
| 4647 | ret = -ENOMEM; |
| 4648 | goto kfree_obj; |
| 4649 | } |
| 4650 | #ifdef CONFIG_X86 |
| 4651 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4652 | #endif |
| 4653 | |
| 4654 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4655 | |
| 4656 | return 0; |
| 4657 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4658 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4659 | return ret; |
| 4660 | } |
| 4661 | |
| 4662 | void i915_gem_free_phys_object(struct drm_device *dev, int id) |
| 4663 | { |
| 4664 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4665 | struct drm_i915_gem_phys_object *phys_obj; |
| 4666 | |
| 4667 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4668 | return; |
| 4669 | |
| 4670 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4671 | if (phys_obj->cur_obj) { |
| 4672 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4673 | } |
| 4674 | |
| 4675 | #ifdef CONFIG_X86 |
| 4676 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4677 | #endif |
| 4678 | drm_pci_free(dev, phys_obj->handle); |
| 4679 | kfree(phys_obj); |
| 4680 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4681 | } |
| 4682 | |
| 4683 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4684 | { |
| 4685 | int i; |
| 4686 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4687 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4688 | i915_gem_free_phys_object(dev, i); |
| 4689 | } |
| 4690 | |
| 4691 | void i915_gem_detach_phys_object(struct drm_device *dev, |
| 4692 | struct drm_gem_object *obj) |
| 4693 | { |
| 4694 | struct drm_i915_gem_object *obj_priv; |
| 4695 | int i; |
| 4696 | int ret; |
| 4697 | int page_count; |
| 4698 | |
| 4699 | obj_priv = obj->driver_private; |
| 4700 | if (!obj_priv->phys_obj) |
| 4701 | return; |
| 4702 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4703 | ret = i915_gem_object_get_pages(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4704 | if (ret) |
| 4705 | goto out; |
| 4706 | |
| 4707 | page_count = obj->size / PAGE_SIZE; |
| 4708 | |
| 4709 | for (i = 0; i < page_count; i++) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4710 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4711 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4712 | |
| 4713 | memcpy(dst, src, PAGE_SIZE); |
| 4714 | kunmap_atomic(dst, KM_USER0); |
| 4715 | } |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4716 | drm_clflush_pages(obj_priv->pages, page_count); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4717 | drm_agp_chipset_flush(dev); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4718 | |
| 4719 | i915_gem_object_put_pages(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4720 | out: |
| 4721 | obj_priv->phys_obj->cur_obj = NULL; |
| 4722 | obj_priv->phys_obj = NULL; |
| 4723 | } |
| 4724 | |
| 4725 | int |
| 4726 | i915_gem_attach_phys_object(struct drm_device *dev, |
| 4727 | struct drm_gem_object *obj, int id) |
| 4728 | { |
| 4729 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4730 | struct drm_i915_gem_object *obj_priv; |
| 4731 | int ret = 0; |
| 4732 | int page_count; |
| 4733 | int i; |
| 4734 | |
| 4735 | if (id > I915_MAX_PHYS_OBJECT) |
| 4736 | return -EINVAL; |
| 4737 | |
| 4738 | obj_priv = obj->driver_private; |
| 4739 | |
| 4740 | if (obj_priv->phys_obj) { |
| 4741 | if (obj_priv->phys_obj->id == id) |
| 4742 | return 0; |
| 4743 | i915_gem_detach_phys_object(dev, obj); |
| 4744 | } |
| 4745 | |
| 4746 | |
| 4747 | /* create a new object */ |
| 4748 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4749 | ret = i915_gem_init_phys_object(dev, id, |
| 4750 | obj->size); |
| 4751 | if (ret) { |
Linus Torvalds | aeb565d | 2009-01-26 10:01:53 -0800 | [diff] [blame] | 4752 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4753 | goto out; |
| 4754 | } |
| 4755 | } |
| 4756 | |
| 4757 | /* bind to the object */ |
| 4758 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4759 | obj_priv->phys_obj->cur_obj = obj; |
| 4760 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4761 | ret = i915_gem_object_get_pages(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4762 | if (ret) { |
| 4763 | DRM_ERROR("failed to get page list\n"); |
| 4764 | goto out; |
| 4765 | } |
| 4766 | |
| 4767 | page_count = obj->size / PAGE_SIZE; |
| 4768 | |
| 4769 | for (i = 0; i < page_count; i++) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4770 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4771 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4772 | |
| 4773 | memcpy(dst, src, PAGE_SIZE); |
| 4774 | kunmap_atomic(src, KM_USER0); |
| 4775 | } |
| 4776 | |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4777 | i915_gem_object_put_pages(obj); |
| 4778 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4779 | return 0; |
| 4780 | out: |
| 4781 | return ret; |
| 4782 | } |
| 4783 | |
| 4784 | static int |
| 4785 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 4786 | struct drm_i915_gem_pwrite *args, |
| 4787 | struct drm_file *file_priv) |
| 4788 | { |
| 4789 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 4790 | void *obj_addr; |
| 4791 | int ret; |
| 4792 | char __user *user_data; |
| 4793 | |
| 4794 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 4795 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; |
| 4796 | |
Dave Airlie | e08fb4f | 2009-02-25 14:52:30 +1000 | [diff] [blame] | 4797 | DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4798 | ret = copy_from_user(obj_addr, user_data, args->size); |
| 4799 | if (ret) |
| 4800 | return -EFAULT; |
| 4801 | |
| 4802 | drm_agp_chipset_flush(dev); |
| 4803 | return 0; |
| 4804 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4805 | |
| 4806 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv) |
| 4807 | { |
| 4808 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; |
| 4809 | |
| 4810 | /* Clean up our request list when the client is going away, so that |
| 4811 | * later retire_requests won't dereference our soon-to-be-gone |
| 4812 | * file_priv. |
| 4813 | */ |
| 4814 | mutex_lock(&dev->struct_mutex); |
| 4815 | while (!list_empty(&i915_file_priv->mm.request_list)) |
| 4816 | list_del_init(i915_file_priv->mm.request_list.next); |
| 4817 | mutex_unlock(&dev->struct_mutex); |
| 4818 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4819 | |
| 4820 | /* Immediately discard the backing storage */ |
| 4821 | static void |
| 4822 | i915_gem_object_truncate(struct drm_gem_object *obj) |
| 4823 | { |
| 4824 | struct inode *inode; |
| 4825 | |
| 4826 | inode = obj->filp->f_path.dentry->d_inode; |
| 4827 | |
| 4828 | mutex_lock(&inode->i_mutex); |
| 4829 | truncate_inode_pages(inode->i_mapping, 0); |
| 4830 | mutex_unlock(&inode->i_mutex); |
| 4831 | } |
| 4832 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4833 | static int |
| 4834 | i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask) |
| 4835 | { |
| 4836 | drm_i915_private_t *dev_priv, *next_dev; |
| 4837 | struct drm_i915_gem_object *obj_priv, *next_obj; |
| 4838 | int cnt = 0; |
| 4839 | int would_deadlock = 1; |
| 4840 | |
| 4841 | /* "fast-path" to count number of available objects */ |
| 4842 | if (nr_to_scan == 0) { |
| 4843 | spin_lock(&shrink_list_lock); |
| 4844 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 4845 | struct drm_device *dev = dev_priv->dev; |
| 4846 | |
| 4847 | if (mutex_trylock(&dev->struct_mutex)) { |
| 4848 | list_for_each_entry(obj_priv, |
| 4849 | &dev_priv->mm.inactive_list, |
| 4850 | list) |
| 4851 | cnt++; |
| 4852 | mutex_unlock(&dev->struct_mutex); |
| 4853 | } |
| 4854 | } |
| 4855 | spin_unlock(&shrink_list_lock); |
| 4856 | |
| 4857 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 4858 | } |
| 4859 | |
| 4860 | spin_lock(&shrink_list_lock); |
| 4861 | |
| 4862 | /* first scan for clean buffers */ |
| 4863 | list_for_each_entry_safe(dev_priv, next_dev, |
| 4864 | &shrink_list, mm.shrink_list) { |
| 4865 | struct drm_device *dev = dev_priv->dev; |
| 4866 | |
| 4867 | if (! mutex_trylock(&dev->struct_mutex)) |
| 4868 | continue; |
| 4869 | |
| 4870 | spin_unlock(&shrink_list_lock); |
| 4871 | |
| 4872 | i915_gem_retire_requests(dev); |
| 4873 | |
| 4874 | list_for_each_entry_safe(obj_priv, next_obj, |
| 4875 | &dev_priv->mm.inactive_list, |
| 4876 | list) { |
| 4877 | if (i915_gem_object_is_purgeable(obj_priv)) { |
| 4878 | struct drm_gem_object *obj = obj_priv->obj; |
| 4879 | i915_gem_object_unbind(obj); |
| 4880 | i915_gem_object_truncate(obj); |
| 4881 | |
| 4882 | if (--nr_to_scan <= 0) |
| 4883 | break; |
| 4884 | } |
| 4885 | } |
| 4886 | |
| 4887 | spin_lock(&shrink_list_lock); |
| 4888 | mutex_unlock(&dev->struct_mutex); |
| 4889 | |
| 4890 | if (nr_to_scan <= 0) |
| 4891 | break; |
| 4892 | } |
| 4893 | |
| 4894 | /* second pass, evict/count anything still on the inactive list */ |
| 4895 | list_for_each_entry_safe(dev_priv, next_dev, |
| 4896 | &shrink_list, mm.shrink_list) { |
| 4897 | struct drm_device *dev = dev_priv->dev; |
| 4898 | |
| 4899 | if (! mutex_trylock(&dev->struct_mutex)) |
| 4900 | continue; |
| 4901 | |
| 4902 | spin_unlock(&shrink_list_lock); |
| 4903 | |
| 4904 | list_for_each_entry_safe(obj_priv, next_obj, |
| 4905 | &dev_priv->mm.inactive_list, |
| 4906 | list) { |
| 4907 | if (nr_to_scan > 0) { |
| 4908 | struct drm_gem_object *obj = obj_priv->obj; |
| 4909 | i915_gem_object_unbind(obj); |
| 4910 | if (i915_gem_object_is_purgeable(obj_priv)) |
| 4911 | i915_gem_object_truncate(obj); |
| 4912 | |
| 4913 | nr_to_scan--; |
| 4914 | } else |
| 4915 | cnt++; |
| 4916 | } |
| 4917 | |
| 4918 | spin_lock(&shrink_list_lock); |
| 4919 | mutex_unlock(&dev->struct_mutex); |
| 4920 | |
| 4921 | would_deadlock = 0; |
| 4922 | } |
| 4923 | |
| 4924 | spin_unlock(&shrink_list_lock); |
| 4925 | |
| 4926 | if (would_deadlock) |
| 4927 | return -1; |
| 4928 | else if (cnt > 0) |
| 4929 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 4930 | else |
| 4931 | return 0; |
| 4932 | } |
| 4933 | |
| 4934 | static struct shrinker shrinker = { |
| 4935 | .shrink = i915_gem_shrink, |
| 4936 | .seeks = DEFAULT_SEEKS, |
| 4937 | }; |
| 4938 | |
| 4939 | __init void |
| 4940 | i915_gem_shrinker_init(void) |
| 4941 | { |
| 4942 | register_shrinker(&shrinker); |
| 4943 | } |
| 4944 | |
| 4945 | __exit void |
| 4946 | i915_gem_shrinker_exit(void) |
| 4947 | { |
| 4948 | unregister_shrinker(&shrinker); |
| 4949 | } |