Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/kernel/irq/chip.c |
| 3 | * |
| 4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
| 5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King |
| 6 | * |
| 7 | * This file contains the core interrupt handling code, for irq-chip |
| 8 | * based architectures. |
| 9 | * |
| 10 | * Detailed information is available in Documentation/DocBook/genericirq |
| 11 | */ |
| 12 | |
| 13 | #include <linux/irq.h> |
Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 14 | #include <linux/msi.h> |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 15 | #include <linux/module.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/kernel_stat.h> |
Jiang Liu | f8264e3 | 2014-11-06 22:20:14 +0800 | [diff] [blame] | 18 | #include <linux/irqdomain.h> |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 19 | |
Steven Rostedt | f069686 | 2012-01-25 20:18:55 -0500 | [diff] [blame] | 20 | #include <trace/events/irq.h> |
| 21 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 22 | #include "internals.h" |
| 23 | |
Mika Westerberg | e509bd7 | 2015-10-05 13:12:15 +0300 | [diff] [blame] | 24 | static irqreturn_t bad_chained_irq(int irq, void *dev_id) |
| 25 | { |
| 26 | WARN_ONCE(1, "Chained irq %d should not call an action\n", irq); |
| 27 | return IRQ_NONE; |
| 28 | } |
| 29 | |
| 30 | /* |
| 31 | * Chained handlers should never call action on their IRQ. This default |
| 32 | * action will emit warning if such thing happens. |
| 33 | */ |
| 34 | struct irqaction chained_action = { |
| 35 | .handler = bad_chained_irq, |
| 36 | }; |
| 37 | |
Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 38 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 39 | * irq_set_chip - set the irq chip for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 40 | * @irq: irq number |
| 41 | * @chip: pointer to irq chip description structure |
| 42 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 43 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 44 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 45 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 46 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 47 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 48 | if (!desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 49 | return -EINVAL; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 50 | |
| 51 | if (!chip) |
| 52 | chip = &no_irq_chip; |
| 53 | |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 54 | desc->irq_data.chip = chip; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 55 | irq_put_desc_unlock(desc, flags); |
David Daney | d72274e | 2011-03-25 12:38:48 -0700 | [diff] [blame] | 56 | /* |
| 57 | * For !CONFIG_SPARSE_IRQ make the irq show up in |
Thomas Gleixner | f63b6a0 | 2014-05-07 15:44:21 +0000 | [diff] [blame] | 58 | * allocated_irqs. |
David Daney | d72274e | 2011-03-25 12:38:48 -0700 | [diff] [blame] | 59 | */ |
Thomas Gleixner | f63b6a0 | 2014-05-07 15:44:21 +0000 | [diff] [blame] | 60 | irq_mark_irq(irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 61 | return 0; |
| 62 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 63 | EXPORT_SYMBOL(irq_set_chip); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 64 | |
| 65 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 66 | * irq_set_type - set the irq trigger type for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 67 | * @irq: irq number |
David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 68 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 69 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 70 | int irq_set_irq_type(unsigned int irq, unsigned int type) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 71 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 72 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 73 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 74 | int ret = 0; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 75 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 76 | if (!desc) |
| 77 | return -EINVAL; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 78 | |
Jiang Liu | a1ff541 | 2015-06-23 19:47:29 +0200 | [diff] [blame] | 79 | ret = __irq_set_trigger(desc, type); |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 80 | irq_put_desc_busunlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 81 | return ret; |
| 82 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 83 | EXPORT_SYMBOL(irq_set_irq_type); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 84 | |
| 85 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 86 | * irq_set_handler_data - set irq handler data for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 87 | * @irq: Interrupt number |
| 88 | * @data: Pointer to interrupt specific data |
| 89 | * |
| 90 | * Set the hardware irq controller data for an irq |
| 91 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 92 | int irq_set_handler_data(unsigned int irq, void *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 93 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 94 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 95 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 96 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 97 | if (!desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 98 | return -EINVAL; |
Jiang Liu | af7080e | 2015-06-01 16:05:21 +0800 | [diff] [blame] | 99 | desc->irq_common_data.handler_data = data; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 100 | irq_put_desc_unlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 101 | return 0; |
| 102 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 103 | EXPORT_SYMBOL(irq_set_handler_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 104 | |
| 105 | /** |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 106 | * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset |
| 107 | * @irq_base: Interrupt number base |
| 108 | * @irq_offset: Interrupt number offset |
| 109 | * @entry: Pointer to MSI descriptor data |
| 110 | * |
| 111 | * Set the MSI descriptor entry for an irq at offset |
| 112 | */ |
| 113 | int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, |
| 114 | struct msi_desc *entry) |
| 115 | { |
| 116 | unsigned long flags; |
| 117 | struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
| 118 | |
| 119 | if (!desc) |
| 120 | return -EINVAL; |
Jiang Liu | b237721 | 2015-06-01 16:05:43 +0800 | [diff] [blame] | 121 | desc->irq_common_data.msi_desc = entry; |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 122 | if (entry && !irq_offset) |
| 123 | entry->irq = irq_base; |
| 124 | irq_put_desc_unlock(desc, flags); |
| 125 | return 0; |
| 126 | } |
| 127 | |
| 128 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 129 | * irq_set_msi_desc - set MSI descriptor data for an irq |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 130 | * @irq: Interrupt number |
Randy Dunlap | 472900b | 2007-02-16 01:28:25 -0800 | [diff] [blame] | 131 | * @entry: Pointer to MSI descriptor data |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 132 | * |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 133 | * Set the MSI descriptor entry for an irq |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 134 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 135 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 136 | { |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 137 | return irq_set_msi_desc_off(irq, 0, entry); |
Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | /** |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 141 | * irq_set_chip_data - set irq chip data for an irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 142 | * @irq: Interrupt number |
| 143 | * @data: Pointer to chip specific data |
| 144 | * |
| 145 | * Set the hardware irq chip data for an irq |
| 146 | */ |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 147 | int irq_set_chip_data(unsigned int irq, void *data) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 148 | { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 149 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 150 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 151 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 152 | if (!desc) |
Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 153 | return -EINVAL; |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 154 | desc->irq_data.chip_data = data; |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 155 | irq_put_desc_unlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 156 | return 0; |
| 157 | } |
Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 158 | EXPORT_SYMBOL(irq_set_chip_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 159 | |
Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 160 | struct irq_data *irq_get_irq_data(unsigned int irq) |
| 161 | { |
| 162 | struct irq_desc *desc = irq_to_desc(irq); |
| 163 | |
| 164 | return desc ? &desc->irq_data : NULL; |
| 165 | } |
| 166 | EXPORT_SYMBOL_GPL(irq_get_irq_data); |
| 167 | |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 168 | static void irq_state_clr_disabled(struct irq_desc *desc) |
| 169 | { |
Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 170 | irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED); |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 171 | } |
| 172 | |
| 173 | static void irq_state_set_disabled(struct irq_desc *desc) |
| 174 | { |
Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 175 | irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 176 | } |
| 177 | |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 178 | static void irq_state_clr_masked(struct irq_desc *desc) |
| 179 | { |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 180 | irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | static void irq_state_set_masked(struct irq_desc *desc) |
| 184 | { |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 185 | irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 186 | } |
| 187 | |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 188 | int irq_startup(struct irq_desc *desc, bool resend) |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 189 | { |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 190 | int ret = 0; |
| 191 | |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 192 | irq_state_clr_disabled(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 193 | desc->depth = 0; |
| 194 | |
Jiang Liu | f8264e3 | 2014-11-06 22:20:14 +0800 | [diff] [blame] | 195 | irq_domain_activate_irq(&desc->irq_data); |
Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 196 | if (desc->irq_data.chip->irq_startup) { |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 197 | ret = desc->irq_data.chip->irq_startup(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 198 | irq_state_clr_masked(desc); |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 199 | } else { |
| 200 | irq_enable(desc); |
Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 201 | } |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 202 | if (resend) |
Jiang Liu | 0798abe | 2015-06-04 12:13:27 +0800 | [diff] [blame] | 203 | check_irq_resend(desc); |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 204 | return ret; |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 205 | } |
| 206 | |
| 207 | void irq_shutdown(struct irq_desc *desc) |
| 208 | { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 209 | irq_state_set_disabled(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 210 | desc->depth = 1; |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 211 | if (desc->irq_data.chip->irq_shutdown) |
| 212 | desc->irq_data.chip->irq_shutdown(&desc->irq_data); |
Geert Uytterhoeven | ed585a6 | 2011-09-11 13:59:27 +0200 | [diff] [blame] | 213 | else if (desc->irq_data.chip->irq_disable) |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 214 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
| 215 | else |
| 216 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Jiang Liu | f8264e3 | 2014-11-06 22:20:14 +0800 | [diff] [blame] | 217 | irq_domain_deactivate_irq(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 218 | irq_state_set_masked(desc); |
Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 219 | } |
| 220 | |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 221 | void irq_enable(struct irq_desc *desc) |
| 222 | { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 223 | irq_state_clr_disabled(desc); |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 224 | if (desc->irq_data.chip->irq_enable) |
| 225 | desc->irq_data.chip->irq_enable(&desc->irq_data); |
| 226 | else |
| 227 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 228 | irq_state_clr_masked(desc); |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 229 | } |
| 230 | |
Andreas Fenkart | d671a60 | 2013-05-10 12:21:30 +0200 | [diff] [blame] | 231 | /** |
Xie XiuQi | f788e7b | 2013-10-18 09:12:04 +0800 | [diff] [blame] | 232 | * irq_disable - Mark interrupt disabled |
Andreas Fenkart | d671a60 | 2013-05-10 12:21:30 +0200 | [diff] [blame] | 233 | * @desc: irq descriptor which should be disabled |
| 234 | * |
| 235 | * If the chip does not implement the irq_disable callback, we |
| 236 | * use a lazy disable approach. That means we mark the interrupt |
| 237 | * disabled, but leave the hardware unmasked. That's an |
| 238 | * optimization because we avoid the hardware access for the |
| 239 | * common case where no interrupt happens after we marked it |
| 240 | * disabled. If an interrupt happens, then the interrupt flow |
| 241 | * handler masks the line at the hardware level and marks it |
| 242 | * pending. |
Thomas Gleixner | e984977 | 2015-10-09 23:28:58 +0200 | [diff] [blame] | 243 | * |
| 244 | * If the interrupt chip does not implement the irq_disable callback, |
| 245 | * a driver can disable the lazy approach for a particular irq line by |
| 246 | * calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can |
| 247 | * be used for devices which cannot disable the interrupt at the |
| 248 | * device level under certain circumstances and have to use |
| 249 | * disable_irq[_nosync] instead. |
Andreas Fenkart | d671a60 | 2013-05-10 12:21:30 +0200 | [diff] [blame] | 250 | */ |
Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 251 | void irq_disable(struct irq_desc *desc) |
| 252 | { |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 253 | irq_state_set_disabled(desc); |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 254 | if (desc->irq_data.chip->irq_disable) { |
| 255 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
Thomas Gleixner | a61d825 | 2011-02-21 12:54:34 +0100 | [diff] [blame] | 256 | irq_state_set_masked(desc); |
Thomas Gleixner | e984977 | 2015-10-09 23:28:58 +0200 | [diff] [blame] | 257 | } else if (irq_settings_disable_unlazy(desc)) { |
| 258 | mask_irq(desc); |
Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 259 | } |
Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 260 | } |
| 261 | |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 262 | void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu) |
| 263 | { |
| 264 | if (desc->irq_data.chip->irq_enable) |
| 265 | desc->irq_data.chip->irq_enable(&desc->irq_data); |
| 266 | else |
| 267 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
| 268 | cpumask_set_cpu(cpu, desc->percpu_enabled); |
| 269 | } |
| 270 | |
| 271 | void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu) |
| 272 | { |
| 273 | if (desc->irq_data.chip->irq_disable) |
| 274 | desc->irq_data.chip->irq_disable(&desc->irq_data); |
| 275 | else |
| 276 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
| 277 | cpumask_clear_cpu(cpu, desc->percpu_enabled); |
| 278 | } |
| 279 | |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 280 | static inline void mask_ack_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 281 | { |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 282 | if (desc->irq_data.chip->irq_mask_ack) |
| 283 | desc->irq_data.chip->irq_mask_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 284 | else { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 285 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 286 | if (desc->irq_data.chip->irq_ack) |
| 287 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 288 | } |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 289 | irq_state_set_masked(desc); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 290 | } |
| 291 | |
Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 292 | void mask_irq(struct irq_desc *desc) |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 293 | { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 294 | if (desc->irq_data.chip->irq_mask) { |
| 295 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 296 | irq_state_set_masked(desc); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 297 | } |
| 298 | } |
| 299 | |
Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 300 | void unmask_irq(struct irq_desc *desc) |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 301 | { |
Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 302 | if (desc->irq_data.chip->irq_unmask) { |
| 303 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 304 | irq_state_clr_masked(desc); |
Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 305 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 306 | } |
| 307 | |
Thomas Gleixner | 328a497 | 2014-03-13 19:03:51 +0100 | [diff] [blame] | 308 | void unmask_threaded_irq(struct irq_desc *desc) |
| 309 | { |
| 310 | struct irq_chip *chip = desc->irq_data.chip; |
| 311 | |
| 312 | if (chip->flags & IRQCHIP_EOI_THREADED) |
| 313 | chip->irq_eoi(&desc->irq_data); |
| 314 | |
| 315 | if (chip->irq_unmask) { |
| 316 | chip->irq_unmask(&desc->irq_data); |
| 317 | irq_state_clr_masked(desc); |
| 318 | } |
| 319 | } |
| 320 | |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 321 | /* |
| 322 | * handle_nested_irq - Handle a nested irq from a irq thread |
| 323 | * @irq: the interrupt number |
| 324 | * |
| 325 | * Handle interrupts which are nested into a threaded interrupt |
| 326 | * handler. The handler function is called inside the calling |
| 327 | * threads context. |
| 328 | */ |
| 329 | void handle_nested_irq(unsigned int irq) |
| 330 | { |
| 331 | struct irq_desc *desc = irq_to_desc(irq); |
| 332 | struct irqaction *action; |
| 333 | irqreturn_t action_ret; |
| 334 | |
| 335 | might_sleep(); |
| 336 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 337 | raw_spin_lock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 338 | |
Thomas Gleixner | 293a7a0 | 2012-10-16 15:07:49 -0700 | [diff] [blame] | 339 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 340 | |
| 341 | action = desc->action; |
Ning Jiang | 23812b9 | 2012-05-22 00:19:20 +0800 | [diff] [blame] | 342 | if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) { |
| 343 | desc->istate |= IRQS_PENDING; |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 344 | goto out_unlock; |
Ning Jiang | 23812b9 | 2012-05-22 00:19:20 +0800 | [diff] [blame] | 345 | } |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 346 | |
Sudeep Holla | a946e8c | 2015-11-04 18:32:37 +0000 | [diff] [blame] | 347 | kstat_incr_irqs_this_cpu(desc); |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 348 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 349 | raw_spin_unlock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 350 | |
| 351 | action_ret = action->thread_fn(action->irq, action->dev_id); |
| 352 | if (!noirqdebug) |
Jiang Liu | 0dcdbc9 | 2015-06-04 12:13:28 +0800 | [diff] [blame] | 353 | note_interrupt(desc, action_ret); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 354 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 355 | raw_spin_lock_irq(&desc->lock); |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 356 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 357 | |
| 358 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 359 | raw_spin_unlock_irq(&desc->lock); |
Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 360 | } |
| 361 | EXPORT_SYMBOL_GPL(handle_nested_irq); |
| 362 | |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 363 | static bool irq_check_poll(struct irq_desc *desc) |
| 364 | { |
Thomas Gleixner | 6954b75 | 2011-02-07 20:55:35 +0100 | [diff] [blame] | 365 | if (!(desc->istate & IRQS_POLL_INPROGRESS)) |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 366 | return false; |
| 367 | return irq_wait_for_poll(desc); |
| 368 | } |
| 369 | |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 370 | static bool irq_may_run(struct irq_desc *desc) |
| 371 | { |
Thomas Gleixner | 9ce7a25 | 2014-08-29 14:00:16 +0200 | [diff] [blame] | 372 | unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED; |
| 373 | |
| 374 | /* |
| 375 | * If the interrupt is not in progress and is not an armed |
| 376 | * wakeup interrupt, proceed. |
| 377 | */ |
| 378 | if (!irqd_has_set(&desc->irq_data, mask)) |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 379 | return true; |
Thomas Gleixner | 9ce7a25 | 2014-08-29 14:00:16 +0200 | [diff] [blame] | 380 | |
| 381 | /* |
| 382 | * If the interrupt is an armed wakeup source, mark it pending |
| 383 | * and suspended, disable it and notify the pm core about the |
| 384 | * event. |
| 385 | */ |
| 386 | if (irq_pm_check_wakeup(desc)) |
| 387 | return false; |
| 388 | |
| 389 | /* |
| 390 | * Handle a potential concurrent poll on a different core. |
| 391 | */ |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 392 | return irq_check_poll(desc); |
| 393 | } |
| 394 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 395 | /** |
| 396 | * handle_simple_irq - Simple and software-decoded IRQs. |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 397 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 398 | * |
| 399 | * Simple interrupts are either sent from a demultiplexing interrupt |
| 400 | * handler or come from hardware, where no interrupt hardware control |
| 401 | * is necessary. |
| 402 | * |
| 403 | * Note: The caller is expected to handle the ack, clear, mask and |
| 404 | * unmask issues if necessary. |
| 405 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 406 | void handle_simple_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 407 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 408 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 409 | |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 410 | if (!irq_may_run(desc)) |
| 411 | goto out_unlock; |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 412 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 413 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 414 | |
Ning Jiang | 23812b9 | 2012-05-22 00:19:20 +0800 | [diff] [blame] | 415 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
| 416 | desc->istate |= IRQS_PENDING; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 417 | goto out_unlock; |
Ning Jiang | 23812b9 | 2012-05-22 00:19:20 +0800 | [diff] [blame] | 418 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 419 | |
Sudeep Holla | a946e8c | 2015-11-04 18:32:37 +0000 | [diff] [blame] | 420 | kstat_incr_irqs_this_cpu(desc); |
Thomas Gleixner | 107781e | 2011-02-07 01:21:02 +0100 | [diff] [blame] | 421 | handle_irq_event(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 422 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 423 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 424 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 425 | } |
Jonathan Cameron | edf76f8 | 2011-05-18 10:39:04 +0100 | [diff] [blame] | 426 | EXPORT_SYMBOL_GPL(handle_simple_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 427 | |
Keith Busch | edd14cf | 2016-06-17 16:00:20 -0600 | [diff] [blame] | 428 | /** |
| 429 | * handle_untracked_irq - Simple and software-decoded IRQs. |
| 430 | * @desc: the interrupt description structure for this irq |
| 431 | * |
| 432 | * Untracked interrupts are sent from a demultiplexing interrupt |
| 433 | * handler when the demultiplexer does not know which device it its |
| 434 | * multiplexed irq domain generated the interrupt. IRQ's handled |
| 435 | * through here are not subjected to stats tracking, randomness, or |
| 436 | * spurious interrupt detection. |
| 437 | * |
| 438 | * Note: Like handle_simple_irq, the caller is expected to handle |
| 439 | * the ack, clear, mask and unmask issues if necessary. |
| 440 | */ |
| 441 | void handle_untracked_irq(struct irq_desc *desc) |
| 442 | { |
| 443 | unsigned int flags = 0; |
| 444 | |
| 445 | raw_spin_lock(&desc->lock); |
| 446 | |
| 447 | if (!irq_may_run(desc)) |
| 448 | goto out_unlock; |
| 449 | |
| 450 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
| 451 | |
| 452 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
| 453 | desc->istate |= IRQS_PENDING; |
| 454 | goto out_unlock; |
| 455 | } |
| 456 | |
| 457 | desc->istate &= ~IRQS_PENDING; |
| 458 | irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
| 459 | raw_spin_unlock(&desc->lock); |
| 460 | |
| 461 | __handle_irq_event_percpu(desc, &flags); |
| 462 | |
| 463 | raw_spin_lock(&desc->lock); |
| 464 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); |
| 465 | |
| 466 | out_unlock: |
| 467 | raw_spin_unlock(&desc->lock); |
| 468 | } |
| 469 | EXPORT_SYMBOL_GPL(handle_untracked_irq); |
| 470 | |
Thomas Gleixner | ac56376 | 2012-02-07 17:58:03 +0100 | [diff] [blame] | 471 | /* |
| 472 | * Called unconditionally from handle_level_irq() and only for oneshot |
| 473 | * interrupts from handle_fasteoi_irq() |
| 474 | */ |
| 475 | static void cond_unmask_irq(struct irq_desc *desc) |
| 476 | { |
| 477 | /* |
| 478 | * We need to unmask in the following cases: |
| 479 | * - Standard level irq (IRQF_ONESHOT is not set) |
| 480 | * - Oneshot irq which did not wake the thread (caused by a |
| 481 | * spurious interrupt or a primary handler handling it |
| 482 | * completely). |
| 483 | */ |
| 484 | if (!irqd_irq_disabled(&desc->irq_data) && |
| 485 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) |
| 486 | unmask_irq(desc); |
| 487 | } |
| 488 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 489 | /** |
| 490 | * handle_level_irq - Level type irq handler |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 491 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 492 | * |
| 493 | * Level type interrupts are active as long as the hardware line has |
| 494 | * the active level. This may require to mask the interrupt and unmask |
| 495 | * it after the associated handler has acknowledged the device, so the |
| 496 | * interrupt line is back to inactive. |
| 497 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 498 | void handle_level_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 499 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 500 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 501 | mask_ack_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 502 | |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 503 | if (!irq_may_run(desc)) |
| 504 | goto out_unlock; |
Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 505 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 506 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 507 | |
| 508 | /* |
| 509 | * If its disabled or no action available |
| 510 | * keep it masked and get out of here |
| 511 | */ |
Thomas Gleixner | d4dc0f9 | 2012-04-25 12:54:54 +0200 | [diff] [blame] | 512 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
| 513 | desc->istate |= IRQS_PENDING; |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 514 | goto out_unlock; |
Thomas Gleixner | d4dc0f9 | 2012-04-25 12:54:54 +0200 | [diff] [blame] | 515 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 516 | |
Sudeep Holla | a946e8c | 2015-11-04 18:32:37 +0000 | [diff] [blame] | 517 | kstat_incr_irqs_this_cpu(desc); |
Thomas Gleixner | 1529866 | 2011-02-07 01:22:17 +0100 | [diff] [blame] | 518 | handle_irq_event(desc); |
Thomas Gleixner | b25c340 | 2009-08-13 12:17:22 +0200 | [diff] [blame] | 519 | |
Thomas Gleixner | ac56376 | 2012-02-07 17:58:03 +0100 | [diff] [blame] | 520 | cond_unmask_irq(desc); |
| 521 | |
Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 522 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 523 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 524 | } |
Ingo Molnar | 14819ea | 2009-01-14 12:34:21 +0100 | [diff] [blame] | 525 | EXPORT_SYMBOL_GPL(handle_level_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 526 | |
Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 527 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI |
| 528 | static inline void preflow_handler(struct irq_desc *desc) |
| 529 | { |
| 530 | if (desc->preflow_handler) |
| 531 | desc->preflow_handler(&desc->irq_data); |
| 532 | } |
| 533 | #else |
| 534 | static inline void preflow_handler(struct irq_desc *desc) { } |
| 535 | #endif |
| 536 | |
Thomas Gleixner | 328a497 | 2014-03-13 19:03:51 +0100 | [diff] [blame] | 537 | static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip) |
| 538 | { |
| 539 | if (!(desc->istate & IRQS_ONESHOT)) { |
| 540 | chip->irq_eoi(&desc->irq_data); |
| 541 | return; |
| 542 | } |
| 543 | /* |
| 544 | * We need to unmask in the following cases: |
| 545 | * - Oneshot irq which did not wake the thread (caused by a |
| 546 | * spurious interrupt or a primary handler handling it |
| 547 | * completely). |
| 548 | */ |
| 549 | if (!irqd_irq_disabled(&desc->irq_data) && |
| 550 | irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) { |
| 551 | chip->irq_eoi(&desc->irq_data); |
| 552 | unmask_irq(desc); |
| 553 | } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) { |
| 554 | chip->irq_eoi(&desc->irq_data); |
| 555 | } |
| 556 | } |
| 557 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 558 | /** |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 559 | * handle_fasteoi_irq - irq handler for transparent controllers |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 560 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 561 | * |
Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 562 | * Only a single callback will be issued to the chip: an ->eoi() |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 563 | * call when the interrupt has been serviced. This enables support |
| 564 | * for modern forms of interrupt handlers, which handle the flow |
| 565 | * details in hardware, transparently. |
| 566 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 567 | void handle_fasteoi_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 568 | { |
Thomas Gleixner | 328a497 | 2014-03-13 19:03:51 +0100 | [diff] [blame] | 569 | struct irq_chip *chip = desc->irq_data.chip; |
| 570 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 571 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 572 | |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 573 | if (!irq_may_run(desc)) |
| 574 | goto out; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 575 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 576 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 577 | |
| 578 | /* |
| 579 | * If its disabled or no action available |
Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 580 | * then mask it and get out of here: |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 581 | */ |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 582 | if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 583 | desc->istate |= IRQS_PENDING; |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 584 | mask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 585 | goto out; |
Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 586 | } |
Thomas Gleixner | c69e375 | 2011-03-02 11:49:21 +0100 | [diff] [blame] | 587 | |
Sudeep Holla | a946e8c | 2015-11-04 18:32:37 +0000 | [diff] [blame] | 588 | kstat_incr_irqs_this_cpu(desc); |
Thomas Gleixner | c69e375 | 2011-03-02 11:49:21 +0100 | [diff] [blame] | 589 | if (desc->istate & IRQS_ONESHOT) |
| 590 | mask_irq(desc); |
| 591 | |
Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 592 | preflow_handler(desc); |
Thomas Gleixner | a7ae4de | 2011-02-07 01:23:07 +0100 | [diff] [blame] | 593 | handle_irq_event(desc); |
Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 594 | |
Thomas Gleixner | 328a497 | 2014-03-13 19:03:51 +0100 | [diff] [blame] | 595 | cond_unmask_eoi_irq(desc, chip); |
Thomas Gleixner | ac56376 | 2012-02-07 17:58:03 +0100 | [diff] [blame] | 596 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 597 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 598 | return; |
| 599 | out: |
Thomas Gleixner | 328a497 | 2014-03-13 19:03:51 +0100 | [diff] [blame] | 600 | if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED)) |
| 601 | chip->irq_eoi(&desc->irq_data); |
| 602 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 603 | } |
Vincent Stehlé | 7cad45e | 2014-08-22 01:31:20 +0200 | [diff] [blame] | 604 | EXPORT_SYMBOL_GPL(handle_fasteoi_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 605 | |
| 606 | /** |
| 607 | * handle_edge_irq - edge type IRQ handler |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 608 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 609 | * |
| 610 | * Interrupt occures on the falling and/or rising edge of a hardware |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 611 | * signal. The occurrence is latched into the irq controller hardware |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 612 | * and must be acked in order to be reenabled. After the ack another |
| 613 | * interrupt can happen on the same source even before the first one |
Uwe Kleine-König | dfff061 | 2010-02-12 21:58:11 +0100 | [diff] [blame] | 614 | * is handled by the associated event handler. If this happens it |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 615 | * might be necessary to disable (mask) the interrupt depending on the |
| 616 | * controller hardware. This requires to reenable the interrupt inside |
| 617 | * of the loop which handles the interrupts which have arrived while |
| 618 | * the handler was running. If all pending interrupts are handled, the |
| 619 | * loop is left. |
| 620 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 621 | void handle_edge_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 622 | { |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 623 | raw_spin_lock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 624 | |
Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 625 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | c3d7acd | 2014-08-29 13:46:08 +0200 | [diff] [blame] | 626 | |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 627 | if (!irq_may_run(desc)) { |
| 628 | desc->istate |= IRQS_PENDING; |
| 629 | mask_ack_irq(desc); |
| 630 | goto out_unlock; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 631 | } |
Thomas Gleixner | c3d7acd | 2014-08-29 13:46:08 +0200 | [diff] [blame] | 632 | |
| 633 | /* |
| 634 | * If its disabled or no action available then mask it and get |
| 635 | * out of here. |
| 636 | */ |
| 637 | if (irqd_irq_disabled(&desc->irq_data) || !desc->action) { |
| 638 | desc->istate |= IRQS_PENDING; |
| 639 | mask_ack_irq(desc); |
| 640 | goto out_unlock; |
| 641 | } |
| 642 | |
Jiang Liu | b51bf95 | 2015-06-04 12:13:25 +0800 | [diff] [blame] | 643 | kstat_incr_irqs_this_cpu(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 644 | |
| 645 | /* Start handling the irq */ |
Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 646 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 647 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 648 | do { |
Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 649 | if (unlikely(!desc->action)) { |
Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 650 | mask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 651 | goto out_unlock; |
| 652 | } |
| 653 | |
| 654 | /* |
| 655 | * When another irq arrived while we were handling |
| 656 | * one, we could have masked the irq. |
| 657 | * Renable it, if it was not disabled in meantime. |
| 658 | */ |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 659 | if (unlikely(desc->istate & IRQS_PENDING)) { |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 660 | if (!irqd_irq_disabled(&desc->irq_data) && |
| 661 | irqd_irq_masked(&desc->irq_data)) |
Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 662 | unmask_irq(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 663 | } |
| 664 | |
Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 665 | handle_irq_event(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 666 | |
Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 667 | } while ((desc->istate & IRQS_PENDING) && |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 668 | !irqd_irq_disabled(&desc->irq_data)); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 669 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 670 | out_unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 671 | raw_spin_unlock(&desc->lock); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 672 | } |
Jiri Kosina | 3911ff3 | 2012-05-13 12:13:15 +0200 | [diff] [blame] | 673 | EXPORT_SYMBOL(handle_edge_irq); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 674 | |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 675 | #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER |
| 676 | /** |
| 677 | * handle_edge_eoi_irq - edge eoi type IRQ handler |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 678 | * @desc: the interrupt description structure for this irq |
| 679 | * |
| 680 | * Similar as the above handle_edge_irq, but using eoi and w/o the |
| 681 | * mask/unmask logic. |
| 682 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 683 | void handle_edge_eoi_irq(struct irq_desc *desc) |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 684 | { |
| 685 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 686 | |
| 687 | raw_spin_lock(&desc->lock); |
| 688 | |
| 689 | desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); |
Thomas Gleixner | c3d7acd | 2014-08-29 13:46:08 +0200 | [diff] [blame] | 690 | |
Thomas Gleixner | c7bd3ec0 | 2014-08-29 13:39:37 +0200 | [diff] [blame] | 691 | if (!irq_may_run(desc)) { |
| 692 | desc->istate |= IRQS_PENDING; |
| 693 | goto out_eoi; |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 694 | } |
Thomas Gleixner | c3d7acd | 2014-08-29 13:46:08 +0200 | [diff] [blame] | 695 | |
| 696 | /* |
| 697 | * If its disabled or no action available then mask it and get |
| 698 | * out of here. |
| 699 | */ |
| 700 | if (irqd_irq_disabled(&desc->irq_data) || !desc->action) { |
| 701 | desc->istate |= IRQS_PENDING; |
| 702 | goto out_eoi; |
| 703 | } |
| 704 | |
Jiang Liu | b51bf95 | 2015-06-04 12:13:25 +0800 | [diff] [blame] | 705 | kstat_incr_irqs_this_cpu(desc); |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 706 | |
| 707 | do { |
| 708 | if (unlikely(!desc->action)) |
| 709 | goto out_eoi; |
| 710 | |
| 711 | handle_irq_event(desc); |
| 712 | |
| 713 | } while ((desc->istate & IRQS_PENDING) && |
| 714 | !irqd_irq_disabled(&desc->irq_data)); |
| 715 | |
Stephen Rothwell | ac0e044 | 2011-03-30 10:55:12 +1100 | [diff] [blame] | 716 | out_eoi: |
Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 717 | chip->irq_eoi(&desc->irq_data); |
| 718 | raw_spin_unlock(&desc->lock); |
| 719 | } |
| 720 | #endif |
| 721 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 722 | /** |
Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 723 | * handle_percpu_irq - Per CPU local irq handler |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 724 | * @desc: the interrupt description structure for this irq |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 725 | * |
| 726 | * Per CPU interrupts on SMP machines without locking requirements |
| 727 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 728 | void handle_percpu_irq(struct irq_desc *desc) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 729 | { |
Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 730 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 731 | |
Jiang Liu | b51bf95 | 2015-06-04 12:13:25 +0800 | [diff] [blame] | 732 | kstat_incr_irqs_this_cpu(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 733 | |
Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 734 | if (chip->irq_ack) |
| 735 | chip->irq_ack(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 736 | |
Huang Shijie | 71f6434 | 2015-09-02 10:24:55 +0800 | [diff] [blame] | 737 | handle_irq_event_percpu(desc); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 738 | |
Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 739 | if (chip->irq_eoi) |
| 740 | chip->irq_eoi(&desc->irq_data); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 741 | } |
| 742 | |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 743 | /** |
| 744 | * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 745 | * @desc: the interrupt description structure for this irq |
| 746 | * |
| 747 | * Per CPU interrupts on SMP machines without locking requirements. Same as |
| 748 | * handle_percpu_irq() above but with the following extras: |
| 749 | * |
| 750 | * action->percpu_dev_id is a pointer to percpu variables which |
| 751 | * contain the real device id for the cpu on which this handler is |
| 752 | * called |
| 753 | */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 754 | void handle_percpu_devid_irq(struct irq_desc *desc) |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 755 | { |
| 756 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 757 | struct irqaction *action = desc->action; |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 758 | unsigned int irq = irq_desc_get_irq(desc); |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 759 | irqreturn_t res; |
| 760 | |
Jiang Liu | b51bf95 | 2015-06-04 12:13:25 +0800 | [diff] [blame] | 761 | kstat_incr_irqs_this_cpu(desc); |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 762 | |
| 763 | if (chip->irq_ack) |
| 764 | chip->irq_ack(&desc->irq_data); |
| 765 | |
Thomas Gleixner | fc590c2 | 2016-09-02 14:45:19 +0200 | [diff] [blame] | 766 | if (likely(action)) { |
| 767 | trace_irq_handler_entry(irq, action); |
| 768 | res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id)); |
| 769 | trace_irq_handler_exit(irq, action, res); |
| 770 | } else { |
| 771 | unsigned int cpu = smp_processor_id(); |
| 772 | bool enabled = cpumask_test_cpu(cpu, desc->percpu_enabled); |
| 773 | |
| 774 | if (enabled) |
| 775 | irq_percpu_disable(desc, cpu); |
| 776 | |
| 777 | pr_err_once("Spurious%s percpu IRQ%u on CPU%u\n", |
| 778 | enabled ? " and unmasked" : "", irq, cpu); |
| 779 | } |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 780 | |
| 781 | if (chip->irq_eoi) |
| 782 | chip->irq_eoi(&desc->irq_data); |
| 783 | } |
| 784 | |
Wei Yongjun | b8129a1 | 2016-09-25 15:36:39 +0000 | [diff] [blame] | 785 | static void |
Russell King | 3b0f95b | 2015-06-16 23:06:20 +0100 | [diff] [blame] | 786 | __irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle, |
| 787 | int is_chained, const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 788 | { |
Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 789 | if (!handle) { |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 790 | handle = handle_bad_irq; |
Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 791 | } else { |
Marc Zyngier | f86eff2 | 2014-11-15 10:49:13 +0000 | [diff] [blame] | 792 | struct irq_data *irq_data = &desc->irq_data; |
| 793 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
| 794 | /* |
| 795 | * With hierarchical domains we might run into a |
| 796 | * situation where the outermost chip is not yet set |
| 797 | * up, but the inner chips are there. Instead of |
| 798 | * bailing we install the handler, but obviously we |
| 799 | * cannot enable/startup the interrupt at this point. |
| 800 | */ |
| 801 | while (irq_data) { |
| 802 | if (irq_data->chip != &no_irq_chip) |
| 803 | break; |
| 804 | /* |
| 805 | * Bail out if the outer chip is not set up |
| 806 | * and the interrrupt supposed to be started |
| 807 | * right away. |
| 808 | */ |
| 809 | if (WARN_ON(is_chained)) |
Russell King | 3b0f95b | 2015-06-16 23:06:20 +0100 | [diff] [blame] | 810 | return; |
Marc Zyngier | f86eff2 | 2014-11-15 10:49:13 +0000 | [diff] [blame] | 811 | /* Try the parent */ |
| 812 | irq_data = irq_data->parent_data; |
| 813 | } |
| 814 | #endif |
| 815 | if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip)) |
Russell King | 3b0f95b | 2015-06-16 23:06:20 +0100 | [diff] [blame] | 816 | return; |
Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 817 | } |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 818 | |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 819 | /* Uninstall? */ |
| 820 | if (handle == handle_bad_irq) { |
Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 821 | if (desc->irq_data.chip != &no_irq_chip) |
Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 822 | mask_ack_irq(desc); |
Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 823 | irq_state_set_disabled(desc); |
Mika Westerberg | e509bd7 | 2015-10-05 13:12:15 +0300 | [diff] [blame] | 824 | if (is_chained) |
| 825 | desc->action = NULL; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 826 | desc->depth = 1; |
| 827 | } |
| 828 | desc->handle_irq = handle; |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 829 | desc->name = name; |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 830 | |
| 831 | if (handle != handle_bad_irq && is_chained) { |
Marc Zyngier | 1984e07 | 2016-09-19 09:49:27 +0100 | [diff] [blame] | 832 | unsigned int type = irqd_get_trigger_type(&desc->irq_data); |
| 833 | |
Marc Zyngier | 1e12c4a | 2016-08-11 14:19:42 +0100 | [diff] [blame] | 834 | /* |
| 835 | * We're about to start this interrupt immediately, |
| 836 | * hence the need to set the trigger configuration. |
| 837 | * But the .set_type callback may have overridden the |
| 838 | * flow handler, ignoring that we're dealing with a |
| 839 | * chained interrupt. Reset it immediately because we |
| 840 | * do know better. |
| 841 | */ |
Marc Zyngier | 1984e07 | 2016-09-19 09:49:27 +0100 | [diff] [blame] | 842 | if (type != IRQ_TYPE_NONE) { |
| 843 | __irq_set_trigger(desc, type); |
| 844 | desc->handle_irq = handle; |
| 845 | } |
Marc Zyngier | 1e12c4a | 2016-08-11 14:19:42 +0100 | [diff] [blame] | 846 | |
Thomas Gleixner | 1ccb4e6 | 2011-02-09 14:44:17 +0100 | [diff] [blame] | 847 | irq_settings_set_noprobe(desc); |
| 848 | irq_settings_set_norequest(desc); |
Paul Mundt | 7f1b124 | 2011-04-07 06:01:44 +0900 | [diff] [blame] | 849 | irq_settings_set_nothread(desc); |
Mika Westerberg | e509bd7 | 2015-10-05 13:12:15 +0300 | [diff] [blame] | 850 | desc->action = &chained_action; |
Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 851 | irq_startup(desc, true); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 852 | } |
Russell King | 3b0f95b | 2015-06-16 23:06:20 +0100 | [diff] [blame] | 853 | } |
| 854 | |
| 855 | void |
| 856 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
| 857 | const char *name) |
| 858 | { |
| 859 | unsigned long flags; |
| 860 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); |
| 861 | |
| 862 | if (!desc) |
| 863 | return; |
| 864 | |
| 865 | __irq_do_set_handler(desc, handle, is_chained, name); |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 866 | irq_put_desc_busunlock(desc, flags); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 867 | } |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 868 | EXPORT_SYMBOL_GPL(__irq_set_handler); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 869 | |
| 870 | void |
Russell King | 3b0f95b | 2015-06-16 23:06:20 +0100 | [diff] [blame] | 871 | irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, |
| 872 | void *data) |
| 873 | { |
| 874 | unsigned long flags; |
| 875 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); |
| 876 | |
| 877 | if (!desc) |
| 878 | return; |
| 879 | |
| 880 | __irq_do_set_handler(desc, handle, 1, NULL); |
Jiang Liu | af7080e | 2015-06-01 16:05:21 +0800 | [diff] [blame] | 881 | desc->irq_common_data.handler_data = data; |
Russell King | 3b0f95b | 2015-06-16 23:06:20 +0100 | [diff] [blame] | 882 | |
| 883 | irq_put_desc_busunlock(desc, flags); |
| 884 | } |
| 885 | EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data); |
| 886 | |
| 887 | void |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 888 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 889 | irq_flow_handler_t handle, const char *name) |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 890 | { |
Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 891 | irq_set_chip(irq, chip); |
Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 892 | __irq_set_handler(irq, handle, 0, name); |
Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 893 | } |
Kuninori Morimoto | b3ae66f | 2012-07-30 22:39:06 -0700 | [diff] [blame] | 894 | EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 895 | |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 896 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 897 | { |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 898 | unsigned long flags; |
Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 899 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 900 | |
Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 901 | if (!desc) |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 902 | return; |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 903 | irq_settings_clr_and_set(desc, clr, set); |
| 904 | |
Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 905 | irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | |
Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 906 | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 907 | if (irq_settings_has_no_balance_set(desc)) |
| 908 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); |
| 909 | if (irq_settings_is_per_cpu(desc)) |
| 910 | irqd_set(&desc->irq_data, IRQD_PER_CPU); |
Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 911 | if (irq_settings_can_move_pcntxt(desc)) |
| 912 | irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); |
Thomas Gleixner | 0ef5ca1 | 2011-03-28 21:59:37 +0200 | [diff] [blame] | 913 | if (irq_settings_is_level(desc)) |
| 914 | irqd_set(&desc->irq_data, IRQD_LEVEL); |
Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 915 | |
Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 916 | irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); |
| 917 | |
Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 918 | irq_put_desc_unlock(desc, flags); |
Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 919 | } |
Jonathan Cameron | edf76f8 | 2011-05-18 10:39:04 +0100 | [diff] [blame] | 920 | EXPORT_SYMBOL_GPL(irq_modify_status); |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 921 | |
| 922 | /** |
| 923 | * irq_cpu_online - Invoke all irq_cpu_online functions. |
| 924 | * |
| 925 | * Iterate through all irqs and invoke the chip.irq_cpu_online() |
| 926 | * for each. |
| 927 | */ |
| 928 | void irq_cpu_online(void) |
| 929 | { |
| 930 | struct irq_desc *desc; |
| 931 | struct irq_chip *chip; |
| 932 | unsigned long flags; |
| 933 | unsigned int irq; |
| 934 | |
| 935 | for_each_active_irq(irq) { |
| 936 | desc = irq_to_desc(irq); |
| 937 | if (!desc) |
| 938 | continue; |
| 939 | |
| 940 | raw_spin_lock_irqsave(&desc->lock, flags); |
| 941 | |
| 942 | chip = irq_data_get_irq_chip(&desc->irq_data); |
Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 943 | if (chip && chip->irq_cpu_online && |
| 944 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 945 | !irqd_irq_disabled(&desc->irq_data))) |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 946 | chip->irq_cpu_online(&desc->irq_data); |
| 947 | |
| 948 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
| 949 | } |
| 950 | } |
| 951 | |
| 952 | /** |
| 953 | * irq_cpu_offline - Invoke all irq_cpu_offline functions. |
| 954 | * |
| 955 | * Iterate through all irqs and invoke the chip.irq_cpu_offline() |
| 956 | * for each. |
| 957 | */ |
| 958 | void irq_cpu_offline(void) |
| 959 | { |
| 960 | struct irq_desc *desc; |
| 961 | struct irq_chip *chip; |
| 962 | unsigned long flags; |
| 963 | unsigned int irq; |
| 964 | |
| 965 | for_each_active_irq(irq) { |
| 966 | desc = irq_to_desc(irq); |
| 967 | if (!desc) |
| 968 | continue; |
| 969 | |
| 970 | raw_spin_lock_irqsave(&desc->lock, flags); |
| 971 | |
| 972 | chip = irq_data_get_irq_chip(&desc->irq_data); |
Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 973 | if (chip && chip->irq_cpu_offline && |
| 974 | (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 975 | !irqd_irq_disabled(&desc->irq_data))) |
David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 976 | chip->irq_cpu_offline(&desc->irq_data); |
| 977 | |
| 978 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
| 979 | } |
| 980 | } |
Jiang Liu | 85f08c1 | 2014-11-06 22:20:16 +0800 | [diff] [blame] | 981 | |
| 982 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
| 983 | /** |
Stefan Agner | 3cfeffc | 2015-05-16 11:44:14 +0200 | [diff] [blame] | 984 | * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if |
| 985 | * NULL) |
| 986 | * @data: Pointer to interrupt specific data |
| 987 | */ |
| 988 | void irq_chip_enable_parent(struct irq_data *data) |
| 989 | { |
| 990 | data = data->parent_data; |
| 991 | if (data->chip->irq_enable) |
| 992 | data->chip->irq_enable(data); |
| 993 | else |
| 994 | data->chip->irq_unmask(data); |
| 995 | } |
| 996 | |
| 997 | /** |
| 998 | * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if |
| 999 | * NULL) |
| 1000 | * @data: Pointer to interrupt specific data |
| 1001 | */ |
| 1002 | void irq_chip_disable_parent(struct irq_data *data) |
| 1003 | { |
| 1004 | data = data->parent_data; |
| 1005 | if (data->chip->irq_disable) |
| 1006 | data->chip->irq_disable(data); |
| 1007 | else |
| 1008 | data->chip->irq_mask(data); |
| 1009 | } |
| 1010 | |
| 1011 | /** |
Jiang Liu | 85f08c1 | 2014-11-06 22:20:16 +0800 | [diff] [blame] | 1012 | * irq_chip_ack_parent - Acknowledge the parent interrupt |
| 1013 | * @data: Pointer to interrupt specific data |
| 1014 | */ |
| 1015 | void irq_chip_ack_parent(struct irq_data *data) |
| 1016 | { |
| 1017 | data = data->parent_data; |
| 1018 | data->chip->irq_ack(data); |
| 1019 | } |
Jake Oshins | a4289dc | 2015-12-10 17:52:59 +0000 | [diff] [blame] | 1020 | EXPORT_SYMBOL_GPL(irq_chip_ack_parent); |
Jiang Liu | 85f08c1 | 2014-11-06 22:20:16 +0800 | [diff] [blame] | 1021 | |
| 1022 | /** |
Yingjoe Chen | 56e8aba | 2014-11-13 23:37:05 +0800 | [diff] [blame] | 1023 | * irq_chip_mask_parent - Mask the parent interrupt |
| 1024 | * @data: Pointer to interrupt specific data |
| 1025 | */ |
| 1026 | void irq_chip_mask_parent(struct irq_data *data) |
| 1027 | { |
| 1028 | data = data->parent_data; |
| 1029 | data->chip->irq_mask(data); |
| 1030 | } |
Quan Nguyen | 52b2a05 | 2016-03-03 21:56:52 +0700 | [diff] [blame] | 1031 | EXPORT_SYMBOL_GPL(irq_chip_mask_parent); |
Yingjoe Chen | 56e8aba | 2014-11-13 23:37:05 +0800 | [diff] [blame] | 1032 | |
| 1033 | /** |
| 1034 | * irq_chip_unmask_parent - Unmask the parent interrupt |
| 1035 | * @data: Pointer to interrupt specific data |
| 1036 | */ |
| 1037 | void irq_chip_unmask_parent(struct irq_data *data) |
| 1038 | { |
| 1039 | data = data->parent_data; |
| 1040 | data->chip->irq_unmask(data); |
| 1041 | } |
Quan Nguyen | 52b2a05 | 2016-03-03 21:56:52 +0700 | [diff] [blame] | 1042 | EXPORT_SYMBOL_GPL(irq_chip_unmask_parent); |
Yingjoe Chen | 56e8aba | 2014-11-13 23:37:05 +0800 | [diff] [blame] | 1043 | |
| 1044 | /** |
| 1045 | * irq_chip_eoi_parent - Invoke EOI on the parent interrupt |
| 1046 | * @data: Pointer to interrupt specific data |
| 1047 | */ |
| 1048 | void irq_chip_eoi_parent(struct irq_data *data) |
| 1049 | { |
| 1050 | data = data->parent_data; |
| 1051 | data->chip->irq_eoi(data); |
| 1052 | } |
Quan Nguyen | 52b2a05 | 2016-03-03 21:56:52 +0700 | [diff] [blame] | 1053 | EXPORT_SYMBOL_GPL(irq_chip_eoi_parent); |
Yingjoe Chen | 56e8aba | 2014-11-13 23:37:05 +0800 | [diff] [blame] | 1054 | |
| 1055 | /** |
| 1056 | * irq_chip_set_affinity_parent - Set affinity on the parent interrupt |
| 1057 | * @data: Pointer to interrupt specific data |
| 1058 | * @dest: The affinity mask to set |
| 1059 | * @force: Flag to enforce setting (disable online checks) |
| 1060 | * |
| 1061 | * Conditinal, as the underlying parent chip might not implement it. |
| 1062 | */ |
| 1063 | int irq_chip_set_affinity_parent(struct irq_data *data, |
| 1064 | const struct cpumask *dest, bool force) |
| 1065 | { |
| 1066 | data = data->parent_data; |
| 1067 | if (data->chip->irq_set_affinity) |
| 1068 | return data->chip->irq_set_affinity(data, dest, force); |
| 1069 | |
| 1070 | return -ENOSYS; |
| 1071 | } |
| 1072 | |
| 1073 | /** |
Grygorii Strashko | b7560de | 2015-08-14 15:20:26 +0300 | [diff] [blame] | 1074 | * irq_chip_set_type_parent - Set IRQ type on the parent interrupt |
| 1075 | * @data: Pointer to interrupt specific data |
| 1076 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
| 1077 | * |
| 1078 | * Conditional, as the underlying parent chip might not implement it. |
| 1079 | */ |
| 1080 | int irq_chip_set_type_parent(struct irq_data *data, unsigned int type) |
| 1081 | { |
| 1082 | data = data->parent_data; |
| 1083 | |
| 1084 | if (data->chip->irq_set_type) |
| 1085 | return data->chip->irq_set_type(data, type); |
| 1086 | |
| 1087 | return -ENOSYS; |
| 1088 | } |
Quan Nguyen | 52b2a05 | 2016-03-03 21:56:52 +0700 | [diff] [blame] | 1089 | EXPORT_SYMBOL_GPL(irq_chip_set_type_parent); |
Grygorii Strashko | b7560de | 2015-08-14 15:20:26 +0300 | [diff] [blame] | 1090 | |
| 1091 | /** |
Jiang Liu | 85f08c1 | 2014-11-06 22:20:16 +0800 | [diff] [blame] | 1092 | * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware |
| 1093 | * @data: Pointer to interrupt specific data |
| 1094 | * |
| 1095 | * Iterate through the domain hierarchy of the interrupt and check |
| 1096 | * whether a hw retrigger function exists. If yes, invoke it. |
| 1097 | */ |
| 1098 | int irq_chip_retrigger_hierarchy(struct irq_data *data) |
| 1099 | { |
| 1100 | for (data = data->parent_data; data; data = data->parent_data) |
| 1101 | if (data->chip && data->chip->irq_retrigger) |
| 1102 | return data->chip->irq_retrigger(data); |
| 1103 | |
Grygorii Strashko | 6d4affe | 2015-08-14 15:20:25 +0300 | [diff] [blame] | 1104 | return 0; |
Jiang Liu | 85f08c1 | 2014-11-06 22:20:16 +0800 | [diff] [blame] | 1105 | } |
Marc Zyngier | 08b55e2 | 2015-03-11 15:43:43 +0000 | [diff] [blame] | 1106 | |
| 1107 | /** |
Jiang Liu | 0a4377d | 2015-05-19 17:07:14 +0800 | [diff] [blame] | 1108 | * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt |
| 1109 | * @data: Pointer to interrupt specific data |
Masanari Iida | 8505a81 | 2015-07-29 19:09:36 +0900 | [diff] [blame] | 1110 | * @vcpu_info: The vcpu affinity information |
Jiang Liu | 0a4377d | 2015-05-19 17:07:14 +0800 | [diff] [blame] | 1111 | */ |
| 1112 | int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info) |
| 1113 | { |
| 1114 | data = data->parent_data; |
| 1115 | if (data->chip->irq_set_vcpu_affinity) |
| 1116 | return data->chip->irq_set_vcpu_affinity(data, vcpu_info); |
| 1117 | |
| 1118 | return -ENOSYS; |
| 1119 | } |
| 1120 | |
| 1121 | /** |
Marc Zyngier | 08b55e2 | 2015-03-11 15:43:43 +0000 | [diff] [blame] | 1122 | * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt |
| 1123 | * @data: Pointer to interrupt specific data |
| 1124 | * @on: Whether to set or reset the wake-up capability of this irq |
| 1125 | * |
| 1126 | * Conditional, as the underlying parent chip might not implement it. |
| 1127 | */ |
| 1128 | int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on) |
| 1129 | { |
| 1130 | data = data->parent_data; |
| 1131 | if (data->chip->irq_set_wake) |
| 1132 | return data->chip->irq_set_wake(data, on); |
| 1133 | |
| 1134 | return -ENOSYS; |
| 1135 | } |
Jiang Liu | 85f08c1 | 2014-11-06 22:20:16 +0800 | [diff] [blame] | 1136 | #endif |
Jiang Liu | 515085e | 2014-11-06 22:20:17 +0800 | [diff] [blame] | 1137 | |
| 1138 | /** |
| 1139 | * irq_chip_compose_msi_msg - Componse msi message for a irq chip |
| 1140 | * @data: Pointer to interrupt specific data |
| 1141 | * @msg: Pointer to the MSI message |
| 1142 | * |
| 1143 | * For hierarchical domains we find the first chip in the hierarchy |
| 1144 | * which implements the irq_compose_msi_msg callback. For non |
| 1145 | * hierarchical we use the top level chip. |
| 1146 | */ |
| 1147 | int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) |
| 1148 | { |
| 1149 | struct irq_data *pos = NULL; |
| 1150 | |
| 1151 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
| 1152 | for (; data; data = data->parent_data) |
| 1153 | #endif |
| 1154 | if (data->chip && data->chip->irq_compose_msi_msg) |
| 1155 | pos = data; |
| 1156 | if (!pos) |
| 1157 | return -ENOSYS; |
| 1158 | |
| 1159 | pos->chip->irq_compose_msi_msg(pos, msg); |
| 1160 | |
| 1161 | return 0; |
| 1162 | } |
Jon Hunter | be45beb | 2016-06-07 16:12:29 +0100 | [diff] [blame] | 1163 | |
| 1164 | /** |
| 1165 | * irq_chip_pm_get - Enable power for an IRQ chip |
| 1166 | * @data: Pointer to interrupt specific data |
| 1167 | * |
| 1168 | * Enable the power to the IRQ chip referenced by the interrupt data |
| 1169 | * structure. |
| 1170 | */ |
| 1171 | int irq_chip_pm_get(struct irq_data *data) |
| 1172 | { |
| 1173 | int retval; |
| 1174 | |
| 1175 | if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) { |
| 1176 | retval = pm_runtime_get_sync(data->chip->parent_device); |
| 1177 | if (retval < 0) { |
| 1178 | pm_runtime_put_noidle(data->chip->parent_device); |
| 1179 | return retval; |
| 1180 | } |
| 1181 | } |
| 1182 | |
| 1183 | return 0; |
| 1184 | } |
| 1185 | |
| 1186 | /** |
| 1187 | * irq_chip_pm_put - Disable power for an IRQ chip |
| 1188 | * @data: Pointer to interrupt specific data |
| 1189 | * |
| 1190 | * Disable the power to the IRQ chip referenced by the interrupt data |
| 1191 | * structure, belongs. Note that power will only be disabled, once this |
| 1192 | * function has been called for all IRQs that have called irq_chip_pm_get(). |
| 1193 | */ |
| 1194 | int irq_chip_pm_put(struct irq_data *data) |
| 1195 | { |
| 1196 | int retval = 0; |
| 1197 | |
| 1198 | if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) |
| 1199 | retval = pm_runtime_put(data->chip->parent_device); |
| 1200 | |
| 1201 | return (retval < 0) ? retval : 0; |
| 1202 | } |