blob: 70b8975d107ee185e9b4b3bcf6e220ff9b4d555e [file] [log] [blame]
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001/*
2 * drivers/dma/imx-dma.c
3 *
4 * This file contains a driver for the Freescale i.MX DMA engine
5 * found on i.MX1/21/27
6 *
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
Javier Martin9e15db72012-03-02 09:28:47 +01008 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
Sascha Hauer1f1846c2010-10-06 10:25:55 +02009 *
10 * The code contained herein is licensed under the GNU General Public
11 * License. You may obtain a copy of the GNU General Public License
12 * Version 2 or later at the following locations:
13 *
14 * http://www.opensource.org/licenses/gpl-license.html
15 * http://www.gnu.org/copyleft/gpl.html
16 */
Thierry Reding73312052013-01-21 11:09:00 +010017#include <linux/err.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020018#include <linux/init.h>
19#include <linux/types.h>
20#include <linux/mm.h>
21#include <linux/interrupt.h>
22#include <linux/spinlock.h>
23#include <linux/device.h>
24#include <linux/dma-mapping.h>
25#include <linux/slab.h>
26#include <linux/platform_device.h>
Javier Martin6bd08122012-03-22 14:54:01 +010027#include <linux/clk.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020028#include <linux/dmaengine.h>
Paul Gortmaker5c45ad72011-07-31 16:14:17 -040029#include <linux/module.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020030
31#include <asm/irq.h>
Arnd Bergmann82906b12012-08-24 15:14:29 +020032#include <linux/platform_data/dma-imx.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020033
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000034#include "dmaengine.h"
Javier Martin9e15db72012-03-02 09:28:47 +010035#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
Javier Martin6bd08122012-03-22 14:54:01 +010036#define IMX_DMA_CHANNELS 16
37
Javier Martinf606ab82012-03-22 14:54:14 +010038#define IMX_DMA_2D_SLOTS 2
39#define IMX_DMA_2D_SLOT_A 0
40#define IMX_DMA_2D_SLOT_B 1
41
Javier Martin6bd08122012-03-22 14:54:01 +010042#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
43#define IMX_DMA_MEMSIZE_32 (0 << 4)
44#define IMX_DMA_MEMSIZE_8 (1 << 4)
45#define IMX_DMA_MEMSIZE_16 (2 << 4)
46#define IMX_DMA_TYPE_LINEAR (0 << 10)
47#define IMX_DMA_TYPE_2D (1 << 10)
48#define IMX_DMA_TYPE_FIFO (2 << 10)
49
50#define IMX_DMA_ERR_BURST (1 << 0)
51#define IMX_DMA_ERR_REQUEST (1 << 1)
52#define IMX_DMA_ERR_TRANSFER (1 << 2)
53#define IMX_DMA_ERR_BUFFER (1 << 3)
54#define IMX_DMA_ERR_TIMEOUT (1 << 4)
55
56#define DMA_DCR 0x00 /* Control Register */
57#define DMA_DISR 0x04 /* Interrupt status Register */
58#define DMA_DIMR 0x08 /* Interrupt mask Register */
59#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
60#define DMA_DRTOSR 0x10 /* Request timeout Register */
61#define DMA_DSESR 0x14 /* Transfer Error Status Register */
62#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
63#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
64#define DMA_WSRA 0x40 /* W-Size Register A */
65#define DMA_XSRA 0x44 /* X-Size Register A */
66#define DMA_YSRA 0x48 /* Y-Size Register A */
67#define DMA_WSRB 0x4c /* W-Size Register B */
68#define DMA_XSRB 0x50 /* X-Size Register B */
69#define DMA_YSRB 0x54 /* Y-Size Register B */
70#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
71#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
72#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
73#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
74#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
75#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
76#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
77#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
78#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
79
80#define DCR_DRST (1<<1)
81#define DCR_DEN (1<<0)
82#define DBTOCR_EN (1<<15)
83#define DBTOCR_CNT(x) ((x) & 0x7fff)
84#define CNTR_CNT(x) ((x) & 0xffffff)
85#define CCR_ACRPT (1<<14)
86#define CCR_DMOD_LINEAR (0x0 << 12)
87#define CCR_DMOD_2D (0x1 << 12)
88#define CCR_DMOD_FIFO (0x2 << 12)
89#define CCR_DMOD_EOBFIFO (0x3 << 12)
90#define CCR_SMOD_LINEAR (0x0 << 10)
91#define CCR_SMOD_2D (0x1 << 10)
92#define CCR_SMOD_FIFO (0x2 << 10)
93#define CCR_SMOD_EOBFIFO (0x3 << 10)
94#define CCR_MDIR_DEC (1<<9)
95#define CCR_MSEL_B (1<<8)
96#define CCR_DSIZ_32 (0x0 << 6)
97#define CCR_DSIZ_8 (0x1 << 6)
98#define CCR_DSIZ_16 (0x2 << 6)
99#define CCR_SSIZ_32 (0x0 << 4)
100#define CCR_SSIZ_8 (0x1 << 4)
101#define CCR_SSIZ_16 (0x2 << 4)
102#define CCR_REN (1<<3)
103#define CCR_RPT (1<<2)
104#define CCR_FRC (1<<1)
105#define CCR_CEN (1<<0)
106#define RTOR_EN (1<<15)
107#define RTOR_CLK (1<<14)
108#define RTOR_PSC (1<<13)
Javier Martin9e15db72012-03-02 09:28:47 +0100109
110enum imxdma_prep_type {
111 IMXDMA_DESC_MEMCPY,
112 IMXDMA_DESC_INTERLEAVED,
113 IMXDMA_DESC_SLAVE_SG,
114 IMXDMA_DESC_CYCLIC,
115};
116
Javier Martinf606ab82012-03-22 14:54:14 +0100117struct imx_dma_2d_config {
118 u16 xsr;
119 u16 ysr;
120 u16 wsr;
121 int count;
122};
123
Javier Martin9e15db72012-03-02 09:28:47 +0100124struct imxdma_desc {
125 struct list_head node;
126 struct dma_async_tx_descriptor desc;
127 enum dma_status status;
128 dma_addr_t src;
129 dma_addr_t dest;
130 size_t len;
Javier Martin2efc3442012-03-22 14:54:03 +0100131 enum dma_transfer_direction direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100132 enum imxdma_prep_type type;
133 /* For memcpy and interleaved */
134 unsigned int config_port;
135 unsigned int config_mem;
136 /* For interleaved transfers */
137 unsigned int x;
138 unsigned int y;
139 unsigned int w;
140 /* For slave sg and cyclic */
141 struct scatterlist *sg;
142 unsigned int sgcount;
143};
144
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200145struct imxdma_channel {
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100146 int hw_chaining;
147 struct timer_list watchdog;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200148 struct imxdma_engine *imxdma;
149 unsigned int channel;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200150
Javier Martin9e15db72012-03-02 09:28:47 +0100151 struct tasklet_struct dma_tasklet;
152 struct list_head ld_free;
153 struct list_head ld_queue;
154 struct list_head ld_active;
155 int descs_allocated;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200156 enum dma_slave_buswidth word_size;
157 dma_addr_t per_address;
158 u32 watermark_level;
159 struct dma_chan chan;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200160 struct dma_async_tx_descriptor desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200161 enum dma_status status;
162 int dma_request;
163 struct scatterlist *sg_list;
Javier Martin359291a2012-03-22 14:54:06 +0100164 u32 ccr_from_device;
165 u32 ccr_to_device;
Javier Martinf606ab82012-03-22 14:54:14 +0100166 bool enabled_2d;
167 int slot_2d;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200168};
169
Shawn Guoe51d0f02012-09-15 21:11:28 +0800170enum imx_dma_type {
171 IMX1_DMA,
172 IMX21_DMA,
173 IMX27_DMA,
174};
175
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200176struct imxdma_engine {
177 struct device *dev;
Sascha Hauer1e070a62011-01-12 13:14:37 +0100178 struct device_dma_parameters dma_parms;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200179 struct dma_device dma_device;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100180 void __iomem *base;
Fabio Estevama2367db2012-07-03 15:33:29 -0300181 struct clk *dma_ahb;
182 struct clk *dma_ipg;
Javier Martinf606ab82012-03-22 14:54:14 +0100183 spinlock_t lock;
184 struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS];
Javier Martin6bd08122012-03-22 14:54:01 +0100185 struct imxdma_channel channel[IMX_DMA_CHANNELS];
Shawn Guoe51d0f02012-09-15 21:11:28 +0800186 enum imx_dma_type devtype;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200187};
188
Shawn Guoe51d0f02012-09-15 21:11:28 +0800189static struct platform_device_id imx_dma_devtype[] = {
190 {
191 .name = "imx1-dma",
192 .driver_data = IMX1_DMA,
193 }, {
194 .name = "imx21-dma",
195 .driver_data = IMX21_DMA,
196 }, {
197 .name = "imx27-dma",
198 .driver_data = IMX27_DMA,
199 }, {
200 /* sentinel */
201 }
202};
203MODULE_DEVICE_TABLE(platform, imx_dma_devtype);
204
205static inline int is_imx1_dma(struct imxdma_engine *imxdma)
206{
207 return imxdma->devtype == IMX1_DMA;
208}
209
210static inline int is_imx21_dma(struct imxdma_engine *imxdma)
211{
212 return imxdma->devtype == IMX21_DMA;
213}
214
215static inline int is_imx27_dma(struct imxdma_engine *imxdma)
216{
217 return imxdma->devtype == IMX27_DMA;
218}
219
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200220static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
221{
222 return container_of(chan, struct imxdma_channel, chan);
223}
224
Javier Martin9e15db72012-03-02 09:28:47 +0100225static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200226{
Javier Martin9e15db72012-03-02 09:28:47 +0100227 struct imxdma_desc *desc;
228
229 if (!list_empty(&imxdmac->ld_active)) {
230 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
231 node);
232 if (desc->type == IMXDMA_DESC_CYCLIC)
233 return true;
234 }
235 return false;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200236}
237
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200238
Javier Martincd5cf9d2012-03-22 14:54:12 +0100239
240static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
241 unsigned offset)
Javier Martin6bd08122012-03-22 14:54:01 +0100242{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100243 __raw_writel(val, imxdma->base + offset);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200244}
245
Javier Martincd5cf9d2012-03-22 14:54:12 +0100246static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200247{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100248 return __raw_readl(imxdma->base + offset);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200249}
250
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100251static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200252{
Shawn Guoe51d0f02012-09-15 21:11:28 +0800253 struct imxdma_engine *imxdma = imxdmac->imxdma;
254
255 if (is_imx27_dma(imxdma))
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100256 return imxdmac->hw_chaining;
Javier Martin6bd08122012-03-22 14:54:01 +0100257 else
258 return 0;
259}
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200260
Javier Martin6bd08122012-03-22 14:54:01 +0100261/*
262 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
263 */
Javier Martina6cbb2d2012-03-22 14:54:11 +0100264static inline int imxdma_sg_next(struct imxdma_desc *d)
Javier Martin6bd08122012-03-22 14:54:01 +0100265{
Javier Martin2efc3442012-03-22 14:54:03 +0100266 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100267 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martina6cbb2d2012-03-22 14:54:11 +0100268 struct scatterlist *sg = d->sg;
Javier Martin6bd08122012-03-22 14:54:01 +0100269 unsigned long now;
270
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200271 now = min(d->len, sg_dma_len(sg));
Javier Martin6b0e2f52012-03-22 14:54:09 +0100272 if (d->len != IMX_DMA_LENGTH_LOOP)
273 d->len -= now;
Javier Martin6bd08122012-03-22 14:54:01 +0100274
Javier Martin2efc3442012-03-22 14:54:03 +0100275 if (d->direction == DMA_DEV_TO_MEM)
Javier Martincd5cf9d2012-03-22 14:54:12 +0100276 imx_dmav1_writel(imxdma, sg->dma_address,
277 DMA_DAR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100278 else
Javier Martincd5cf9d2012-03-22 14:54:12 +0100279 imx_dmav1_writel(imxdma, sg->dma_address,
280 DMA_SAR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100281
Javier Martincd5cf9d2012-03-22 14:54:12 +0100282 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100283
Javier Martinf9b283a2012-03-22 14:54:13 +0100284 dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
285 "size 0x%08x\n", __func__, imxdmac->channel,
Javier Martincd5cf9d2012-03-22 14:54:12 +0100286 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
287 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
288 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
Javier Martin6bd08122012-03-22 14:54:01 +0100289
290 return now;
291}
292
Javier Martin2efc3442012-03-22 14:54:03 +0100293static void imxdma_enable_hw(struct imxdma_desc *d)
Javier Martin6bd08122012-03-22 14:54:01 +0100294{
Javier Martin2efc3442012-03-22 14:54:03 +0100295 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100296 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100297 int channel = imxdmac->channel;
298 unsigned long flags;
299
Javier Martinf9b283a2012-03-22 14:54:13 +0100300 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100301
Javier Martin6bd08122012-03-22 14:54:01 +0100302 local_irq_save(flags);
303
Javier Martincd5cf9d2012-03-22 14:54:12 +0100304 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
305 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
306 ~(1 << channel), DMA_DIMR);
307 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
308 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100309
Shawn Guoe51d0f02012-09-15 21:11:28 +0800310 if (!is_imx1_dma(imxdma) &&
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100311 d->sg && imxdma_hw_chain(imxdmac)) {
Javier Martin833bc032012-03-22 14:54:07 +0100312 d->sg = sg_next(d->sg);
313 if (d->sg) {
Javier Martin6bd08122012-03-22 14:54:01 +0100314 u32 tmp;
Javier Martina6cbb2d2012-03-22 14:54:11 +0100315 imxdma_sg_next(d);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100316 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
317 imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
318 DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100319 }
320 }
Javier Martin6bd08122012-03-22 14:54:01 +0100321
322 local_irq_restore(flags);
323}
324
325static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
326{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100327 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100328 int channel = imxdmac->channel;
329 unsigned long flags;
330
Javier Martinf9b283a2012-03-22 14:54:13 +0100331 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100332
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100333 if (imxdma_hw_chain(imxdmac))
334 del_timer(&imxdmac->watchdog);
Javier Martin6bd08122012-03-22 14:54:01 +0100335
336 local_irq_save(flags);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100337 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
338 (1 << channel), DMA_DIMR);
339 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
340 ~CCR_CEN, DMA_CCR(channel));
341 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100342 local_irq_restore(flags);
343}
344
Javier Martin6bd08122012-03-22 14:54:01 +0100345static void imxdma_watchdog(unsigned long data)
346{
347 struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100348 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100349 int channel = imxdmac->channel;
350
Javier Martincd5cf9d2012-03-22 14:54:12 +0100351 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100352
353 /* Tasklet watchdog error handler */
354 tasklet_schedule(&imxdmac->dma_tasklet);
Javier Martinf9b283a2012-03-22 14:54:13 +0100355 dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
356 imxdmac->channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100357}
358
359static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
360{
361 struct imxdma_engine *imxdma = dev_id;
Javier Martin6bd08122012-03-22 14:54:01 +0100362 unsigned int err_mask;
363 int i, disr;
364 int errcode;
365
Javier Martincd5cf9d2012-03-22 14:54:12 +0100366 disr = imx_dmav1_readl(imxdma, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100367
Javier Martincd5cf9d2012-03-22 14:54:12 +0100368 err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
369 imx_dmav1_readl(imxdma, DMA_DRTOSR) |
370 imx_dmav1_readl(imxdma, DMA_DSESR) |
371 imx_dmav1_readl(imxdma, DMA_DBOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100372
373 if (!err_mask)
374 return IRQ_HANDLED;
375
Javier Martincd5cf9d2012-03-22 14:54:12 +0100376 imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100377
378 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
379 if (!(err_mask & (1 << i)))
380 continue;
Javier Martin6bd08122012-03-22 14:54:01 +0100381 errcode = 0;
382
Javier Martincd5cf9d2012-03-22 14:54:12 +0100383 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
384 imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100385 errcode |= IMX_DMA_ERR_BURST;
386 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100387 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
388 imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100389 errcode |= IMX_DMA_ERR_REQUEST;
390 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100391 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
392 imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
Javier Martin6bd08122012-03-22 14:54:01 +0100393 errcode |= IMX_DMA_ERR_TRANSFER;
394 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100395 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
396 imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100397 errcode |= IMX_DMA_ERR_BUFFER;
398 }
399 /* Tasklet error handler */
400 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
401
402 printk(KERN_WARNING
403 "DMA timeout on channel %d -%s%s%s%s\n", i,
404 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
405 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
406 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
407 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
408 }
409 return IRQ_HANDLED;
410}
411
412static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
413{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100414 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100415 int chno = imxdmac->channel;
Javier Martin2efc3442012-03-22 14:54:03 +0100416 struct imxdma_desc *desc;
Javier Martin6bd08122012-03-22 14:54:01 +0100417
Javier Martinf606ab82012-03-22 14:54:14 +0100418 spin_lock(&imxdma->lock);
Javier Martin833bc032012-03-22 14:54:07 +0100419 if (list_empty(&imxdmac->ld_active)) {
Javier Martinf606ab82012-03-22 14:54:14 +0100420 spin_unlock(&imxdma->lock);
Javier Martin833bc032012-03-22 14:54:07 +0100421 goto out;
422 }
423
424 desc = list_first_entry(&imxdmac->ld_active,
425 struct imxdma_desc,
426 node);
Javier Martinf606ab82012-03-22 14:54:14 +0100427 spin_unlock(&imxdma->lock);
Javier Martin833bc032012-03-22 14:54:07 +0100428
429 if (desc->sg) {
Javier Martin6bd08122012-03-22 14:54:01 +0100430 u32 tmp;
Javier Martin833bc032012-03-22 14:54:07 +0100431 desc->sg = sg_next(desc->sg);
Javier Martin6bd08122012-03-22 14:54:01 +0100432
Javier Martin833bc032012-03-22 14:54:07 +0100433 if (desc->sg) {
Javier Martina6cbb2d2012-03-22 14:54:11 +0100434 imxdma_sg_next(desc);
Javier Martin6bd08122012-03-22 14:54:01 +0100435
Javier Martincd5cf9d2012-03-22 14:54:12 +0100436 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100437
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100438 if (imxdma_hw_chain(imxdmac)) {
Javier Martin6bd08122012-03-22 14:54:01 +0100439 /* FIXME: The timeout should probably be
440 * configurable
441 */
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100442 mod_timer(&imxdmac->watchdog,
Javier Martin6bd08122012-03-22 14:54:01 +0100443 jiffies + msecs_to_jiffies(500));
444
445 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100446 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100447 } else {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100448 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
449 DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100450 tmp |= CCR_CEN;
451 }
452
Javier Martincd5cf9d2012-03-22 14:54:12 +0100453 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100454
455 if (imxdma_chan_is_doing_cyclic(imxdmac))
456 /* Tasklet progression */
457 tasklet_schedule(&imxdmac->dma_tasklet);
458
459 return;
460 }
461
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100462 if (imxdma_hw_chain(imxdmac)) {
463 del_timer(&imxdmac->watchdog);
Javier Martin6bd08122012-03-22 14:54:01 +0100464 return;
465 }
466 }
467
Javier Martin2efc3442012-03-22 14:54:03 +0100468out:
Javier Martincd5cf9d2012-03-22 14:54:12 +0100469 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100470 /* Tasklet irq */
Javier Martin9e15db72012-03-02 09:28:47 +0100471 tasklet_schedule(&imxdmac->dma_tasklet);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200472}
473
Javier Martin6bd08122012-03-22 14:54:01 +0100474static irqreturn_t dma_irq_handler(int irq, void *dev_id)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200475{
Javier Martin6bd08122012-03-22 14:54:01 +0100476 struct imxdma_engine *imxdma = dev_id;
Javier Martin6bd08122012-03-22 14:54:01 +0100477 int i, disr;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200478
Shawn Guoe51d0f02012-09-15 21:11:28 +0800479 if (!is_imx1_dma(imxdma))
Javier Martin6bd08122012-03-22 14:54:01 +0100480 imxdma_err_handler(irq, dev_id);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200481
Javier Martincd5cf9d2012-03-22 14:54:12 +0100482 disr = imx_dmav1_readl(imxdma, DMA_DISR);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200483
Javier Martinf9b283a2012-03-22 14:54:13 +0100484 dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
Javier Martin6bd08122012-03-22 14:54:01 +0100485
Javier Martincd5cf9d2012-03-22 14:54:12 +0100486 imx_dmav1_writel(imxdma, disr, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100487 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100488 if (disr & (1 << i))
Javier Martin6bd08122012-03-22 14:54:01 +0100489 dma_irq_handle_channel(&imxdma->channel[i]);
Javier Martin6bd08122012-03-22 14:54:01 +0100490 }
491
492 return IRQ_HANDLED;
Javier Martin9e15db72012-03-02 09:28:47 +0100493}
494
495static int imxdma_xfer_desc(struct imxdma_desc *d)
496{
497 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martin3b4b6df2012-03-22 14:54:04 +0100498 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martinf606ab82012-03-22 14:54:14 +0100499 unsigned long flags;
500 int slot = -1;
501 int i;
Javier Martin9e15db72012-03-02 09:28:47 +0100502
503 /* Configure and enable */
504 switch (d->type) {
Javier Martinf606ab82012-03-22 14:54:14 +0100505 case IMXDMA_DESC_INTERLEAVED:
506 /* Try to get a free 2D slot */
507 spin_lock_irqsave(&imxdma->lock, flags);
508 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
509 if ((imxdma->slots_2d[i].count > 0) &&
510 ((imxdma->slots_2d[i].xsr != d->x) ||
511 (imxdma->slots_2d[i].ysr != d->y) ||
512 (imxdma->slots_2d[i].wsr != d->w)))
513 continue;
514 slot = i;
515 break;
516 }
Wei Yongjun720dfd22012-10-21 19:58:30 +0800517 if (slot < 0) {
518 spin_unlock_irqrestore(&imxdma->lock, flags);
Javier Martinf606ab82012-03-22 14:54:14 +0100519 return -EBUSY;
Wei Yongjun720dfd22012-10-21 19:58:30 +0800520 }
Javier Martinf606ab82012-03-22 14:54:14 +0100521
522 imxdma->slots_2d[slot].xsr = d->x;
523 imxdma->slots_2d[slot].ysr = d->y;
524 imxdma->slots_2d[slot].wsr = d->w;
525 imxdma->slots_2d[slot].count++;
526
527 imxdmac->slot_2d = slot;
528 imxdmac->enabled_2d = true;
529 spin_unlock_irqrestore(&imxdma->lock, flags);
530
531 if (slot == IMX_DMA_2D_SLOT_A) {
532 d->config_mem &= ~CCR_MSEL_B;
533 d->config_port &= ~CCR_MSEL_B;
534 imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
535 imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
536 imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
537 } else {
538 d->config_mem |= CCR_MSEL_B;
539 d->config_port |= CCR_MSEL_B;
540 imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
541 imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
542 imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
543 }
544 /*
545 * We fall-through here intentionally, since a 2D transfer is
546 * similar to MEMCPY just adding the 2D slot configuration.
547 */
Javier Martin9e15db72012-03-02 09:28:47 +0100548 case IMXDMA_DESC_MEMCPY:
Javier Martincd5cf9d2012-03-22 14:54:12 +0100549 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
550 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
551 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
Javier Martin3b4b6df2012-03-22 14:54:04 +0100552 DMA_CCR(imxdmac->channel));
553
Javier Martincd5cf9d2012-03-22 14:54:12 +0100554 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
Javier Martin3b4b6df2012-03-22 14:54:04 +0100555
556 dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
557 "dma_length=%d\n", __func__, imxdmac->channel,
558 d->dest, d->src, d->len);
559
560 break;
Javier Martin6bd08122012-03-22 14:54:01 +0100561 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
Javier Martin9e15db72012-03-02 09:28:47 +0100562 case IMXDMA_DESC_CYCLIC:
Javier Martin9e15db72012-03-02 09:28:47 +0100563 case IMXDMA_DESC_SLAVE_SG:
Javier Martin359291a2012-03-22 14:54:06 +0100564 if (d->direction == DMA_DEV_TO_MEM) {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100565 imx_dmav1_writel(imxdma, imxdmac->per_address,
Javier Martin359291a2012-03-22 14:54:06 +0100566 DMA_SAR(imxdmac->channel));
Javier Martincd5cf9d2012-03-22 14:54:12 +0100567 imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
Javier Martin359291a2012-03-22 14:54:06 +0100568 DMA_CCR(imxdmac->channel));
569
570 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
571 "total length=%d dev_addr=0x%08x (dev2mem)\n",
572 __func__, imxdmac->channel, d->sg, d->sgcount,
573 d->len, imxdmac->per_address);
574 } else if (d->direction == DMA_MEM_TO_DEV) {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100575 imx_dmav1_writel(imxdma, imxdmac->per_address,
Javier Martin359291a2012-03-22 14:54:06 +0100576 DMA_DAR(imxdmac->channel));
Javier Martincd5cf9d2012-03-22 14:54:12 +0100577 imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
Javier Martin359291a2012-03-22 14:54:06 +0100578 DMA_CCR(imxdmac->channel));
579
580 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
581 "total length=%d dev_addr=0x%08x (mem2dev)\n",
582 __func__, imxdmac->channel, d->sg, d->sgcount,
583 d->len, imxdmac->per_address);
584 } else {
585 dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
586 __func__, imxdmac->channel);
587 return -EINVAL;
588 }
589
Javier Martina6cbb2d2012-03-22 14:54:11 +0100590 imxdma_sg_next(d);
Javier Martin359291a2012-03-22 14:54:06 +0100591
Javier Martin9e15db72012-03-02 09:28:47 +0100592 break;
593 default:
594 return -EINVAL;
595 }
Javier Martin2efc3442012-03-22 14:54:03 +0100596 imxdma_enable_hw(d);
Javier Martin9e15db72012-03-02 09:28:47 +0100597 return 0;
598}
599
600static void imxdma_tasklet(unsigned long data)
601{
602 struct imxdma_channel *imxdmac = (void *)data;
603 struct imxdma_engine *imxdma = imxdmac->imxdma;
604 struct imxdma_desc *desc;
605
Javier Martinf606ab82012-03-22 14:54:14 +0100606 spin_lock(&imxdma->lock);
Javier Martin9e15db72012-03-02 09:28:47 +0100607
608 if (list_empty(&imxdmac->ld_active)) {
609 /* Someone might have called terminate all */
610 goto out;
611 }
612 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
613
614 if (desc->desc.callback)
615 desc->desc.callback(desc->desc.callback_param);
616
Masanari Iidad73111c2012-08-04 23:37:53 +0900617 /* If we are dealing with a cyclic descriptor, keep it on ld_active
618 * and dont mark the descriptor as complete.
Vinod Koul60f29512012-04-20 15:28:07 +0530619 * Only in non-cyclic cases it would be marked as complete
620 */
Javier Martin9e15db72012-03-02 09:28:47 +0100621 if (imxdma_chan_is_doing_cyclic(imxdmac))
622 goto out;
Vinod Koul60f29512012-04-20 15:28:07 +0530623 else
624 dma_cookie_complete(&desc->desc);
Javier Martin9e15db72012-03-02 09:28:47 +0100625
Javier Martinf606ab82012-03-22 14:54:14 +0100626 /* Free 2D slot if it was an interleaved transfer */
627 if (imxdmac->enabled_2d) {
628 imxdma->slots_2d[imxdmac->slot_2d].count--;
629 imxdmac->enabled_2d = false;
630 }
631
Javier Martin9e15db72012-03-02 09:28:47 +0100632 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
633
634 if (!list_empty(&imxdmac->ld_queue)) {
635 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
636 node);
637 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
638 if (imxdma_xfer_desc(desc) < 0)
639 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
640 __func__, imxdmac->channel);
641 }
642out:
Javier Martinf606ab82012-03-22 14:54:14 +0100643 spin_unlock(&imxdma->lock);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200644}
645
646static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
647 unsigned long arg)
648{
649 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
650 struct dma_slave_config *dmaengine_cfg = (void *)arg;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100651 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100652 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200653 unsigned int mode = 0;
654
655 switch (cmd) {
656 case DMA_TERMINATE_ALL:
Javier Martin6bd08122012-03-22 14:54:01 +0100657 imxdma_disable_hw(imxdmac);
Javier Martin9e15db72012-03-02 09:28:47 +0100658
Javier Martinf606ab82012-03-22 14:54:14 +0100659 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin9e15db72012-03-02 09:28:47 +0100660 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
661 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
Javier Martinf606ab82012-03-22 14:54:14 +0100662 spin_unlock_irqrestore(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200663 return 0;
664 case DMA_SLAVE_CONFIG:
Vinod Kouldb8196d2011-10-13 22:34:23 +0530665 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200666 imxdmac->per_address = dmaengine_cfg->src_addr;
667 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
668 imxdmac->word_size = dmaengine_cfg->src_addr_width;
669 } else {
670 imxdmac->per_address = dmaengine_cfg->dst_addr;
671 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
672 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
673 }
674
675 switch (imxdmac->word_size) {
676 case DMA_SLAVE_BUSWIDTH_1_BYTE:
677 mode = IMX_DMA_MEMSIZE_8;
678 break;
679 case DMA_SLAVE_BUSWIDTH_2_BYTES:
680 mode = IMX_DMA_MEMSIZE_16;
681 break;
682 default:
683 case DMA_SLAVE_BUSWIDTH_4_BYTES:
684 mode = IMX_DMA_MEMSIZE_32;
685 break;
686 }
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200687
Javier Martinbef2a8d2012-10-30 15:58:50 +0000688 imxdmac->hw_chaining = 0;
689
Javier Martin359291a2012-03-22 14:54:06 +0100690 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
Javier Martinbdc0c752012-03-22 14:54:05 +0100691 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
692 CCR_REN;
Javier Martin359291a2012-03-22 14:54:06 +0100693 imxdmac->ccr_to_device =
Javier Martinbdc0c752012-03-22 14:54:05 +0100694 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
695 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100696 imx_dmav1_writel(imxdma, imxdmac->dma_request,
Javier Martinbdc0c752012-03-22 14:54:05 +0100697 DMA_RSSR(imxdmac->channel));
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200698
Javier Martin6bd08122012-03-22 14:54:01 +0100699 /* Set burst length */
Javier Martincd5cf9d2012-03-22 14:54:12 +0100700 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
701 imxdmac->word_size, DMA_BLR(imxdmac->channel));
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200702
703 return 0;
704 default:
705 return -ENOSYS;
706 }
707
708 return -EINVAL;
709}
710
711static enum dma_status imxdma_tx_status(struct dma_chan *chan,
712 dma_cookie_t cookie,
713 struct dma_tx_state *txstate)
714{
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000715 return dma_cookie_status(chan, cookie, txstate);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200716}
717
718static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
719{
720 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
Javier Martinf606ab82012-03-22 14:54:14 +0100721 struct imxdma_engine *imxdma = imxdmac->imxdma;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200722 dma_cookie_t cookie;
Javier Martin9e15db72012-03-02 09:28:47 +0100723 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200724
Javier Martinf606ab82012-03-22 14:54:14 +0100725 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin660cd0d2012-03-22 14:54:15 +0100726 list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000727 cookie = dma_cookie_assign(tx);
Javier Martinf606ab82012-03-22 14:54:14 +0100728 spin_unlock_irqrestore(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200729
730 return cookie;
731}
732
733static int imxdma_alloc_chan_resources(struct dma_chan *chan)
734{
735 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
736 struct imx_dma_data *data = chan->private;
737
Javier Martin6c05f092012-02-28 17:08:17 +0100738 if (data != NULL)
739 imxdmac->dma_request = data->dma_request;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200740
Javier Martin9e15db72012-03-02 09:28:47 +0100741 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
742 struct imxdma_desc *desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200743
Javier Martin9e15db72012-03-02 09:28:47 +0100744 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
745 if (!desc)
746 break;
747 __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
748 dma_async_tx_descriptor_init(&desc->desc, chan);
749 desc->desc.tx_submit = imxdma_tx_submit;
750 /* txd.flags will be overwritten in prep funcs */
751 desc->desc.flags = DMA_CTRL_ACK;
752 desc->status = DMA_SUCCESS;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200753
Javier Martin9e15db72012-03-02 09:28:47 +0100754 list_add_tail(&desc->node, &imxdmac->ld_free);
755 imxdmac->descs_allocated++;
756 }
757
758 if (!imxdmac->descs_allocated)
759 return -ENOMEM;
760
761 return imxdmac->descs_allocated;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200762}
763
764static void imxdma_free_chan_resources(struct dma_chan *chan)
765{
766 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
Javier Martinf606ab82012-03-22 14:54:14 +0100767 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100768 struct imxdma_desc *desc, *_desc;
769 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200770
Javier Martinf606ab82012-03-22 14:54:14 +0100771 spin_lock_irqsave(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200772
Javier Martin6bd08122012-03-22 14:54:01 +0100773 imxdma_disable_hw(imxdmac);
Javier Martin9e15db72012-03-02 09:28:47 +0100774 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
775 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
776
Javier Martinf606ab82012-03-22 14:54:14 +0100777 spin_unlock_irqrestore(&imxdma->lock, flags);
Javier Martin9e15db72012-03-02 09:28:47 +0100778
779 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
780 kfree(desc);
781 imxdmac->descs_allocated--;
782 }
783 INIT_LIST_HEAD(&imxdmac->ld_free);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200784
785 if (imxdmac->sg_list) {
786 kfree(imxdmac->sg_list);
787 imxdmac->sg_list = NULL;
788 }
789}
790
791static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
792 struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530793 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500794 unsigned long flags, void *context)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200795{
796 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
797 struct scatterlist *sg;
Javier Martin9e15db72012-03-02 09:28:47 +0100798 int i, dma_length = 0;
799 struct imxdma_desc *desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200800
Javier Martin9e15db72012-03-02 09:28:47 +0100801 if (list_empty(&imxdmac->ld_free) ||
802 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200803 return NULL;
804
Javier Martin9e15db72012-03-02 09:28:47 +0100805 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200806
807 for_each_sg(sgl, sg, sg_len, i) {
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200808 dma_length += sg_dma_len(sg);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200809 }
810
Sascha Hauerd07102a2011-01-12 14:13:23 +0100811 switch (imxdmac->word_size) {
812 case DMA_SLAVE_BUSWIDTH_4_BYTES:
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200813 if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
Sascha Hauerd07102a2011-01-12 14:13:23 +0100814 return NULL;
815 break;
816 case DMA_SLAVE_BUSWIDTH_2_BYTES:
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200817 if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
Sascha Hauerd07102a2011-01-12 14:13:23 +0100818 return NULL;
819 break;
820 case DMA_SLAVE_BUSWIDTH_1_BYTE:
821 break;
822 default:
823 return NULL;
824 }
825
Javier Martin9e15db72012-03-02 09:28:47 +0100826 desc->type = IMXDMA_DESC_SLAVE_SG;
827 desc->sg = sgl;
828 desc->sgcount = sg_len;
829 desc->len = dma_length;
Javier Martin2efc3442012-03-22 14:54:03 +0100830 desc->direction = direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100831 if (direction == DMA_DEV_TO_MEM) {
Javier Martin9e15db72012-03-02 09:28:47 +0100832 desc->src = imxdmac->per_address;
833 } else {
Javier Martin9e15db72012-03-02 09:28:47 +0100834 desc->dest = imxdmac->per_address;
835 }
836 desc->desc.callback = NULL;
837 desc->desc.callback_param = NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200838
Javier Martin9e15db72012-03-02 09:28:47 +0100839 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200840}
841
842static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
843 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500844 size_t period_len, enum dma_transfer_direction direction,
Peter Ujfalusiec8b5e42012-09-14 15:05:47 +0300845 unsigned long flags, void *context)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200846{
847 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
848 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100849 struct imxdma_desc *desc;
850 int i;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200851 unsigned int periods = buf_len / period_len;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200852
853 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
854 __func__, imxdmac->channel, buf_len, period_len);
855
Javier Martin9e15db72012-03-02 09:28:47 +0100856 if (list_empty(&imxdmac->ld_free) ||
857 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200858 return NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200859
Javier Martin9e15db72012-03-02 09:28:47 +0100860 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200861
862 if (imxdmac->sg_list)
863 kfree(imxdmac->sg_list);
864
865 imxdmac->sg_list = kcalloc(periods + 1,
866 sizeof(struct scatterlist), GFP_KERNEL);
867 if (!imxdmac->sg_list)
868 return NULL;
869
870 sg_init_table(imxdmac->sg_list, periods);
871
872 for (i = 0; i < periods; i++) {
873 imxdmac->sg_list[i].page_link = 0;
874 imxdmac->sg_list[i].offset = 0;
875 imxdmac->sg_list[i].dma_address = dma_addr;
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200876 sg_dma_len(&imxdmac->sg_list[i]) = period_len;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200877 dma_addr += period_len;
878 }
879
880 /* close the loop */
881 imxdmac->sg_list[periods].offset = 0;
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200882 sg_dma_len(&imxdmac->sg_list[periods]) = 0;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200883 imxdmac->sg_list[periods].page_link =
884 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
885
Javier Martin9e15db72012-03-02 09:28:47 +0100886 desc->type = IMXDMA_DESC_CYCLIC;
887 desc->sg = imxdmac->sg_list;
888 desc->sgcount = periods;
889 desc->len = IMX_DMA_LENGTH_LOOP;
Javier Martin2efc3442012-03-22 14:54:03 +0100890 desc->direction = direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100891 if (direction == DMA_DEV_TO_MEM) {
Javier Martin9e15db72012-03-02 09:28:47 +0100892 desc->src = imxdmac->per_address;
893 } else {
Javier Martin9e15db72012-03-02 09:28:47 +0100894 desc->dest = imxdmac->per_address;
895 }
896 desc->desc.callback = NULL;
897 desc->desc.callback_param = NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200898
Javier Martin9e15db72012-03-02 09:28:47 +0100899 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200900}
901
Javier Martin6c05f092012-02-28 17:08:17 +0100902static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
903 struct dma_chan *chan, dma_addr_t dest,
904 dma_addr_t src, size_t len, unsigned long flags)
905{
906 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
907 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100908 struct imxdma_desc *desc;
Javier Martin6c05f092012-02-28 17:08:17 +0100909
910 dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
911 __func__, imxdmac->channel, src, dest, len);
912
Javier Martin9e15db72012-03-02 09:28:47 +0100913 if (list_empty(&imxdmac->ld_free) ||
914 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200915 return NULL;
916
Javier Martin9e15db72012-03-02 09:28:47 +0100917 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Javier Martin6c05f092012-02-28 17:08:17 +0100918
Javier Martin9e15db72012-03-02 09:28:47 +0100919 desc->type = IMXDMA_DESC_MEMCPY;
920 desc->src = src;
921 desc->dest = dest;
922 desc->len = len;
Javier Martin2efc3442012-03-22 14:54:03 +0100923 desc->direction = DMA_MEM_TO_MEM;
Javier Martin9e15db72012-03-02 09:28:47 +0100924 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
925 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
926 desc->desc.callback = NULL;
927 desc->desc.callback_param = NULL;
928
929 return &desc->desc;
Javier Martin6c05f092012-02-28 17:08:17 +0100930}
931
Javier Martinf606ab82012-03-22 14:54:14 +0100932static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
933 struct dma_chan *chan, struct dma_interleaved_template *xt,
934 unsigned long flags)
935{
936 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
937 struct imxdma_engine *imxdma = imxdmac->imxdma;
938 struct imxdma_desc *desc;
939
940 dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n"
941 " src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__,
942 imxdmac->channel, xt->src_start, xt->dst_start,
943 xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
944 xt->numf, xt->frame_size);
945
946 if (list_empty(&imxdmac->ld_free) ||
947 imxdma_chan_is_doing_cyclic(imxdmac))
948 return NULL;
949
950 if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
951 return NULL;
952
953 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
954
955 desc->type = IMXDMA_DESC_INTERLEAVED;
956 desc->src = xt->src_start;
957 desc->dest = xt->dst_start;
958 desc->x = xt->sgl[0].size;
959 desc->y = xt->numf;
960 desc->w = xt->sgl[0].icg + desc->x;
961 desc->len = desc->x * desc->y;
962 desc->direction = DMA_MEM_TO_MEM;
963 desc->config_port = IMX_DMA_MEMSIZE_32;
964 desc->config_mem = IMX_DMA_MEMSIZE_32;
965 if (xt->src_sgl)
966 desc->config_mem |= IMX_DMA_TYPE_2D;
967 if (xt->dst_sgl)
968 desc->config_port |= IMX_DMA_TYPE_2D;
969 desc->desc.callback = NULL;
970 desc->desc.callback_param = NULL;
971
972 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200973}
974
975static void imxdma_issue_pending(struct dma_chan *chan)
976{
Sascha Hauer5b316872012-01-09 10:32:49 +0100977 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
Javier Martin9e15db72012-03-02 09:28:47 +0100978 struct imxdma_engine *imxdma = imxdmac->imxdma;
979 struct imxdma_desc *desc;
980 unsigned long flags;
Sascha Hauer5b316872012-01-09 10:32:49 +0100981
Javier Martinf606ab82012-03-22 14:54:14 +0100982 spin_lock_irqsave(&imxdma->lock, flags);
Javier Martin9e15db72012-03-02 09:28:47 +0100983 if (list_empty(&imxdmac->ld_active) &&
984 !list_empty(&imxdmac->ld_queue)) {
985 desc = list_first_entry(&imxdmac->ld_queue,
986 struct imxdma_desc, node);
987
988 if (imxdma_xfer_desc(desc) < 0) {
989 dev_warn(imxdma->dev,
990 "%s: channel: %d couldn't issue DMA xfer\n",
991 __func__, imxdmac->channel);
992 } else {
993 list_move_tail(imxdmac->ld_queue.next,
994 &imxdmac->ld_active);
995 }
996 }
Javier Martinf606ab82012-03-22 14:54:14 +0100997 spin_unlock_irqrestore(&imxdma->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200998}
999
1000static int __init imxdma_probe(struct platform_device *pdev)
Javier Martin6bd08122012-03-22 14:54:01 +01001001 {
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001002 struct imxdma_engine *imxdma;
Shawn Guo73930eb2012-09-15 15:57:00 +08001003 struct resource *res;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001004 int ret, i;
Shawn Guo73930eb2012-09-15 15:57:00 +08001005 int irq, irq_err;
Javier Martin6bd08122012-03-22 14:54:01 +01001006
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001007 imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001008 if (!imxdma)
1009 return -ENOMEM;
1010
Shawn Guoe51d0f02012-09-15 21:11:28 +08001011 imxdma->devtype = pdev->id_entry->driver_data;
1012
Shawn Guo73930eb2012-09-15 15:57:00 +08001013 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding73312052013-01-21 11:09:00 +01001014 imxdma->base = devm_ioremap_resource(&pdev->dev, res);
1015 if (IS_ERR(imxdma->base))
1016 return PTR_ERR(imxdma->base);
Shawn Guo73930eb2012-09-15 15:57:00 +08001017
1018 irq = platform_get_irq(pdev, 0);
1019 if (irq < 0)
1020 return irq;
Javier Martincd5cf9d2012-03-22 14:54:12 +01001021
Fabio Estevama2367db2012-07-03 15:33:29 -03001022 imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001023 if (IS_ERR(imxdma->dma_ipg))
1024 return PTR_ERR(imxdma->dma_ipg);
Fabio Estevama2367db2012-07-03 15:33:29 -03001025
1026 imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001027 if (IS_ERR(imxdma->dma_ahb))
1028 return PTR_ERR(imxdma->dma_ahb);
Fabio Estevama2367db2012-07-03 15:33:29 -03001029
1030 clk_prepare_enable(imxdma->dma_ipg);
1031 clk_prepare_enable(imxdma->dma_ahb);
Javier Martin6bd08122012-03-22 14:54:01 +01001032
1033 /* reset DMA module */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001034 imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
Javier Martin6bd08122012-03-22 14:54:01 +01001035
Shawn Guoe51d0f02012-09-15 21:11:28 +08001036 if (is_imx1_dma(imxdma)) {
Shawn Guo73930eb2012-09-15 15:57:00 +08001037 ret = devm_request_irq(&pdev->dev, irq,
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001038 dma_irq_handler, 0, "DMA", imxdma);
Javier Martin6bd08122012-03-22 14:54:01 +01001039 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +01001040 dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001041 goto err;
Javier Martin6bd08122012-03-22 14:54:01 +01001042 }
1043
Shawn Guo73930eb2012-09-15 15:57:00 +08001044 irq_err = platform_get_irq(pdev, 1);
1045 if (irq_err < 0) {
1046 ret = irq_err;
1047 goto err;
1048 }
1049
1050 ret = devm_request_irq(&pdev->dev, irq_err,
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001051 imxdma_err_handler, 0, "DMA", imxdma);
Javier Martin6bd08122012-03-22 14:54:01 +01001052 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +01001053 dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001054 goto err;
Javier Martin6bd08122012-03-22 14:54:01 +01001055 }
1056 }
1057
1058 /* enable DMA module */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001059 imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
Javier Martin6bd08122012-03-22 14:54:01 +01001060
1061 /* clear all interrupts */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001062 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +01001063
1064 /* disable interrupts */
Javier Martincd5cf9d2012-03-22 14:54:12 +01001065 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001066
1067 INIT_LIST_HEAD(&imxdma->dma_device.channels);
1068
Sascha Hauerf8a356f2011-01-31 11:35:59 +01001069 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
1070 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
Javier Martin6c05f092012-02-28 17:08:17 +01001071 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
Javier Martinf606ab82012-03-22 14:54:14 +01001072 dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
1073
1074 /* Initialize 2D global parameters */
1075 for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
1076 imxdma->slots_2d[i].count = 0;
1077
1078 spin_lock_init(&imxdma->lock);
Sascha Hauerf8a356f2011-01-31 11:35:59 +01001079
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001080 /* Initialize channel parameters */
Javier Martin6bd08122012-03-22 14:54:01 +01001081 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001082 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1083
Shawn Guoe51d0f02012-09-15 21:11:28 +08001084 if (!is_imx1_dma(imxdma)) {
Shawn Guo73930eb2012-09-15 15:57:00 +08001085 ret = devm_request_irq(&pdev->dev, irq + i,
Javier Martin6bd08122012-03-22 14:54:01 +01001086 dma_irq_handler, 0, "DMA", imxdma);
1087 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +01001088 dev_warn(imxdma->dev, "Can't register IRQ %d "
1089 "for DMA channel %d\n",
Shawn Guo73930eb2012-09-15 15:57:00 +08001090 irq + i, i);
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001091 goto err;
Javier Martin6bd08122012-03-22 14:54:01 +01001092 }
Javier Martin2d9c2fc2012-03-22 14:54:10 +01001093 init_timer(&imxdmac->watchdog);
1094 imxdmac->watchdog.function = &imxdma_watchdog;
1095 imxdmac->watchdog.data = (unsigned long)imxdmac;
Sascha Hauer8267f162010-10-20 08:37:19 +02001096 }
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001097
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001098 imxdmac->imxdma = imxdma;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001099
Javier Martin9e15db72012-03-02 09:28:47 +01001100 INIT_LIST_HEAD(&imxdmac->ld_queue);
1101 INIT_LIST_HEAD(&imxdmac->ld_free);
1102 INIT_LIST_HEAD(&imxdmac->ld_active);
1103
1104 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
1105 (unsigned long)imxdmac);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001106 imxdmac->chan.device = &imxdma->dma_device;
Russell King - ARM Linux8ac69542012-03-06 22:36:27 +00001107 dma_cookie_init(&imxdmac->chan);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001108 imxdmac->channel = i;
1109
1110 /* Add the channel to the DMAC list */
Javier Martin9e15db72012-03-02 09:28:47 +01001111 list_add_tail(&imxdmac->chan.device_node,
1112 &imxdma->dma_device.channels);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001113 }
1114
1115 imxdma->dev = &pdev->dev;
1116 imxdma->dma_device.dev = &pdev->dev;
1117
1118 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1119 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1120 imxdma->dma_device.device_tx_status = imxdma_tx_status;
1121 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1122 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
Javier Martin6c05f092012-02-28 17:08:17 +01001123 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
Javier Martinf606ab82012-03-22 14:54:14 +01001124 imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001125 imxdma->dma_device.device_control = imxdma_control;
1126 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1127
1128 platform_set_drvdata(pdev, imxdma);
1129
Javier Martin6c05f092012-02-28 17:08:17 +01001130 imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
Sascha Hauer1e070a62011-01-12 13:14:37 +01001131 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
1132 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1133
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001134 ret = dma_async_device_register(&imxdma->dma_device);
1135 if (ret) {
1136 dev_err(&pdev->dev, "unable to register\n");
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001137 goto err;
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001138 }
1139
1140 return 0;
1141
Shawn Guo04bbd8e2012-09-15 15:16:47 +08001142err:
Fabio Estevama2367db2012-07-03 15:33:29 -03001143 clk_disable_unprepare(imxdma->dma_ipg);
1144 clk_disable_unprepare(imxdma->dma_ahb);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001145 return ret;
1146}
1147
1148static int __exit imxdma_remove(struct platform_device *pdev)
1149{
1150 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001151
1152 dma_async_device_unregister(&imxdma->dma_device);
1153
Fabio Estevama2367db2012-07-03 15:33:29 -03001154 clk_disable_unprepare(imxdma->dma_ipg);
1155 clk_disable_unprepare(imxdma->dma_ahb);
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001156
1157 return 0;
1158}
1159
1160static struct platform_driver imxdma_driver = {
1161 .driver = {
1162 .name = "imx-dma",
1163 },
Shawn Guoe51d0f02012-09-15 21:11:28 +08001164 .id_table = imx_dma_devtype,
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001165 .remove = __exit_p(imxdma_remove),
1166};
1167
1168static int __init imxdma_module_init(void)
1169{
1170 return platform_driver_probe(&imxdma_driver, imxdma_probe);
1171}
1172subsys_initcall(imxdma_module_init);
1173
1174MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1175MODULE_DESCRIPTION("i.MX dma driver");
1176MODULE_LICENSE("GPL");